Sensor devices and related methods and systems

Abstract

Embodiments of the present disclosure relate to sensor devices and related methods and systems. The sensor includes detection circuitry and control circuitry coupled to the detection circuitry. The detection circuitry generates a detection signal indicative of the detected physical quantity. The control circuitry in operation receives the detection signal and the frequency indication signal and generates a trigger signal based on the frequency indication signal and a set of local reference signals. The sensor generates a digital output signal and a lock signal based on the trigger signal and the detection signal. Generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The lock signal is temporally aligned with the digital output signal.

Description

[0001] RELATED APPLICATIONS

[0002] This application is a divisional application of the application for invention patent with Chinese national application number 202210328955.4, application date March 30, 2022, and invention name “Sensor device and related methods and systems”. TECHNICAL FIELD

[0003] The present disclosure relates to sensors, for example, obtained in MEMS (Micro-Electro-Mechanical System) technology. BACKGROUND

[0004] It is known, for example in the field of consumer electronics, as well as in the industrial and automotive field, electronic devices incorporating a plurality of sensors, each configured to detect one or more respective physical quantities for operating the respective electronic device.

[0005] For example, the sensors can be accelerometers, gyroscopes, temperature sensors, pressure sensors, resistance sensors, mechanical stress sensors and strain gauges, etc.

[0006] It is also known to manufacture such sensors using MEMS technology, which makes it possible to obtain sensors with small size, low energy consumption and high detection accuracy.

[0007] The MEMS sensors convert the physical quantities into respective electric signals of the analog type, whose temporal evolution is a function of the temporal evolution of the detected physical quantities. Furthermore, the MEMS sensors are each configured to convert the respective analog signals into corresponding (digital) discretized signals having a respective output sampling rate, and to provide the respective discretized signals to a control unit of the electronic device.

[0008] The control unit of the electronic device is configured to process the discretized signals received from the plurality of sensors.

[0009] It is desirable to ensure that the sensors send the respective discretized signals to the electronic device in a mutually synchronized manner. Different methods are adopted for this purpose.

[0010] In one method, the analog signals generated by the sensors are first stored in a sample-and-hold circuit, and then discretized by a single analog-to-digital converter.

[0011] In another method, the sensors each comprise a respective analog-to-digital converter, whose discretization function is controlled in parallel by a single trigger signal.

[0012] However, both methods involve incorporating additional devices in the electronic device, and therefore involve high cost and high energy consumption of the electronic device. Additionally, these methods are not suitable for applications requiring a high output data rate from the sensors.

[0013] In another approach, a control unit of the electronic device is configured to receive specific configuration information from the sensor, and the control unit determines a series of synchronization instructions to be sent to the sensor based on the specific configuration information. However, this approach requires a large amount of computational resources of the control unit of the electronic device, resulting in high energy consumption. In addition, this approach also requires the use of a dedicated communication interface between the sensor and the control unit, thereby reducing the versatility and simplicity of the implementation of the electronic device. SUMMARY

[0014] In one embodiment, a sensor includes a detection circuitry that, in operation, generates a detection signal indicative of a detected physical quantity, and a control circuitry coupled to the detection circuitry, wherein the control circuitry, in operation, receives the detection signal and a frequency indication signal and generates a trigger signal based on the frequency indication signal and a set of local reference signals. The sensor generates a digital output signal and a lock signal based on the trigger signal and the detection signal. Generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal, and the lock signal is time-aligned with the digital output signal.

[0015] In one embodiment, a system includes a plurality of sensors, each sensor including a detection circuitry that, in operation, generates a detection signal indicative of a detected physical quantity, and a processing circuitry coupled to the detection circuitry, wherein the processing circuitry, in operation, receives the detection signal, receives a frequency indication signal, generates a trigger signal based on the frequency indication signal and a set of local reference signals, and generates a digital output signal and a lock signal based on the trigger signal and the detection signal, wherein generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal, and the lock signal is time-aligned with the digital output signal, wherein the plurality of sensors includes a reference sensor and a slave sensor coupled to the reference sensor, and the lock signal of the reference sensor is the received frequency indication signal of the slave sensor.

[0016] In one embodiment, a method includes synchronizing samples of digital output signals of a plurality of sensors, the plurality of sensors including a reference sensor and a slave sensor, the synchronizing including receiving, by the reference sensor, a first frequency indication signal, generating, by the reference sensor, a first trigger signal based on the first frequency indication signal and a first set of local reference signals, generating, by the reference sensor, a sample of a digital output signal of the reference sensor and a first lock signal based on the first trigger signal, the first lock signal being time-aligned with the digital output signal of the reference sensor, receiving, by the slave sensor, the first lock signal, generating, by the slave sensor, a second trigger signal based on the first lock signal and a second set of local reference signals, and generating, by the slave sensor, a sample of a digital output signal of the slave sensor and a second lock signal based on the second trigger signal, the second lock signal being time-aligned with the digital output signal of the slave sensor.

[0017] In one embodiment, the content of a non-transitory computer-readable medium configures a processing circuitry to synchronize samples of digital output signals from a plurality of sensors, including a reference sensor and a slave sensor. The synchronization includes: receiving a first frequency indication signal by the reference sensor; generating a first trigger signal by the reference sensor based on the first frequency indication signal and a first local reference signal set; generating samples of the reference sensor's digital output signals and a first lock signal by the reference sensor based on the first trigger signal, the first lock signal being time-aligned with the digital output signals of the reference sensor; receiving the first lock signal by the slave sensor; generating a second trigger signal by the slave sensor based on the first lock signal and a second local reference signal set; and generating samples of the slave sensor's digital output signals and a second lock signal by the slave sensor based on the second trigger signal, the second lock signal being time-aligned with the digital output signals of the slave sensor. Attached Figure Description

[0018] To better understand this disclosure, some embodiments thereof will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0019] FIG. 1 A block diagram of an electronic device including multiple sensors according to one embodiment is shown;

[0020] FIG. 2 It shows FIG. 1 A block diagram of an embodiment of a sensor for an electronic device;

[0021] FIG. 3 It shows FIG. 1 A block diagram of an embodiment of another sensor for an electronic device;

[0022] FIG. 4 An extractor is shown according to one embodiment. FIG. 2 and FIG. 3 The structure of the frame;

[0023] FIG. 5 An embodiment is shown. FIG. 4 The structure of the extractor in the box;

[0024] FIG. 6 An embodiment is shown. FIG. 3 The structure of the sensor's frame;

[0025] FIG. 7 It shows FIG. 6 Example trends of how the input signal changes over time in the use of the box;

[0026] FIG. 8 An embodiment is shown.FIG. 3 the structure of another block of sensors;

[0027] FIG. 9 a flowchart of a method performed by a block of FIG. 8

[0028] FIG. 10 a block diagram of an electronic device comprising a plurality of sensors according to an embodiment; and

[0029] FIG. 11 a block diagram of a sensor of an electronic device according to an embodiment. FIG. 10

[0030] In the following, if not otherwise stated, reference is made to the frequency of a discretized (digital) signal to indicate its sampling frequency, the data rate at which samples of the discretized signal are provided at the output of the corresponding block from which it is generated. DETAILED DESCRIPTION

[0031] FIG. 1 is a schematic view of an electronic system or device 1, for example a smartphone, a wearable device, a device for augmented reality or virtual reality, a device for monitoring one or more physical quantities, for example for monitoring vibrations, a car control system, etc.

[0032] The electronic device 1 comprises a plurality of sensors 5, a control unit or circuit 7 and an interface 10 operatively coupling the plurality of sensors 5 and the control unit 7 to each other.

[0033] The control unit 7 comprises a memory 8 and a processing unit or core and is configured to send instructions, for example configuration instructions, to the sensors 5 and to receive measurement data or samples from the sensors 5 by means of the interface 10, for example a bus of the known type for the transmission of electrical signals.

[0034] The electronic device 1 further comprises input and output peripherals 12, for example a screen, in particular of the touch screen type, one or more keys, etc., and a power supply unit 14, for example a battery. The input and output peripherals 12 and the power supply unit 14 are coupled to the control unit 7. The power supply unit 14 can also be configured to provide a power supply voltage to the sensors 5 by means of the interface 10.

[0035] The plurality of sensors 5 here comprises a first sensor 5A, a second sensor 5B and a third sensor 5C, each of which is configured to detect one or more respective physical quantities associated with the operation of the electronic device 1. Embodiments can comprise more or fewer sensors 5.

[0036] ​​For example, the first, second and third sensors 5A, 5B, 5C can each be, for example, an acceleration sensor, a temperature sensor, a pressure sensor, a mechanical stress sensor, a resistance sensor, a gyroscope, etc.

[0037] In particular, in this embodiment, the first, second and third sensors 5A, 5B, 5C are sensors of the MEMS type.

[0038] Furthermore, the first, second and third sensors 5A, 5B, 5C are configured to provide, by means of the interface 10, a respective output signal S O of digital type to the control unit 7, each. O According to one or more respective detected physical quantities and having an output frequency f ou . In particular, samples of the output signal S O of the sensors 5 are provided and stored in the memory 8.

[0039] As described in detail hereinafter, the first, second and third sensors 5A, 5B, 5C are configured to provide samples of the respective output signal S O to the control unit 7 in a mutually synchronized manner, so as to have the same output frequency f ou and the same phase (to be aligned in time).

[0040] In particular, in this embodiment, FIG. 2 the first sensor 5A shown in Fig. 1 is configured to operate as a reference (or master) sensor, while the second and third sensors 5B, 5C FIG. 3 are configured to operate as slave sensors, each.

[0041] As described in detail hereinafter, here the first, second and third sensors 5A, 5B, 5C can have a general structure similar to each other, except for the differences discussed below; therefore, common elements are indicated by the same reference numerals. In particular, here the second and third sensors 5B, 5C can have a similar general structure, except for the sensitive part, which is optimized for detecting one or more specific physical quantities, each. Therefore, for example, FIG. 3 the reference 5 can indicate any of the second sensor 5B or the third sensor 5C, without selection.

[0042] As shown in Figs. 1 and 2, FIG. 2 and FIG. 3 the first, second and third sensors 5A, 5B, 5C each comprise a detection unit 20, a signal conditioning stage 25 and a clock 30.

[0043] The detection unit 20 is the sensitive part of the first, second and third sensors 5A, 5B, 5C; the detection unit or circuit 20 is configured to detect a respective physical quantity associated with the operation of the electronic device 1 and to generate one or more electrical signals, here analog signals S A .

[0044] In particular, in the present embodiment, the detection unit 20 comprises a sensing element 35 and a mechanical oscillator 37.

[0045] The detection unit 20 of the first, second and third sensors 5A, 5B, 5C, in particular the sensing element 35 and / or the mechanical oscillator 37, are designed based on the specific physical quantity to be detected and on the specific application; therefore, they can be different in each sensor 5. In particular, the second and third sensors 5B, 5C can be identical to each other, apart from the differences in the respective sensing element 35 and / or in the respective mechanical oscillator 37.

[0046] The mechanical oscillator 37 comprises a structure, for example movable in an elastic manner and / or deformable, such as a cantilever beam, a membrane, or a structure having any other shape, having a resonance frequency f r .

[0047] In use, the mechanical oscillator 37 is actuated, for example according to electrostatic, piezoelectric or electromagnetic actuation principles, so that the respective movable and / or deformable structure oscillates at an operating frequency f o . Typically, the operating frequency f o is a function of the resonance frequency f r , for example it is equal to the resonance frequency f r .

[0048] The mechanical oscillator 37 is configured so that the physical quantity to be detected changes the movement of the movable and / or deformable structure of the mechanical oscillator 37, for example changing its phase, amplitude and / or frequency.

[0049] The sensing element 35 is configured for detecting the movement of the movable and / or deformable structure of the mechanical oscillator 37, for example according to electrostatic, piezoresistive, piezoelectric or electromagnetic detection principles, and converting it into an analog signal S A . The trend of the analog signal S A over time thus indicates the changes in movement of the movable and / or deformable structure of the mechanical oscillator 37, which are caused by the temporal variations of the physical quantity to be detected.

[0050] The clock 30 is configured to provide a periodic signal having a clock frequency f clk of the order of, for example, several megahertz, hereinafter referred to as clock signal CLK, for example a square wave signal. For example, the clock 30 can be formed by any type of known electronic oscillator, such as a voltage-controlled oscillator.

[0051] Signal conditioning stage or circuit 25 receives clock signal CLK and analog signal S. A And generate output signal S O As discussed below, the output signal S O From analog signal S A The discretization is obtained.

[0052] In detail, the signal conditioning stage 25 includes an analog conditioning circuit (or analog front end, AFE) 40, an analog-to-digital converter 43, a filter 46, and an output data rate (ODR) modification block or circuit 49, hereinafter also referred to as ODR modification block 49.

[0053] Analog adjustment circuit 40 includes, for example, one or more operational amplifiers and is configured, for example, to adjust analog signal S A Filtering, amplification, or demodulation is performed to provide a regulated analog signal S'. A .

[0054] Analog-to-digital converter 43 is configured to receive a regulated analog signal S' A Provide sampling signal S S Sampling signal S S By using a sampling frequency f s For the regulated analog signal S' A It is obtained by discretization.

[0055] sampling frequency f s The selection is based on the specific application requirements during the design phase. For example, the sampling frequency f s Satisfying the Nyquist sampling theorem, the operating frequency f of the mechanical oscillator 37 of the detection unit 20 is greater than that of the oscillator 37. o Twice as much.

[0056] The sampled signal S output from analog-to-digital converter 43 S Therefore, it has a sampling frequency f. s The sampling frequency.

[0057] Filter 46 includes one or more low-pass or band-pass type filters, having one or more corresponding cutoff frequencies, and is configured to receive the sampled signal S. S Provides digital signal S D Therefore, the digital signal S D By sampling signal S S Filtering is performed to obtain, for example, to remove unwanted spectral components introduced by the analog-to-digital converter 43, the analog conditioning circuit 40, and / or the detection unit 20.

[0058] Depending on the specific application and design requirements, such as to meet die area requirements, filter 46 can also be configured to reduce the sampling signal S.S the frequency of the digital signal S s , e.g. reducing the integer reduction factor, the integer reduction factor being comprised between 1 and 1024, for example.

[0059] Therefore, the digital signal S D has an adjusted sampling frequency f s which is here lower than the sampling frequency f s . In other applications, the adjusted sampling frequency f s is equal to the sampling frequency f s . s s .

[0060] In this embodiment, the signal conditioning stage 25 of the first, second and third sensors 5A, 5B, 5C further receives a respective set of configuration signals CONF including a frequency selection signal F_C and an output trigger signal OUT_TRG. As described below, each signal conditioning stage 25 further generates a respective reference signal EXT_REF, INT_REF.

[0061] In detail, the ODR modification block 49 is configured to receive the digital signal S D and the set of configuration signals CONF and to provide the output signal S O and the reference signals EXT_REF, INT_REF.

[0062] The output signal S O is obtained by modifying the sampling frequency of the digital signal S D .

[0063] Here, the reference signals are indicated as external reference signal EXT_REF for the first sensor 5A FIG. 2 and as internal reference signals INT_REF for the second sensor 5B FIG. 3 and for the third sensor 5C. The reference signals can be referred to as lock signals.

[0064] The external reference signal EXT_REF is a periodic signal, e.g. a square wave signal, whose frequency is equal to the output sampling rate f O of the output signal S ou of the first sensor 5A in this embodiment.

[0065] However, in general, the frequency of the reference signal EXT_REF can be a divisor of the output sampling rate f O of the output signal S ou of the first sensor 5A.

[0066] In detail, the first sensor 5A is coupled to the second and third sensors 5B, 5C and, in use, generates and provides the external reference signal EXT_REF to the second sensor 5B and to the third sensor 5C.

[0067] The internal reference signal INT_REF of the second sensor 5B and the internal reference signal INT_REF of the third sensor 5C are both periodic signals, for example square wave signals, whose frequency is equal to the frequency of the respective output signal S O at the output sampling rate f ou .

[0068] As described in detail hereinafter, the second sensor 5B and the third sensor 5C each receive an external reference signal EXT_REF and generate samples of the respective output signal S O in response to a comparison between the external reference signal EXT_REF and the respective internal reference signal INT_REF.

[0069] As illustrated in detail in FIG. 4 , the ODR modification block 49 of the first, second and third sensors 5A, 5B, 5C comprises an interpolator 52, a decimator 55 and a reference block or circuit 58.

[0070] The interpolator 52 comprises an interpolation filter 61 configured to receive at the input a digital signal S s having an adjusted sampling frequency f D and configured to provide at the output an interpolated digital signal S s having an interpolation frequency f int higher than the adjusted sampling frequency f D,int . In particular, here the interpolation frequency f int is obtained by increasing the adjusted sampling frequency f s by an interpolation factor I1 according to the formula f int = f s · I1.

[0071] The interpolator 52, in particular the respective interpolation filter 61, can for example use linear or non-linear phase interpolation circuits, in particular of the CIC (Cascade Integrator Comb) type, the Spline type, the Lagrange type or the Hermite type, in a known manner.

[0072] The decimator 55 is configured to receive the interpolated digital signal S D,int and a set of configuration signals CONF and to provide the output signal S O in response to receiving an output trigger signal OUT_TRG.

[0073] In detail, as illustrated in FIG. 5 , the decimator 55 comprises a filtering stage or circuit 65, a down-sampler 68 and a gain block or circuit 71, cascaded to each other.

[0074] Filter stage 65 is a low-pass filter, such as an infinite impulse response (IIR) filter or a finite impulse response (FIR) filter, like a CIC circuit, and is configured to receive the frequency selection signal F_C and the interpolated digital signal S. D,int It also provides a filtered signal F.

[0075] Filter stage 65 has a transfer function with a cutoff frequency f. c Cutoff frequency f c Based on the output frequency f ou In particular, selection is based on the frequency selection signal F_C.

[0076] For example, the cutoff frequency f c Selected to make the output signal S O Frequency and cutoff frequency f c The ratio between them conforms to the Nyquist sampling theorem. Furthermore, the cutoff frequency f... c It was selected to suppress the high-frequency spectral image introduced by interpolator 52.

[0077] The transfer function of filter stage 65, especially the cutoff frequency f. c It can be modified in a known manner during use. For example, in the case where filter stage 65 is formed by an Nth-order CIC filter, the corresponding coefficients of its transfer function can be determined in a known manner based on the output signal S. O Frequency and interpolated digital signal S D,int The ratio between the frequencies is used to determine the transfer function. In the case where filter stage 65 is formed by an IIR filter, the corresponding coefficients for determining its transfer function can be selected from a specific lookup table stored, for example, in memory 8.

[0078] The downsampler 68 is configured to receive the filtered signal F and output the trigger signal OUT_TRG, and provide the downsampled signal DS.

[0079] Specifically, the downsampler 68 is configured to respond to receiving a first sample F of the filtered signal F at a first time t1. i (t1) is used to store the first sample F. i (t1), and in response to the second time t2 after the first time t1, the second sample F of the filtered signal F is received. i (t2) and using the second sample F i (t2) Overwrite the first sample F i (t1).

[0080] Downsampler 68 is configured to provide a sample F of the currently stored filtered signal F at the output in response to the detection of an event of the output trigger signal OUT_TRG (specifically a switching edge, such as a rising or falling edge). iFor example, if the down-sampler 68 does not detect any event of the output trigger signal OUT_TRG between a first time instant tl and a second time instant t2, and detects an event of the output trigger signal OUT_TRG after the second time instant t2, the down-sampler 68 provides at the output a second sample F i of the filtered signal F i at the output instant t2. The set of samples F O constitutes the down-sampled signal DS.

[0081] In other words, the down-sampler 68 is configured so that the sampling frequency of the down-sampled signal DS is lower than or at most equal to the sampling frequency of the filtered signal F.

[0082] The gain block 71 is configured to receive the down-sampled signal DS and the frequency selection signal F_C and to provide an output signal S i .

[0083] In detail, the gain block 71 is configured to amplify or attenuate the value of the sample F N of the down-sampled signal DS corresponding to the d.c. component (zero frequency component) of the down-sampled signal DS with a gain factor G. For example, the zero frequency component of the down-sampled signal DS is identified by performing a Fourier transform on the down-sampled signal DS. The gain factor G is selected as a function of the frequency selection signal F_C and of the type of filter used in the filtering stage 65.

[0084] In particular, if the filtering stage 65 is obtained using an IIR filter, the gain factor G can be selected from a specific table stored in the memory 8. If the filtering stage 43 is obtained using a CIC filter, the gain factor G can be calculated as 1 / D1 O , where N is the order of the CIC filter of the filtering stage 65 and D1 is a value indicative of the ratio between the frequency of the output signal S D,int and the frequency of the interpolated digital signal S D .

[0085] In practice, in use, the samples of the respective digital signals S D provided by the ODR modification block 49 of the reference sensor 5A and of the slave sensors 5B, 5C comprise up-sampling the respective digital signals S D,int , thus generating the interpolated signals S D,int and down-sampling the interpolated signals S O , thus generating the respective output signals S D，int .

[0086] Moreover, down-sampling the interpolated signals S ca low-pass filter (filter stage 65) filters the interpolated signal, thereby obtaining a filtered signal F; in response to receiving the respective output trigger signal OUT TRG by the reference sensor 5A and the slave sensors 5B, 5C, downsamples the filtered signal F, thereby obtaining a downsampled signal DS having a d.c. component; and modifies the d.c. component of the downsampled signal DS by amplifying or attenuating the d.c. component using a gain value G.

[0087] The reference block or circuit 58 FIG. 4 is configured to receive the output trigger signal OUT TRG and, in response to receiving the respective output trigger signal OUT TRG, provide a respective reference signal (external reference signal EXT REF in case of the first sensor 5A and internal reference signal INT REF in case of the second and third sensors 5B, 5C).

[0088] In detail, the reference block 58 is configured to, in response to receiving the respective output trigger signal OUT TRG, in particular in response to detecting a switching event or switching edge (e.g. a rising edge or a falling edge) of the output trigger signal OUT TRG, generate a switching edge (e.g. a rising edge or a falling edge) of the respective reference signal. In other words, the switching edge of the external reference signal EXT REF of the first sensor 5A is aligned in time with a sample of the output signal S O of the first sensor 5A provided in response to receiving the respective output trigger signal OUT TRG.

[0089] Likewise, the switching edge of the internal reference signal INT REF of the second sensor 5B is aligned in time with a sample of the output signal S O of the second sensor 5B provided in response to receiving the respective output trigger signal OUT TRG. Additionally, the switching edge of the internal reference signal INT REF of the third sensor 5C is aligned in time with a sample of the output signal S O of the third sensor 5C provided in response to receiving the respective output trigger signal OUT TRG.

[0090] Referring again to FIG. 2 , the first sensor 5A further comprises a configuration block or circuit 80 configured to receive the respective clock signal CLK and the user signal S U and to generate a respective set of configuration signals CONF.

[0091] As shown in FIG. 1 , the user signal S U is transmitted by the control unit 7 to the first sensor 5A via the interface 10 and indicates a desired output data rate ODR E from the plurality of sensors 5.

[0092] For example, in use, a user of the electronic device 1 can indicate, via the peripheral unit 12, a desired output data rate ODR E .

[0093] In this embodiment, the user signal S U indicates a set value N s equal to a number of cycles of the clock signal CLK of the first sensor 5A, for example a number of rising edges or falling edges. The configuration block 80 FIG. 2 of the first sensor 5A is configured to count the cycles of the respective clock signal CLK and to generate a respective set of configuration signals CONF when the number of cycles of the respective clock signal CLK is equal to the set value N s . In particular, the frequency selection signal F_C of the first sensor 5A indicates the set value N s .

[0094] With reference to FIG. 3 , the configuration blocks or circuits of the second and third sensors 5B, 5C, indicated by 83, are configured to receive the clock signal CLK from the respective clock 30, the internal reference signal INT_REF from the respective reference block 58 (see FIG. 4 ) and the external reference signal EXT_REF from the first sensor 5A and to generate a respective set of configuration signals CONF.

[0095] The configuration block 83 of the second sensor 5B and the configuration block 83 of the third sensor 5C each comprise a respective measurement block or circuit 85 and a respective correction block or circuit 90.

[0096] The measurement blocks 85 of the second and third sensors 5B, 5C are configured to receive the respective clock signal CLK, the respective internal reference signal INT_REF and the external reference signal EXT_REF; and to generate a respective set of correction signals CORR comprising a phase correction signal PH_C and a frequency selection signal F_C.

[0097] As illustrated in detail in FIG. 6 , the measurement block 85 comprises a counter 100, a first register 105A, a second register 105B, a third register 105C, a first subtraction device 110A and a second subtraction device 110B.

[0098] The counter 100 is a self-running counter configured to receive a clock signal CLK, store a count value and provide a clock count signal N CLK indicative of the count value. The counter 100 increases the count by one unit at each period of the clock signal CLK (e.g. at each rising or falling edge). In other words, the count value has an increasing monotonic value which is equal to the number of periods of the clock signal CLK counted since the last reset of the counter 100 (e.g. at the electronic device 1 reboot).

[0099] The first register 105A is configured to receive and store the clock count signal N CLK, receive the internal reference signal INT REF and provide an internal phase signal N INT in response to detecting a switching edge (e.g. a rising or falling edge) of the internal reference signal INT REF. When a switching edge of the internal reference signal INT REF is detected, the internal phase signal N INT is equal to the value of the clock count signal N CLK stored in the first register 105A.

[0100] The second register 105B is configured to receive and store the clock count signal N CLK, receive the external reference signal EXT REF and provide a first external count signal N1 EXT in response to detecting a switching edge (e.g. a rising or falling edge) of the external reference signal EXT REF. When a switching edge of the external reference signal EXT REF is detected, the first external count signal N1 EXT is equal to the value of the clock count signal N CLK stored in the second register 105B.

[0101] The first subtraction element 110A is configured to receive the internal phase signal N INT and the first external count signal N1 EXT and provide a phase correction signal PH C. The phase correction signal PH C is given by the difference between the internal phase signal N INT and the first external count signal N1 EXT and corresponds to the number Nd of phase-shifted periods of the clock signal CLK. As shown, the phase correction signal PH C is indicative of the phase difference AF between the internal phase signal N INT and the first external count signal N1 EXT. FIG. 7

[0102] In other words, the phase correction signal PH C generated by the measurement block 85 of the second sensor 5B is indicative of the time offset (phase shift) between the internal reference signal INT REF and the external reference signal EXT REF of the second sensor 5B (in particular, between the rising edge of the internal reference signal INT REF and the rising edge of the external reference signal EXT REF of the second sensor 5B), the time offset (phase shift) being expressed as a number of periods of the clock signal CLK of the second sensor 5B.

[0103] ​Likewise, the phase correction signal PH_C generated by the measurement block 85 of the third sensor 5C is indicative of the phase shift between the internal reference signal INT_REF and the external reference signal EXT_REF of the third sensor 5C, in particular between the rising edge of the internal reference signal INT_REF and the rising edge of the external reference signal EXT_REF of the third sensor 5C, expressed as a number of periods of the clock signal CLK of the third sensor 5C.

[0104] Referring again to FIG. 6 , the third register 105C is configured to receive and store the first external count signal N1_EXT, to receive the external reference signal EXT_REF and to provide the second external count signal N2_EXT in response to detecting a switching edge, e.g. a rising edge or a falling edge, of the external reference signal EXT_REF. Upon detecting a switching edge of the external reference signal EXT_REF, the second external count signal N2_EXT is equal to the value of the first external count signal N1_EXT stored in the third register 105C.

[0105] The second subtraction element 110B is configured to receive the first external count signal N1_EXT and the second external count signal N2_EXT and to provide the frequency selection signal F_C. The frequency selection signal F_C is given by the difference between the first external count signal N1_EXT and the second external count signal N2_EXT and corresponds to a number of frequency periods Nf of the clock signal CLK. As FIG. 7 can be seen, the frequency selection signal F_C is indicative of the time difference At between two consecutive switching edges, in particular two consecutive rising edges, of the external reference signal EXT_REF.

[0106] In practice, the frequency selection signals F_C generated by the measurement blocks 85 of the second and third sensors 5B, 5C are indicative of the frequency of the external reference signal EXT_REF, of the output frequency f O of the output signal S ou of the first sensor 5A, and thus of the desired output data rate ODR E from the plurality of sensors 5, expressed as a number of periods of the clock signal CLK of the second sensor 5B and of the third sensor 5C, respectively.

[0107] FIG. 8 A possible implementation of the correction block 90 of the second sensor 5B and of the third sensor 5C is shown.

[0108] In detail, FIG. 8 the correction block 90 comprises an extraction counter 120 and a comparator 125 cascaded to the extraction counter 120.

[0109] The extraction counter 120 is configured to count the number of periods of the clock signal CLK of the respective sensor 5B, 5C FIG. 3) receive the phase correction signal PH C; receive the clock signal CLK from the corresponding clock 30; store the corresponding decimation count k; and provide a corresponding comparison signal C indicative of the decimation count k.

[0110] The comparator 125 is configured to receive the comparison signal C and the frequency selection signal F C, and to generate an output trigger signal OUT TRG upon occurrence of a trigger condition.

[0111] In this embodiment, the comparator 125 is further configured to provide a reset signal RST to the decimation counter 120 upon occurrence of the trigger condition.

[0112] FIG. 8 The operation of the correction block 90 is represented in the flowchart 149 of FIG. 9 Fig. 15.

[0113] In detail, in an initial step 150, e.g. at the start-up of the electronic device 1, the decimation counter 120 resets the value of the decimation count k to zero. Next, at each cycle of the clock signal CLK, e.g. at each rising or falling edge of the clock signal CLK, the counter 120 verifies (step 152) whether the phase correction signal PH C, the number of phase shift periods Nd, is not zero. If not (output N of step 152), the decimation counter 120 updates the decimation count k, increasing it by one unit (step 154). If yes (output Y of step 152), the decimation counter 120 updates the decimation count k, increasing it by one unit and by the value indicated by the phase correction signal PH C (step 156); k = k + 1 + Nd.

[0114] The comparator 125 then verifies the trigger condition (step 158) by comparing the value indicated by the comparison signal C (decimation count k) with the value indicated by the frequency selection signal F C. In particular, the trigger condition comprises verifying whether the decimation count k is greater than or equal to the number of frequency periods Nf indicated by the frequency selection signal F C.

[0115] If not (output N from step 158), the correction block 90 repeats step 152.

[0116] If yes (output Y of step 158), the comparator 125 generates the output trigger signal OUT TRG (step 160) and the reset signal RST (step 162).

[0117] In response to receiving the reset signal RST, the decimation counter 120 resets the decimation count k. In this embodiment, the decimation counter 120 resets the decimation count k to a value equal to the result of a modulo operation between the decimation count k and the number of frequency periods Nf: k = mod(k, Nf).

[0118] The correction block 90 then returns to step 152.

[0119] In practice, in use and with reference to FIG. 1 and FIG. 2 the user signal S U sent by the user of the electronic device 1 to the first sensor 5A E i.e. the desired output frequency f O of the samples of the corresponding output signal S ou .

[0120] In particular, the output trigger signal OUT_TRG of the first sensor 5A is generated by the corresponding configuration block 80 to trigger the decimator 55( FIG. 4 ) to provide the samples of the output signal S O at the output frequency f ou .

[0121] The reference block 58 of the first sensor 5A generates, in response to receiving the output trigger signal OUT_TRG, the external reference signal EXT_REF so that its rising (or falling) edge is generated with the same phase and frequency as the samples of the output signal S O of the first sensor 5A.

[0122] As discussed in detail with reference to FIG. 6-FIG. 9 the external reference signal EXT_REF provided by the first sensor 5A to the second and third sensors 5B, 5C is therefore used by the latter to set the frequency of the samples of the corresponding output signal S O .

[0123] Moreover, in response to receiving the output trigger signal OUT_TRG, the second and third sensors 5B, 5C each generate, through the corresponding reference block 58, a respective internal reference signal INT_REF. The rising (or falling) edge of the internal reference signal INT_REF of the second sensor 5B is generated with the same phase and frequency as the samples of the output signal S O of the second sensor 5B. Likewise, the rising (or falling) edge of the internal reference signal INT_REF of the third sensor 5C is generated with the same phase and frequency as the samples of the output signal S O of the third sensor 5C.

[0124] Therefore, since the second and third sensors 5B, 5C each compare the external reference signal EXT_REF with the respective internal reference signal INT_REF, as described in detail with reference to FIG. 6-FIG. 9 , they are also able to align in time the corresponding output signal S O with the output signal S O of the first sensor 5A, thereby compensating for possible phase shifts (e.g. FIG. 7 the phase difference ΔΦ).

[0125] Therefore, in addition to the initial transient period after the start of the electronic device 1, for example after an initial number of samples of the output signals S O of the plurality of sensors 5 (for example comprised between 1 and 100) is adjusted, the first, second and third sensors 5A, 5B, 5C generate samples of the respective output signals S O in a mutually synchronized manner. In particular, in one embodiment, the samples of the output signals S O of the plurality of sensors 5 are coherent with each other in time. They not only have the same output frequency f ou , but they are also aligned with each other in time (they are in phase).

[0126] This facilitates a number of advantages.

[0127] In fact, the fact that the sensors 5 provide the samples of the respective output signals S O to the memory 8 at the same time means that the control unit 7 of the electronic device 1 can be configured to read the data received from all the sensors 5, from the memory 8, immediately at the output frequency f ou . Therefore, the control unit 7 can allocate a shorter time for the data collection activity. This means that the electronic device 1 has a lower energy consumption with respect to the case in which the samples of the output signals S O are not synchronized, in which the control unit 7 should control the effective arrival of said samples periodically. Alternatively, the time saved by the control unit 7 in the data collection can be used for other activities, thus improving the performance and / or the operating efficiency of the electronic device 1.

[0128] Furthermore, in the electronic device 1, the plurality of sensors 5 is able to self-synchronize by implementing the transmission of only one signal between the sensors 5 (the external reference signal EXT_REF). Furthermore, used by the second and third sensors 5B, 5C, the external reference signal EXT_REF and the respective internal reference signal INT_REF are able to compensate for possible variations in the behavior of the clock 30, for example shifts and drifts due to variations in the conditions of use such as temperature.

[0129] In other words, the synchronization of the data at the output of the sensors 5 of the electronic device 1 can occur without the control unit 7 being configured to perform complex synchronization protocols which would involve significant hardware and software resources. Also for this reason, the electronic device 1 has an improved efficiency.

[0130] Additionally, the interface 10 can be a communication interface that is general purpose and known. This makes it possible to easily incorporate the high versatility of use of the plurality of sensors 5 in the electronic device 1.

[0131] At the same time, the output signals S of the sensors 5O The fact of being temporally coherent (frequency and phase aligned) enables the control unit 7 to properly use the data provided by the sensor 5 in subsequent processing operations, for example for subsequent combined processing of the data of the sensor 5 to perform advanced functions of the electronic device 1, for example multi-sensor data fusion processing, advanced compensation, batch processing in particular in FIFO (First In First Out / First Out) type buffers.

[0132] FIG. 10 A different embodiment of the present electronic device is shown here, indicated by 200.

[0133] The electronic device 200 has a general structure similar to that of the electronic device 1 of FIG. 1 ; therefore, the common elements have the same reference numerals and are briefly described.

[0134] In detail, the electronic device 200 comprises a control unit or circuit 7, a memory 8, an interface 10 and a plurality of sensors, indicated here by 205.

[0135] Furthermore, also here, the electronic device 200 comprises a power supply unit 14 and input and output peripheral devices 12.

[0136] The plurality of sensors 205 here also comprises a first sensor 205A, a second sensor 205B and a third sensor 205C. Fewer or additional sensors can be employed in various embodiments.

[0137] The first sensor 205A has the same structure as the first sensor 5A of FIG. 1 ; therefore it is not further shown and reference is made to the description of FIG. 2 .

[0138] In the present embodiment, the first sensor 205A generates a reference signal, referred to as first external reference signal REF1 and intended to be provided only to the second sensor 205B.

[0139] The second sensor 205B, whose block diagram is illustrated in FIG. 11 , here also comprises a detection unit 20, a signal conditioning stage 25 with ODR modification block 49, a clock 30 and a synchronization block 83 with measurement block 85 and correction block 90.

[0140] The synchronization block 83, in particular the measurement block 85, is here configured to receive at the input a respective internal reference signal INT_REF and the first external reference signal REF1 generated by the first sensor 205A as external reference signal.

[0141] In this embodiment, the second sensor 205B is configured to also generate a second external reference signal REF2 and provide it to the third sensor 205C. The second external reference signal REF2 is a periodic signal, such as a square wave signal, whose rising (or falling) edge coincides with the corresponding output signal S. O The sample alignment.

[0142] In detail, in this embodiment, the second external reference signal REF2 is generated by reference block 58 of ODR modification block 49 and is the same as the internal reference signal INT_REF.

[0143] The third sensor 205C has the same... FIG. 11 The second sensor 205B shown has the same structure and therefore will not be illustrated further. The third sensor 205C here also includes a detection unit 20, a signal conditioning stage 25 with an ODR modification block 49, a clock 30, and a synchronization block 83 with a measurement block 85 and a calibration block 90. ​​However, the synchronization block 83, and particularly the measurement block 85, receives a second external reference signal REF2 generated by the second sensor 205B as an external reference signal at its input, in addition to the corresponding internal reference signal INT_REF.

[0144] Therefore, in this embodiment, the second sensor 205B operates as a subordinate sensor relative to the first sensor 205A and as a reference sensor relative to the third sensor 205C.

[0145] In practice, the multiple sensors 205 of device 200 are configured to perform self-synchronization in a manner similar to that described above for electronic device 1. Therefore, electronic device 200 shares the aforementioned potential advantages of electronic device 1.

[0146] Finally, it is clear that modifications and variations may be made to the electronic devices 1, 200 and the corresponding synchronization methods described and illustrated herein without departing from the scope of this disclosure as defined in the appended claims.

[0147] For example, the various embodiments described can be combined to provide further solutions.

[0148] For example, in FIG. 1 In electronic device 1, the first sensor 5A can also provide the external reference signal EXT_REF to control unit 7 via dedicated connection 210. Dedicated connection 210 is provided by... FIG. 1 The dashed arrow in the diagram indicates this. Thus, control unit 7 can read the output signal S in response to receiving the external reference signal EXT_REF. O The sample.

[0149] Similarly, in FIG. 10In the electronic device 200, the first sensor 5A can send the first external reference signal REF1 to the control unit 7 by means of a dedicated connection, also indicated here by 210 and represented by the dashed arrow. In another embodiment, the second sensor 5B can send the second external reference signal REF2 to the control unit 7 by means of a respective dedicated connection. In this way, the control unit 7 can read the output signal S O samples of the output signal S

[0150] For example, the control unit 7 can be configured to read the samples of the output signal S ou at intervals corresponding to divisors of the output frequency f O , thus achieving energy savings.

[0151] For example, the sensors 5, 205 can have the same structure and be configured to operate as reference and slave sensors, respectively. In an initial configuration step of the electronic device 1, 200, the user of the electronic device 1, 200 can select which sensor to use as reference sensor by means of the interface 10 by sending a specific configuration instruction. In particular, the user can select the sensor with the lower operating frequency f o as reference sensor.

[0152] The sensors 5, 205 can be equal to each other to detect the same physical quantity in different conditions and / or positions, or different from each other to detect different physical quantities.

[0153] The sensors 5, 205 can also differ in terms of the respective clock 30. For example, the sensors 5, 205 can each have a different type of respective clock 30; in particular, they can each have a respective clock frequency f clk .

[0154] The sensors 5, 205 can each be formed in a respective die or in a plurality of dies of semiconductor material; moreover, a plurality of sensors can be formed in only one die. In particular, for each sensor 5, the detection unit 20 can be formed in a different die with respect to the other circuit components, with respect to the signal conditioning stage 25, the clock 30 and the synchronization blocks 80, 83. Alternatively, for each of a plurality of sensors 5, the components of analog type, such as the analog conditioning circuit 40, can be formed in a different die with respect to the components of digital type, such as the clock 30, the ODR modification block 49 and the synchronization blocks 80, 83.

[0155] As already illustrated, for each sensor 5, 205, the die can integrate a respective detection unit 20 and part of the signal conditioning stage 25, in particular the analog conditioning circuit 40, the analog-to-digital converter converter 43 and possibly the filter 46, the ODR modification block 49 being provided on a separate die.

[0156] In general, in any case, for each sensor 5, 205, the detection unit 20, the analog conditioning circuit 40 and the analog-to-digital converter 43 can be considered functionally to form a digital detector 48, represented by the dashed block in FIG. 2 、 FIG. 3 and FIG. 11 . In some applications, the filter 46 can also be considered to belong to the digital detector 48.

[0157] According to one embodiment, the configuration block 58 of the reference sensor (first sensor 5A of the electronic device 1 and first and second sensors 205A, 205B of the electronic device 200) can be configured so that the frequency of the respective external reference signal EXT_REF, REF1, REF2 is equal to a divisor of the SM order of the output sampling rate f ou of the reference sensor. In other words, the external reference signal is generated every SM samples of the respective output signal S O . The configuration block 83 of the slave sensor (second sensor 5B, 205B and third sensor 5C, 205C) is therefore configured so that the frequency selection signal F_C indicates the number of frequency periods Nf measured by the respective measurement block 85 divided by the order SM of the frequency divisor.

[0158] In practice, the digital output signal S O has a first frequency (output sampling rate f o u) and the reference or frequency indication signal EXT_REF, REF1, REF2 has a second frequency, wherein the second frequency is a divisor equal to the first frequency divided by the division order SM, and wherein the first number of periods (number of frequency periods Nf) indicates the number of periods of the clock signal CLK between two consecutive events of the frequency indication signal divided by the division order SM.

[0159] Finally, all or part of the operations performed by the signal conditioning stage 25 and the configuration blocks 80, 83 can be obtained via dedicated circuits using hardware solutions or via dedicated computer programs using software solutions.

[0160] An integrated sensor (5A-5C; 205A-205C) configured to receive a frequency indication signal (S U , EXT_REF; REF1, REF2) and to provide an output digital signal (S O), the integrated sensor can be summarized as comprising: a digital detector (48) configured to detect a physical quantity and generate a discrete detection signal (S D ) indicative of the detected physical quantity; an output timing regulation block (80, 83) configured for receiving a frequency indication signal (S U , EXT_REF; REF1, REF2) and a set of local reference signals (CLK, INT_REF) and generating a trigger signal (OUT_TRG) from the frequency indication signal and the set of local reference signals; and an output stage (49) configured for receiving the discrete detection signal and the trigger signal (OUT_TRG) and providing a digital output signal (S O ) and a lock signal (EXT_REF, INT_REF; REF1, REF2), wherein the output stage (49) is configured to provide a sample of the discrete detection signal in response to receiving the trigger signal, thereby generating the digital output signal, and to provide the lock signal in response to receiving the trigger signal, the lock signal being temporally aligned with the digital output signal.

[0161] The digital detector (48) can comprise: a detection unit (20) configured to detect a physical quantity and generate an analog signal (S A ) indicative of the detected physical quantity, and an analog-to-digital conversion stage (40, 43, 46) configured for receiving the analog signal (S A ) and discretizing it and generating the discrete detection signal (S D ).

[0162] The integrated sensor can comprise a clock (30) configured to generate a clock signal (CLK) of a periodic type having a period, wherein the set of local reference signals can comprise the lock signal (INT_REF) and the clock signal, and the output timing adjustment block (83) can comprise at least one counter (100, 120) configured for counting the periods of the clock signal; a frequency measurement circuit (105B, 105C, 110B) configured to count a first number of periods (Nf) of the clock signal (CLK) between two consecutive events of the frequency indication signal and to generate an internal frequency signal (F_C) indicative of the first number of periods, the first number of periods measuring a frequency (At) of the frequency indication signal (EXT_REF; REF1, REF2); a phase measurement circuit (105A, 110A) configured to count a second number of periods (Nd) of the clock signal (CLK) between an event of the frequency indication signal (EXT_REF; REF1, REF2) and an event of the lock signal (INT_REF) and to generate an internal phase signal (PH_C) indicative of the second number of periods, the second number of periods measuring a time offset (ΔΦ) between the frequency indication signal (EXT_REF; REF1, REF2) and the lock signal (INT_REF); and a comparison circuit (90, 120, 125) configured to generate a trigger signal (OUT_TRG) after a third number of periods of the clock signal, the third number of periods being a function of the first number of periods and of the second number of periods.

[0163] The comparison circuit (90, 125) can comprise a respective counter (120) configured to store a count value (k) and to increase the count value by an increment at each period of the clock signal, the increment being a function of the second number of periods (Nd), the comparison circuit being configured to generate the trigger signal (OUT_TRG) if the count value is greater than or equal to the first number of periods (Nf).

[0164] The comparison circuit (90) can be configured to perform a modulo operation between the count value (k) and the first number of periods if the count value is greater than or equal to the first number of periods, to generate a modulo value and to reset the count value (k) to the modulo value.

[0165] The output stage (49) can comprise an interpolator (52) configured to up-sample the discrete detection signal (S D ) so as to generate an interpolated signal (S D,int ), and a decimator (55) configured to down-sample the interpolated signal so as to generate the digital output signal in response to receiving the trigger signal.

[0166] The decimator (55) can comprise a filtering stage (65), a down-sampling stage (68) and a gain stage (71); the filtering stage (65) comprises a low-pass filter having a respective cut-off frequency (fc) and is configured to receive the interpolated signal (S D , int) and generate a filtered signal (F); the down-sampling stage is configured to down-sample the filtered signal in response to receiving a trigger signal (OUT_TRG) and generate a down-sampled signal (DS) having a d.c. component; and the gain stage (71) is configured to amplify or attenuate the d.c. component of the down-sampled signal by a gain value (G).

[0167] The cut-off frequency of the filtering stage (65) and the gain value of the gain stage (71) can be a function of the frequency indication signal (EXT_REF, F_C).

[0168] The integrated sensor can be a MEMS sensor.

[0169] The detection unit (20) can comprise a mechanical oscillator (37) subject to oscillation and a sensing element (35), the mechanical oscillator being configured to be actuated at an operating frequency (f o ) and to oscillate at an oscillation frequency, the oscillation frequency being related to the operating frequency and to the physical quantity to be detected, and the sensing element being configured to convert the oscillation of the mechanical oscillator into an analog signal (S A ).

[0170] The electronic device can be summarized as comprising a plurality of integrated sensors, wherein the plurality of integrated sensors can comprise a reference sensor (5A; 205A, 205B) and a slave sensor (5B, 5C; 205B, 205C) coupled to each other, the reference sensor being configured to provide a respective lock signal (EXT_REF; REF1, REF2) to the slave sensor, wherein the frequency indication signal of the slave sensor is the lock signal of the reference sensor.

[0171] The device can comprise a control unit (7) coupled to the plurality of integrated sensors, the integrated sensors being configured to each send a respective digital output signal (S O ) to the control unit.

[0172] The reference sensor can be configured to send the respective lock signal to the control unit, the control unit being configured to read the digital output signals received from the plurality of integrated sensors in response to receiving the lock signal.

[0173] A method for synchronizing digital output signals (S O) of samples of a sample of a physical quantity, the plurality of integrated sensors comprising a reference sensor (5A; 205A, 205B) and a slave sensor (5B, 5C; 205B, 205C), the integrated sensors of the plurality of integrated sensors each comprising an output timing conditioning block (80, 83) and an output stage (49), wherein the output stage receives a discrete detection signal (S D ) related to the physical quantity to be detected, the method can be summarized as comprising: receiving, by the output timing conditioning block (80) of the reference sensor, a first frequency indication signal (S U ) and a first set of local reference signals (CLK); providing, by the output conditioning block (83) of the reference sensor, a first trigger signal (OUT_TRG) as a function of the first frequency indication signal and the first set of local reference signals (CLK); providing, by the output stage of the reference sensor, in response to receiving the first trigger signal (OUT_TRG), a sample of the corresponding discrete detection signal, thereby generating a corresponding digital output signal; providing, by the output stage of the reference sensor, in response to receiving the first trigger signal, a first locked signal (EXT_REF) in time alignment with the corresponding digital output signal; receiving, by the output conditioning block (83) of the slave sensor, the first locked signal; providing, by the output conditioning block of the slave sensor, a second trigger signal (OUT_TRG) as a function of the first locked signal and a second set of local reference signals (CLK, INT_REF); providing, by the output stage (49) of the slave sensor, in response to receiving the second trigger signal (OUT_TRG), a sample of the corresponding discrete detection signal, thereby generating a corresponding digital output signal; and providing, by the output stage (49) of the slave sensor, in response to receiving the second trigger signal (OUT_TRG), a second locked signal (INT_REF; REF2) in time alignment with the corresponding digital output signal.

[0174] The output timing adjustment block of the slave sensor, the second trigger signal can comprise: counting a number of periods of a clock signal (CLK) of the slave sensor; counting a first number of periods (Nf) of the clock signal (CLK) between two successive events of the first locked signal (EXT_REF; REF1, REF2); generating an internal frequency signal (F_C) indicative of the first number of periods, the first number of periods measuring a frequency (At) of the first locked signal (EXT_REF; REF1, REF2); counting a second number of periods (Nd) of the clock signal (CLK) between an event of the first locked signal (EXT_REF; REF1, REF2) and an event of the second locked signal (INT_REF); generating an internal phase signal (PH_C) indicative of the second number of periods, the second number of periods measuring a time offset (APhi) between the first locked signal (EXT_REF; REF1, REF2) and the second locked signal (INT_REF); and generating the second trigger signal (OUT_TRG) after a third number of periods of the clock signal, the third number of periods being a function of the first number of periods and the second number of periods.

[0175] The digital output signal of the reference sensor can have a first frequency (fou), and the first locked signal (EXT_REF; REF1, REF2) can have a second frequency, the second frequency being a divisor of the first frequency equal to a division order (SM), and counting the first number of periods of the clock signal can comprise dividing the first number of periods (Nf) by the division order.

[0176] Generating the second trigger signal (OUT_TRG) after the third number of periods can comprise: storing a count value (k) by the output timing adjustment block of the slave sensor; increasing the count value by an increment at each period of the clock signal, the increment being a function of the second number of periods (Nd); verifying whether the count value is greater than or equal to the first number of periods (Nf); and generating the second trigger signal (OUT_TRG) if the count value is greater than or equal to the first number of periods.

[0177] The method can comprise performing a modulo operation between the count value (k) and the first number of periods (Nf), generating a modulo value, and resetting the count value (k) to the modulo value if the count value is greater than or equal to the first number of periods.

[0178] In one embodiment, the sensor includes a detection circuitry and a control circuitry coupled with the detection circuitry. The detection circuitry generates a detection signal indicative of a detected physical quantity. The control circuitry, in operation, receives the detection signal and a frequency indication signal, and generates a trigger signal based on the frequency indication signal and a set of local reference signals. The sensor generates a digital output signal and a lock signal based on the trigger signal and the detection signal. Generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The lock signal is aligned in time with the digital output signal. In one embodiment, the detection circuitry includes a detector, in operation, that detects the physical quantity and generates an analog signal indicative of the detected physical quantity, and an analog-to-digital (A / D) converter coupled with the detector, in operation, that generates the detection signal based on the analog signal indicative of the detected physical quantity. In one embodiment, the sensor includes a clock, in operation, that generates a periodic clock signal, wherein the set of local reference signals includes the lock signal and the periodic clock signal, and the control circuitry, in operation, generates a frequency signal indicative of a frequency of the frequency indication signal based on the periodic clock signal and the frequency indication signal, generates a phase signal indicative of a phase shift between the frequency indication signal and the lock signal, and generates the trigger signal based on the generated frequency signal and the generated phase signal. In one embodiment, the control circuitry includes a counter, in operation, that generates a count value based on the periodic clock signal and the generated phase signal, and a comparator, in operation, that compares the count value with the generated frequency signal to generate the trigger signal. In one embodiment, the control circuitry, in operation, performs a modulo operation between the count value and the generated frequency signal to generate a modulo value, and resets the count value to the modulo value in response to the count value being greater than or equal to the generated frequency signal. In one embodiment, the control circuitry includes an interpolator, in operation, that upsamples the detection signal to generate an interpolated signal, and a decimator coupled with the interpolator, wherein the decimator, in operation, downsamples the interpolated signal based on the trigger signal to generate the digital output signal. In one embodiment, the decimator includes a low-pass filter, in operation, that filters the interpolated signal to generate a filtered signal, a downsampler, in operation, that downsamples the filtered signal to generate a downsampled signal, and a gain circuit, in operation, that applies a gain to a direct current component of the downsampled signal to generate the digital output signal. In one embodiment, a cutoff frequency of the low-pass filter and the gain are based on the frequency indication signal. In one embodiment, the sensor is a MEMS sensor. In one embodiment, the detector includes a mechanical oscillator, in operation, that oscillates at an oscillation frequency based on the detected physical quantity, and a sense element coupled with the mechanical oscillator, wherein the sense element, in operation, generates the analog signal based on the oscillation frequency of the mechanical oscillator.

[0179] In one embodiment, a system includes a plurality of sensors, each sensor including: a detection circuit arrangement that, in operation, generates a detection signal indicative of a detected physical quantity; and a processing circuit arrangement coupled with the detection circuit arrangement, wherein the processing circuit arrangement, in operation, receives the detection signal; receives a frequency indication signal; generates a trigger signal based on the frequency indication signal and a set of local reference signals; generates a digital output signal and a lock signal based on the trigger signal and the detection signal, wherein generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal and the lock signal is aligned in time with the digital output signal, wherein the plurality of sensors includes a reference sensor and a slave sensor coupled with the reference sensor; the lock signal of the reference sensor is the received frequency indication signal of the slave sensor. In one embodiment, a system includes: a control circuit arrangement coupled with the plurality of sensors, wherein the sensors, in operation, provide respective digital output signals to the control circuit arrangement. In one embodiment, the control circuit arrangement, in operation: receives the lock signal of the reference sensor; and in response to receiving the lock signal of the reference sensor, reads the digital output signals of the plurality of sensors.

[0180] In one embodiment, the method includes synchronizing samples of digital output signals of a plurality of sensors, the plurality of sensors including a reference sensor and a slave sensor, the synchronizing including receiving, by the reference sensor, a first frequency indication signal; generating, by the reference sensor, a first trigger signal from the first frequency indication signal and a first set of local reference signals; generating, by the reference sensor, a sample of the digital output signal of the reference sensor and a first lock signal based on the first trigger signal, the first lock signal being aligned in time with the digital output signal of the reference sensor; receiving, by the slave sensor, the first lock signal; generating, by the slave sensor, a second trigger signal from the first lock signal and a second set of local reference signals; and generating, by the slave sensor, a sample of the digital output signal of the slave sensor and a second lock signal based on the second trigger signal, the second lock signal being aligned in time with the digital output signal of the slave sensor. In one embodiment, generating the second trigger signal includes counting cycles of a clock signal of the slave sensor; counting a first number of cycles of the clock signal between two consecutive events of the first lock signal; generating an internal frequency signal indicative of the first number of cycles, the first number of cycles being indicative of a frequency of the first lock signal; counting a second number of cycles of the clock signal between an event of the first lock signal and an event of the second lock signal; generating an internal phase signal indicative of the second number of cycles, the second number of cycles being indicative of a time offset between the first lock signal and the second lock signal; and generating the second trigger signal after a third number of cycles of the clock signal, the third number of cycles being a function of the first number of cycles and the second number of cycles. In one embodiment, the digital output signal of the reference sensor has a first frequency and the first lock signal has a second frequency, the second frequency being a divisor of the first frequency equal to a division order, and wherein counting the first number of cycles of the clock signal includes dividing the first number of cycles by the division order. In one embodiment, generating the second trigger signal after the third number of cycles includes the slave sensor storing a count value; incrementing the count value by an increment at each cycle of the clock signal, the increment being a function of the second number of cycles; determining whether the count value is greater than or equal to the first number of cycles; and generating the second trigger signal if the count value is greater than or equal to the first number of cycles. In one embodiment, the method includes performing a modulo operation between the count value and the first number of cycles if the count value is greater than or equal to the first number of cycles, generating a modulo value, and resetting the count value to the modulo value.

[0181] In one embodiment, the content of the non-transitory computer readable medium configures the processing circuitry to synchronize samples of digital output signals of a plurality of sensors, the plurality of sensors including a reference sensor and a slave sensor, the synchronizing including: receiving, by the reference sensor, a first frequency indication signal; generating, by the reference sensor, a first trigger signal from the first frequency indication signal and a first set of local reference signals; generating, by the reference sensor, a sample of the digital output signal of the reference sensor and a first lock signal based on the first trigger signal, the first lock signal being time-aligned with the digital output signal of the reference sensor; receiving, by the slave sensor, the first lock signal; generating, by the slave sensor, a second trigger signal from the first lock signal and a second set of local reference signals; generating, by the slave sensor, a sample of the digital output signal of the slave sensor and a second lock signal based on the second trigger signal, the second lock signal being time-aligned with the digital output signal of the slave sensor. In one embodiment, the content includes instructions for execution by the processing circuitry.

[0182] Some embodiments can take the form of or include a computer program product. For example, according to one embodiment, a computer readable medium is provided that includes a computer program adapted to perform one or more of the above-described methods or functions. The medium can be a physical storage medium such as, for example, a Read Only Memory (ROM) chip, or a disk such as a Digital Versatile Disk (DVD-ROM), a Compact Disk (CD-ROM), a hard disk, a memory such as would be read by an appropriate drive or through an appropriate connection, including encoded in one or more barcodes or other related code stored on and readable by a suitable reader device, a network, or a portable media article.

[0183] Further, in some embodiments, some or all of the methods and / or functionality can be implemented or provided in other manners, such as at least partially in firmware and / or hardware, including, but not limited to, one or more application-specific integrated circuits (ASICs), digital signal processors, etc., standard integrated circuits, controller(s), such as through an appropriate controller, including a microcontroller and / or embedded controller, field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., and / or other combinations of hardware and / or firmware.

[0184] The various embodiments described above can be combined to provide further embodiments. Aspects of an embodiment can be modified, if necessary, to employ concepts of various patents, applications, and publications to provide yet further embodiments.

[0185] These and other changes can be made to the embodiments in light of the above detailed description. In general, the terms used in the appended claims should not be construed to limit the claims of the application to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims should not be limited by the disclosure.

Claims

1. A system comprising: a digital signal processing circuitry that, in operation, processes a digital signal; and a first sensor coupled to the digital signal processing circuitry, the first sensor comprising: a detection circuitry that, in operation, generates a detection signal indicative of a detected physical quantity; and a control circuitry coupled to the detection circuitry, wherein the control circuitry, in operation: receives the detection signal; receives a frequency indication signal; generates a trigger signal based on the frequency indication signal and a set of local reference signals; and generates a digital output signal and a lock signal based on the trigger signal and the detection signal, wherein generating the digital output signal comprises outputting a sample of the digital output signal based on the trigger signal, and the lock signal is aligned in time with the digital output signal, wherein the detection circuitry comprises: a detector that, in operation, detects the physical quantity and generates an analog signal indicative of the detected physical quantity; and an analog-to-digital (A / D) converter coupled to the detector that, in operation, generates the detection signal based on the analog signal indicative of the detected physical quantity; and the control circuitry comprises: an interpolator that, in operation, upsamples the detection signal, thereby generating an interpolated signal; and a decimator coupled to the interpolator, wherein the decimator, in operation, downsamples the interpolated signal based on the trigger signal, thereby generating the digital output signal.

2. The system of claim 1, wherein the decimator comprises: a low-pass filter that, in operation, filters the interpolated signal, thereby generating a filtered signal; a downsampler that, in operation, downsamples the filtered signal, thereby generating a downsampled signal; and a gain circuitry that, in operation, applies a gain to a direct current component of the downsampled signal, thereby generating the digital output signal.

3. The system of claim 2, wherein a cutoff frequency of the low-pass filter and the gain are based on the frequency indication signal.

4. The system of claim 1, wherein the first sensor is a MEMS sensor.

5. The system of claim 1, comprising: a second sensor coupled to the digital signal processing circuitry and the first sensor, wherein, in operation, the first sensor is a reference sensor and the second sensor is a slave sensor; and the lock signal generated by the first sensor is provided to the second sensor as a frequency indication signal.

6. The system of claim 1, comprising: a set of slave sensors coupled to the digital signal processing circuitry and the first sensor, wherein the digital signal processing circuitry, in operation: receives the lock signal of the first sensor; and in response to the receipt of the lock signal of the first sensor, reads digital output signals of the set of slave sensors.

7. A method comprising: ​ ​ generating an analog detection signal indicative of a detected physical quantity; converting the analog detection signal to a digital detection signal indicative of the detected physical quantity; generating a trigger signal based on a frequency indication signal and a set of local reference signals; generating an interpolated signal by upsampling the digital detection signal; generating a digital output signal by decimating the interpolated signal; generating a lock signal based on the trigger signal and the digital detection signal, wherein the generation of the digital output signal comprises outputting a sample of the digital output signal based on the trigger signal, and the lock signal is time-aligned with the digital output signal; and synchronizing samples of digital output signals of a plurality of sensors based on the lock signal.

8. The method of claim 7, wherein the decimating comprises: low-pass filtering the interpolated signal, thereby generating a filtered signal; down-sampling the filtered signal, thereby generating a down-sampled signal; and applying a gain to a direct current component of the down-sampled signal, thereby generating the digital output signal.

9. The method of claim 8, wherein a cut-off frequency of the low-pass filtering and the gain are based on the frequency indication signal.

10. The method of claim 7, wherein the plurality of sensors comprises a reference sensor and a slave sensor, and the method comprises: generating the lock signal using the reference sensor; and providing the lock signal generated by the reference sensor as a frequency indication signal to the slave sensor.

11. The method of claim 7, wherein the plurality of sensors comprises a reference sensor and a set of slave sensors, and the method comprises: generating the lock signal using the reference sensor; and reading digital output signals of the set of slave sensors in response to receipt of the lock signal of the reference sensor.

12. A non-transitory computer readable medium having content to configure a sensor system to synchronize samples of digital output signals of a plurality of sensors of the sensor system, the plurality of sensors comprising a reference sensor and a set of slave sensors, the synchronization comprising: generating an analog detection signal indicative of a detected physical quantity; converting the analog detection signal to a digital detection signal indicative of the detected physical quantity; generating a trigger signal based on a frequency indication signal and a set of local reference signals; generating an interpolated signal by upsampling the digital detection signal; generating a digital output signal by decimating the interpolated signal; generating a lock signal based on the trigger signal and the digital detection signal, wherein the generation of the digital output signal comprises outputting a sample of the digital output signal based on the trigger signal, and the lock signal is time-aligned with the digital output signal; and synchronizing samples of digital output signals of a plurality of sensors based on the lock signal.

13. The non-transitory computer readable medium of claim 12, wherein the decimating comprises: low-pass filtering the interpolated signal, thereby generating a filtered signal; down-sampling the filtered signal, thereby generating a down-sampled signal; and applying a gain to a direct current component of the down-sampled signal, thereby generating the digital output signal. down-sampling the filtered signal, thereby generating a down-sampled signal; and applying a gain to a direct current component of the down-sampled signal, thereby generating the digital output signal.

14. The non-transitory computer readable medium of claim 13, wherein a cut-off frequency of the low pass filtering and the gain are based on the frequency indication signal.

15. The non-transitory computer readable medium of claim 12, wherein the plurality of sensors includes a reference sensor and a slave sensor, and the synchronizing includes: generating the lock signal using the reference sensor; and providing the lock signal generated by the reference sensor as a frequency indication signal to the slave sensor.

16. The non-transitory computer readable medium of claim 12, wherein the content includes instructions that are, in operation, executed by processing circuitry of the sensor system.

17. A sensing device, comprising: a first sensor of a set of sensors coupled together, wherein the first sensor, in operation: generates a first detection signal indicative of a first detected physical quantity; receives a first frequency indication signal; generates a first trigger signal from the first frequency indication signal; and generates a first digital output signal and a first lock signal based on the first trigger signal and the first detection signal, the first lock signal being time-aligned with the first digital output signal; a second sensor of the set of sensors, wherein the second sensor, in operation: generates a second detection signal indicative of a second detected physical quantity; receives the first lock signal from the first sensor; generates a second trigger signal from the first lock signal; and generates a second digital output signal and a second lock signal based on the second trigger signal and the second detection signal, the second lock signal being time-aligned with the second digital output signal; and a third sensor of the set of sensors, wherein the third sensor, in operation: generates a third detection signal indicative of a third detected physical quantity; receives the second lock signal from the second sensor; generates a third trigger signal from the second lock signal; and generates a third digital output signal based on the third trigger signal and the third detection signal.

18. The sensing device of claim 17, comprising: a digital signal processing circuitry coupled to the set of sensors, wherein the digital signal processing circuitry, in operation: receives the first lock signal and the first digital output signal from the first sensor; and processes the first digital output signal based on the first lock signal.

19. The sensing device of claim 18, wherein the digital signal processing circuitry, in operation: receives the second lock signal and the second digital output signal from the second sensor; and processes the second digital output signal based on the second lock signal.

20. The sensing device of claim 18, wherein the digital signal processing circuitry, in operation: Select a sensor from the set of sensors; and Configure the selected sensor as the first sensor.

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