A method, apparatus, terminal device, storage medium, and program product for detecting the operation of a chip.

Abstract

This application provides a method, apparatus, terminal device, storage medium, and program product for chip operation detection. The method includes: acquiring real-time data streams of the data path according to a preset cycle during chip operation; invoking a preset comparison method to compare the real-time data streams with preset abnormal data streams to determine whether the real-time data streams and abnormal data streams are consistent; the abnormal data streams are data streams written into the monitoring unit after chip production and confirmed to cause errors; if consistent, determining a target avoidance method corresponding to the real-time data streams and invoking the target avoidance method to perform avoidance operations on the real-time data streams. This method can prevent errors caused by the chip continuing to run the real-time data streams and ensure the normal execution of the real-time data stream functions, thereby effectively detecting and avoiding errors that may occur during chip operation even after chip production, ensuring the safety and reliability of chip operation.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip operation testing method, apparatus, terminal equipment, storage medium, and program product. Background Technology

[0002] With the rapid development of integrated circuit design and manufacturing technologies, chip size and system complexity continue to increase, leading to a technical demand for full-function verification of ultra-large-scale logic structures such as CPU cores and high-speed system buses. Such verification technologies need to possess high coverage, high accuracy, and efficient traversal of massive state spaces to ensure that as many design defects as possible are eliminated before tape-out.

[0003] In traditional technologies, chip design companies primarily rely on pre-tapeout verification methods such as simulation testing, formal verification, and random constraint testing. These methods aim to identify and correct design errors using limited test cases and coverage models. However, current verification methods are limited by the explosive growth of state combinations and the practical constraints of simulation resources, making it difficult to fully traverse complex interaction scenarios, such as specific instruction sequences with superimposed interrupts or multi-master bus contention. Undiscovered systemic functional errors may remain after chip production; if exposed in real-world applications, these errors will lead to chip malfunction and significant economic and time losses.

[0004] Therefore, how to effectively detect and avoid errors that may occur during chip operation after chip production, and maintain normal function execution, is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a method, apparatus, terminal device, computer-readable storage medium, and computer program product for detecting chip operation, which can effectively detect and avoid errors that may occur during chip operation even after chip production.

[0006] Firstly, this application provides a method for detecting the operation of a chip. Applied to a monitoring unit disposed on the data path of the chip, the method includes:

[0007] During chip operation, the real-time data stream of the data path is acquired in each clock cycle;

[0008] A preset comparison method is invoked to compare the real-time data stream with a preset abnormal data stream to determine whether the real-time data stream and the abnormal data stream are consistent; the abnormal data stream is a data stream that has been written into the monitoring unit after the chip is manufactured and has been confirmed to cause an error.

[0009] If they match, the target avoidance method corresponding to the real-time data stream is determined, and the target avoidance method is invoked to perform an avoidance operation on the real-time data stream.

[0010] In one embodiment, if the real-time data stream is a real-time operation stream; and the abnormal operation stream is a preset operation stream in which the operation steps have an incorrect sequential dependency; determining the target avoidance method corresponding to the real-time data stream and invoking the target avoidance method to perform an avoidance operation on the real-time data stream includes:

[0011] Determine the target avoidance method corresponding to the real-time operation flow; the target avoidance method is to read a preset invalid address;

[0012] The target evasion method is executed at a designated location in the real-time operation stream to perform an evasion operation on the real-time operation stream.

[0013] In one embodiment, if the real-time data stream is a real-time operation stream; and the abnormal operation stream is a preset operation stream where each operation step depends on an access address error; determining the target avoidance method corresponding to the real-time data stream and invoking the target avoidance method to perform an avoidance operation on the real-time data stream includes:

[0014] Determine the target avoidance method corresponding to the real-time operation flow; the target avoidance method is address mapping;

[0015] According to the preset mapping relationship, the access address in the operation steps is mapped to a replacement region in order to perform an evasion operation on the real-time operation stream.

[0016] In one embodiment, if the real-time data stream is a real-time command stream; determining the target evasion method corresponding to the real-time data stream and invoking the target evasion method to perform an evasion operation on the real-time data stream includes:

[0017] Determine the target avoidance method corresponding to the real-time instruction stream; the target avoidance method is to insert a non-functional instruction.

[0018] Non-functional instructions are inserted into the real-time instruction stream to perform an evasion operation on the real-time instruction stream.

[0019] In one embodiment, if the real-time data stream is a streaming media pixel sequence or an artificial intelligence network parameter sequence; the step of determining the target avoidance method corresponding to the real-time data stream and invoking the target avoidance method to perform an avoidance operation on the real-time data stream includes:

[0020] Determine the target avoidance method corresponding to the streaming media pixel sequence or the artificial intelligence network parameter sequence; the target avoidance method is to insert a null operation;

[0021] Insert a null operation into the streaming media pixel sequence or the artificial intelligence network parameter sequence to perform an evasion operation on the streaming media pixel sequence or the artificial intelligence network parameter sequence.

[0022] In one embodiment, the monitoring unit is pre-configured with multiple independently configurable comparison logic units; each comparison logic unit is configured with a corresponding comparison method.

[0023] The step of invoking a preset comparison method to determine whether the real-time data stream and the abnormal data stream are consistent includes:

[0024] The corresponding comparison logic unit is activated based on the abnormal data stream;

[0025] The preset comparison method set in the enabled comparison logic unit is invoked to determine whether the real-time data stream and the abnormal data stream are consistent.

[0026] In one embodiment, the invocation of a preset comparison method set in the enabled comparison logic unit to determine whether the real-time data stream and the abnormal data stream are consistent includes:

[0027] The preset comparison method set in the enabled comparison logic unit is invoked to determine whether the real-time data stream and the abnormal data stream are consistent in parallel and / or in series.

[0028] Secondly, this application also provides a chip operation detection device. Applied to a monitoring unit disposed on the data path of the chip, the device includes:

[0029] The acquisition module is used to acquire the real-time data stream of the data path at each clock cycle during the operation of the chip;

[0030] The comparison module is used to call a preset comparison method to compare the real-time data stream with a preset abnormal data stream to determine whether the real-time data stream and the abnormal data stream are consistent; the abnormal data stream is a data stream that has been written into the monitoring unit after the chip is manufactured and has been confirmed to cause an error.

[0031] An execution module is used to determine the target avoidance method corresponding to the real-time data stream if the data stream is consistent, and to call the target avoidance method to perform an avoidance operation on the real-time data stream.

[0032] Thirdly, this application also provides a terminal device. The terminal device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described above.

[0033] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described above.

[0034] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the method described above.

[0035] This application provides a chip program detection method applied to a monitoring unit located on the chip's data path. In this method, during chip operation, if a preset comparison method determines that the chip's real-time data stream matches an abnormal data stream (i.e., it's determined that an erroneous real-time data stream exists within the real-time data stream, and continued chip operation according to this stream would result in an error), a target avoidance method corresponding to the real-time data stream is determined, and this method is invoked to perform an avoidance operation on the real-time data stream, preventing the chip from continuing to run the real-time data stream and causing an error. Furthermore, the avoidance operation only changes the combined behavior of the erroneous sequence, thus ensuring that the result of the sequence's functional execution remains unchanged, guaranteeing the normal execution of the real-time data stream. Therefore, this method can effectively detect and avoid errors that may occur during chip operation even after chip manufacturing, ensuring the safety and reliability of chip operation.

[0036] It is understood that the chip operation detection device, terminal device, computer-readable storage medium and computer program product provided in the embodiments of this application have the same beneficial effects as the chip operation detection method described above, and will not be repeated here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0038] Figure 1 A flowchart illustrating a chip operation detection method provided in an embodiment of this application;

[0039] Figure 2 A schematic diagram illustrating a method for monitoring real-time operation flow provided in an embodiment of this application;

[0040] Figure 3 A schematic diagram illustrating a method for monitoring the execution of a real-time instruction stream, provided in an embodiment of this application;

[0041] Figure 4 A schematic diagram of the structure of a chip operation detection device provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Detailed Implementation

[0043] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0044] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0045] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0046] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0047] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0048] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" means "two or more."

[0049] This application provides a chip operation detection method, which is applied to a monitoring unit located on the chip's data path.

[0050] It should be noted that the chip in this embodiment refers to a complex integrated circuit, such as a CPU or a System-on-a-Chip (SoC). The monitoring unit is a hardware structure pre-embedded within the chip during the design phase, including a configuration register and a comparator; abnormal data streams are written to the configuration register, and the comparator compares the data streams. The monitoring unit can specifically be a logic circuit, a state machine, etc.

[0051] In this context, the data path refers to the critical path for the flow of instructions and data within the chip. In a processor, the monitoring unit can be located in the instruction decoding and instruction dispatch stages of the chip's instruction pipeline; these two pipeline stages can detect and determine the order of instruction execution. In a bus system, the monitoring unit can also be located at the master port of a aggregation node; an important slave port, such as a DDR controller; or the bus arbiter that aggregates all transmissions; this embodiment does not limit the specific location of the monitoring unit.

[0052] Figure 1 The flowchart illustrates a chip operation detection method provided in this application embodiment. For ease of explanation, only the parts relevant to this embodiment are shown. The method provided in this embodiment includes the following steps:

[0053] S100: During chip operation, acquire the real-time data stream of the data path according to each clock cycle.

[0054] This step involves post-processing monitoring performed after the chip has been manufactured and is in its actual working state (dynamic operation). Chip manufacturing, or chip tape-out, specifically refers to the conversion of the designed chip circuit pattern into a physical structure on the actual silicon wafer. Specifically, when the chip is in its actual working state, the monitoring unit synchronizes with the chip clock and collects real-time data streams flowing through the data path at each clock cycle. In this embodiment, the clock cycle can be the instant the chip's clock signal transitions from low (0) to high (1), or the instant the clock signal transitions from high (1) to low (0).

[0055] Real-time data stream refers to the information being transmitted on the data path; on the instruction pipeline, real-time data stream is one or more instructions being processed, i.e., real-time instruction stream; on the bus system, real-time data stream is the bus transmission information that is taking place, i.e., real-time operation stream.

[0056] S200: Call the preset comparison method to compare the real-time data stream with the preset abnormal data stream to determine whether the real-time data stream and the abnormal data stream are consistent; the abnormal data stream is the data stream that is written into the monitoring unit after chip production and is confirmed to cause an error.

[0057] Errors include producing incorrect calculation results, causing system crashes or freezes, or other incorrect results.

[0058] In practical applications, after chip production, when an erroneous data stream is discovered later, the data stream that is confirmed to be erroneous is written into the monitoring unit through the configuration register, thus obtaining the abnormal data stream.

[0059] The preset comparison methods include: determining read / write order by monitoring the order of bus operations; determining address by matching specific access addresses or address ranges; determining sideband signals by monitoring control signals accompanying the main operation, such as interrupt signals, cache maintenance operations, and security attributes; and determining instruction type and sequence by matching specific instruction codes and their order.

[0060] It should be noted that multiple comparison logic units that can be independently enabled or disabled are pre-set in the monitoring unit, and the corresponding comparison method is written in each comparison logic unit; therefore, each comparison method can be used independently or in combination.

[0061] In practical applications, the comparison method is pre-written into the monitoring unit through the configuration register. After acquiring the real-time data stream of the preset period, the preset comparison method is called to compare the real-time data stream with the preset abnormal data stream to determine whether the real-time data stream and the abnormal data stream are consistent.

[0062] Specifically, the consistency between real-time and abnormal data streams can be determined by checking whether the read and / or write order of the real-time data stream and the abnormal data stream are consistent, whether the access address or address range of the real-time data stream and the abnormal data stream are consistent, and whether the sideband signals of the real-time data stream and the abnormal data stream are consistent.

[0063] If they are inconsistent, it means that the real-time data stream is not the pre-determined abnormal data stream. That is, the chip will not make a mistake if it continues to run according to the real-time data stream, so no additional operation is required. If they are consistent, then S300 is executed.

[0064] S300: Determine the target evasion method corresponding to the real-time data stream, and call the target evasion method to perform evasion operation on the real-time data stream.

[0065] In this context, avoidance methods refer to interrupting, altering, or replacing the original operating steps to prevent errors from occurring. Avoidance methods include inserting no-ops (NOPs), inserting invalid bus accesses, and performing address remapping—operations that do not affect functional correctness.

[0066] In this embodiment, after determining that the real-time data stream and the abnormal data stream are consistent, the corresponding target avoidance method is first determined based on the real-time data stream, and then the target avoidance method is called to perform an avoidance operation on the real-time data stream.

[0067] In practical applications, after determining that the real-time data stream and the abnormal data stream are consistent, a corresponding prompt message can be generated and sent to the host computer to prompt the host computer to perform fault checks and handling based on the prompt message; the prompt message can be an interrupt message.

[0068] In practical applications, corresponding monitoring units can be set at multiple locations on the chip, which means multiple detections are performed on the real-time data stream, thereby monitoring different abnormal data streams separately.

[0069] This application provides a chip program detection method applied to a monitoring unit located on the chip's data path. In this method, during chip operation, if a preset comparison method determines that the chip's real-time data stream matches an abnormal data stream (i.e., it's determined that an error-prone real-time data stream exists within the real-time data stream, and continued chip operation according to this stream would result in an error), a target avoidance method corresponding to the real-time data stream is determined, and this method is invoked to perform an avoidance operation on the real-time data stream, preventing the chip from continuing to run the real-time data stream and causing an error. Furthermore, the avoidance operation only changes the combined behavior of the erroneous sequence, thus ensuring that the result of the sequence's functional execution remains unchanged, guaranteeing the normal execution of the real-time data stream. Therefore, this method can effectively detect and avoid errors that may occur during chip operation even after chip manufacturing, ensuring the safety and reliability of chip operation.

[0070] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, if the real-time data stream is a real-time operation stream; and the abnormal operation stream is a preset operation stream in which the operation steps have an incorrect sequential dependency relationship; a target avoidance method corresponding to the real-time data stream is determined, and the target avoidance method is invoked to perform avoidance operation on the real-time data stream, including:

[0071] Determine the target avoidance method corresponding to the real-time operation flow; the target avoidance method is to read a preset invalid address;

[0072] Execute the target evasion method at a specified location in the real-time operation flow to perform evasion operations on the real-time operation flow.

[0073] Real-time operation flow refers to a series of data information representing operation steps that pass through the data path sequentially according to the clock cycle during chip operation.

[0074] In this embodiment, if the abnormal data stream is due to an error in the sequential dependency relationship between the operation steps in the preset operation stream, when it is determined that the real-time operation stream is consistent with the abnormal data stream, the corresponding target avoidance method is determined to be reading the preset invalid address.

[0075] Specifically, reading from a preset invalid address refers to dynamically inserting one or more additional operations into the real-time operation stream. These additional operations involve reading data from the preset invalid address, obtaining the corresponding read result, and then deleting the read result. After performing this action, the operation steps in the real-time operation stream continue to be executed.

[0076] Figure 2 This diagram illustrates a method for monitoring the operation flow of a real-time operation stream, as provided in an embodiment of this application. Assume that when a chip executes five specific operation steps (A→B→C→D→E), a calculation error occurs due to defects in the chip's internal microarchitecture (such as timing conflicts or resource contention), thus identifying the abnormal data stream as the operation step sequence (A→B→C→D→E). If the monitoring unit detects that the real-time operation stream matches this abnormal data stream, it executes a target avoidance method within the real-time operation stream to interrupt the operation step sequence, thereby achieving an avoidance operation on the real-time data stream. For example, an additional operation step is inserted between operation steps C and D, namely, reading a preset invalid address, modifying the real-time operation stream sequence to A→B→C→additional operation step→D→E.

[0077] For example, suppose the operation steps corresponding to the abnormal data stream are read 1 → read 2 → write 1 → write 2 → read 3 → write 3; if the real-time operation stream is consistent with the abnormal data stream, an additional operation can be inserted after operation step write 1 to read the preset invalid address; after performing this operation, the operation step write 2 can be performed.

[0078] According to the method of this embodiment, it is possible to accurately avoid abnormal operation flows in which there are errors in the sequential dependencies of each operation step in the preset operation flow, thereby preventing the actual operation flow from running incorrectly.

[0079] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, if the real-time data stream is a real-time operation stream, and the real-time abnormal operation stream is an operation step in the preset operation stream where the access address depends on an error, a target avoidance method corresponding to the real-time data stream is determined, and the target avoidance method is invoked to perform an avoidance operation on the real-time data stream, including:

[0080] Determine the target avoidance method corresponding to the real-time operation flow; the target avoidance method is address mapping.

[0081] According to a preset mapping relationship, the access addresses in the operation steps are mapped to replacement regions to perform evasion operations on the real-time operation flow. Here, the real-time operation flow refers to a series of data information representing operation steps that pass through the data path sequentially according to the clock cycle during chip operation.

[0082] In this context, the access address refers to the address that the read and write operations of a process step must access. An operation step depending on the access address means that the execution effect, success or failure, and even the meaning of an operation step are determined by the address it accesses. In other words, errors in the abnormal data stream are caused by accessing a specific address; if access address A is problematic, accessing that address when the chip executes an operation step will result in an error in the chip's operation.

[0083] Address mapping refers to the process of replacing the access address in the operation steps with another storage space; when performing address mapping, the operation steps are actually performing operations on the replacement area of ​​the access address mapping.

[0084] In this embodiment, the type of real-time data stream is first determined. If the real-time data stream is a real-time operation stream, it is further determined whether each operation step in the real-time operation stream depends on the access address. If it depends on the access address, when the real-time operation stream and the abnormal data stream are consistent, the corresponding target avoidance method is determined to be address mapping.

[0085] Suppose that when a chip performs a write operation on a specific physical address range (e.g., 0xFFFF_0000~0xFFFF_00FF), a design flaw in the hardware module corresponding to that range could lead to a system deadlock. Therefore, the physical address range for the abnormal data stream's access address is determined to be 0xFFFF_0000~0xFFFF_00FF. If the monitoring unit detects that the real-time operation stream has an address dependency and that the real-time operation stream shares the same access address as the abnormal data stream, it replaces the access address during operation execution with a preset mapping relationship, such as mapping the access address to 0xAAAA_BBBB, while keeping the operation type and the data written unchanged. In this way, the access to the problematic address 0xFFFF_0008 does not actually occur; instead, the memory at address 0xAAAA_BBBB replaces the original 0xFFFF_0008 address space, thus completely avoiding potential system access errors or deadlock errors.

[0086] In practical applications, corresponding mapping addresses can be set for different types of access addresses, but this embodiment does not limit this.

[0087] According to the method of this embodiment, when the monitoring unit detects that the operation step sequence is about to access a known access address that will cause an error, it maps the access address to a preset address through an address mapping mechanism, thereby realizing the execution of avoidance operation on the real-time operation stream and avoiding the occurrence of operation errors.

[0088] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, if the real-time data stream is a real-time command stream; the target evasion method corresponding to the real-time data stream is determined, and the target evasion method is invoked to perform an evasion operation on the real-time data stream, including:

[0089] Determine the target avoidance method corresponding to the real-time instruction stream; the target avoidance method is to insert a non-functional instruction.

[0090] Insert non-functional instructions into the real-time instruction stream to perform evasion operations on the real-time instruction stream.

[0091] Instruction stream refers to the sequence of machine instructions that are being processed, decoded, and executed sequentially in the chip's instruction pipeline. Real-time instruction streams can be fixed instruction combinations, such as sequential combinations of addition, shift, multiplication, and store instructions; or the execution of one instruction may depend on the results of one or more previous instructions, for example, instruction B may require the register value calculated by instruction A.

[0092] In this embodiment, if the abnormal data stream is an instruction stream, then when it is determined that the real-time instruction stream is consistent with the abnormal data stream, the corresponding target avoidance method is determined to be the insertion of a non-functional instruction.

[0093] Non-functional instructions occupy one or more chip execution cycles, do not change the program architecture state, and do not modify the contents of general-purpose registers, status registers, or memory.

[0094] Figure 3 This diagram illustrates a method for monitoring the execution of a real-time instruction stream, as provided in an embodiment of this application. Assume that when a chip executes a specific instruction sequence (e.g., instruction A → instruction B → instruction C), due to microarchitectural defects within the chip, such as data hazards, resource conflicts, or timing issues, a calculation error or system crash may occur, thus identifying the abnormal data stream as A → B → C. If the monitoring unit detects that the real-time instruction stream matches this abnormal data stream, it inserts a non-functional instruction into the real-time operation stream. For example, a NOP instruction is inserted between instruction B and instruction C, modifying the real-time instruction stream to A → B → NOP instruction → C.

[0095] It should be noted that multiple non-functional instructions can be inserted at a specified position in the real-time instruction stream, or corresponding non-functional instructions can be inserted at multiple positions in the real-time instruction stream. This embodiment does not limit this.

[0096] According to the method of this embodiment, when the real-time data stream is a real-time instruction stream, when the monitoring unit detects that an error will occur in the instruction sequence in the instruction pipeline, it changes the timing and execution process of the original instruction sequence by inserting non-functional instructions into the real-time instruction stream, thereby realizing the execution of avoidance operation on the real-time operation stream and avoiding the occurrence of runtime errors.

[0097] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, if the real-time data stream is a streaming media pixel sequence or an artificial intelligence network parameter sequence; the target avoidance method corresponding to the real-time data stream is determined, and the target avoidance method is invoked to perform an avoidance operation on the real-time data stream, including:

[0098] Determine the target avoidance method corresponding to the streaming media pixel sequence or the artificial intelligence network parameter sequence; the target avoidance method is to insert a null operation;

[0099] Insert a null operation into the streaming pixel sequence or the AI ​​network parameter sequence to perform an evasion operation on the streaming pixel sequence or the AI ​​network parameter sequence.

[0100] In this context, a streaming pixel sequence refers to a series of pixel data or pixel operation commands that are being processed continuously in a graphics processor, video codec, or display controller. For example, a streaming pixel sequence can be a sequence of RGB value combinations or a sequence of geometric shape rendering commands.

[0101] In this context, the no-operation corresponding to the streaming media pixel sequence refers to an operation in the pixel processing pipeline that does not produce any actual valid pixel output; no-operation includes inserting a blank pixel or a transparent pixel, inserting an empty packet, and skipping a calculation cycle, etc., which are not limited in this embodiment.

[0102] Among them, the artificial intelligence network parameter sequence refers to the ordered and continuous hardware-level operations performed by the chip when executing the neural network model. These operations are responsible for transferring the model parameters, such as weights and biases, from memory to the computing unit and performing the corresponding calculations.

[0103] Null operations corresponding to the parameter sequence of artificial intelligence networks include inserting computational pipeline cavitation, loading neutral or invalid data, executing harmless placeholder computation instructions, and dynamic operator scheduling / redirection.

[0104] In this embodiment, the type of abnormal data stream is first determined. If the abnormal data stream is a streaming media pixel sequence, then when it is determined that the currently collected streaming media pixel sequence is consistent with the abnormal data stream, the target avoidance method corresponding to the streaming media pixel sequence is determined. If the abnormal data stream is an artificial intelligence network parameter sequence, then when it is determined that the currently collected artificial intelligence network parameter sequence is consistent with the abnormal data stream, the target avoidance method corresponding to the artificial intelligence network parameter sequence is determined.

[0105] Suppose that when the chip executes a specific pixel sequence, it causes a calculation error in a stage of the rendering pipeline, ultimately resulting in a distorted screen. Therefore, this pixel sequence is identified as an abnormal data stream. If the monitoring unit detects that the streaming pixel sequence matches the abnormal data stream in the pixel pipeline, it inserts a "no-operation" at a specified position in the streaming pixel sequence. This could be done by inserting a completely transparent pixel that will not be visible, or simply allowing the pipeline to idle for one cycle, thus performing an avoidance operation on the streaming pixel sequence.

[0106] According to the method of this embodiment, when the real-time data stream is a streaming media pixel sequence, when the monitoring unit detects that an error will occur in the streaming media pixel sequence in the pixel pipeline, it changes the timing and execution process of the original streaming media pixel sequence by inserting a no-operation into the streaming media pixel sequence, thereby realizing the execution of an avoidance operation on the streaming media pixel sequence and avoiding the occurrence of runtime errors.

[0107] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, the monitoring unit is pre-configured with multiple independently configurable comparison logic units; each comparison logic unit is configured with a corresponding comparison method.

[0108] Invoke a preset comparison method to determine whether the real-time data stream and the abnormal data stream are consistent, including:

[0109] The corresponding comparison logic unit is activated based on the abnormal data stream;

[0110] Invoke the preset comparison method set in the enabled comparison logic unit to determine whether the real-time data stream and the abnormal data stream are consistent.

[0111] In this embodiment, multiple independently configurable comparison logic units are pre-set in the monitoring unit, meaning each comparison logic unit can be configured independently, including being enabled or disabled independently. Furthermore, each comparison logic unit can have its corresponding comparison method written into its configuration register; that is, each comparison logic unit has a pre-set comparison method.

[0112] For example, suppose the monitoring unit has 10 comparison logic units, and each comparison logic unit has a corresponding comparison method, meaning it can judge a maximum of 10 data stream combinations. In practical applications, only 3 of the comparison logic units can be enabled, and the other 7 comparison logic units can be disabled. That is, only the comparison results of 3 comparison logic units are needed to determine whether the real-time data stream and the abnormal data stream are consistent.

[0113] In this embodiment, the required comparison logic units can first be determined based on the abnormal data stream, that is, the content or characteristics of the abnormal data stream that caused the error can be determined, and one or more comparison logic units that need to be enabled can be identified. Then, the preset comparison method set in the enabled comparison logic unit is called to compare and judge whether the real-time data stream and the abnormal data stream are consistent.

[0114] As can be seen, the method of this embodiment can select the corresponding comparison method according to actual needs to determine whether the real-time data stream and the abnormal data stream are consistent, avoid invalid comparison operations, and save processing resources.

[0115] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, a preset comparison method set in the enabled comparison logic unit is invoked to determine whether the real-time data stream and the abnormal data stream are consistent, including:

[0116] Invoke the preset comparison method set in the enabled comparison logic unit to determine whether the real-time data stream and the abnormal data stream are consistent in parallel and / or in series.

[0117] In the parallel mode, when the number of comparison logic units is greater than or equal to the number of operation steps or instructions in the abnormal data stream, all enabled comparison logic units simultaneously and independently compare the real-time data stream with the abnormal data stream, obtain the corresponding comparison results, and then comprehensively determine whether the real-time data stream and the abnormal data stream are consistent based on the comparison results to obtain the final comparison result.

[0118] For example, suppose P comparison logic units are enabled, and each comparison logic unit, such as comparator 1, comparator 2, ..., comparator P, works in parallel. Each unit uses its own preset comparison method to perform comparison and judgment operations on the corresponding operation steps or instructions in the real-time data stream. After each comparison logic unit obtains its corresponding comparison result, the final comparison result is determined through a "logical AND" relationship. That is, if the comparison results of all specified participating comparison logic units are "consistent", then the final comparison result is determined to be "consistent", and the following is triggered: determine the target avoidance method corresponding to the real-time data stream, and call the target avoidance method to perform avoidance operations on the real-time data stream.

[0119] The serial method refers to the process where, when the number of comparison logic units is less than or equal to the number of operation steps or instructions in the abnormal data stream, each comparison logic unit compares and judges each operation step or instruction in the real-time data stream in a certain order or logical dependency, and determines the final comparison result of whether the real-time data stream and the abnormal data stream are consistent based on the comparison results.

[0120] For example, suppose there is one comparison logic unit, namely comparator 1; the number of operation steps in the abnormal data stream is 3; all comparison methods corresponding to the abnormal data stream are pre-set in comparator 1; comparator 1 is used to judge the 3 operation steps in the real-time data stream respectively: comparator 1 compares and judges operation step 1 in the first clock cycle and obtains the corresponding judgment result; compares and judges operation step 2 in the second clock cycle and obtains the corresponding judgment result; compares and judges operation step 3 in the third clock cycle and obtains the corresponding judgment result; after comparing and judging each operation step in turn and obtaining the corresponding comparison result, the comparison results are combined to determine whether the real-time data stream and the abnormal data stream are consistent.

[0121] In practical applications, the consistency between real-time and abnormal data streams can be determined by combining parallel and serial methods. For example, suppose there are only three comparison logic units, such as comparator 1, comparator 2, and comparator 3, while the abnormal data stream contains six operation steps. First, in the first clock cycle, the three comparators, connected in parallel, compare the first three operation steps in the real-time data stream (e.g., operation steps A, B, and C) with the first three operation steps in the abnormal data stream, obtaining the corresponding comparison results. Only after confirming that all three comparison results are consistent does the next clock cycle continue to check whether the remaining three operation steps in the real-time data stream are consistent with the last three operation steps in the abnormal data stream, obtaining the corresponding comparison results. If any operation step in the real-time data stream does not match the comparison result of the corresponding operation step in the abnormal data stream, it indicates that the real-time and abnormal data streams are inconsistent, and further comparison is unnecessary.

[0122] According to the method of this embodiment, determining whether the real-time data stream and the abnormal data stream are consistent in parallel can improve the completeness and efficiency of monitoring; determining whether the real-time data stream and the abnormal data stream are consistent in serial mode can save monitoring resources and design costs; determining whether the real-time data stream and the abnormal data stream are consistent in a combination of parallel and serial mode can improve the completeness and efficiency of monitoring.

[0123] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0124] It should be noted that the information collection process (such as the facial image collection process, fingerprint information collection process, etc.) / feature extraction process involved in this application is carried out with the user's knowledge and permission. That is, the information collection process / feature extraction process complies with the requirements of laws and regulations and does not constitute an act that harms the public interest.

[0125] Figure 4 The diagram shown is a schematic representation of a chip operation detection device according to an embodiment of this application. This embodiment provides a chip operation detection device applied to a monitoring unit, which is located on the chip's data path. Figure 4 As shown, the chip operation detection device of this embodiment includes an acquisition module 410, a comparison module 420, and an execution module 430; wherein,

[0126] The acquisition module 410 is used to acquire the real-time data stream of the data path according to each clock cycle during chip operation;

[0127] The comparison module 420 is used to call a preset comparison method to compare the real-time data stream with a preset abnormal data stream to determine whether the real-time data stream and the abnormal data stream are consistent; the abnormal data stream is a data stream that is written into the monitoring unit after chip production and is confirmed to cause an error.

[0128] The execution module 430 is used to determine the target avoidance method corresponding to the real-time data stream if the data stream is consistent, and to call the target avoidance method to perform avoidance operation on the real-time data stream.

[0129] The chip operation detection device provided in this application embodiment has the same beneficial effects as the chip operation detection method described above.

[0130] In one embodiment, if the real-time data stream is a real-time operation stream; and the abnormal operation stream is an error in the sequential dependency relationship between operation steps in a preset operation stream; the execution module includes:

[0131] The first evasion method determination submodule is used to determine the target evasion method corresponding to the real-time operation flow; the target evasion method is to read a preset invalid address;

[0132] The first execution submodule is used to execute the target evasion method at a specified position in the real-time operation stream in order to perform evasion operations on the real-time operation stream.

[0133] In one embodiment, the real-time abnormal operation flow is that each operation step in the preset operation flow depends on an access address error; the execution module includes:

[0134] The second evasion method determination submodule is used to determine the target evasion method corresponding to the real-time operation flow; the target evasion method is address mapping.

[0135] The second execution submodule is used to map and replace the access address in the operation steps with the preset address of the replacement area according to the preset mapping relationship, so as to perform evasion operation on the real-time operation flow.

[0136] In one embodiment, if the real-time data stream is a real-time instruction stream, the execution module includes:

[0137] The third evasion method determination submodule is used to determine the target evasion method corresponding to the real-time instruction stream; the target evasion method is to insert a non-functional instruction.

[0138] The third execution submodule is used to insert non-functional instructions into the real-time instruction stream in order to perform evasion operations on the real-time instruction stream.

[0139] In one embodiment, if the real-time data stream is a streaming media pixel sequence, the execution module includes:

[0140] The fourth avoidance method determination submodule is used to determine the target avoidance method corresponding to the streaming media pixel sequence; the target avoidance method is to insert a null operation.

[0141] The fourth execution submodule is used to insert null operations into the streaming pixel sequence to perform evasion operations on the streaming pixel sequence.

[0142] In one embodiment, the monitoring unit is pre-configured with multiple independently configurable comparison logic units; each comparison logic unit is configured with a corresponding comparison method.

[0143] The execution module includes:

[0144] Enable submodule, used to determine the corresponding comparison logic unit to enable based on abnormal data stream;

[0145] The calling submodule is used to invoke the preset comparison method set in the enabled comparison logic unit to determine whether the real-time data stream and the abnormal data stream are consistent.

[0146] In one embodiment, calling the submodule includes:

[0147] The calling unit is used to invoke the preset comparison method set in the enabled comparison logic unit to determine whether the real-time data stream and the abnormal data stream are consistent in parallel and / or in series.

[0148] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0149] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0150] Figure 5 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Figure 5 As shown, the terminal device 500 of this embodiment includes a memory 510, a processor 520, and a computer program 530 stored in the memory 510 and executable on the processor 520; when the processor 520 executes the computer program 530, it implements the steps in the above-described chip operation detection method embodiments; or when the processor 520 executes the computer program 530, it implements the functions of each module / unit in the above-described device embodiments.

[0151] For example, the computer program 530 can be divided into one or more modules / units, one or more of which are stored in the memory 510 and executed by the processor 520 to implement the method of the embodiments of this application. One or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program 530 in the terminal device 500. For example, the computer program 530 can be divided into an acquisition module, a comparison module, and an execution module, with the specific functions of each module as follows:

[0152] The chip operation detection device of this embodiment includes; wherein,

[0153] The acquisition module is used to acquire the real-time data stream of the data path at each clock cycle during chip operation;

[0154] The comparison module is used to call a preset comparison method to compare the real-time data stream with a preset abnormal data stream to determine whether the real-time data stream and the abnormal data stream are consistent; the abnormal data stream is the data stream that is written into the monitoring unit after chip production and is confirmed to cause errors.

[0155] The execution module is used to determine the target avoidance method corresponding to the real-time data stream if the data stream is consistent, and then call the target avoidance method to perform the avoidance operation on the real-time data stream.

[0156] The chip operation detection device provided in this application embodiment has the same beneficial effects as the chip operation detection method described above.

[0157] Terminal device 500 may include, but is not limited to, memory 510 and processor 520. Those skilled in the art will understand that... Figure 5 This is merely an example of a terminal device and does not constitute a limitation on the terminal device. It may include more or fewer components than shown, or combine certain components, or different components. For example, a terminal device may also include input / output devices, network access devices, buses, etc.; among which, input / output devices may include cameras, audio acquisition / playback devices, displays, etc.; network access devices may include communication modules for wireless communication with external devices.

[0158] In applications, the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0159] In applications, memory can be an internal storage unit of a terminal device, such as its hard drive or RAM; it can also be an external storage device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card; or it can include both internal and external storage units. Memory is used to store operating systems, applications, boot loaders, data, and other programs, such as computer program code. Memory can also be used to temporarily store data that has been output or will be output.

[0160] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above-described method embodiments.

[0161] This application implements all or part of the processes in the methods of the above embodiments, which can be accomplished by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate form. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, such as a USB flash drive, a portable hard drive, a magnetic disk, or an optical disk.

[0162] The computer-readable storage medium provided in this application embodiment has the same beneficial effects as the chip operation detection method described above.

[0163] This application also provides a computer program product, including a computer program that, when executed by a processor, can implement the steps in the various method embodiments described above.

[0164] The computer program product provided in this application embodiment has the same beneficial effects as the chip operation detection method described above.

[0165] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0166] Those skilled in the art will recognize that the device and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0167] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interface, or the device may be indirectly coupled or communicated, and may be electrical, mechanical, or other forms.

[0168] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for detecting the operation of a chip, characterized in that, The method is applied to a monitoring unit, which is located on the data path of a chip, and includes: During chip operation, the real-time data stream of the data path is acquired every clock cycle; the real-time data stream includes real-time operation stream, real-time instruction stream, streaming media pixel sequence, or artificial intelligence network parameter sequence; A preset comparison method is invoked to compare the real-time data stream with a preset abnormal data stream to determine whether the real-time data stream and the abnormal data stream are consistent; the abnormal data stream is a data stream written into the monitoring unit after the chip is manufactured and is confirmed to cause errors; the preset comparison method includes determining the read order / write order; determining the address; determining the sideband signal; and determining the instruction type and sequence. If they match, the target avoidance method corresponding to the real-time data stream is determined, and the target avoidance method is invoked to perform an avoidance operation on the real-time data stream; the avoidance method includes inserting a no-operation, inserting an invalid bus access, and performing address remapping; If the real-time data stream is the real-time operation stream; and the abnormal operation stream is a preset operation stream in which the operation steps have an incorrect sequential dependency relationship; the step of determining the target avoidance method corresponding to the real-time data stream and calling the target avoidance method to perform an avoidance operation on the real-time data stream includes: Determine the target avoidance method corresponding to the real-time operation flow; the target avoidance method is to read a preset invalid address; The target evasion method is executed at a designated location in the real-time operation stream to perform an evasion operation on the real-time operation stream.

2. The method according to claim 1, characterized in that, If the real-time data stream is the real-time operation stream; the abnormal operation stream is an error in the access address that each operation step in the preset operation stream depends on. The step of determining the target avoidance method corresponding to the real-time data stream and invoking the target avoidance method to perform an avoidance operation on the real-time data stream includes: Determine the target avoidance method corresponding to the real-time operation flow; the target avoidance method is address mapping; According to the preset mapping relationship, the access address in the operation steps is mapped to a replacement region in order to perform an evasion operation on the real-time operation stream.

3. The method according to claim 1, characterized in that, If the real-time data stream is the real-time instruction stream; determining the target evasion method corresponding to the real-time data stream and invoking the target evasion method to perform an evasion operation on the real-time data stream includes: Determine the target avoidance method corresponding to the real-time instruction stream; the target avoidance method is to insert a non-functional instruction. Non-functional instructions are inserted into the real-time instruction stream to perform an evasion operation on the real-time instruction stream.

4. The method according to claim 1, characterized in that, If the real-time data stream is the streaming media pixel sequence or the artificial intelligence network parameter sequence; the step of determining the target avoidance method corresponding to the real-time data stream and invoking the target avoidance method to perform an avoidance operation on the real-time data stream includes: Determine the target avoidance method corresponding to the streaming media pixel sequence or the artificial intelligence network parameter sequence; the target avoidance method is to insert a null operation; Insert a null operation into the streaming media pixel sequence or the artificial intelligence network parameter sequence to perform an evasion operation on the streaming media pixel sequence or the artificial intelligence network parameter sequence.

5. The method according to any one of claims 1 to 4, characterized in that, The monitoring unit is pre-configured with multiple independently configurable comparison logic units; each comparison logic unit is configured with a corresponding comparison method. The step of invoking a preset comparison method to determine whether the real-time data stream and the abnormal data stream are consistent includes: The corresponding comparison logic unit is activated based on the abnormal data stream; The preset comparison method set in the enabled comparison logic unit is invoked to determine whether the real-time data stream and the abnormal data stream are consistent.

6. The method according to claim 5, characterized in that, The invocation of the preset comparison method set in the enabled comparison logic unit to determine whether the real-time data stream and the abnormal data stream are consistent includes: The preset comparison method set in the enabled comparison logic unit is invoked to determine whether the real-time data stream and the abnormal data stream are consistent in parallel and / or in series.

7. A chip operation detection device, characterized in that, The device is applied to a monitoring unit, which is disposed on the data path of the chip, and includes: The acquisition module is used to acquire the real-time data stream of the data path at each clock cycle during chip operation; the real-time data stream includes operation stream, instruction stream, streaming media pixel sequence, or artificial intelligence network parameter sequence; The comparison module is used to call a preset comparison method to compare the real-time data stream with a preset abnormal data stream to determine whether the real-time data stream and the abnormal data stream are consistent; the abnormal data stream is a data stream that has been written into the monitoring unit after the chip is manufactured and has been confirmed to cause errors; the preset comparison method includes determining the read order / write order; determining the address; determining the sideband signal; and determining the instruction type and sequence. An execution module is used to determine the target avoidance method corresponding to the real-time data stream if the data stream is consistent, and to call the target avoidance method to perform an avoidance operation on the real-time data stream; the avoidance method includes inserting a no-operation, inserting an invalid bus access, and performing address remapping. If the real-time data stream is a real-time operation stream; and the abnormal operation stream is a preset operation stream in which the operation steps have an incorrect sequential dependency relationship; the execution module includes: The first evasion method determination submodule is used to determine the target evasion method corresponding to the real-time operation flow; the target evasion method is to read a preset invalid address; The first execution submodule is used to execute the target evasion method at a specified position in the real-time operation stream to perform evasion operations on the real-time operation stream.

8. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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