A solar water heater PCB control panel structure optimization method and system

Abstract

The present application relates to the technical field of defect detection, and in particular to a solar water heater PCB control panel structure optimization method and system. The method comprises: obtaining thermal parameters of each component, calculating time-weighted thermal power, generating a panel heat source distribution map, evaluating the condensation risk of each area of the panel according to the heat source distribution map and the preset installation inclination angle of the PCB control panel and generating a condensation risk distribution map, constructing an electromagnetic coupling model between the key signal traces and the power supply traces, calculating the basic electromagnetic interference intensity, extracting the condensation risk distribution on the key signal trace path, correcting the basic electromagnetic interference intensity to obtain a comprehensive risk assessment value, and optimizing the wiring according to the priority strategy when the comprehensive risk assessment value is greater than the preset threshold. That is, the scheme of the present application can predict and quantify the condensation risk area of the panel, and can also associate the condensation risk with the electromagnetic interference risk, thereby improving the working reliability of the PCB control panel in a wet and hot alternating environment.

Description

Technical Field

[0001] This invention relates to the field of defect detection technology. More specifically, this invention relates to a method and system for optimizing the structure of a PCB control board for a solar water heater. Background Technology

[0002] Solar water heaters are a type of clean energy device. Their stable and reliable operation relies on a PCB control board installed outdoors or in a semi-outdoor environment. This working environment presents the PCB control board with the dual challenges of temperature and humidity: On the one hand, the power modules, driver chips, and other components on the control board continuously generate heat during operation. Uneven heat distribution or poor heat dissipation can cause localized overheating, directly accelerating the aging of electronic components and shortening the overall lifespan of the PCB control board. On the other hand, due to the temperature difference between the inside and outside of the device and the influence of ambient humidity, condensation easily forms on the surface of the PCB control board. The presence of condensation reduces the insulation resistance of the board surface and can even cause micro-short circuits and solder pad corrosion, potentially leading to control system malfunction. In addition, electromagnetic compatibility is another core issue in ensuring the reliability of the PCB control board of a solar water heater. Since the control board has traces for processing weak and sensitive signals from external sensors such as temperature and water level, as well as traces for power drive units such as switching power supplies and relays that generate strong electromagnetic radiation, if high-frequency noise couples from the power traces to the sensitive signal traces during layout, it will cause signal distortion, leading to misjudgments of key parameters such as temperature and water level by the controller, directly affecting the heating efficiency and operational safety of the equipment.

[0003] When faced with the above challenges, firstly, existing technologies typically employ passive protection methods such as applying conformal coatings or adding protective shells to address heat and condensation issues; secondly, existing technologies typically use common electromagnetic compatibility design principles such as increasing trace spacing and ground shielding for PCB routing to reduce interference risks and resolve electromagnetic compatibility problems.

[0004] However, the measures adopted in the existing technology still have significant shortcomings. First, in the PCB layout design stage, there is a lack of systematic analysis that combines heat distribution under different operating modes with the device mounting angle, thus failing to proactively predict and avoid high condensation risk areas from the source. Second, existing electromagnetic compatibility design guidelines do not fully consider the dynamic impact of environmental factors on electromagnetic interference. In particular, when there is condensation on the board surface, the formed water film will change the parasitic capacitance and impedance between traces, leading to new noise coupling paths, making the original electromagnetic interference problem more complex and severe. There is a lack of a comprehensive design method to assess the correlation between condensation risk and electromagnetic interference risk, resulting in a high risk of malfunction for PCB control boards in harsh environments with alternating humidity and heat. Summary of the Invention

[0005] The purpose of this invention is to propose a method and system for optimizing the structure of a PCB control board for solar water heaters, in order to solve the problems in the prior art that it is impossible to actively predict and avoid high condensation risk areas from the source, and that the PCB control board still has a high risk of failure in harsh environments with alternating humidity and heat; to this end, this invention provides solutions in the following two aspects.

[0006] In a first aspect, the present invention provides a method for optimizing the structure of a solar water heater PCB control board, comprising:

[0007] The thermal parameters of each component on the PCB control board are obtained. Combined with a preset solar radiation model and user water usage habits, the time-weighted thermal power of each component under heat collection, electric heating, and heat preservation modes is calculated to generate a heat source distribution map of the board surface. Based on the heat source distribution map and the preset installation tilt angle of the PCB control board, the condensation risk of each area on the board surface is assessed, generating a condensation risk distribution map. An electromagnetic coupling model is constructed between the critical signal traces connecting external sensors and the switching power supply traces of the power drive unit, and the basic electromagnetic interference intensity between the critical signal traces and the switching power supply traces is calculated. The condensation risk distribution on the path of the critical signal traces is extracted, and the basic electromagnetic interference intensity is corrected using the condensation risk distribution to obtain a comprehensive risk assessment value. When the comprehensive risk assessment value is greater than a preset threshold, the routing is optimized according to a priority strategy. The priority strategy includes: rerouting the critical signal traces to areas with low condensation risk; increasing the distance or intersection angle between the critical signal traces and the switching power supply traces.

[0008] Preferably, the calculation of the time-weighted thermal power of each component in the heat collection, electric heating, and heat preservation modes includes: obtaining data from the solar water heater over a typical 24-hour period, specifying 8 hours of operation in heat collection mode, 2 hours in electric heating mode, and 14 hours in heat preservation mode; and multiplying the rated power of each component in the three modes by the corresponding time coefficient. , and Then, add the three products together to obtain the time-weighted thermal power of each component.

[0009] Preferably, the assessment of condensation risk in each area of ​​the board surface includes: dividing the board surface into several grid units; calculating the steady-state surface temperature of each grid unit at a preset installation tilt angle using finite element analysis based on the heat source distribution map and the thermal conductivity of the PCB material; comparing the steady-state surface temperature with the dew point temperature calculated according to environmental conditions; and assigning a corresponding condensation risk level to each grid unit based on the degree to which the steady-state surface temperature is lower than the dew point temperature.

[0010] Preferably, the calculation of the basic electromagnetic interference intensity between the critical signal trace and the switching power supply trace includes: acquiring the signal trace connected to the external sensor as the critical signal trace, and acquiring the switching power supply trace of the power drive unit as the interference source trace; inputting the geometric parameters, material properties of the two traces and the operating frequency, voltage or current change rate of the interference source trace into the three-dimensional electromagnetic simulation software, and calculating the peak noise voltage induced on the critical signal trace, wherein the peak noise voltage is the basic electromagnetic interference intensity.

[0011] Preferably, the step of using the condensation risk distribution to correct the basic electromagnetic interference intensity to obtain a comprehensive risk assessment value includes: calculating the weighted condensation risk index on the critical signal trace path. : The comprehensive risk assessment value is obtained by correcting the basic electromagnetic interference intensity based on the weighted condensation risk index, which satisfies the following: In the formula, This is a weighted condensation risk index for critical signal trace paths. For the first The length of each condensation risk zone For the first The condensation risk level corresponding to each condensation risk zone This refers to the total length of the critical signal traces. This represents the total number of condensation risk sections traversed by critical signal traces. This is a comprehensive risk assessment value. Based on the basic electromagnetic interference intensity, This is the risk correction factor.

[0012] Preferably, the step of rerouting the critical signal traces to an area with low condensation risk includes: identifying all continuous areas with condensation risk levels less than or equal to a preset safety level on a condensation risk distribution map; calling the routing engine of the PCB design software to define the continuous areas as preferred routing areas; obtaining constraints to guide the critical signal trace path to be completely contained within the preferred routing area, and regenerating the trace path.

[0013] Preferably, increasing the distance between the critical signal trace and the switching power supply trace includes: performing a spacing modification operation in the PCB routing editor to increase the distance between the parallel routing segments of the critical signal trace and the switching power supply trace to a preset safe distance, while ensuring that the modified layout meets the requirements of the design rule check.

[0014] Preferably, the risk correction coefficient represents the enhancing effect of condensation on electromagnetic interference and is a preset value of 0.4.

[0015] Preferably, the components include a microcontroller, a power management chip, and a relay.

[0016] In a second aspect, a solar water heater PCB control board structure optimization system includes:

[0017] The system includes a processor and a memory, the memory storing computer program instructions for optimizing the structure of a solar water heater PCB control board. When the computer program instructions are executed by the processor, the aforementioned method for optimizing the structure of a solar water heater PCB control board is implemented.

[0018] The beneficial effects of this invention are as follows: By analyzing the heat distribution and preset installation tilt angle under different operating modes, this invention can predict and quantify the condensation risk area on the PCB board surface, proactively avoiding short circuits or corrosion risks caused by condensation during the layout stage; furthermore, this invention introduces condensation risk into electromagnetic compatibility assessment, establishing a quantitative correlation between environmental factors and electromagnetic interference, making the interference assessment of critical signal traces closer to actual harsh operating conditions; by obtaining clear priority strategies, it guides the wiring design to prioritize solving the fundamental problems caused by condensation, rather than simply relying on adjusting the trace spacing; thus, it can improve the working reliability and long-term stability of the solar water heater PCB control board in humid and hot alternating environments from the source, reducing the risk of failure and the failure rate. Attached Figure Description

[0019] Figure 1 This schematically illustrates a flowchart of the steps involved in optimizing the structure of a solar water heater PCB control board in this embodiment.

[0020] Figure 2 The schematic diagram illustrates a structural block diagram of a solar water heater PCB control board structure optimization system in this embodiment. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0022] like Figure 1 As shown, the method for optimizing the structure of a solar water heater PCB control board in this embodiment includes steps S1 to S4:

[0023] Step S1: Obtain the thermal parameters of each component on the PCB control board. Combine the preset solar radiation model and user water usage habits to calculate the time-weighted thermal power of each component under heat collection, electric heating and heat preservation modes, and generate a heat source distribution map of the board surface.

[0024] In one embodiment, the components include a microcontroller, a power management chip, and a relay.

[0025] The thermal resistance and rated power consumption of major heat-generating components such as microcontrollers (MCUs), power management chips, and relays can be obtained by consulting the component datasheets.

[0026] In one embodiment, calculating the time-weighted thermal power of each component under heat collection, electric heating, and heat preservation modes includes:

[0027] Based on data from solar water heaters during a typical 24-hour cycle, the following parameters were obtained: 8 hours of operation in collector mode, 2 hours of operation in electric heating mode, and 14 hours of operation in heat preservation mode.

[0028] Multiply the rated power of each component in the three modes by the corresponding time coefficient. , and Then, add the three products together to obtain the time-weighted thermal power of each component.

[0029] Specifically, a typical 24-hour work cycle is obtained, where the solar radiation model defines the daytime light intensity variation curve, determining the operating duration of the heat collection mode; for example, 8 hours from 8:00 AM to 4:00 PM. User water usage habits define the peak hot water usage time, determining the start-up period of the electric heating mode; for example, 2 hours from 7:00 PM to 9:00 PM. The remaining 14 hours are for heat preservation mode. The calculated time coefficients are as follows: , and The time-weighted thermal power of each component is obtained by multiplying its rated power in each of the three modes by its corresponding time coefficient and then summing the results. For example, taking a microcontroller chip on a PCB board, the rated power of the microcontroller chip in three operating modes is obtained: 0.5 watts in heat collection mode, 0.8 watts in electric heating mode due to increased power consumption during operation when the electric heating auxiliary function is activated, and 0.4 watts in nighttime heat preservation mode due to low power consumption. The products of the rated power and the corresponding time coefficient for each mode are approximately 0.167 watts, 0.067 watts, and 0.233 watts, respectively. Summing these three values ​​yields the time-weighted thermal power of the microcontroller, which is 0.467 watts. This time-weighted thermal power value will be used as the heat source input for subsequent thermal simulation analysis.

[0030] In PCB layout software, the calculated time-weighted thermal power values ​​are assigned to the corresponding component packages to generate a heat source distribution map identified by power density, thereby obtaining the heat source distribution map of the board surface.

[0031] Step S2: Based on the heat source distribution map and the preset installation tilt angle of the PCB control board, assess the condensation risk in each area of ​​the board and generate a condensation risk distribution map; construct an electromagnetic coupling model between the key signal traces connecting external sensors and the switching power supply traces of the power drive unit, and calculate the basic electromagnetic interference intensity between the key signal traces and the switching power supply traces.

[0032] In one embodiment, assessing the condensation risk in each area of ​​the panel includes:

[0033] The plate surface is divided into several grid units;

[0034] Based on the heat source distribution diagram and the thermal conductivity of the PCB board, the steady-state surface temperature of each grid cell under the preset installation tilt angle is calculated using the finite element analysis method.

[0035] The steady-state surface temperature is compared with the dew point temperature calculated based on environmental conditions, and each grid cell is assigned a corresponding condensation risk level based on the degree to which the steady-state surface temperature is lower than the dew point temperature.

[0036] Specifically, a 100mm x 80mm PCB control board is modeled and divided into 8000 1mm x 1mm mesh units in the simulation software. The material properties of the PCB control board are input; for example, the thermal conductivity of the FR-4 substrate is 0.3 W / m Kelvin. Simultaneously, the time-weighted thermal power values ​​of all components calculated in the previous step are used as heat sources and applied to the corresponding locations in the model, i.e., the heat source distribution map generated in the previous step is used as the thermal load input. A harsh external environmental condition is obtained; for example, the ambient temperature is 25 degrees Celsius and the relative humidity is 90%. The PCB mounting angle is set to 45 degrees with respect to the horizontal plane to simulate the actual mounting posture. The finite element thermal analysis software is run to calculate the steady-state surface temperature of each mesh unit when it reaches thermal equilibrium under the combined effects of the heat source and environmental convection heat dissipation, generating a steady-state surface temperature distribution map of the PCB. For example, the temperature of a unit near the main control chip may be 40 degrees Celsius, while the temperature of a unit in the edge region far from the heat source may be as low as 27 degrees Celsius. Simultaneously, the dew point temperature of the air is calculated based on the ambient temperature and humidity. The calculation formula is a conventional technique in this field and will not be elaborated in this embodiment. For example, based on the obtained ambient temperature of 25 degrees Celsius and relative humidity of 90%, the dew point temperature is calculated to be approximately 23.3 degrees Celsius. The steady-state surface temperature of each grid cell is compared with the calculated dew point temperature. When the steady-state surface temperature is higher than 23.3 degrees Celsius, the condensation risk level is 0; when the steady-state surface temperature is between 21.3 and 23.3 degrees Celsius, the condensation risk level is 1; and when the steady-state surface temperature is lower than 21.3 degrees Celsius, the condensation risk level is 2. The threshold of 21.3 degrees Celsius, which differs from the dew point temperature of 23.3 degrees Celsius, is set to quantify the severity of the risk and represents a safety margin. This threshold is set based on experience. A steady-state surface temperature between 21.3 and 23.3 degrees Celsius indicates that condensation may occur, but the process is relatively slow, resulting in a thin water film that evaporates quickly. This is a region that requires vigilance but is tolerable.

[0037] Each grid cell is assigned a corresponding condensation risk level using the above method, resulting in a visualized condensation risk distribution map. Typically, the lower edge of the plate has the highest condensation risk due to the lower temperature caused by the rising of hot air.

[0038] In an optional embodiment, calculating the basic electromagnetic interference intensity between the critical signal trace and the switching power supply trace includes:

[0039] The signal traces for connecting external sensors are identified as critical signal traces, and the switching power supply traces for the power drive unit are identified as interference source traces.

[0040] The geometric parameters, material properties, and operating frequency, voltage or current change rate of the interference source traces of the two traces are input into the three-dimensional electromagnetic simulation software to calculate the peak noise voltage induced on the key signal traces. The peak noise voltage is the basic electromagnetic interference intensity.

[0041] Specifically, in the PCB layout, an analog signal trace connecting to an external water temperature sensor is selected as the critical signal trace; for example, the signal trace of the water temperature sensor NTC is selected, with a length of 60 mm and a width of 0.25 mm. Simultaneously, a nearby switching power supply trace powering the water pump is selected; this switching power supply trace is the trace from the switching transistor to the inductor in the switching power supply, and is selected as the interference source trace; for example, its length is 40 mm and its width is 1.5 mm. Measurements show that the two traces have a parallel distance of 30 mm and a spacing of 3 mm at one point. The geometric parameters (length, width, parallel distance, spacing, etc.), material properties (thermal conductivity, etc.) of the two traces, as well as the operating frequency, voltage or current change rate of the interference source trace, are input into the 3D electromagnetic simulation software. In 3D electromagnetic simulation software, the PCB's layer stack-up structure is reconstructed, such as a four-layer board model. The geometry and relative positions of the two aforementioned traces are drawn, thereby establishing a parasitic parameter model of mutual inductance and capacitance between the two traces based on the PCB's layer stack-up structure and material parameters. An excitation signal is obtained for the interference source trace, with operating parameters of a switching frequency of 150 kHz, a current jump from 0 Amperes in the undriven state to 2 Amperes in the driven state, and an edge rise time of 100 nanoseconds. Electromagnetic compatibility simulation analysis is run. The software calculates the coupling effect of the time-varying electromagnetic field generated by the switching power supply trace on the key signal trace by solving Maxwell's equations. After the simulation, the voltage waveform induced on the key signal trace is viewed in the results, and the maximum peak value is read, which is the noise voltage peak value. For example, the simulation results show that the peak value of the induced noise voltage is 80 millivolts, so 80 millivolts is the basic electromagnetic interference intensity.

[0042] Step S3: Extract the condensation risk distribution on the key signal trace path, and use the condensation risk distribution to correct the basic electromagnetic interference intensity to obtain a comprehensive risk assessment value.

[0043] In one embodiment, the step of correcting the basic electromagnetic interference intensity using the condensation risk distribution to obtain a comprehensive risk assessment value includes:

[0044] Calculate the weighted condensation risk index on the critical signal trace path. : ;

[0045] The comprehensive risk assessment value is obtained by correcting the basic electromagnetic interference intensity based on the weighted condensation risk index, which satisfies the following: ;

[0046] In the formula, This is a weighted condensation risk index for critical signal trace paths. For the first The length of each condensation risk zone For the first The condensation risk level corresponding to each condensation risk zone This refers to the total length of the critical signal traces. This represents the total number of condensation risk sections traversed by critical signal traces. This is a comprehensive risk assessment value. Based on the basic electromagnetic interference intensity, This is the risk correction factor.

[0047] The risk correction coefficient represents the enhancing effect of condensation on electromagnetic interference, and is a preset value of 0.4.

[0048] Specifically, the 60mm critical signal trace selected in step S2 was overlaid onto the condensation risk distribution map for analysis. It was found that this critical signal trace was not in a single-risk environment; rather, 35mm of its length was within the safe zone (condensation risk level 0), 20mm passed through the low-risk zone (condensation risk level 1), and 5mm passed through the high-risk zone (condensation risk level 2). Applying the formula for calculating the weighted condensation risk index, the numerator was calculated as follows: the first segment length (35mm) multiplied by condensation risk level 0, the second segment length (20mm) multiplied by condensation risk level 1, and the third segment length (5mm) multiplied by condensation risk level 2. These three values ​​were added together to obtain 30. The result 30 was divided by the total critical signal trace length of 60mm to obtain the weighted condensation risk index. The value is 0.5. The comprehensive risk assessment value is calculated using the corrected formula, given the known baseline electromagnetic interference intensity. It is 80 millivolts, with a risk correction factor. Based on experience and presuppositions, take =0.4, substitute into the formula to calculate The value is 96, resulting in a comprehensive risk assessment value of 96 millivolts.

[0049] Step S4: When the comprehensive risk assessment value is greater than the preset threshold, optimize the routing according to the priority strategy; the priority strategy includes: rerouting the critical signal traces to areas with low condensation risk; increasing the distance or crossing angle between the critical signal traces and the switching power supply traces.

[0050] Specifically, the preset threshold is an empirically preset allowable noise threshold for an external sensor signal, set to 100 millivolts. When the currently calculated comprehensive risk assessment value is 150 millivolts, which is greater than the preset threshold, optimized routing is initiated, executing priority strategy one. In the PCB layout, the critical signal traces are rearranged from the high condensation risk area at the bottom edge of the board to the middle of the board near the microcontroller chip. The area where the chip is located on the board has a higher temperature due to chip heat generation and belongs to a lower condensation risk area. Then, the risk assessment is re-performed. If the comprehensive risk assessment value drops to 90 millivolts, which is less than the preset threshold, the optimization ends. If the comprehensive risk assessment value is still 110 millivolts after rerouting, priority strategy two is initiated. While maintaining the new path, the parallel spacing between the critical signal traces and the switching power supply traces is increased, or the crossing angle is ensured to be 90 degrees at necessary intersections, until the calculated comprehensive risk assessment value is less than or equal to 100 millivolts.

[0051] In an optional embodiment, rerouting critical signal traces to areas with low condensation risk includes:

[0052] On the condensation risk distribution map, identify all continuous areas where the condensation risk level is less than or equal to the preset safety level;

[0053] The routing engine of the PCB design software is invoked to define the continuous area as the preferred routing area; constraints are obtained to guide the routing path of the key signal to be completely contained within the preferred routing area, and the routing path is regenerated.

[0054] Specifically, engineers preset a safety level on the generated condensation risk distribution map based on experience. In this embodiment, the area with a condensation risk level of 0 is defined as the safe routing area, and condensation risk level 0 is the preset safety level. On the condensation risk distribution map, all continuous areas with a condensation risk level less than or equal to the preset safety level are identified and highlighted. These continuous areas with a risk level of 0 are typically located near components with high heat generation or in the center of the PCB board. In the PCB design software, using the area definition or rule setting function, these highlighted safe areas are defined as a specific routing space, named the safe routing area, also known as the preferred routing area. For the network category to which the critical signal traces belong, such as a sensor signal network, a design rule is added, forcing all traces of the sensor signal network to be completely routed within the preferred routing area. The original critical signal traces are deleted, and automatic or manual routing is performed on the sensor signal network. When performing routing, the routing engine strictly adheres to the newly acquired rule, searching for a new path from the signal start point to the end point that is completely within the preferred routing area. Even if the new path is longer than the original path or requires more vias, as long as the rules are met, the above-mentioned new routing layout that avoids all condensation risk areas will be generated.

[0055] In an optional embodiment, increasing the distance between the critical signal trace and the switching power supply trace includes:

[0056] In the PCB routing editor, perform a spacing modification operation to increase the distance between the parallel routing segments of the critical signal traces and the switching power supply traces to a preset safe distance, while ensuring that the modified layout meets the requirements of the design rule check.

[0057] Specifically, open the design file in the PCB layout editor, highlighting the power supply trace (the source of interference) and the critical signal trace (the object of interference). Use the software's measurement tool to confirm the distance between the parallel segments of the two traces; for example, 3 mm. Based on the comprehensive risk assessment value calculated for the new path, increase the parallel spacing between the critical signal trace and the power supply trace until the calculated comprehensive risk assessment value is less than or equal to a preset threshold. At this point, the distance between the two traces is the preset safe distance; for example, increase the spacing to 6 mm. Enter routing editing mode, select the segment of the critical signal trace parallel to the power supply trace, and use drag or move commands to translate this segment away from the power supply trace. Simultaneously observe the dynamically displayed coordinates or spacing readings on the software interface until the distance between the two traces reaches or exceeds 6 mm. During the movement, the software's real-time routing function will automatically adjust other parts connected to the critical signal trace to maintain network connectivity. After the operation is complete, to ensure that this modification has not introduced new design problems, a full-board design rule check needs to be run. The design rule check verifies whether the new routing layout meets all preset design rules such as minimum trace spacing and trace-pad spacing. If the design rule check report shows no errors, it means that the spacing increase operation was successfully completed, and the modified layout file can be saved at this time.

[0058] This invention also provides a system for optimizing the structure of a solar water heater PCB control board. For example... Figure 2 As shown, the system includes a processor and a memory. The memory stores computer program instructions for optimizing the structure of a solar water heater PCB control board. When the computer program instructions are executed by the processor, a solar water heater PCB control board structure optimization method according to the present invention is implemented.

[0059] The system also includes other components well known to those skilled in the art, such as communication buses and communication interfaces, the settings and functions of which are known in the art and therefore will not be described in detail here.

[0060] In this invention, the aforementioned memory can be any tangible medium containing or storing a program that can be used or combined with an instruction execution system, apparatus, or device. For example, a computer-readable storage medium can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc., or any other medium that can be used to store desired information and can be accessed by an application, module, or both. Any such computer storage medium can be part of a device or accessible to or connected to a device. Any application or module described in this invention can be implemented by computer-readable / executable instructions stored or otherwise maintained on such a computer-readable medium.

[0061] In the description of this specification, "multiple" means at least two, such as two, three or more, etc., unless otherwise expressly and specifically defined.

[0062] While various embodiments of the invention have been shown and described in this specification, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and essence of the invention.

Claims

1. A method of optimizing a solar water heater PCB control board structure, characterized in that, The method comprises the following steps: Obtain the thermal parameters of each component on the PCB control panel, combine the preset solar model and the user's water usage habits, calculate the time-weighted thermal power of each component in the heat collection, electric heating and heat preservation modes, and generate a heat source distribution map of the panel surface; According to the heat source distribution map and the preset installation angle of the PCB control panel, evaluate the condensation risk of each area on the panel surface, generate a condensation risk distribution map, and construct an electromagnetic coupling model between the key signal lines connected to the external sensor and the switching power supply lines of the power driving unit. Calculate the basic electromagnetic interference intensity between the key signal lines and the switching power supply lines. Extract the condensation risk distribution along the critical signal trace paths, and use the condensation risk distribution to correct the basic electromagnetic interference intensity to obtain a comprehensive risk assessment value, including: calculating the weighted condensation risk index along the critical signal trace paths. : The comprehensive risk assessment value is obtained by correcting the basic electromagnetic interference intensity based on the weighted condensation risk index. ; For the first The length of each condensation risk zone For the first The condensation risk level corresponding to each condensation risk zone This refers to the total length of the critical signal traces. This represents the total number of condensation risk sections traversed by critical signal traces. This is a comprehensive risk assessment value. Based on the basic electromagnetic interference intensity, This is a risk correction factor; When the comprehensive risk assessment value is greater than the preset threshold value, the wiring is optimized according to the priority strategy; the priority strategy includes: re-wiring the key signal lines to the area with low condensation risk; increasing the distance or intersection angle between the key signal lines and the switching power supply lines.

2. The method of optimizing a solar water heater PCB structure according to claim 1, wherein, The calculation of the time-weighted thermal power of each component in the heat collection, electric heating and heat preservation modes comprises: According to the data of the solar water heater in a typical 24-hour period, the heat collection mode runs for 8 hours, the electric heating mode runs for 2 hours, and the heat preservation mode runs for 14 hours. The rated power of each component in the three modes is multiplied by the corresponding time coefficient, respectively , and The three products are added to obtain the time-weighted thermal power of each component.

3. The method of claim 1, wherein the method further comprises: The evaluation of the condensation risk of each area on the panel surface comprises: Divide the panel surface into a plurality of grid units; Based on the heat source distribution map and the thermal conductivity of the PCB panel material, the steady-state surface temperature of each grid unit under the preset installation angle is calculated by using the finite element analysis method; Compare the steady-state surface temperature with the dew point temperature calculated according to the environmental conditions, and assign a corresponding condensation risk level to each grid unit according to the degree to which the steady-state surface temperature is lower than the dew point temperature.

4. The method of claim 1, wherein the method further comprises: The calculation of the basic electromagnetic interference intensity between the key signal lines and the switching power supply lines comprises: Obtain the signal lines connected to the external sensor as the key signal lines, and obtain the switching power supply lines of the power driving unit as the interference source lines; Input the geometric parameters, material properties, and the working frequency, voltage or current change rate of the interference source lines of the two lines into a three-dimensional electromagnetic simulation software, and calculate the induced noise voltage peak value on the key signal lines, which is the basic electromagnetic interference intensity.

5. The method of optimizing a solar water heater PCB structure according to claim 1, wherein, The re-wiring of the key signal lines to the area with low condensation risk comprises: Identify all continuous areas with a condensation risk level less than or equal to a preset safety level on the condensation risk distribution map; Call the wiring engine of the PCB design software to define the continuous area as the preferred wiring area; obtain the constraint conditions to guide the key signal line path to be completely contained in the preferred wiring area, and regenerate the wiring path.

6. The method of optimizing a solar water heater PCB structure according to claim 1, wherein, The increase of the distance between the key signal lines and the switching power supply lines comprises: In the PCB wiring editor, perform the distance modification operation to increase the distance between the parallel wiring segments of the key signal lines and the switching power supply lines to a preset safety distance, while ensuring that the modified layout meets the requirements of the design rule check.

7. The method of optimizing a solar water heater PCB structure according to claim 1, wherein, The risk correction coefficient represents the enhancement effect of condensation on electromagnetic interference, which is a preset value of 0.

4.

8. The method of optimizing a solar water heater PCB structure according to claim 1, wherein, The components include a microcontroller, a power management chip and a relay.

9. A solar water heater PCB control board structure optimization system, characterized in that, The method comprises the following steps: A processor and a memory, the memory storing computer program instructions for solar water heater PCB control panel structure optimization, which, when executed by the processor, implement a solar water heater PCB control panel structure optimization method according to any one of claims 1-8.

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