Semiconductor device

Abstract

And the quality is improved. The semiconductor device includes: a wiring substrate; a first laminated body including N (an integer of 2 or more) first plate-shaped portions having a first width in a width direction intersecting the vertical direction, the N first plate-shaped portions being laminated in the vertical direction above the wiring substrate; and a second laminated body including: a second plate-shaped portion having a second width greater than the first width in the width direction, the second plate-shaped portion being provided above the first laminated body; and M (an integer of 1 or more) third plate-shaped parts provided above the second plate-shaped part and having a first width in the width direction, the second plate-shaped part and the M third plate-shaped parts being stacked in the vertical direction, the first plate-shaped part including a first memory chip, the second plate-shaped part including a second memory chip, and the M third plate-shaped parts including a second memory chip. The second plate-shaped portion includes a second memory chip and a first resin layer connected to a first side of the second memory chip in a first width direction, the third plate-shaped portion includes a third memory chip, and a second side opposite to the first side of the first laminated body and the second laminated body in the width direction is stepped. The end portion of the second side of the second laminate is positioned closer to the second side than the end portion of the second side of the first laminate.

Description

TECHNICAL FIELD

[0001] The present embodiment relates to a semiconductor device. BACKGROUND

[0002] In a semiconductor device, there is a semiconductor device in which a plurality of chips are provided on a substrate in a stacked manner.

[0003] Patent Document 1: US Patent Application Publication No. US2018 / 0240782 Specification Patent Document 2: US Patent Application Publication No. US2022 / 0336417 Specification Patent Document 3: US Patent Application Publication No. US2023 / 0378128 Specification SUMMARY

[0004] There is a case where the quality of a semiconductor device is degraded due to a stacking method of a plurality of chips.

[0005] An object of the present disclosure is to provide a semiconductor device capable of improving the quality.

[0006] A semiconductor device according to the present disclosure includes a wiring substrate having a main surface intersecting an up-down direction, a first stack including N first plate-shaped portions each having a first width in a first width direction intersecting the up-down direction, the N first plate-shaped portions being stacked in the up-down direction above the wiring substrate, and a second stack including a second plate-shaped portion having a second width larger than the first width in the first width direction, disposed above the first stack, and M third plate-shaped portions each having the first width in the first width direction, disposed above the second plate-shaped portion, the second plate-shaped portion and the M third plate-shaped portions being stacked in the up-down direction, the first plate-shaped portion including a first memory chip, a face above the first memory chip being provided with a first electrode pad electrically connected to the wiring substrate by a first bonding wire, The second plate-shaped portion includes a second memory chip whose upper face is provided with a second electrode pad electrically connected to the wiring substrate by a second bonding wire, and a first resin layer connected to a first side in the first width direction of the second memory chip, the third plate-shaped portion includes a third memory chip whose upper face is provided with a third electrode pad electrically connected to the wiring substrate by the second bonding wire, an opposite side, i.e., a second side, of the first side of the first layer stack is stepped such that the first electrode pad is located on a stepped face, the second side of the second layer stack is stepped such that the second electrode pad or the third electrode pad is located on a stepped face, and when the main face is viewed in plan, an end portion of the second side of the second layer stack is located at a position closer to the second side than an end portion of the second side of the first layer stack. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic view showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Figure 2 is a plan view when the semiconductor chip according to the first embodiment is viewed from above. Figure 3 is a plan view when the plate-shaped portion 411 is viewed from above. Figure 4 is a plan view when the plate-shaped portion 412 is viewed from above. Figure 5 is a schematic view showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Figure 6 is a schematic view showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Figure 7 is a schematic view showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Figure 8 is a schematic view showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Figure 9 is a schematic view showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Figure 10 is a schematic view showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Figure 11 is a schematic view showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Figure 12This is a schematic diagram of a cross-section parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first embodiment. Figure 13 This is a schematic diagram of a cross-section parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first embodiment. Figure 14 This is a schematic diagram showing a cross-section of the semiconductor device involved in the comparative example from the side view. Figure 15 This is a top view of the semiconductor chip in the comparison model. Figure 16 This is a schematic diagram showing a cross-section of the semiconductor device according to the second embodiment. Figure 17 This is a schematic diagram of a cross-section parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. Figure 18 This is a schematic diagram of a cross-section parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. Figure 19 This is a schematic cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment. Figure 20 This is a schematic diagram showing a cross-section of a second modified example of the semiconductor device according to the second embodiment. Figure 21 This is a schematic diagram showing a cross-section of a third variation of the semiconductor device according to the second embodiment. Figure 22 This is a schematic diagram showing a cross-section of a fourth variation of the semiconductor device according to the second embodiment. Figure 23 This is a schematic diagram showing a cross-section of a fifth variation of the semiconductor device according to the second embodiment. Figure 24 This is a schematic diagram showing a cross-section of a sixth variation of the semiconductor device according to the second embodiment. Figure 25 This is a schematic diagram showing a cross-section of a seventh variation of the semiconductor device according to the second embodiment. Figure 26 This is a schematic diagram showing a cross-section of the semiconductor device according to the third embodiment. Figure 27 This is a schematic diagram showing a cross-section of the semiconductor device according to the fourth embodiment. Figure 28 This is a schematic diagram of a cross-section parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the fourth embodiment. Figure 29This is a schematic diagram of a cross-section parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the fourth embodiment. Figure 30 This is a schematic diagram of a cross-section parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the fourth embodiment. Detailed Implementation

[0008] Hereinafter, this embodiment will be described with reference to the accompanying drawings. To facilitate understanding, the same reference numerals will be used as much as possible to refer to the same constituent elements in each drawing, and repeated descriptions will be omitted.

[0009] (First Implementation) The configuration of the semiconductor device according to the first embodiment will now be described. The X-axis, Y-axis, and Z-axis are sometimes shown in the accompanying drawings. The X-axis, Y-axis, and Z-axis form a right-handed three-dimensional Cartesian coordinate system. Hereinafter, the direction of the arrow on the X-axis is sometimes referred to as the X-axis+ direction, and the direction opposite to the arrow is sometimes referred to as the X-axis- direction; the same applies to the other axes. Furthermore, the Z-axis+ direction and Z-axis- direction are sometimes referred to as "above" and "below," respectively. Additionally, the planes orthogonal to the X-axis, Y-axis, or Z-axis are sometimes referred to as the YZ plane, ZX plane, or XY plane, respectively. Furthermore, the Z-axis direction is sometimes referred to as the "vertical direction." "Above," "below," and "vertical direction" are merely terms used to illustrate relative positional relationships within the accompanying drawings and are not terms used to determine orientation relative to the plumb line.

[0010] In addition, unless otherwise specifically stated, the dimensions of the constituent elements shown in the accompanying drawings are sometimes shown in a manner different from the actual dimensions in order to facilitate the understanding of the explanation.

[0011] In this specification, "connection" includes not only physical connections but also electrical connections, and unless otherwise specified, it includes not only direct connections but also indirect connections.

[0012] In this specification, "formed above" includes not only cases formed with the ground above, but also cases formed above via other objects, unless otherwise specified. The same applies to cases such as "formed below".

[0013] Figure 1 This is a schematic diagram showing a cross-section of the semiconductor device according to the first embodiment, parallel to the YZ plane. Figure 2 This is a top view of the semiconductor chip according to the first embodiment, viewed from above. Furthermore, to facilitate understanding of the description, Figure 2 The sealing resin 65 is not shown in the figure.

[0014] like Figure 1 and Figure 2As shown, the semiconductor device 11 includes a wiring substrate 25, a sealing resin 65 (an example of a "sixth resin layer"), and two single-tower structures 501. The single-tower structure 501 includes bonding wires 81a (an example of a "first bonding wire") and 81b (an example of a "second bonding wire"), as well as laminates 401 (an example of a "first laminate") and 402 (an example of a "second laminate").

[0015] One of the two single-tower structures 501 is a component formed by rotating the other single-tower structure 501 180° about the Z-axis. The single-tower structure 501 on the Y-axis side will be described representatively below, but the same applies to the single-tower structure 501 on the Y-axis+ side.

[0016] The wiring substrate 25 has a surface 25a (an example of a "main surface") that intersects the vertical direction (Z-axis direction). In this embodiment, surface 25a is substantially parallel to the XY plane.

[0017] Multiple substrate electrodes 26a and multiple substrate electrodes 26b are provided on surface 25a.

[0018] Multiple substrate electrodes 26a are arranged in a row along the X-axis to form bonding fingers. The bonding fingers of the substrate electrodes 26a are located on the Y-axis side of the single-tower structure 501.

[0019] Similarly, multiple substrate electrodes 26b are arranged in a row along the X-axis to form bonding fingers. The bonding fingers of the substrate electrodes 26b are located on the Y-axis side of the bonding fingers of the substrate electrodes 26a.

[0020] A plurality of solder balls 64 are disposed on the surface below the wiring substrate 25. In addition, an electrode pattern (not shown) is formed on the wiring substrate 25. Part or all of the substrate electrodes 26a and 26b are electrically connected to the plurality of solder balls 64 via the electrode pattern formed on the wiring substrate 25.

[0021] Figure 3 This is a top view of the plate-shaped part 411 as seen from above. (Example) Figures 1-3 As shown, the laminate 401 includes N (N is an integer greater than or equal to 2) plate-shaped portions 411 (an example of a "first plate-shaped portion") and N wafer bonding films 421. In this embodiment, the laminate 401 includes 4 plate-shaped portions 411 and 4 wafer bonding films 421.

[0022] The plate-shaped portion 411 has a width W1 (an example of the "first width") in the Y-axis direction (an example of the "first width direction") intersecting the vertical direction. Furthermore, the width W1 of each plate-shaped portion 411 may fluctuate within the range of manufacturing tolerances.

[0023] In this embodiment, the thickness of the lowest plate-shaped portion 411 among the four plate-shaped portions 411 is greater than the thickness of the other three plate-shaped portions 411. Furthermore, the thickness of each plate-shaped portion 411 in the vertical direction can also be the same.

[0024] The plate-shaped portion 411 includes a memory chip 411a (an example of a "first memory chip"), a CMOS (Complementary Metal-Oxide-Semiconductor) chip 411b (an example of a "second semiconductor chip"), a molding resin 411c (an example of a "resin layer"), and multiple electrode pads 411d (an example of a "first electrode pad").

[0025] The memory chip 411a is, for example, a NAND flash memory chip. The memory chip 411a is located closer to the end of the plate-shaped portion 411 in the Y-axis direction than the end in the Y-axis+ direction.

[0026] Multiple electrode pads 411d are disposed on the surface above the memory chip 411a. The number of electrode pads 411d is the same as the number of substrate electrodes 26a forming the bonding fingers.

[0027] Multiple electrode pads 411d are located closer to the Y-axis side than the Y-axis side of the memory chip 411a, and are arranged in a row along the X-axis. The multiple electrode pads 411d are electrically connected to multiple substrate electrodes 26a via bonding wires 81a.

[0028] CMOS chip 411b controls memory chip 411a. Memory chip 411a is bonded to a portion of the surface above CMOS chip 411b (hereinafter sometimes referred to as the bonding surface). CMOS chip 411b and memory chip 411a are electrically and mechanically bonded by direct bonding. Details of direct bonding will be described later.

[0029] The molding resin 411c is connected to the Y-axis+ direction side (an example of the “first side”) of the memory chip 411a.

[0030] In this embodiment, molding resin 411c is attached to the upper surface of the CMOS chip 411b (excluding the bonding surface), and to the side surface of the memory chip 411a parallel to the ZX plane and the side surface parallel to the YZ plane. The width of the molding resin 411c in the Y-axis direction and the width of the CMOS chip 411b are both W1. The width W1 of the CMOS chip 411b is larger than the width of the memory chip 411a in the Y-axis direction.

[0031] A wafer bonding film 421 is disposed on the surface below the CMOS chip 411b. The manufacturing method of the plate-shaped part 411 will be described in detail later.

[0032] Four plate-shaped portions 411 are stacked vertically above the wiring substrate 25. Specifically, the bottommost plate-shaped portion 411 is connected to the surface 25a of the wiring substrate 25, for example, by a wafer bonding film 421 with a width of W1 in the Y-axis direction. The second layer of plate-shaped portions 411 below is connected to the surface above the bottommost plate-shaped portion 411 by the wafer bonding film 421. In this way, the four plate-shaped portions 411 are stacked to form a laminate 401.

[0033] The opposite side of the Y-axis+ direction of the laminate 401, namely the Y-axis-direction side (an example of the "second side"), becomes stepped. The step has step surfaces (terrace surfaces) SP1 parallel to the XY plane. Electrode pads 411d are located on step surfaces SP1.

[0034] Figure 4 This is a top view of the plate-shaped part 412 as seen from above. (Example) Figures 1-4 As shown, the laminate 402 includes a plate-shaped portion 412 (an example of a "second plate-shaped portion"), M (M is an integer greater than or equal to 1) plate-shaped portions 413 (an example of a "third plate-shaped portion"), a wafer bonding film 422, and M wafer bonding films 423.

[0035] In this embodiment, the laminate 402 includes a plate-shaped portion 412, three plate-shaped portions 413, a wafer bonding film 422, and three wafer bonding films 423.

[0036] The plate-shaped portion 412 is disposed above the laminate 401 and has a width W2 (an example of a "second width") that is larger than the width W1 in the Y-axis direction. The plate-shaped portion 412 includes a memory chip 412a (an example of a "second memory chip"), a CMOS chip 412b (an example of a "second semiconductor chip"), a molding resin 412c (an example of a "first resin layer"), and a plurality of electrode pads 412d (an example of "second electrode pads").

[0037] Memory chip 412a is, for example, the same NAND flash memory chip as memory chip 411a. Memory chip 412a is located closer to the end of the plate-shaped portion 412 in the Y-axis direction than the end in the Y-axis direction of the plate-shaped portion 412. The width of memory chip 412a in the Y-axis direction is approximately the same as the width of memory chip 411a in the Y-axis direction.

[0038] Multiple electrode pads 412d are disposed on the surface above the memory chip 412a. The number of electrode pads 412d is the same as the number of substrate electrodes 26b forming the bonding fingers.

[0039] Multiple electrode pads 412d are located closer to the Y-axis side than the Y-axis side of the memory chip 412a, and are arranged in a row along the X-axis. The multiple electrode pads 412d are electrically connected to multiple substrate electrodes 26b via bonding wires 81b.

[0040] CMOS chip 412b is, for example, the same chip as CMOS chip 411b. CMOS chip 412b controls memory chip 412a. The width of CMOS chip 412b in the Y-axis direction is approximately the same as the width of CMOS chip 411b in the Y-axis direction. Memory chip 412a is bonded to a portion of the surface above CMOS chip 412b (hereinafter, sometimes referred to as the bonding surface).

[0041] The molding resin 412c is connected to the Y-axis+ direction side (an example of the “first side”) of the memory chip 412a.

[0042] In this embodiment, the molding resin 412c is connected to the upper surface of the CMOS chip 412b (excluding the bonding surface), and the side surface of the memory chip 412a that is parallel to the ZX surface and the side surface that is parallel to the YZ surface.

[0043] The width of the molding resin 412c in the Y-axis direction is larger than the width of the CMOS chip 412b in the Y-axis direction. Specifically, the molding resin 412c extends further into the Y-axis direction than the end of the CMOS chip 412b in the Y-axis+ direction.

[0044] Therefore, the width W2 of the plate-shaped portion 412 becomes larger than the width W1 of the plate-shaped portion 411. That is, the plate-shaped portion 412 is extended in the Y-axis + direction than the plate-shaped portion 411 by the molding resin 412c. Hereinafter, the molding resin 412c located in the Y-axis + direction than the end of the CMOS chip 412b is sometimes referred to as the extension portion.

[0045] A wafer bonding film 422 is provided on the surface below the CMOS chip 412b and the surface below the extension of the molding resin 412c. The wafer bonding film 422 has a width greater than the width W1 in the Y-axis direction of the wafer bonding film 421, for example, a width W2. The manufacturing method of the plate-shaped portion 412 will be described in detail later.

[0046] like Figures 1-3As shown, three plate-shaped portions 413 are disposed above the plate-shaped portion 412. Each plate-shaped portion 413 has a width W1 in the Y-axis direction. Furthermore, the width W1 of each plate-shaped portion 413 can fluctuate within the range of manufacturing tolerances.

[0047] The plate-shaped portion 413 includes a memory chip 413a (an example of a "third memory chip"), a CMOS chip 413b (an example of a "second semiconductor chip"), a molding resin 413c (an example of a "resin layer"), and a plurality of electrode pads 413d (an example of a "third electrode pad").

[0048] The memory chip 413a, CMOS chip 413b, molding resin 413c, electrode pad 413d, and wafer bonding film 423 are the same as those in the plate-shaped portion 411.

[0049] The memory chip 413a is located closer to the end of the plate-shaped portion 413 in the Y-axis direction than the end in the Y-axis+ direction. On the surface above the memory chip 413a, the same number of electrode pads 413d as the number of substrate electrodes 26b forming the bonding fingers are provided.

[0050] Multiple electrode pads 413d are located closer to the Y-axis side than the Y-axis side of the memory chip 413a, and are arranged in a row along the X-axis. The multiple electrode pads 413d are electrically connected to multiple substrate electrodes 26b via bonding wires 81b.

[0051] Plate-shaped portions 412 and three plate-shaped portions 413 are stacked vertically above the laminate 401. Specifically, the bottommost plate-shaped portion 412 is connected to the surface above the topmost plate-shaped portion 411 in the laminate 401 via a wafer bonding film 422. To embed the bonding wire 81a, the vertical thickness of the wafer bonding film 422 is greater than that of the wafer bonding films 421 and 423.

[0052] The second layer of plate-shaped portion 413 is connected to the surface above the bottommost plate-shaped portion 412 via a wafer bonding film 423. In this way, the plate-shaped portion 412 and the three plate-shaped portions 411 are stacked to form a laminate 402.

[0053] The Y-axis side of the laminate 402 is stepped. The step has a step surface (platform surface) SP2 that is parallel to the XY plane. Electrode pads 412d or 413d are located on the step surface SP2.

[0054] When viewed from above on surface 25a of wiring substrate 25, end 402a of laminate 402 on the Y-axis side is located further on the Y-axis side than end 401a of laminate 401 on the Y-axis side.

[0055] The sealing resin 65 seals at least one of the single-tower structures 501. Specifically, the sealing resin 65 covers the two single-tower structures 501 and the surface 25a of the wiring substrate 25 above the wiring substrate 25. The two single-tower structures 501 and the surface 25a of the wiring substrate 25 are insulated and sealed by the sealing resin 65.

[0056] The sealing resin 65 has a composition different from that of the molding resins 411c, 412c, or 413c. Furthermore, the sealing resin 65 has a composition different from that of the wafer bonding films 421, 422, or 423.

[0057] Specifically, the materials of the sealing resin 65, the molding resins 411c, 412c, or 413c, and the wafer bonding films 421, 422, or 423 are all different. Furthermore, some or all of the above materials may be the same.

[0058] More specifically, molding resins 411c, 412c, or 413c are, for example, resins used in fluoropolymer substrates without fiberglass cloth. Furthermore, molding resins 411c, 412c, or 413c may also contain fiberglass cloth. This increases the hardness of the molding resins 411c, 412c, or 413c.

[0059] (Manufacturing method of semiconductor device 11) Hereinafter, as an example of a method for manufacturing a semiconductor device according to this embodiment, the method for manufacturing semiconductor device 11 will be described.

[0060] First, such as Figure 5 As shown, a CMOS chip 410b is mounted on top of a silicon wafer 311. CMOS circuitry is formed on the surface above the semiconductor layer 61 in the CMOS chip 410b. Furthermore, an insulating layer 62, including a pad 51 (an example of a "first pad") and a wiring layer 62a, is formed above the CMOS circuitry in the semiconductor layer 61. The pad 51 is formed to be exposed substantially coplanar with the bonding surface 37 above the insulating layer 62.

[0061] Furthermore, beneath the semiconductor layer 71 in the memory chip 410a, an insulating layer 72 is formed, comprising a memory array 72a, vias 72b and 72c, a wiring layer 72d, and pads 52 (an example of a "second pad"). The semiconductor layer 71 contains, for example, silicon. The pads 52 are formed to be exposed substantially coplanar with the surface beneath the insulating layer 72. The vias 72c have a shape extending in the vertical direction. The lower end of the vias 72c is electrically connected to the pads 52.

[0062] Annealing is performed while pads 51 and 52 are in contact, bonding pads 51 and 52, thereby bonding memory chip 410a and CMOS chip 410b at the bonding surface 37. Specifically, pads 51 and 52 are bonded by direct bonding, where the copper in pads 51 and 52 directly adhere to each other. Thus, pads 51 and 52 are electrically and mechanically bonded. At this time, the upper surface of insulating layer 62 and the lower surface of insulating layer 72 are bonded by hydrogen bonding.

[0063] Next, as Figure 6 As shown, molding resin 410c is formed on top of silicon wafer 311. Thus, memory chip 410a and CMOS chip 410b are sealed by molding resin 410c.

[0064] Next, as Figure 7 As shown, the surface above the molding resin 410c is chemically and mechanically polished, thereby exposing the surface 22c of the memory chip 410a above the semiconductor layer 71 from the molding resin 410c. Then, the silicon wafer 311 is degassed and annealed.

[0065] Next, as Figure 8 As shown, after film formation, resist coating, exposure, development and stripping are performed on the surface 22c of the memory chip 410a by PEP (Photo Engraving Process), a hole 22b penetrating to the insulating layer 72 is formed in the memory chip 410a by reactive ion etching.

[0066] Next, as Figure 9 As shown, after film formation, resist coating, exposure, development and stripping are performed on the surface 22c of the memory chip 410a by the PEP method, an insulating layer 74 containing, for example, polyimide is formed on the top of the memory chip 410a.

[0067] Next, as Figure 10As shown, an insulating layer 75, which serves as a photoresist, is formed by performing film deposition, photoresist coating, exposure, development, and stripping on the surface above the insulating layer 74 using the PEP method. Then, electrode pads 410d are formed by nickel and gold vapor deposition.

[0068] Electrode pad 410d is electrically connected to the upper end of the pass 72c. Thus, electrode pad 410d is electrically connected to the CMOS circuit formed on semiconductor layer 61 through pass 72c, pad 52, pad 51 and wiring layer 62a.

[0069] The CMOS circuit is electrically connected to the memory array 72a through wiring layer 62a, pad 51, pad 52 and wiring layer 72d or path 72b.

[0070] Next, as Figure 11 As shown, for example, the insulating layer 75 is removed by etching.

[0071] Next, as Figure 12 As shown, the silicon wafer 311 is cut along the cutting line 112X. By performing chemical mechanical polishing on the lower surface of the separated silicon wafer 311, a portion of the silicon wafer 311 is separated into a plate-shaped portion 412 (see reference). Figure 1 and Figure 4 For example, silicon wafer 311 can be removed by chemical mechanical polishing. Alternatively, a portion of silicon wafer 311 can be retained by chemical mechanical polishing.

[0072] The separated memory chip 410a, CMOS chip 410b, molding resin 410c and electrode pad 410d become memory chip 412a, CMOS chip 412b, molding resin 412c and electrode pad 412d, respectively.

[0073] In addition, such as Figure 13 As shown, the silicon wafer 311 is cut along the cutting line 111X. By performing chemical mechanical polishing on the lower surface of the separated silicon wafer 311, a portion of the silicon wafer 311 is separated into plate-shaped portions 411 or 413 (see reference). Figures 1-3 The separated memory chip 410a, CMOS chip 410b, molding resin 410c, and electrode pad 410d become memory chip 411a, CMOS chip 411b, molding resin 411c, and electrode pad 411d, respectively. Since the plate-shaped portion 413 has the same structure as the plate-shaped portion 411, its description is omitted.

[0074] Next, as Figure 1As shown, four plate-shaped portions 411 are respectively disposed on the surface 25a of the wiring substrate 25 or the surface above the plate-shaped portions 411 below the surface via a wafer bonding film 421, thereby forming a laminate 401. Then, plate-shaped portions 412 are disposed on the surface above the laminate 401 via a wafer bonding film 422, and three plate-shaped portions 413 are respectively disposed on the surface above the plate-shaped portions 412 or the surface above the plate-shaped portions 413 below the surface via a wafer bonding film 423, thereby forming a laminate 402.

[0075] (Effect) Figure 14 This is a schematic diagram showing a cross-section of the semiconductor device involved in the comparative example from the side view. Figure 15 This is a top view of the semiconductor chip in the comparative example, taken from above. Furthermore, to facilitate understanding, Figure 15 The sealing resin 65 is not shown in the figure.

[0076] like Figure 14 and Figure 15 As shown, the semiconductor device 91 and semiconductor device 11 involved in the comparative example (refer to...) Figure 1 In comparison, the alternative to the 501 which has two single-tower structures is the 901 which has two single-tower structures.

[0077] In the single-tower structure 901, the laminate 401 is disposed above the laminate 401. In the single-tower structure 901, when viewed from above the surface 25a of the wiring substrate 25, the ends 402a of the two laminates 401 on the Y-axis direction side are aligned.

[0078] Therefore, the plurality of substrate electrodes 26a forming the bonding fingers and the plurality of substrate electrodes 26b forming the bonding fingers are arranged close together, thereby increasing the density of substrate electrodes 26a and 26b. Alternatively, if the substrate electrodes 26a and 26b are arranged separately, the length of the bonding line 81b will increase.

[0079] In contrast, in the semiconductor device 11, by configuring the width W2 of the plate-shaped portion 412 in the laminate 402 to be larger than the width W1 of the plate-shaped portion 411 in the laminate 401, it is possible to stably achieve a configuration in which the end 402a of the laminate 402 is located on the Y-axis side more than the end 401a of the laminate 401 when the surface 25a of the wiring substrate 25 is viewed from above.

[0080] Therefore, without increasing the length of the bonding wire 81b, the substrate electrode 26a and substrate electrode 26b can be configured separately, thus reducing the density of the substrate electrodes 26a and 26b. Furthermore, since the distance between the bonding wires 81a and 81b can be increased, a semiconductor device that reduces the mounting problems of the bonding wires 81a and 81b and improves quality can be provided.

[0081] (Second Implementation) The semiconductor device according to the second embodiment will be described. From the second embodiment onwards, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same effects obtained through the same configuration will not be mentioned repeatedly in each embodiment.

[0082] Figure 16 This is a schematic diagram showing a cross-section of the semiconductor device according to the second embodiment. Furthermore, Figure 16 Observation methods and Figure 1 same.

[0083] like Figure 16 As shown, with Figure 1 Compared to the semiconductor device 11 shown, the semiconductor device 12 differs from the semiconductor device 11 of the first embodiment in that the two plate-shaped portions 412 included in the two single-tower structures 501 are combined into one to form a double-tower connection structure 502.

[0084] and Figure 1 Compared to the semiconductor device 11 shown, the semiconductor device 12 has a dual-tower connection structure 502 instead of two single-tower structures 501.

[0085] The dual-tower connection structure 502 includes bonding wires 81a (an example of a "first bonding wire"), 81b (an example of a "second bonding wire"), 81c (an example of a "third bonding wire"), and 81d (an example of a "fourth bonding wire"), as well as laminates 401 (an example of a "first laminate"), 402 (an example of a "second laminate"), and 403 (an example of a "third laminate").

[0086] The laminate 403 includes N plate-shaped portions 414 (an example of a "fourth plate-shaped portion") and N wafer bonding films 424. In this embodiment, the laminate 403 has the same configuration as the component after the laminate 401 is rotated 180° about the Z-axis.

[0087] In detail, the laminate 403 includes four plate-shaped portions 414 and four wafer bonding films 424. The plate-shaped portions 414 have a width W1 in the Y-axis direction. Furthermore, the width W1 of each plate-shaped portion 414 can also fluctuate within the range of manufacturing tolerances.

[0088] The plate-shaped portion 414 includes a memory chip 414a (an example of a "fourth memory chip"), a CMOS chip 414b (an example of a "second semiconductor chip"), a molding resin 414c (an example of a "resin layer"), and a plurality of electrode pads 414d (an example of a "fourth electrode pad").

[0089] The memory chip 414a, CMOS chip 414b, molding resin 414c, electrode pad 414d, and wafer bonding film 424 are the same as those in the plate-shaped portion 411.

[0090] The memory chip 414a is located closer to the end of the plate-shaped portion 414 in the Y-axis direction than the end in the Y-axis direction. On the surface above the memory chip 414a, the same number of electrode pads 414d as the number of substrate electrodes 26a forming the bonding fingers are provided.

[0091] Multiple electrode pads 414d are located closer to the Y-axis+ direction end than the Y-axis-side end of the memory chip 414a, and are arranged in a row along the X-axis direction. Each of the multiple electrode pads 414d is electrically connected to multiple substrate electrodes 26a via bonding wires 81c.

[0092] Four plate-shaped portions 414 are stacked vertically along the Y-axis+ direction of the laminate 401. Specifically, the bottommost plate-shaped portion 414 is connected to the surface 25a of the wiring substrate 25, for example, via a wafer bonding film 424 with a width W1 in the Y-axis direction. The second layer of plate-shaped portions 414 below is connected to the surface above the bottommost plate-shaped portion 414 via the wafer bonding film 424. Thus, the four plate-shaped portions 414 are stacked to form the laminate 403.

[0093] The Y-axis+ direction side of the laminate 403 is stepped. The step has a step surface (platform surface) SP3 parallel to the XY plane. The electrode pad 414d is located on the step surface SP3.

[0094] and Figure 1 Compared to the stack 402 shown, the stack 402 in the semiconductor device 12 also includes three plate-shaped portions 415 (an example of a "fifth plate-shaped portion") and three wafer bonding films 425.

[0095] and Figure 1 Compared to the plate-shaped portion 412 shown, the plate-shaped portion 412 in the semiconductor device 12 also includes a memory chip 412f (an example of a "fifth memory chip"), a CMOS chip 412g, and a plurality of electrode pads 412i (an example of a "fifth electrode pad").

[0096] The plate-shaped portion 412 is provided on the surface above the laminate 401 and the surface above the laminate 403.

[0097] A wafer bonding film 422 (an example of a "second resin layer") is disposed between the plate-shaped portion 412 and the laminates 401 and 403 in the laminate 402. Specifically, the upper surface of the wafer bonding film 422 is in contact with the lower surface of the plate-shaped portion 412. The lower surface of the wafer bonding film 422 is in contact with the upper surfaces of the laminates 401 and 403.

[0098] The memory chip 412f in the plate-shaped portion 412 has the same structure as the component after rotating the memory chip 412a 180° about the Z-axis.

[0099] The memory chip 412f is disposed on the Y-axis+ direction side of the molding resin 412c. In this embodiment, the memory chip 412f is located closer to the Y-axis+ direction side end of the plate-shaped portion 412 than the end of the plate-shaped portion 412 on the Y-axis-direction side, and is connected to the Y-axis+ direction side of the molding resin 412c.

[0100] An electrode pad 412i is provided on the surface above the memory chip 412f, with the same number of electrode pads 412i as the number of substrate electrodes 26b forming the bonding fingers.

[0101] Multiple electrode pads 412i are located closer to the Y-axis+ direction end than the Y-axis-direction end of the memory chip 412f, and are arranged in a row along the X-axis direction. Each of the multiple electrode pads 412i is electrically connected to multiple substrate electrodes 26b via bonding wires 81d.

[0102] A CMOS chip 412g is attached to the surface below the memory chip 412f. The CMOS chip 412g has the same structure as the component after rotating the CMOS chip 412b 180° about the Z-axis.

[0103] In this embodiment, the three plate-shaped portions 415 have the same configuration as the component after the three plate-shaped portions 413 are rotated 180° about the Z-axis.

[0104] Specifically, three plate-shaped portions 415 are provided on the Y-axis+ direction side of the three plate-shaped portions 413. Each plate-shaped portion 415 has a width W1 in the Y-axis direction. Furthermore, the width W1 of each plate-shaped portion 415 can fluctuate within the range of manufacturing tolerances.

[0105] The plate-shaped portion 415 includes a memory chip 415a (an example of a "sixth memory chip"), a CMOS chip 415b (an example of a "second semiconductor chip"), a molding resin 415c (an example of a "resin layer"), and a plurality of electrode pads 415d (an example of a "sixth electrode pad").

[0106] The memory chip 415a, CMOS chip 415b, molding resin 415c, electrode pad 415d and wafer bonding film 425 are the same as the memory chip 411a, CMOS chip 411b, molding resin 411c, electrode pad 411d and wafer bonding film 421 in the plate-shaped portion 411.

[0107] The memory chip 415a is located closer to the end of the plate-shaped portion 415 in the Y-axis direction than the end in the Y-axis direction. On the surface above the memory chip 415a, the same number of electrode pads 415d as the number of substrate electrodes 26b forming the bonding fingers are provided.

[0108] Multiple electrode pads 415d are located closer to the Y-axis+ direction end than the Y-axis-side end of the memory chip 415a, and are arranged in a row along the X-axis direction. The multiple electrode pads 415d are electrically connected to multiple substrate electrodes 26b via bonding wires 81d.

[0109] Three plate-shaped portions 415 are stacked vertically above plate-shaped portions 412 and along the Y-axis+ direction of the three plate-shaped portions 413. Specifically, the bottommost plate-shaped portion 415 is connected to the upper surface of plate-shaped portion 412 via a wafer bonding film 425. The second layer of plate-shaped portions 415 is connected to the upper surface of the bottommost plate-shaped portion 415 via a wafer bonding film 425. Thus, the three plate-shaped portions 415 are stacked to form a laminate 402.

[0110] The Y-axis+ direction side of the laminate 402 is stepped. The step has a step surface (platform surface) SP4 parallel to the XY plane. Electrode pads 412i or 415d are located on the step surface SP4.

[0111] When viewed from above on surface 25a of wiring substrate 25, end 402b of laminate 402 on the Y-axis + direction side is located further on the Y-axis + direction side than end 403a of laminate 403 on the Y-axis + direction side.

[0112] (Manufacturing method of semiconductor device 12) As a method for manufacturing semiconductor device 12, firstly as Figure 17 As shown, when the CMOS chip 410b on the Y-axis side and the CMOS chip 410b on the Y-axis+ side are placed on the silicon wafer 311, they are placed in the same orientation as the other after rotating it 180° with the Z-axis as the rotation axis.

[0113] Specifically, in the CMOS chip 410b on the Y-axis side, the electrode pad 410d is located on the Y-axis side. On the other hand, in the CMOS chip 410b on the Y-axis side, the electrode pad 410d is located on the Y-axis side.

[0114] Next, proceed with... Figures 6-11 The process shown is the same.

[0115] Next, as Figure 18 As shown, the silicon wafer 311 is cut along the cutting line 122X. By performing chemical mechanical polishing on the lower surface of the separated silicon wafer 311, a portion of the silicon wafer 311 is separated into a plate-shaped portion 412 (see reference). Figure 16 ).

[0116] The separated Y-axis-direction side storage chip 410a and Y-axis+direction side storage chip 410a become storage chip 412a and storage chip 412f, respectively.

[0117] The separated Y-axis-direction side CMOS chip 410b and Y-axis+direction side CMOS chip 410b become CMOS chip 412b and CMOS chip 412g, respectively.

[0118] The separated electrode pads 410d on the Y-axis and Y+ directions become electrode pads 412d and 412i, respectively.

[0119] (Effect) Thus, by utilizing the configuration where the plate-shaped portion 412 in the laminate 402 extends over the upper surface of the laminate 401 and the upper surface of the laminate 403, the rigidity against warping of the wiring substrate 25 can be improved, thereby suppressing warping of the wiring substrate 25. Therefore, a semiconductor device with improved quality can be provided.

[0120] (First variation of semiconductor device 12) Figure 19 This is a schematic cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment. Figure 19 As shown, the first variation of semiconductor device 12, namely semiconductor device 12A and Figure 16 The difference in the semiconductor device 12 shown is that a controller chip 63A (an example of a “first semiconductor chip”) is provided between the stacked bodies 401 and 403 and is connected to the surface 25a of the wiring substrate 25.

[0121] The control chip 63A is, for example, flip-chip connected to the wiring substrate 25 and electrically connected to the wiring substrate 25. The control chip 63A controls, for example, CMOS chips 411b, 412b, 412g, 413b, 414b, and 415b.

[0122] By forming a stepped configuration on the Y-axis side of the stacked body 401 and the Y-axis+ side of the stacked body 403, a downwardly extending space is formed between the stacked bodies 401 and 402. By configuring the control chip 63A in such a space, the space of the semiconductor device 12A can be utilized efficiently, and the size of the semiconductor device 12A can be made more compact.

[0123] (Second variation of semiconductor device 12) Figure 20 This is a schematic cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment. For example... Figure 20 As shown, the second variation of semiconductor device 12, namely semiconductor device 12B, and Figure 19 The difference in the semiconductor device 12A shown is that the plate-shaped portion 412 also includes a molding resin 412h (an example of a "third resin layer") connected to the Y-axis direction side of the memory chip 412f, and a semiconductor layer 451B (an example of a "first semiconductor layer") connected to the Y-axis + direction side of the molding resin 412c and the Y-axis - direction side of the molding resin 412h.

[0124] Semiconductor layer 451B contains, for example, silicon. Semiconductor layer 451B is, for example, a spacer. The rigidity of semiconductor layer 451B is higher than that of molding resins 412c and 412h. Furthermore, semiconductor layer 451B can also be formed using non-semiconductor materials, provided that the rigidity is high and there is no electrical interference with other chips.

[0125] Thus, by providing a semiconductor layer 451B between the memory chip 412a and the CMOS chip 412b, and between the memory chip 412f and the CMOS chip 412g, the bending rigidity of the plate-shaped portion 412 can be improved. This effectively suppresses warping of the wiring substrate 25.

[0126] (Third variation of semiconductor device 12) Figure 21 This is a schematic cross-sectional view showing a third variation of the semiconductor device according to the second embodiment. (As shown) Figure 21 As shown, the third variation of semiconductor device 12, namely semiconductor device 12C, and Figure 19 The difference in the semiconductor device 12A shown is that it also has a semiconductor layer 451C (an example of a “first semiconductor layer”) disposed above the molding resin 412c.

[0127] Semiconductor layer 451C is the same as semiconductor layer 451B. In this modified example, the lower surface of semiconductor layer 451C is in contact with the upper surface of molding resin 412c. As a result, bending deformation of molding resin 412c can be suppressed. That is, since the bending rigidity of plate-shaped portion 412 can be improved, warping of wiring substrate 25 can be effectively suppressed.

[0128] Alternatively, it can be placed below semiconductor layer 451C. Figure 20 The semiconductor layer 451B shown is constructed as follows.

[0129] (Fourth variation of semiconductor device 12) Figure 22 This is a schematic cross-sectional view showing a fourth variation of the semiconductor device according to the second embodiment. Figure 22 As shown, the fourth modification of semiconductor device 12, namely semiconductor device 12D, and... Figure 19 The difference in the semiconductor device 12A shown is that it also has a semiconductor layer 451D (an example of a “first semiconductor layer”) disposed below the molding resin 412c.

[0130] Semiconductor layer 451D is the same as semiconductor layer 451B. In this variation, the upper surface of semiconductor layer 451D is in contact with wafer bonding film 422. The lower surface of semiconductor layer 451D is connected to the upper surface of control chip 63A, for example, via wafer bonding film (not shown).

[0131] Therefore, bending deformation of the molding resin 412c can be suppressed. That is, warping of the wiring substrate 25 can be effectively suppressed by increasing the bending rigidity of the plate-shaped portion 412.

[0132] Alternatively, a semiconductor layer 451B can be disposed above the semiconductor layer 451D (see reference). Figure 20 ) and semiconductor layer 451C (refer to Figure 21 It is a component of at least one of the following.

[0133] (Fifth variation of semiconductor device 12) Figure 23 This is a schematic cross-sectional view showing a fifth variation of the semiconductor device according to the second embodiment. (As shown) Figure 23 As shown, the fifth modification of semiconductor device 12, namely semiconductor device 12E, and... Figure 19 The difference in the semiconductor device 12A shown is that the upper surface of the control chip 63E is in contact with the wafer bonding film 422.

[0134] and Figure 19Compared to the semiconductor device 12A shown, the semiconductor device 12E replaces the control chip 63A with a control chip 63E. The vertical height of the control chip 63E is greater than that of the control chip 63A. The upper surface of the control chip 63E is aligned with the upper surface of the laminate 401 and the upper surface of the laminate 403.

[0135] This configuration helps to suppress the bending deformation of the molding resin 412c. That is, by increasing the bending rigidity of the plate-shaped portion 412, the warping of the wiring substrate 25 can be effectively suppressed.

[0136] (Sixth variation of semiconductor device 12) Figure 24 This is a schematic cross-sectional view showing a sixth modified example of the semiconductor device according to the second embodiment. Figure 24 As shown, the sixth variation of semiconductor device 12, namely semiconductor device 12F, and Figure 19 The difference in the semiconductor device 12A shown is that multiple stacked bodies 402 are stacked.

[0137] and Figure 19 Compared to the dual-tower connection structure 502 in the semiconductor device 12A shown, the dual-tower connection structure 502 in the semiconductor device 12F includes stacked bodies 402A, 402B, and 402C instead of stacked body 402, and also includes bonding lines 81c and 81d.

[0138] Laminated bodies 402A, 402B, and 402C are examples of laminated body 402. In this modified example, two plate-shaped portions 411 and two plate-shaped portions 414 are laminated in laminated bodies 401 and 403, respectively. Alternatively, three or more plate-shaped portions 411 may be laminated in laminated body 401. In this case, the same number of plate-shaped portions 414 as in laminated body 401 are laminated in laminated body 403.

[0139] The laminates 402A, 402B, and 402C are stacked sequentially from bottom to top. In the laminates 402A, 402B, and 402C, plate-shaped portions 413 and 415 are stacked on the surface above the plate-shaped portion 412 on the Y-axis-direction side and the Y-axis+direction side, respectively.

[0140] Alternatively, the following configuration can be adopted: in the laminated bodies 402A, 402B, and 402C, two or more plate-shaped portions 413 are laminated on the surface above the plate-shaped portion 412 in the Y-axis direction. In this case, the same number of plate-shaped portions 415 as the plate-shaped portions 413 are laminated in the Y-axis direction.

[0141] In addition, the number of plate-shaped portions 413 stacked in laminate 402A, the number of plate-shaped portions 413 stacked in laminate 402B, and the number of plate-shaped portions 413 stacked in laminate 402C may be partially the same or different from each other.

[0142] The width of the laminate 402A in the Y-axis direction, the width of the laminate 402B in the Y-axis direction, and the width of the laminate 402C in the Y-axis direction increase sequentially.

[0143] When viewed from above on surface 25a of the wiring substrate 25, the Y-axis side end 402Ca of the laminate 402C, the Y-axis side end 402Ba of the laminate 402B, and the Y-axis side end 402Aa of the laminate 402A are located closer to the Y-axis side than the Y-axis side end 402Ba, the Y-axis side end 402Aa, and the Y-axis side end 401a of the laminate 401, respectively.

[0144] When viewed from above on surface 25a of the wiring substrate 25, the Y-axis + direction side end 402Cb of laminate 402C, the Y-axis + direction side end 402Bb of laminate 402B, and the Y-axis + direction side end 402Ab of laminate 402A are located closer to the Y-axis + direction side than the Y-axis + direction side end 402Bb, end 402Ab, and the Y-axis + direction side end 403a of laminate 403, respectively.

[0145] With this configuration, the electrode spacing in the Y-axis direction of the substrate electrodes 26a-26d can be increased without increasing the length of the bonding wires 81a-81d. This allows for a reduction in the density of the substrate electrodes 26a-26d.

[0146] (Seventh variation of semiconductor device 12) Figure 25 This is a schematic cross-sectional view showing a seventh modified example of the semiconductor device according to the second embodiment. Figure 25 As shown, the seventh modification of semiconductor device 12, namely semiconductor device 12G, and Figure 16 The difference in the semiconductor device 12 shown is that the width direction D1 (an example of the "first width direction") of the stacked bodies 401 and 403 is approximately orthogonal to the width direction D2 (an example of the "second width direction") of the plate-like portions 413 and 415 in the stacked body 402.

[0147] In this variation, the width directions D1 and D2 are approximately parallel to the Y-axis and X-axis directions, respectively.

[0148] On the surface above the plate-shaped portion 412, three plate-shaped portions 413 are stacked vertically on the X-axis-direction side (an example of the "fourth side"), and three plate-shaped portions 415 are stacked vertically on the X-axis+direction side (an example of the "third side").

[0149] Multiple substrate electrodes 26b forming bonding fingers are provided on the X-axis + direction side and the X-axis - direction side of the laminate 402.

[0150] The X-axis side of the laminate 402 is stepped. The step has a step surface SP2 parallel to the XY plane. Electrode pads 412d or 413d are located on the step surface SP2.

[0151] The X-axis+ direction side of the laminate 402 is stepped. The step has a step surface SP4 parallel to the XY plane. Electrode pads 412i or 415d are located on the step surface SP4.

[0152] Furthermore, this variation illustrates a configuration where the width direction D1 and width direction D2 are approximately orthogonal, but it is not limited to this. The angle formed between the width direction D1 and width direction D2 can be any angle within the range of 0° to 180°.

[0153] (Third Implementation) The semiconductor device involved in the third embodiment is described. Figure 26 This is a schematic diagram showing a cross-section of the semiconductor device according to the third embodiment. Furthermore, Figure 26 Observation methods and Figure 1 same.

[0154] like Figure 26 As shown, with Figure 1 Compared to the semiconductor device 11 shown, the semiconductor device 13 differs from the semiconductor device 11 in the first embodiment in that, while the laminates 401 and 402 are respectively arranged below and above, two single-tower structures 501 are stacked in the vertical direction to form a single-tower structure 501A.

[0155] and Figure 1 Compared to the semiconductor device 11 shown, the semiconductor device 13 has a single tower structure 501A instead of two single tower structures 501.

[0156] The single-tower structure 501A includes a control chip 63A, laminates 401L and 401U, and laminates 402L and 402U.

[0157] Laminated bodies 401L and 401U are examples of laminated body 401. In this embodiment, two plate-shaped portions 411 are laminated in laminated bodies 401L and 401U respectively. Alternatively, three or more plate-shaped portions 411 may be laminated in laminated bodies 401L and 401U respectively.

[0158] Laminated bodies 402L and 402U are examples of laminated body 402. In this embodiment, plate-shaped portions 412 and 413 are laminated in laminated bodies 402L and 402U, respectively. Alternatively, a configuration in which plate-shaped portions 412 and multiple plate-shaped portions 413 are laminated in each laminated body 402L and 402U may also be adopted.

[0159] The control chip 63A, the stacked bodies 401L, 401U, 402L and 402U are stacked sequentially from bottom to top.

[0160] The Y-axis+ direction side of laminates 401L and 402L is stepped. The Y-axis- direction side of laminates 401U and 402U is stepped.

[0161] When viewed from above on surface 25a of wiring substrate 25, end 402La of laminate 402L on the Y-axis + direction side is located further on the Y-axis + direction side than end 401La of laminate 401L on the Y-axis + direction side.

[0162] When viewed from above on surface 25a of wiring substrate 25, end 402Ua of laminate 402U on the Y-axis direction side is located further on the Y-axis direction side than end 401Ua of laminate 401U on the Y-axis direction side.

[0163] (Fourth Implementation) The semiconductor device involved in the fourth embodiment is described. Figure 27 This is a schematic diagram showing a cross-section of the semiconductor device according to the fourth embodiment. Furthermore, Figure 27 Observation methods and Figure 1 same.

[0164] like Figure 27 As shown, with Figure 1 Compared to the semiconductor device 11 shown, the semiconductor device 14 differs from the semiconductor device 11 in the first embodiment in that two stacked bodies 401 facing opposite directions are combined to form a stacked body 404.

[0165] and Figure 1 Compared to the semiconductor device 11 shown, the semiconductor device 14 has a dual-tower connection structure 503 instead of two single-tower structures 501.

[0166] The dual-tower connection structure 503 includes bonding wires 81a, 81b, 81c, 81d, and laminates 404L and 404U. Hereinafter, laminates 404L and 404U will each be referred to as laminate 404 (an example of a "fourth laminate").

[0167] The laminate 404L includes L (L is an integer greater than or equal to 1) plate-shaped portions 416 (an example of a "sixth plate-shaped portion"), L plate-shaped portions 417 (an example of a "seventh plate-shaped portion"), plate-shaped portions 418 (an example of an "eighth plate-shaped portion"), L wafer bonding films 426, L wafer bonding films 427, and wafer bonding films 428.

[0168] The laminate 404U includes K (K is an integer greater than or equal to 1) plate-shaped portions 416 (an example of a "ninth plate-shaped portion"), K plate-shaped portions 417 (an example of a "tenth plate-shaped portion"), plate-shaped portions 418 (an example of an "eleventh plate-shaped portion"), K wafer bonding films 426, K wafer bonding films 427, and wafer bonding films 428.

[0169] In this embodiment, the laminates 404L and 404U each include three plate-shaped portions 416, three plate-shaped portions 417, three plate-shaped portions 418, three wafer bonding films 426, three wafer bonding films 427, and a wafer bonding film 428.

[0170] The laminate 404U is stacked on top of the laminate 404L. The following description will focus on the lower laminate 404L, but the same applies to the upper laminate 404U.

[0171] The plate-shaped portion 416 has a width W1 in the Y-axis direction. The plate-shaped portion 416 includes a memory chip 416a (an example of a "seventh memory chip" and an "eleventh memory chip"), a CMOS chip 416b (an example of a "second semiconductor chip"), a molding resin 416c (an example of a "resin layer"), and a plurality of electrode pads 416d.

[0172] The memory chip 416a, CMOS chip 416b, molding resin 416c, electrode pad 416d and wafer bonding film 426 are the same as the memory chip 411a, CMOS chip 411b, molding resin 411c, electrode pad 411d and wafer bonding film 421 in the plate-shaped portion 411.

[0173] The memory chip 416a is located closer to the end of the plate-shaped portion 416 in the Y-axis direction than the end in the Y-axis+ direction. On the surface above the memory chip 416a, the same number of electrode pads 416d as the number of substrate electrodes 26a forming the bonding fingers are provided.

[0174] Multiple electrode pads 416d are located closer to the Y-axis side than the Y-axis side of the memory chip 416a, and are arranged in a row along the X-axis. The multiple electrode pads 416d are electrically connected to multiple substrate electrodes 26a via bonding wires 81a.

[0175] Three plate-shaped portions 416 are stacked vertically above the wiring substrate 25. Specifically, the bottommost plate-shaped portion 416 is connected to the surface 25a of the wiring substrate 25, for example, via a wafer bonding film 426 with a width W1 in the Y-axis direction. The second layer of plate-shaped portions 416 below is connected to the surface above the bottommost plate-shaped portion 416 via the wafer bonding film 426. Thus, three plate-shaped portions 416 are stacked.

[0176] The three plate-shaped portions 417 have the same structure as the component after the three plate-shaped portions 416 are rotated 180° about the Z-axis.

[0177] The plate-shaped portion 417 includes a memory chip 417a (an example of an "eighth memory chip" and a "twelfth memory chip"), a CMOS chip 417b (an example of a "second semiconductor chip"), a molding resin 417c (an example of a "resin layer"), and a plurality of electrode pads 417d.

[0178] The memory chip 417a, CMOS chip 417b, molding resin 417c, electrode pad 417d, and wafer bonding film 427 are the same as those in the plate-shaped portion 411.

[0179] The memory chip 417a is located closer to the end of the plate-shaped portion 417 in the Y-axis direction than the end in the Y-axis direction. On the surface above the memory chip 417a, the same number of electrode pads 417d as the number of substrate electrodes 26a forming the bonding fingers are provided.

[0180] Multiple electrode pads 417d are located closer to the Y-axis+ direction end than the Y-axis-direction end of the memory chip 417a, and are arranged in a row along the X-axis direction. The multiple electrode pads 417d are electrically connected to multiple substrate electrodes 26a via bonding wires 81c.

[0181] Three plate-shaped portions 417 are stacked vertically along the Y-axis+ direction side of the three plate-shaped portions 416. Specifically, the bottommost plate-shaped portion 417 is connected to the surface 25a of the wiring substrate 25, for example, via a wafer bonding film 427 with a width W1 in the Y-axis direction. The second layer of plate-shaped portions 417 is connected to the surface above the bottommost plate-shaped portion 417 via the wafer bonding film 427. Thus, three plate-shaped portions 417 are stacked.

[0182] The plate-shaped portion 418 includes memory chips 418a (an example of "ninth memory chip" and "thirteenth memory chip") and 418f (an example of "tenth memory chip" and "fourteenth memory chip"), CMOS chip 418b (an example of "second semiconductor chip"), molding resin 418c (an example of "fourth resin layer" and "fifth resin layer"), and multiple electrode pads 418d and 418i.

[0183] The plate-shaped portion 418 has a width W2. The plate-shaped portion 418 is provided on the surface above the uppermost plate-shaped portion 416 and the surface above the uppermost plate-shaped portion 417.

[0184] A wafer bonding film 428 is disposed between the plate-shaped portion 418 and the uppermost plate-shaped portions 416 and 417. Specifically, the upper surface of the wafer bonding film 428 is in contact with the lower surface of the plate-shaped portion 418. The lower surface of the wafer bonding film 428 is in contact with the upper surfaces of the uppermost plate-shaped portions 416 and 417.

[0185] Memory chip 418a is related to memory chip 412a (see reference). Figure 1 The same memory chip. The memory chip 418a is located closer to the end of the plate-shaped portion 418 in the Y-axis direction than the end in the Y-axis+ direction.

[0186] An electrode pad 418d is provided on the surface above the memory chip 418a, with the same number of electrode pads 418d as the substrate electrodes 26a forming the bonding fingers.

[0187] Multiple electrode pads 418d are located closer to the Y-axis side than the Y-axis side of the memory chip 418a, and are arranged in a row along the X-axis. The multiple electrode pads 418d are electrically connected to multiple substrate electrodes 26a via bonding wires 81a.

[0188] The molding resin 418c is connected to the Y-axis+ direction side of the memory chip 418a. The memory chip 418f is located closer to the Y-axis+ direction side end of the plate-shaped portion 418 than the Y-axis- direction side end of the plate-shaped portion 418, and is connected to the Y-axis+ direction side of the molding resin 418c.

[0189] The memory chip 418f has the same structure as the component after rotating the memory chip 418a 180° about the Z-axis.

[0190] On the surface above the memory chip 418f, there is a number of electrode pads 418i that are the same number as the number of substrate electrodes 26a forming the bonding fingers.

[0191] Multiple electrode pads 418i are located closer to the Y-axis+ direction end than the Y-axis-direction end of the memory chip 418f, and are arranged in a row along the X-axis direction. The multiple electrode pads 418i are electrically connected to multiple substrate electrodes 26a via bonding wires 81c.

[0192] CMOS chip 418b is related to CMOS chips 412b and 412g (see reference). Figure 16 The CMOS chip 418b controls the memory chips 418a and 418f. The width of the CMOS chip 418b in the Y-axis direction is approximately twice the width of the CMOS chip 412b or CMOS chip 412g in the Y-axis direction. The memory chips 418a and 418f are respectively attached to the mating surfaces on the Y-axis-direction side and the Y-axis+direction side of the surface above the CMOS chip 418b.

[0193] The molding resin 418c is attached to the upper surface of the CMOS chip 418b (excluding the bonding surface), and to the side surfaces of the memory chips 418a and 418f that are parallel to the ZX surface and parallel to the YZ surface.

[0194] A wafer bonding film 428 with a width W2 is disposed on the surface below the CMOS chip 418b.

[0195] The bottom plate-shaped portions 416 and 417 in the laminate 404U are connected to the surface above the plate-shaped portion 418 in the laminate 404L via wafer bonding films 426 and 427, respectively.

[0196] The Y-axis+ direction side of the laminates 404L and 404U is stepped. The Y-axis- direction side of the laminates 404L and 404U is stepped.

[0197] When viewed from above, the Y-axis side end 404a of the bottom plate-shaped portion 416 in the laminate 404U is located further to the Y-axis side than the Y-axis side end 404c of the plate-shaped portion 418 in the laminate 404L.

[0198] When viewed from above on surface 25a of wiring substrate 25, the end 404b of the bottom plate-shaped portion 417 in laminate 404U is located further to the Y-axis + direction side than the end 404d of the plate-shaped portion 418 in laminate 404L.

[0199] Furthermore, although it has been stated that the number of plates 416 in the laminate 401L and the number of plates 416 in the laminate 401U are the same, this is not a limitation. It is also possible to use a configuration where the number of plates 416 in the laminate 401L and the number of plates 416 in the laminate 401U are different.

[0200] Alternatively, it can be configured as follows: In the plate-shaped portion 418, a semiconductor layer 451B is provided between the memory chip 418a and the memory chip 418f (see reference). Figure 20 ).

[0201] (Manufacturing method of semiconductor device 14) As a method for manufacturing semiconductor device 14, firstly as Figure 28 As shown, a plurality of CMOS chips 410b are formed on the surface above the silicon wafer 311, arranged along the Y-axis.

[0202] In the two adjacent CMOS chip 410b dies along the Y-axis direction, the CMOS chip 410b die on the Y-axis side (hereinafter, sometimes referred to as CMOS die CDL) is formed in the same way as the CMOS chip 410b die on the Y-axis side (hereinafter, sometimes referred to as CMOS die CDR) after being rotated 180° about the Z-axis.

[0203] Next, as Figure 29 As shown, two memory chips 410a are attached to the CMOS die CDL and CDR respectively. At this time, the orientation of one of the memory chips 410a is the same as the orientation of the other memory chip 410a after rotating it 180° around the Z-axis.

[0204] Specifically, in the CMOS die CDL on the Y-axis side, the memory chip 410a is bonded such that the passage 72c connected to the electrode pad 410d is located on the Y-axis side. On the other hand, in the CMOS die CDR on the Y-axis side, the memory chip 410a is bonded such that the passage 72c connected to the electrode pad 410d is located on the Y-axis side.

[0205] Next, proceed with... Figures 6-11 The process shown is the same as the process described.

[0206] Next, as Figure 30 As shown, the silicon wafer 311 is cut along the cutting line 132X, and the lower surface of the separated silicon wafer 311 is chemically and mechanically polished, thereby separating a portion of the silicon wafer 311 into a plate-shaped portion 418 (see reference). Figure 27 ).

[0207] The separated Y-axis-direction side storage chip 410a and Y-axis+direction side storage chip 410a become storage chip 418a and storage chip 418f, respectively.

[0208] The CMOS die CDL and CMOS die CDR are separated in an integrated state to form a CMOS chip 418b.

[0209] The separated electrode pads 410d on the Y-axis and Y+ directions become electrode pads 418d and 418i, respectively.

[0210] (a) In this embodiment, the configuration of the plate-shaped portion 411 including a memory chip 411a, which is a NAND flash memory chip, and a CMOS chip 411b, which controls the memory chip 411a, has been described, but it is not limited thereto. The plate-shaped portion 411 may also include a chip of volatile memory such as DRAM (Dynamic Random Access Memory) instead of the memory chip 411a. In addition, the plate-shaped portion 411 may include both a chip of non-volatile memory and a chip of volatile memory. Furthermore, the CMOS chip 411b may also include a chip of CPU (Central Processing Unit) which has arithmetic and control functions. The same applies to plate-shaped portions 412 to 418.

[0211] (b) A semiconductor device comprising: Wiring substrate having a main surface that intersects with the vertical direction; A first laminate comprising N first plate-like portions having a first width in a first width direction intersecting the vertical direction, the N first plate-like portions being stacked above the wiring substrate along the vertical direction; and The second laminate includes: a second plate-shaped portion having a second width greater than the first width in the first width direction, disposed above the first laminate; and M third plate-shaped portions disposed above the second plate-shaped portion, having the first width in the first width direction, wherein the second plate-shaped portion and the M third plate-shaped portions are laminated along the vertical direction. The first plate-shaped portion includes a first memory chip. The second plate-shaped portion includes a second memory chip and a first resin layer connected to a first side of the second memory chip in the first width direction. The third plate-shaped portion includes a third memory chip. The second side, opposite to the first side in the first width direction of the first laminate, becomes stepped. The second side of the second laminate becomes stepped. When viewed from above, the end of the second side of the second laminate is located further to the second side than the end of the second side of the first laminate.

[0212] (c) The semiconductor device further comprises a sixth resin layer having a composition different from that of the first resin layer, sealing the first laminate and the second laminate.

[0213] The present embodiment has been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. As long as it has the features of this disclosure, any configuration obtained by those skilled in the art by making appropriate design changes to these specific examples is also included within the scope of this disclosure. The elements, their configurations, conditions, shapes, etc., possessed by the foregoing specific examples are not limited to the illustrated contents and can be appropriately modified. The elements possessed by the foregoing specific examples can be appropriately combined as long as they do not create technical contradictions. Explanation of reference numerals in the attached figures

[0214] 11, 12, 12A, 12B, 12C, 12D, 12E, 12F, 12G, 13, 14… Semiconductor devices 25… Wiring substrate 25a… 26a, 26b, 26c, 26d… Substrate electrodes 63A, 63E... control chips 65…sealing resin 81a, 81b, 81c, 81d… bond wires 401, 401L, 401U... laminated bodies 401a, 401La, 401Ua… End caps 402, 402A, 402B, 402C, 402L, 402U… laminated bodies 402a, 402b, 402Aa, 402Ab, 402Ba, 402Bb, 402Ca, 402Cb, 402La, 402Ua...end 403…Laminated body 403a…end 404, 404U, 404L... laminated materials 411, 412, 414, 415, 416, 417, 418... plate-shaped part 411a, 412a, 412f, 413a, 414a, 415a, 416a, 417a, 418a, 418f… memory chips CMOS chips: 411b, 412b, 412g, 413b, 414b, 415b, 416b, 417b, 418b… 411c, 412c, 412h, 413c, 414c, 415c, 416c, 417c, 418c… Molding resin 411d, 412d, 412i, 413d, 414d, 415d, 416d, 417d, 418d, 418i… electrode pads 421, 422, 423, 424, 425, 426, 427, 428… wafer bonding film 451B, 451C, 451D… Semiconductor Layers 501, 501A... Single tower structure 502, 503... Twin-tower connection structure

Claims

1. A semiconductor device, have: Wiring substrate having a main surface that intersects with the vertical direction; A first laminate comprises N first plate-shaped portions having a first width in a first width direction intersecting the vertical direction, wherein the N first plate-shaped portions are stacked above the wiring substrate along the vertical direction. N is an integer greater than 2; as well as The second laminate includes: a second plate-shaped portion having a second width greater than the first width in the first width direction, disposed above the first laminate; and M third plate-shaped portions disposed above the second plate-shaped portion, having the first width in the first width direction, wherein the second plate-shaped portion and the M third plate-shaped portions are stacked along the vertical direction, wherein M is an integer greater than or equal to 1. The first plate-shaped portion includes a first memory chip, and the upper surface of the first memory chip is provided with a first electrode pad that is electrically connected to the wiring substrate via a first bonding wire. The second plate-shaped portion includes: a second memory chip, the upper surface of which is provided with a second electrode pad electrically connected to the wiring substrate via a second bonding wire; and a first resin layer connected to a first side of the second memory chip in the first width direction. The third plate-shaped portion includes a third memory chip, and the upper surface of the third memory chip is provided with a third electrode pad that is electrically connected to the wiring substrate via the second bonding wire. The second side, opposite to the first side in the first width direction of the first laminate, forms a stepped shape where the first electrode pad is located on the stepped surface. The second side of the second laminate becomes the second electrode pad or the third electrode pad located in a stepped shape on the stepped surface. When viewed from above, the end of the second side of the second laminate is located further to the second side than the end of the second side of the first laminate.

2. The semiconductor device according to claim 1, wherein, The second memory chip is located closer to the end of the second side of the second plate-shaped portion than to the end of the first side of the second plate-shaped portion.

3. The semiconductor device according to claim 1, wherein, The semiconductor device further comprises a third stack, which includes N fourth plate-like portions having the first width in the first width direction, the N fourth plate-like portions being stacked on the first side of the first stack along the vertical direction. The fourth plate-shaped portion includes a fourth memory chip, and the upper surface of the fourth memory chip is provided with a fourth electrode pad that is electrically connected to the wiring substrate via a third bonding wire. The first side of the third laminate becomes a stepped surface where the fourth electrode pad is located. The second plate-shaped portion in the second laminate extends over the surface above the first laminate and the surface above the third laminate.

4. The semiconductor device according to claim 3, wherein, The second plate-shaped portion further includes a fifth memory chip, which is disposed on the first side of the first resin layer, and its upper surface is provided with a fifth electrode pad electrically connected to the wiring substrate via a fourth bonding wire. The second laminate further includes M fifth plate-like portions, which are disposed on the first side of the M third plate-like portions and have the first width in the first width direction. M of the fifth plate-shaped portions are stacked along the vertical direction. The fifth plate-shaped portion includes a sixth memory chip, and the upper surface of the sixth memory chip is provided with a sixth electrode pad that is electrically connected to the wiring substrate through the fourth bonding wire. The first side of the second laminate becomes a stepped surface where the fifth electrode pad or the sixth electrode pad is located. When viewed from above, the end of the first side of the second laminate is located closer to the first side than the end of the first side of the third laminate.

5. The semiconductor device according to claim 3, wherein, The semiconductor device further includes a second resin layer that is in contact with the lower surface of the second plate-shaped portion in the second stack, and with the upper surface of the first stack and the upper surface of the third stack.

6. The semiconductor device according to claim 3, wherein, The semiconductor device further includes a first semiconductor chip, which is connected to the main surface of the wiring substrate between the first stack and the third stack.

7. The semiconductor device according to claim 6, wherein, The semiconductor device further includes a second resin layer that is in contact with the lower surface of the second plate-shaped portion in the second laminate, and with the upper surfaces of the first laminate and the third laminate. The upper surface of the first semiconductor chip is in contact with the second resin layer.

8. The semiconductor device according to claim 4, wherein, The second plate-shaped portion further includes a third resin layer connected to the second side of the fifth memory chip, and a first semiconductor layer connected to the first side of the first resin layer and the second side of the third resin layer.

9. The semiconductor device according to claim 4, wherein, The fifth memory chip in the second plate-shaped portion is connected to the first side of the first resin layer. The semiconductor device further includes a first semiconductor layer disposed above the first resin layer.

10. The semiconductor device according to claim 4, wherein, The fifth memory chip in the second plate-shaped portion is connected to the first side of the first resin layer. The semiconductor device further includes a first semiconductor layer disposed below the first resin layer.

11. The semiconductor device according to claim 1, wherein, The semiconductor device also includes a control chip disposed below the first laminate and connected to the main surface of the wiring substrate.

12. A semiconductor device, have: A wiring substrate having a main surface intersecting the vertical direction; and The fourth laminate includes L sixth plate-shaped portions and L seventh plate-shaped portions having a first width in a first width direction intersecting the vertical direction, and an eighth plate-shaped portion having a second width greater than the first width in the first width direction. The L sixth plate-shaped portions are stacked above the wiring substrate along the vertical direction, and the L seventh plate-shaped portions are stacked along the vertical direction on a first side of the L sixth plate-shaped portions in the first width direction. The eighth plate-shaped portion is disposed over the surfaces above the uppermost sixth plate-shaped portions and the surfaces above the uppermost seventh plate-shaped portions. L is an integer greater than or equal to 1. The sixth plate-shaped portion and the seventh plate-shaped portion respectively include a seventh memory chip and an eighth memory chip. The eighth plate-shaped portion includes a ninth memory chip, a fourth resin layer connected to the first side of the ninth memory chip, and a tenth memory chip disposed on the first side of the fourth resin layer. The first side and the opposite side of the first side, namely the second side, of the fourth stacked body are stepped.

13. The semiconductor device according to claim 12, wherein, The eighth plate-shaped portion further includes a second semiconductor chip, the second semiconductor chip having an upper surface that is in contact with the lower surface of the ninth memory chip and the lower surface of the tenth memory chip, and controlling the ninth memory chip and the tenth memory chip.

14. The semiconductor device according to claim 12, wherein, It also includes a fifth layer, which comprises K ninth plate-shaped portions and K tenth plate-shaped portions having the first width in the first width direction, and an eleventh plate-shaped portion having the second width in the first width direction. The K ninth plate-shaped portions are stacked above L sixth plate-shaped portions along the vertical direction, and the K tenth plate-shaped portions are stacked on the first side of the K ninth plate-shaped portions along the vertical direction. The eleventh plate-shaped portion is disposed over the surface above the uppermost ninth plate-shaped portion and the surface above the uppermost tenth plate-shaped portion, wherein K is an integer greater than or equal to 1. The ninth plate-shaped portion and the tenth plate-shaped portion respectively include an eleventh memory chip and a twelfth memory chip. The eleventh plate-shaped portion includes a thirteenth memory chip, a fifth resin layer connected to the first side of the thirteenth memory chip, and a fourteenth memory chip disposed on the first side of the fifth resin layer. The first and second sides of the fifth layer are stepped.

15. The semiconductor device according to claim 14, wherein, When viewed from above, the end of the second side of the lowest ninth plate-shaped portion is located closer to the second side than the end of the second side of the eighth plate-shaped portion, and the end of the first side of the lowest tenth plate-shaped portion is located closer to the first side than the end of the first side of the eighth plate-shaped portion.

16. A semiconductor device, have: Wiring substrate having a main surface that intersects with the vertical direction; A first laminate comprises N first plate-shaped portions having a first width in a first width direction intersecting the vertical direction, wherein the N first plate-shaped portions are stacked above the wiring substrate along the vertical direction. N is an integer greater than 2; The third laminate includes N fourth plate-shaped portions having the first width in the first width direction, and the N fourth plate-shaped portions are stacked along the vertical direction on a first side of the first laminate in the first width direction. as well as The second laminate includes: a second plate-shaped portion having a second width greater than the first width in a second width direction intersecting the vertical direction and the first width direction, and disposed on the surface above the first laminate and the surface above the third laminate; M third plate-shaped portions disposed above the second plate-shaped portions and having the first width in the second width direction; and M fifth plate-shaped portions having the first width in the second width direction. The second plate-shaped portion and the M third plate-shaped portions are laminated along the vertical direction, and the M fifth plate-shaped portions are laminated along the vertical direction on a third side of the second width direction of the M third plate-shaped portions, wherein M is an integer greater than or equal to 1. The first plate-shaped portion includes a first memory chip, and the upper surface of the first memory chip is provided with a first electrode pad that is electrically connected to the wiring substrate via a first bonding wire. The fourth plate-shaped portion includes a fourth memory chip, and the upper surface of the fourth memory chip is provided with a fourth electrode pad that is electrically connected to the wiring substrate via a third bonding wire. The second plate-shaped portion includes: a second memory chip, the upper surface of which is provided with a second electrode pad electrically connected to the wiring substrate via a second bonding wire; and a first resin layer connected to the third side of the second memory chip in the second width direction. And a fifth memory chip, which is disposed on the third side of the first resin layer, and the upper surface is provided with a fifth electrode pad electrically connected to the wiring substrate via a fourth bonding wire. The third plate-shaped portion includes a third memory chip, and the upper surface of the third memory chip is provided with a third electrode pad that is electrically connected to the wiring substrate via the second bonding wire. The fifth plate-shaped portion includes a sixth memory chip, and the upper surface of the sixth memory chip is provided with a sixth electrode pad that is electrically connected to the wiring substrate through the fourth bonding wire. The second side, opposite to the first side in the first width direction of the first laminate, forms a stepped shape where the first electrode pad is located on the stepped surface. The first side of the third laminate in the first width direction becomes a stepped shape on the stepped surface where the fourth electrode pad is located. The fourth side, which is opposite to the third side in the second width direction of the second laminate, becomes the step-like structure where the second electrode pad or the third electrode pad is located on the stepped surface. The third side of the second layer in the second width direction becomes the fifth electrode pad or the sixth electrode pad located in a stepped shape on the stepped surface.

17. The semiconductor device according to claim 1, 3, 4, 12, 14 or 16, wherein, The plate-shaped portion, which includes any one of the first to fourteenth memory chips, further includes a second semiconductor chip having an upper surface that is in contact with the lower surface of the memory chip and controls the memory chip. The width of the second semiconductor chip in the width direction is greater than the width of the memory chip in the width direction.

18. The semiconductor device according to claim 17, wherein, A first pad is formed on the surface above the second semiconductor chip. A second pad is formed on the surface below the memory chip. By bonding the first pad to the second pad, the memory chip is thus attached to the second semiconductor chip.

19. The semiconductor device according to claim 18, wherein, The memory chip includes a path along the vertical direction that electrically connects the second pad to the electrode pad on the surface above the memory chip.

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