Adjustable common-mode rejection filter based on three-dimensional integration and design method thereof

Abstract

The invention discloses an adjustable common mode rejection filter based on three-dimensional integration, which comprises a top dielectric RDL layer, a silicon substrate and a bottom dielectric RDL layer which are sequentially arranged from top to bottom, and is characterized in that a symmetrical spiral inductor L1, a symmetrical spiral inductor L2, a symmetrical spiral inductor L3, a symmetrical spiral inductor L4, a symmetrical spiral inductor L5 and a symmetrical spiral inductor L6 are arranged in the top dielectric RDL layer; a TSV capacitor C1, a TSV capacitor C2, a TSV capacitor C3 and a TSV capacitor C4 are arranged in the silicon substrate; and a symmetrical spiral inductor L7, a symmetrical spiral inductor L8 and an RDL inductor L9 are arranged in the bottom dielectric RDL layer. The invention further discloses a design method of the adjustable common-mode rejection filter based on three-dimensional integration. The filter can achieve high-gain and adjustable-bandwidth common-mode noise rejection at the same time.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of three-dimensional integrated circuits, and relates to an adjustable common-mode rejection filter based on three-dimensional integration, and also relates to a design method of the adjustable common-mode rejection filter based on three-dimensional integration. BACKGROUND

[0002] With the continuous development of electronic devices, especially the application of high-performance computing, communication systems and power electronic devices, the problem of common-mode noise has become increasingly prominent. This noise not only affects the integrity of the signal, but also can cause system performance degradation or even failure, especially in high-frequency and high-speed data transmission environments. At present, there are various filters on the market for suppressing common-mode noise, but most traditional filters perform poorly in high-frequency environments or have certain limitations in noise suppression capability, and LC-based filters are large in size under high-gain requirements and are not easy to integrate into small electronic devices. In addition, the bandwidth adjustment capability of existing filters is limited and cannot meet the needs of different application scenarios. In recent years, three-dimensional integration technology (3D Integration) has gradually increased in the application of electronic devices and systems. Three-dimensional integration technology stacks multiple devices together, not only improving the integration of the system, but also reducing the signal transmission path, reducing signal loss and noise. In some specific applications, such as high-frequency communication systems, high-speed data transmission and precision measurement instruments, filters need to have high gain and adjustable bandwidth characteristics. High gain can ensure that noise is effectively suppressed, while adjustable bandwidth allows the filter to adapt to different frequency range noise environments. Therefore, developing a common-mode noise suppression filter that can simultaneously achieve high gain and adjustable bandwidth has important theoretical significance and practical application value. SUMMARY

[0003] The purpose of the present application is to provide an adjustable common-mode rejection filter based on three-dimensional integration, which can simultaneously achieve high gain and adjustable bandwidth common-mode noise suppression.

[0004] Another purpose of the present application is to provide a design method of the adjustable common-mode rejection filter based on three-dimensional integration.

[0005] The first technical solution of the present application is an adjustable common-mode rejection filter based on three-dimensional integration, comprising a top dielectric RDL layer, a silicon substrate and a bottom dielectric RDL layer arranged in sequence from top to bottom, wherein the top dielectric RDL layer is provided with symmetric spiral inductors L1, L2, L3, L4, L5 and L6, one end of the top dielectric RDL layer is provided with input terminals Prot1 and Prot3, and the other end of the top dielectric RDL layer is provided with output terminals Prot2 and Prot4; the silicon substrate is provided with TSV capacitors C1, C2, C3 and C4; and the bottom dielectric RDL layer is provided with symmetric spiral inductors L7, L8 and RDL inductor L9.

[0006] The first technical solution of the present application is also characterized in that: The input terminal Prot1 is connected to the input terminal of the symmetric spiral inductor L1 through an interconnection line, the output terminal of the symmetric spiral inductor L1 is connected to the input terminal of the symmetric spiral inductor L2, the output terminal of the symmetric spiral inductor L2 is connected to the input terminal of the symmetric spiral inductor L3, and the output terminal of the symmetric spiral inductor L3 is connected to the output terminal Prot2; the input terminal Prot3 is connected to the input terminal of the symmetric spiral inductor L4 through an interconnection line, the output terminal of the symmetric spiral inductor L4 is connected to the input terminal of the symmetric spiral inductor L5, the output terminal of the symmetric spiral inductor L5 is connected to the input terminal of the symmetric spiral inductor L6, and the output terminal of the symmetric spiral inductor L6 is connected to the output terminal Prot4.

[0007] The input terminal of the TSV capacitor C1 is connected between the output terminal of the symmetric spiral inductor L1 and the input terminal of the symmetric spiral inductor L2, the input terminal of the TSV capacitor C2 is connected between the output terminal of the symmetric spiral inductor L2 and the input terminal of the symmetric spiral inductor L3, the input terminal of the TSV capacitor C3 is connected between the output terminal of the symmetric spiral inductor L4 and the input terminal of the symmetric spiral inductor L5, and the input terminal of the TSV capacitor C4 is connected between the output terminal of the symmetric spiral inductor L5 and the input terminal of the symmetric spiral inductor L6.

[0008] The output terminals of the TSV capacitors C1 and C3 are connected to the input terminal of the RDL inductor L9, and the output terminals of the TSV capacitors C2 and C4 are connected to the output terminal of the RDL inductor L9.

[0009] The output terminal of the symmetric spiral inductor L7 is connected to the input terminal of the RDL inductor L9, the input terminal of the symmetric spiral inductor L8 is connected to the output terminal of the RDL inductor L9, and the input terminal of the symmetric spiral inductor L7 is connected to the contact G1 and the contact G2 respectively; and the output terminal of the symmetric spiral inductor L8 is connected to the contact G3 and the contact G4 respectively.

[0010] The symmetric spiral inductors L1, L3, L4 and L6 have the same inductance value; the symmetric spiral inductors L2 and L5 have the same inductance value; the symmetric spiral inductors L7 and L8 have the same inductance value; the TSV capacitors C1, C2, C3 and C4 have the same capacitance value.

[0011] The top medium RDL layer comprises four metal layers and three medium layers; and the bottom medium RDL layer comprises two metal layers and two medium layers. The second technical solution of the present application is a design method of a three-dimensional integrated adjustable common-mode rejection filter, and the angular frequency of a common-mode transmission zero point of the filter is The relationship with L9 is shown in the following formula (1): (1)

[0012] wherein, is the angular frequency.

[0013] The present application has the following advantages: in the present application, the RDL inductors L1-L8 all adopt a double-layer symmetric structure, and the input end and the output end are both on the outside of the inductor structure, which can reduce a large number of unnecessary interconnection lines compared with a spiral inductor. Meanwhile, the capacitor adopts a TSV structure, and compared with a traditional flat plate capacitor, the TSV capacitor has a higher integration density, and the introduction of the TSV technology makes the signal path shorter and the parasitic inductance lower. The present application greatly reduces the required area of the chip while improving the circuit performance, and improves the integration density. Moreover, the TSV technology is compatible with the existing general silicon processing technology, which also reduces the process cost. The filter has better common-mode noise rejection capability, simple structure and is easy to design, and can control the CM stopband bandwidth by adjusting a single structure parameter, so that the filter can better adapt to different frequency range noise environments. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is an LC circuit schematic diagram of the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 2 is a three-dimensional view of the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 3 is a longitudinal sectional view of the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 4 is a front view of the upper layer circuit of the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 5is a back view plan of the lower circuit of the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 6 is a 3x3 array TSV capacitor structure used by the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 7 is a symmetrical spiral inductance structure used by the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 8 is the simulation results of Scc21 of the adjustable common-mode rejection filter based on three-dimensional integration of the present application at different lengths d and the differential mode Sdd21 parameter simulation results; Fig. 9 (a)~(c) is the circuit topology structure of the adjustable common-mode rejection filter based on three-dimensional integration of the present application containing one resonant path and its even mode half circuit and odd mode half circuit; Figure 10 is the S parameter simulation diagram of the circuit topology structure of the adjustable common-mode rejection filter based on three-dimensional integration of the present application containing one resonant path; Figure 11 is the circuit topology structure diagram of the adjustable common-mode rejection filter based on three-dimensional integration of the present application containing two resonant paths; Figure 12 is the S parameter simulation diagram of the circuit topology structure of the adjustable common-mode rejection filter based on three-dimensional integration of the present application containing two resonant paths; Figure 13 is the even mode half circuit diagram of the LC circuit of the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Fig. 14 (a)~Fig. 14 (b) is the even-even half circuit and even-odd half circuit diagram of the even mode half circuit of the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 15 is the simulation diagram of the CM transmission zero spacing and the adjusting element of the adjustable common-mode rejection filter based on three-dimensional integration of the present application; Figure 16 is the group delay simulation diagram of the adjustable common-mode rejection filter based on three-dimensional integration of the present application. DETAILED DESCRIPTION

[0015] The following will be described in detail in combination with specific embodiments.

[0016] Embodiment 1 The equivalent circuit schematic diagram of the adjustable common-mode rejection filter based on three-dimensional integration of the present application is as follows, Figure 1As shown, by merging two identical fifth-order low-pass filters (I and II) and introducing three common inductors on their horizontal plane of symmetry to connect to the return path, a symmetrical balanced circuit network is formed. Two transmission channels are used to transmit differential signals with the same amplitude but opposite phase, respectively, to achieve low impedance for differential signals (DM) within the cutoff frequency and high rejection of common-mode signals (CM) within the stopband.

[0017] Example 2 The filter's circuit topology has four ports: input ports Prot1 and Prot3, and output ports Prot2 and Prot4. The filter components include nine inductors (L1, L2, L3, L4, L5, L6, L7, L8, L9) and four capacitors (C1, C2, C3, C4). C1, C2, C3, and C4 are four identical 3×3 array TSV capacitors. The 3×3 array TSV capacitor structure is as follows... Figure 6 As shown, the C input terminal is connected to the upper RDL, the central "+" shaped TSV, and the lower RDL to form the upper substrate of the capacitor. The C output terminal is connected to the lower RDL, the four corner "□" shaped TSVs, and the upper RDL to form the lower substrate of the capacitor. L1, L3, L4, and L6 are symmetrical spiral inductors with the same inductance value; L2 and L5 are symmetrical spiral inductors with the same inductance value; and L7 and L8 are symmetrical spiral inductors with the same inductance value. The symmetrical spiral inductor structure is as follows: Figure 7 As shown, the L input terminal is connected to the RDL and loops around twice. The L output terminal is introduced to the symmetrical position of the L output terminal through two RDL layer swaps. The RDL inductor L9 is the adjustment component.

[0018] Example 3 The overall three-dimensional structure of the circuit is as follows Figure 2 As shown, the overall structure is divided into three parts from top to bottom: the top dielectric RDL (metal wiring layer) layer (represented by the F layer), the silicon substrate (represented by the S layer), and the bottom dielectric RDL layer (represented by the B layer). Figure 3 The diagram shows a longitudinal cross-section of the overall structure. The top dielectric RDL layer (F) comprises four metal layers F-M1, F-M2, F-M3, and F-M4, and dielectric layers F-PI1, F-PI2, and F-PI3. Dielectric layer F-PI1 is located between metal layers F-M1 and F-M2, dielectric layer F-PI2 is located between metal layers F-M2 and F-M3, and dielectric layer F-PI3 is located between metal layers F-M3 and F-M4. The bottom dielectric RDL layer (B) comprises two metal layers B-M1 and B-M2, and dielectric layers B-PI0 and B-PI1. Dielectric layer B-PI0 is located between metal layer B-M1 and the silicon substrate, and dielectric layer B-PI1 is located between metal layers B-M1 and B-M2. Interconnection between F and B is achieved through a TSV (Transient Voltage Supplier) passing through the silicon substrate S.

[0019] The input terminal Prot1 and the input terminal Prot3, the output terminal Prot2 and the output terminal Prot4, the symmetrical spiral inductor L1, the symmetrical spiral inductor L2, the symmetrical spiral inductor L3, the symmetrical spiral inductor L4, the symmetrical spiral inductor L5, the symmetrical spiral inductor L6 and the ground contacts G1, G2, G3, G4 are located in the F layer, as shown in Figure 4 The TSV capacitor C1, the TSV capacitor C2, the TSV capacitor C3, the TSV capacitor C4 are located in the silicon substrate S layer, the symmetrical spiral inductor L7, the symmetrical spiral inductor L8, the RDL inductor L9 are located in the B layer, as shown in Figure 5

[0020] Embodiment 4 The input terminal Prot1 is connected to the input terminal of the symmetrical spiral inductor L1 through an interconnection line, the output terminal of the symmetrical spiral inductor L1 is connected to the input terminal of the symmetrical spiral inductor L2, the output terminal of the symmetrical spiral inductor L2 is connected to the input terminal of the symmetrical spiral inductor L3, and the output terminal of the symmetrical spiral inductor L3 is connected to the output terminal Prot2.

[0021] The input terminal Prot3 is connected to the input terminal of the symmetrical spiral inductor L4 through an interconnection line, the output terminal of the symmetrical spiral inductor L4 is connected to the input terminal of the symmetrical spiral inductor L5, the output terminal of the symmetrical spiral inductor L5 is connected to the input terminal of the symmetrical spiral inductor L6, and the output terminal of the symmetrical spiral inductor L6 is connected to the output terminal Prot4.

[0022] The input terminal of the TSV capacitor C1 is connected to the middle of the output terminal of the symmetrical spiral inductor L1 and the input terminal of the symmetrical spiral inductor L2 through a PI (polyimide) layer via hole, the input terminal of the TSV capacitor C2 is connected to the middle of the output terminal of the symmetrical spiral inductor L2 and the input terminal of the symmetrical spiral inductor L3 through a PI layer via hole, the input terminal of the TSV capacitor C3 is connected to the middle of the output terminal of the symmetrical spiral inductor L4 and the input terminal of the symmetrical spiral inductor L5 through a PI layer via hole, and the input terminal of the TSV capacitor C4 is connected to the middle of the output terminal of the symmetrical spiral inductor L5 and the input terminal of the symmetrical spiral inductor L6 through a PI layer via hole.

[0023] The output terminal of the TSV capacitor C1, the output terminal of the TSV capacitor C2, the output terminal of the TSV capacitor C3, the output terminal of the TSV capacitor C4 are led to the bottom dielectric and RDL layer through TSV, the output terminal of the TSV capacitor C1 and the output terminal of the TSV capacitor C3 are connected to the input terminal of L9, the output terminal of the TSV capacitor C2 and the output terminal of the TSV capacitor C4 are connected to the output terminal of L9. Secondly, the output terminal of the symmetrical spiral inductor L7 is connected to the input terminal of L9, the input terminal of the symmetrical spiral inductor L8 is connected to the output terminal of L9, and finally the input terminal of the symmetrical spiral inductor L7 and the output terminal of the symmetrical spiral inductor L8 are respectively led to the contacts G1, G2 and G3, G4 in the top F-M4 layer through a connecting line and TSV for grounding (GND), completing the connection of the three-dimensional common mode noise suppression circuit.

[0024] ​In the three-dimensional structure design, the RDL line width is 10 um, the metal line thickness is 5 um, the PI layer thickness is also 5 um, and the PI layer through hole diameter is 10 um. The silicon substrate thickness is 100 um, the TSV diameter is 10 um, and the length is 100 um. The inductor and the capacitor adopt a symmetrical layout mode, so that the input differential signals are subjected to the same influence, thereby making the common mode signals be effectively absorbed and suppressed when passing through the filter.

[0025] A second-order T model structure is formed by combining two same low-pass filters, and three common inductances are introduced on the horizontal symmetry surface of the second-order T model structure and connected to a return path to form a balanced circuit network. Two transmission channels are used to transmit differential signals with the same amplitude and opposite phase, and the signal receiving end considers the difference between the two transmission lines to determine the transmission signal and information, so that the characteristics of low impedance for the differential mode (DM) signals within the cutoff frequency and high suppression for the common mode (CM) signals in the stopband are realized.

[0026] The circuit is a passive lumped common mode noise suppression filter, has four ports, and differential signals are input from input ports Prot1 and Prot3 and output from output ports Prot2 and Prot4. Symmetrical spiral inductances L1, L2, L3, L4 and L6 have the same structure, symmetrical spiral inductances L2 and L5 have the same structure, symmetrical spiral inductances L7 and L8 have the same structure, and four TSV capacitors C1-C4 have the same structure. Through reasonable layout design, the two signal paths from the input port Prot1 to the output port Prot2 and from the input port Prot3 to the output port Prot4 are completely the same, and the overall three-dimensional model has horizontal and vertical symmetry, and shows all-pass characteristics for differential signals under odd mode excitation.

[0027] As shown in Figure 5 The common ground symmetrical spiral inductances L7 and L8 introduce two CM transmission zeros TZ1 and TZ2 for the circuit, and the common RDL inductance L9 between the two branches of the LC network can control the separation degree of the two CM transmission zeros, and the inductance value of the RDL inductance L9 is mainly affected by the length d of the “j” shaped structure on both sides of the horizontal symmetry axis, so that the bandwidth of the CM stopband can be flexibly adjusted by adjusting the value of d.

[0028] Embodiment 5 The present application is based on a three-dimensional integrated adjustable common mode suppression filter, and two controllable common mode transmission zeros TZ1 and TZ2 are introduced for the circuit by the spiral inductances L7, L8 and L9. The performance of the filter can be simply and conveniently reconstructed by adjusting only the inductance L9, so that the filter can adapt to more working frequencies. As shown in Figure 8The application is based on the simulation results of the three-dimensional integrated adjustable common-mode rejection filter Scc21 at different lengths d and the parameter simulation results of the differential mode Sdd21, in which d is respectively equal to 10 um, 40 um, 70 um and 100 um to show S CC 21 with the change of d, it can be obviously seen that when d decreases, the impedance decreases, the inductance value of L9 decreases, the separation of TZ1 and TZ2 increases, and the CM rejection band width is significantly expanded. When d increases, the metal line coupling is enhanced, the inductance value of L9 increases, and the CM rejection band is contracted until TZ1 and TZ2 coincide. And in the whole adjustment range, Sdd21 is not affected by the parameter d and shows all-pass to the differential signal below the cutoff frequency, and the CM rejection is always kept below -25 dB. According to formula (1), it can be calculated that the filter has a relative adjustment bandwidth RBW of 37.8% near 17 GHz.

[0029] (1) wherein f c is the center frequency of the stop band, ABW = BW max -BW min , and BW is the absolute bandwidth. The influence of the inductance L9 on the position of the CM transmission zero point can be analyzed in detail by the odd-even mode analysis method, and the relationship between the angular frequency ω of the CM transmission zero points TZ1 and TZ2 and L9 can be expressed by formula (2).

[0030] (2) wherein,

[0031] Table 1 is the numerical values of each device of the three-dimensional integrated adjustable common-mode rejection filter of the application

[0032] Example 6 The three-dimensional integrated adjustable common-mode rejection filter of the application adopts two five-order low-pass filters combined, and three common inductors are introduced on the horizontal symmetry surface to connect to the return path to form a symmetrical balanced circuit network. Two transmission channels are used to transmit differential signals with the same amplitude and opposite phase to realize the characteristics of low impedance to differential signals (DM) and high rejection in the common-mode signal (CM) band within the cutoff frequency.

[0033] Two two-order low-pass filters are combined, and a common ground inductor is introduced on the branch symmetry surface to introduce a common-mode transmission zero point, as shown in Fig. 9 (a), and Fig. 9 (b) and Fig. 9 (c) are the odd mode half circuit and even mode half circuit respectively. The simulation results are shown in Figure 10 the figure, the common-mode transmission zero point is introduced by the ground inductor L GNDand branch series capacitor C resonance. Common-mode transmission zero can be expressed as formula (3), from the odd-even mode circuit can be seen that the ground end of the differential mode equivalent circuit does not contain ground inductance L GND , while the ground end of the common-mode equivalent circuit is equivalent to twice the ground inductance L GND , so changing L GND can change the position of the common-mode transmission zero without affecting the transmission of differential-mode signals.

[0034] (3) In order to widen the CM stopband width, another CM transmission zero point needs to be introduced, that is, another resonant path. But also to ensure good low-pass characteristics of differential signals, and the flattest low-pass filter has the smallest in-band loss compared with other prototype filters, so the flattest low-pass prototype filter is used for filter design. At the same time, the symmetrical circuit structure is conducive to the suppression of common-mode noise, so the filter order adopts odd order (such as three order, five order, seven order). Through comprehensive analysis of the edge drop rate of the cutoff frequency, the insertion loss and the number of circuit elements, a five-order low-pass filter is used for balanced network design.

[0035] As Figure 11 shown is a circuit topology structure containing two resonant paths, Figure 12 and the S parameter simulation result thereof. Through S parameter, it can be seen that there are two CM transmission zeros, and the two CM transmission zeros are controlled by two ground inductances L GND1 and L GND2 , but this also leads to the asymmetry of the circuit structure, thereby affecting S CC21 . The final circuit diagram is shown in Figure 1 , in order to make the overall circuit completely symmetrical, a small inductance L9 is introduced on the symmetry plane between the two resonant paths, which can make the inductance L7 and L8 equal, so as to make the circuit horizontally symmetrical. It is composed of two identical five-order flattest low-pass filters I and II, two identical common ground inductances L7 and L8, and L9 adjusting inductance. The HFSS full-band S parameter simulation is shown in Figure 8 , the results show that the insertion loss of differential signal within the cutoff frequency is good, the maximum is not more than 1.83dB, the common-mode noise suppression is greater than 25dB within 13.2GHz~20.8GHz, and there is a 37.8% relative CM stopband width adjustment range near 17GHz, and the CM stopband center frequency is 17GHz.

[0036] In order to analyze the specific relationship between the adjusting inductance L9 and the bandwidth, the circuit is analyzed in detail by using the odd-even mode analysis method. As Figure 13As shown in the whole circuit even mode half-circuit, by reusing the even-odd mode analysis method, the even mode half-circuit is divided into two single-port networks, as shown in Figure 14 (a) is even-even half-circuit, (b) is even-odd half-circuit, and S21 can be represented by formula (4), wherein Z0 is characteristic impedance, and it is obvious that when the even-even half-circuit input impedance Zin_ee and the even-odd half-circuit input impedance Zin_eo are equal, the transmission zero point frequency ω can be obtained by simultaneous solution. Through the above analysis, the relationship between adjusting inductance L9 and CM stopband bandwidth is as follows Figure 15 As shown in the results, the theoretical bandwidth adjustment capability of L9 is basically consistent with the HFSS model simulation, and since the inductance L9 in the HFSS model is affected by the structure parameter d, with the increase of the structure parameter d, more parasitic and coupling are introduced in the circuit, so that when the inductance L9 is relatively large, the HFSS simulation value and the theoretical value appear a certain deviation.

[0037] (4) In addition, the group delay response of the filter is as shown in the figure Figure 16 In the CM stopband adjustment range, the group delay is basically constant at about 30ps without sharp fluctuation, so that the waveform is not distorted in the differential signal transmission process. In summary, compared with the existing adjustable common mode noise suppression filter, the adjustable common mode noise suppression filter based on three-dimensional integration has good comprehensive performance in common mode suppression, adjustable range, physical size and the like.

[0038] The filter shows good common mode noise suppression characteristics in a wide band, and the differential signal loss is less than -2dB within the cutoff frequency 25GHz, the overall structure is compact, and the integration degree is high. Meanwhile, by adjusting the branch length of the inductance L9, the filter can realize a relative stopband width adjustment range of 37.8% near 17GHz.

[0039] By adjusting the structure parameter d of the RDL inductance L9, the relative CM (common mode) stopband width adjustment range of 37.8% near 17GHz can be realized, so that the filter can adapt to more working frequencies. When d decreases, the impedance decreases, the inductance value decreases, TZ1 and TZ2 separate and increase, and the stopband width is significantly expanded. When d increases, the metal line coupling is enhanced, the inductance value increases, and the CM stopband shrinks until TZ1 and TZ2 coincide. And in the whole adjustment range, the CM suppression is always kept below -25dB.

Claims

1. A tunable common-mode rejection filter based on three-dimensional integration, characterized by: The top medium RDL layer, the silicon substrate and the bottom medium RDL layer are sequentially arranged from top to bottom, the top medium RDL layer is internally provided with symmetrical spiral inductors L1, L2, L3, L4, L5 and L6, one end of the top medium RDL layer is provided with input ends Prot1 and Prot3, and the other end of the top medium RDL layer is provided with output ends Prot2 and Prot4; the silicon substrate is internally provided with TSV capacitors C1, C2, C3 and C4; and the bottom medium RDL layer is internally provided with symmetrical spiral inductors L7 and L8 and an RDL inductor L9.

2. The three-dimensional integration-based adjustable common-mode rejection filter according to claim 1, characterized in that: The input end Prot1 is connected to the input end of the symmetrical spiral inductor L1 through an interconnection line, the output end of the symmetrical spiral inductor L1 is connected to the input end of the symmetrical spiral inductor L2, the output end of the symmetrical spiral inductor L2 is connected to the input end of the symmetrical spiral inductor L3, and the output end of the symmetrical spiral inductor L3 is connected to the output end Prot2. The input end Prot3 is connected to the input end of the symmetrical spiral inductor L4 through an interconnection line, the output end of the symmetrical spiral inductor L4 is connected to the input end of the symmetrical spiral inductor L5, the output end of the symmetrical spiral inductor L5 is connected to the input end of the symmetrical spiral inductor L6, and the output end of the symmetrical spiral inductor L6 is connected to the output end Prot4.

3. The three-dimensional integration-based adjustable common-mode rejection filter according to claim 2, characterized in that: The input end of the TSV capacitor C1 is connected to the middle of the output end of the symmetrical spiral inductor L1 and the input end of the symmetrical spiral inductor L2, the input end of the TSV capacitor C2 is connected to the middle of the output end of the symmetrical spiral inductor L2 and the input end of the symmetrical spiral inductor L3, the input end of the TSV capacitor C3 is connected to the middle of the output end of the symmetrical spiral inductor L4 and the input end of the symmetrical spiral inductor L5, and the input end of the TSV capacitor C4 is connected to the middle of the output end of the symmetrical spiral inductor L5 and the input end of the symmetrical spiral inductor L6.

4. The three-dimensional integrated adjustable common-mode rejection filter of claim 3, wherein: The output ends of the TSV capacitors C1 and C3 are connected to the input end of the RDL inductor L9, and the output ends of the TSV capacitors C2 and C4 are connected to the output end of the RDL inductor L9.

5. The three-dimensional integrated adjustable common-mode rejection filter of claim 4, wherein: The output end of the symmetrical spiral inductor L7 is connected to the input end of the RDL inductor L9, the input end of the symmetrical spiral inductor L8 is connected to the output end of the RDL inductor L9, and the input end of the symmetrical spiral inductor L7 is respectively connected to a contact G1 and a contact G2; and the output end of the symmetrical spiral inductor L8 is respectively connected to a contact G3 and a contact G4.

6. The three-dimensional integrated adjustable common-mode rejection filter of claim 5, wherein: The symmetrical spiral inductors L1, L3, L4 and L6 have the same inductance value, the symmetrical spiral inductors L2 and L5 have the same inductance value, the symmetrical spiral inductors L7 and L8 have the same inductance value, and the TSV capacitors C1, C2, C3 and C4 have the same capacitance value.

7. The three-dimensional integration-based adjustable common-mode rejection filter according to claim 5, characterized in that: The top medium RDL layer comprises four metal layers and three medium layers, and the bottom medium RDL layer comprises two metal layers and two medium layers.

8. A method of designing a tunable common-mode rejection filter based on three-dimensional integration, characterized by: An angle frequency of the filter common mode transmission zero The relationship with L9 is shown in the following equation (1): （1） wherein is the angular frequency.

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