Phase interpolation circuit

Abstract

A phase interpolation circuit is used for generating a phase interpolation signal and comprises a capacitor; the first charging circuit is used for selectively charging the capacitor according to a first clock signal and a first weight control code; the second charging circuit is used for selectively charging the capacitor according to a second clock signal and a second weight control code; the first discharging circuit is used for selectively discharging the capacitor according to the first clock signal and a third weight control code; and the second discharging circuit is used for selectively discharging the capacitor according to the second clock signal and a fourth weight control code. The first, second, third and fourth weight control codes control weights of the first clock signal and the second clock signal in the phase interpolation signal, respectively.

Description

Technical Field

[0001] This invention relates to phase interpolation circuits, and more particularly to phase interpolation circuits that can generate phase interpolation signals through a simple architecture. Background Technology

[0002] In the modern electronics industry, phase interpolation circuits are frequently used to interpolate the required phase interpolation signal. However, existing phase interpolation circuits typically have complex circuit structures and operations, resulting in poor linearity, high power consumption, and long delays.

[0003] Therefore, a new phase interpolation circuit is needed. Summary of the Invention

[0004] One objective of this invention is to provide a phase interpolation circuit that can improve linearity, circuit power consumption, and signal delay.

[0005] An embodiment of the present invention discloses a phase interpolation circuit for generating an interpolated clock signal, comprising: a capacitor; a first charging circuit coupled to the capacitor for selectively charging the capacitor according to a first clock signal and a first weight control code, the first weight control code determining a first weight of the first clock signal in the interpolated clock signal; a second charging circuit coupled to the capacitor for selectively charging the capacitor according to a second clock signal and a second weight control code, the second weight control code determining a second weight of the second clock signal in the interpolated clock signal; a first discharging circuit coupled to the capacitor for selectively discharging the capacitor according to the first clock signal and a third weight control code, the third weight control code determining a third weight of the first clock signal in the interpolated clock signal; and a second discharging circuit coupled to the capacitor for selectively discharging the capacitor according to the second clock signal and a fourth weight control code, the fourth weight control code determining a fourth weight of the second clock signal in the interpolated clock signal.

[0006] Another embodiment of the present invention discloses a phase interpolation circuit for generating an interpolated clock signal, comprising: a capacitor; a first charging circuit coupled to the capacitor for selectively charging the capacitor according to a first clock signal and a first weighting control code; a second charging circuit coupled to the capacitor for selectively charging the capacitor according to a second clock signal and a second weighting control code; a first discharging circuit coupled to the capacitor for selectively discharging the capacitor according to the first clock signal and a third weighting control code; and a second discharging circuit coupled to the capacitor for selectively discharging the capacitor according to the second clock signal and a fourth weighting control code. The first charging circuit and the first discharging circuit are connected in series, and the second charging circuit and the second discharging circuit are connected in series. A first terminal of the capacitor is coupled to the coupling point of the first charging circuit and the first discharging circuit, and a second terminal of the capacitor is coupled to the coupling point of the second charging circuit and the second discharging circuit. The first charging circuit, the second charging circuit, the first discharging circuit, and the second discharging circuit each include switches connected in series. The first weight control code, the second weight control code, the third weight control code, and the fourth weight control code respectively control the number of switches turned on in the first charging circuit, the second charging circuit, the first discharging circuit, and the second discharging circuit.

[0007] According to the foregoing embodiments, a simple circuit can be used to generate a phase interpolation signal, which can increase the linearity of the phase interpolation signal and improve the circuit power consumption and signal delay. Attached Figure Description

[0008] Figure 1 A block diagram of a phase interpolation circuit according to an embodiment of the present invention is shown.

[0009] Figure 2 A circuit diagram of a phase interpolation circuit according to an embodiment of the present invention is shown.

[0010] Figure 3 An embodiment of the present invention is shown. Figure 2 The circuit diagram of the first charging circuit is shown when N=3.

[0011] Figure 4 and Figure 5 An embodiment of the present invention is shown. Figure 2 The diagram shows the operation of the phase interpolation circuit.

[0012] Figure 6 A schematic diagram of an interpolated clock signal according to an embodiment of the present invention is shown.

[0013] Figure 7 A schematic diagram illustrating how weight control codes are generated according to an embodiment of the present invention is shown. Detailed Implementation

[0014] In the description of the following embodiments, the terms "first," "second," and similar descriptions are used only to define different elements, parameters, data, signals, or steps, and are not intended to limit their order. For example, the first device and the second device may be devices with the same structure but different from each other.

[0015] Figure 1 A block diagram of a phase interpolation circuit 100 according to an embodiment of the present invention is shown. Figure 1 As shown, the phase interpolation circuit 100, used to generate an interpolated clock signal, includes a capacitor C, a first charging circuit CC_1, a second charging circuit CC_2, a first discharging circuit DC_1, and a second charging circuit DC_2. The voltage of capacitor C can be used to generate the interpolated clock signal; in the following embodiment, the voltage of capacitor C is directly used as the interpolated clock signal. The first charging circuit CC_1 is coupled to capacitor C and is used to generate the interpolated clock signal based on a first clock signal CK_1 and a first weighting control code SW_P1. <n-1:0>Selectively charge capacitor C, first weight control code SW_P1 <n-1:0>The first weight of the first clock signal CK_1 in the interpolated clock signal is determined. The second charging circuit CC_2 is coupled to capacitor C to determine the weight based on a second clock signal CK_2 and a second weight control code SW_P2. <n-1:0>Selectively charge capacitor C, second weighting control code SW_P2 <n-1:0>Determine a second weight for the second clock signal CK_2 in the interpolated clock signal.

[0016] The first discharge circuit DC_1 is coupled to capacitor C, which is used to discharge according to the first clock signal CK_1 and a third weighted control code SW_N1. <n-1:0>Selectively discharge capacitor C, third weight control code SW_N1 <n-1:0>A third weight is determined for the first clock signal CK_1 in the interpolated clock signal. The second discharge circuit CC_2 is coupled to capacitor C to determine the weight based on the second clock signal CK_2 and a fourth weight control code SW_N2. <n-1:0>Selectively discharge capacitor C, fourth weighting control code SW_N2 <n-1:0>Determine the fourth weight of the second clock signal CK_2 in the interpolated clock signal.

[0017] More specifically, the first charging circuit CC_1 and the first discharging circuit DC_1 are connected in series, and the second charging circuit CC_2 and the second discharging circuit DC_2 are connected in series. A first end of capacitor C is coupled to the coupling point of the first charging circuit CC_1 and the first discharging circuit DC_1, and a second end of capacitor C is coupled to the coupling point of the second charging circuit CC_2 and the second discharging circuit DC_2.

[0018] Figure 1 The charging and discharging circuits shown can have various different circuit architectures. Figure 2 A detailed circuit diagram of a phase interpolation circuit according to an embodiment of the present invention is shown. Figure 2 As shown, the first charging circuit CC_1 includes a first type of clock switch group MP1. <n-1:0>And a first-type weighted switch group MP2 <n-1:0>Type 1 Clock Switch Group MP1 <n-1:0>It includes at least one first-type clock switch, which is simultaneously turned on or simultaneously turned off according to a first clock signal. First-type weighted switch group MP2 <n-1:0>It includes at least one first type one weight switch, which is turned on or off according to the first weight control code.

[0019] In one embodiment, both the first type-1 clock switch and the first type-1 weighted switch are PMOS, but other transistors with the same function can also be used. N is a positive integer not less than 1, representing the number of switches represented in the switch group. For example, if N=1, the first type-1 clock switch group MP1<0:0> and the first type-1 weighted switch group MP2<0:0> each contain one first type-1 clock switch and one first type-1 weighted switch. If N=4, then the first type-1 clock switch group MP1<3:0> and the first type-1 weighted switch group MP2<3:0> each contain four first type-1 clock switches and four first type-1 weighted switches.

[0020] Figure 3 An embodiment of the present invention is shown. Figure 2 The circuit diagram of the first charging circuit shown is shown when N=3. Figure 3 As shown, the first charging circuit CC_1 includes three first-type clock switches MP11, MP12, and MP13, and three first-type weight switches MP21, MP22, and MP23. Each of the first-type clock switches MP11, MP12, and MP13 is connected in series with a different first-type weight switch MP21, MP22, or MP23. The control terminals (e.g., gates) of the first-type clock switches MP11, MP12, and MP13 all receive the first clock signal CK_1, and therefore are simultaneously controlled by the first clock signal CK_1 to be either turned on or off. The control terminals of the first-type weight switches MP21, MP22, and MP23 respectively receive different first weight control codes SW_P1<2:0>, SW_P1<2:1>, and SW_P1<2:2>, and therefore are respectively turned on or off.

[0021] Please return to Figure 2 The second charging circuit CC_2 includes a second type of clock switch group MP3. <n-1:0>And a second type of weighted switch group MP4 <n-1:0>Type 2, Clock Switch Group MP3 <n-1:0>It includes at least one second-type clock switch, which is simultaneously turned on or off according to the second clock signal CK_2. Second-type weighted switch group MP4 <n-1:0>It includes at least one second-type weighted switch, which is based on the second weighted control code SW_P2. <n-1:0>They are either turned on or off respectively. In one embodiment, both the second type-1 clock switch and the second type-1 weight switch are PMOS, but other transistors with the same function can also be used. In one embodiment, each second type-1 clock switch is connected in series with different second type-1 weight switches.

[0022] exist Figure 2 In the embodiment, the first discharge circuit DC_1 includes a first type two-weighted switch group MN1. <n-1:0>And a first-type two-weighted switch group MN2 <n-1:0>Type I weighted switching group MN2 <n-1:0>It includes at least one Type 2 clock switch, which is simultaneously turned on or off according to the first clock signal CK_1. Type 2 weighted switch group MN1 <n-1:0>It includes at least one Type I two-weighted switch, which is based on the third weighted control code SW_N1. <n-1:0>They can be either on or off.

[0023] The second discharge circuit DC_2 includes a second-type two-weighted switch group MN3. <n-1:0>And a second type of two-clock switch group MN4 <n-1:0>Type II clock switch group MN4 <n-1:0>It includes at least one second-type two-clock switch, which is simultaneously turned on or off according to the second clock signal CK_2. Second-type two-weighted switch group MN3 <n-1:0>It includes at least one second-type two-weighted switch, which is based on the fourth weight control code SW_N2. <n-1:0>They are either turned on or off respectively. In one embodiment, the first type II clock switch, the first type II weighted switch, the second type II clock switch, and the second type II weighted switch are all NMOS. Each first type II clock switch is connected in series with a different first type II weighted switch, and each second type II clock switch is connected in series with a different second type II weighted switch. The detailed circuit structure of the second charging circuit CC_2, the first discharging circuit DC_1, and the second discharging circuit DC_2 can be obtained from... Figure 2 The first charging circuit CC_1 and Figure 3 The description is derived from this, so it will not be repeated here.

[0024] Figure 4 and Figure 5 An embodiment of the present invention is shown. Figure 2 The diagram shows the operation of the phase interpolation circuit. Figure 4 and Figure 5 In this context, VP refers to the voltage across capacitor C. Please note that, for ease of explanation, in... Figure 4 and Figure 5 middle, Figure 2 Some of the labels shown are omitted, and the first weight control code SW_P1 <n-1:0>Second weight control code SW_P2 <n-1:0>Third weighted control code SW_N1 <n-1:0>and the fourth weight control code SW_N2 <n-1:0>These are abbreviated as the first weight control code SW_P1, the second weight control code SW_P2, the third weight control code SW_N1, and the fourth weight control code SW_N2, respectively. Type 1 Clock Switch Group MP1 <n-1:0>Type 1 Weighted Switch Group MP2 <n-1:0>Type 2, Clock Switch Group MP3 <n-1:0>Type II Weighted Switch Group MP4 <n-1:0>Type I two-weighted switch group MN1 <n-1:0>Type 1, Clock Switch Group MN2 <n-1:0>Type II weighted switch group MN3 <n-1:0>and the second type of two-clock switch group MN4 <n-1:0>These are simplified as follows: Type 1 Clock Switch Group MP1, Type 1 Weighted Switch Group MP2, Type 2 Clock Switch Group MP3, Type 2 Weighted Switch Group MP4, Type 1 Weighted Switch Group MN1, Type 1 Weighted Switch Group MN2, Type 2 Weighted Switch Group MN3, and Type 2 Clock Switch Group MN4. (See also...) Figure 2 , Figure 4 as well as Figure 5 To better understand this invention.

[0025] In one embodiment, in the initial state (not shown), both the first clock signal CK_1 and the second clock signal CK_2 are 0, and both the first weight control code SW_P1 and the second weight control code SW_P2 are 1. Therefore, the first charging circuit CC_1, the second charging circuit CC_2, the first discharging circuit DC_1, and the second discharging circuit DC_2 are all in the off state. At this time, the capacitor C is fully charged, i.e., the voltage VP is 1. Figure 4 In state 1, the first clock signal CK_1 is 1 and the second clock signal CK_2 is 0. The first weight control code SW_P1 and the second weight control code SW_P2 are both 1. The third weight control code SW_N1 turns on 7 switches and turns off 1 switch in the first type-two weighted switch group MN1. The fourth weight control code SW_N2 turns off 7 switches and turns on 1 switch in the second type-two weighted switch group MN3. Therefore, in state 1, the first discharge circuit DC_1 is on while other charging and discharging circuits are off, thus allowing capacitor C to discharge.

[0026] exist Figure 4 In state 2, both the first clock signal CK_1 and the second clock signal CK_2 are 1, both the first weight control code SW_P1 and the second weight control code SW_P2 are 1, the third weight control code SW_N1 turns on 7 switches and turns off 1 switch in the first type two weighted switch group MN1, and the fourth weight control code SW_N2 turns off 7 switches and turns on 1 switch in the second type two weighted switch group MN2. Therefore, in state 2, the first discharge circuit DC_1 and the second discharge circuit DC_2 are on while other charging circuits are off, causing capacitor C to discharge and its value to change from 1 to 0.

[0027] exist Figure 4 In state 3, both the first clock signal CK_1 and the second clock signal CK_2 are 1. The first weight control code SW_P1 turns on 7 switches and turns off 1 switch in the first type-1 weighted switch group MP2. The second weight control code SW_P2 turns off 7 switches and turns on 1 switch in the second type-1 weighted switch group MN2. The third weight control code SW_N1 and the fourth weight control code SW_N2 are both 0. Therefore, in state 3, capacitor C has been completely discharged and thus becomes 0, while all charging and discharging circuits are closed.

[0028] exist Figure 5 In state 4, the first charging circuit CC_1 is activated while other charging and discharging circuits are deactivated, thus charging of capacitor C begins. Figure 5 In state 5, both the first charging circuit CC_1 and the second charging circuit CC_2 are activated, while the discharge circuits are both deactivated. Therefore, capacitor C is still being charged, causing its value to change from 1 to 0. Figure 5 In state 6, capacitor C is fully charged, and all charging and discharging circuits are closed. Figure 5 The operating principle of the mid-phase interpolation circuit and Figure 4 The principles of their movements are the same, therefore their detailed movements can be derived from... Figure 5 The sign and Figure 4 The description is derived from this, so it will not be repeated here.

[0029] By Figure 4 and Figure 5 The action can change the voltage VP to generate an interpolated clock signal, and the number of weight switches can be changed according to the selected phase (i.e., the weight control code is set), so that the charging speed and discharging speed of capacitor C are different (i.e., the weights of the first clock signal CK_1 and the second clock signal CK_2 are changed). Figure 6 A schematic diagram of an interpolated clock signal generated by the aforementioned phase interpolation circuit according to an embodiment of the present invention is shown. Figure 6 As shown, the interpolated clock signal PIC can have different waveforms at different phases PH[0], PH[1], PH[2]... due to different charging and discharging rates. Figure 4 and Figure 5 In the embodiment, phase PH[1] was selected. In phase PH1, the number of weight switches turned on is 1 or 7. In other phases, the number of weight switches turned on will also be different due to the different weight control codes.

[0030] As mentioned earlier, the phase can be selected by changing the weight control code, and the weight control code can be generated in a variety of ways. Figure 7 A schematic diagram illustrating how weight control codes are generated according to an embodiment of the present invention is shown. Figure 7 In one embodiment, the phase interpolation circuit includes a weighted control code generation circuit 700, which includes an inverter INV, NAND gates NA_1 and NA_2, and NOR gates NOR_1 and NOR_2. Figure 7 As shown, the weight control code generation circuit 700 receives a phase selection code P_SEL. <n-1:0>This is used to determine the aforementioned first weight control code SW_P1 <n-1:0>Second weight control code SW_P2 <n-1:0>Third weighted control code SW_N1 <n-1:0>and the fourth weight control code SW_N2 <n-1:0>This determines the first weight, the second weight, the third weight, and the fourth weight.

[0031] Specifically, the inverter INV receives voltage VP to generate an inverted voltage VC, and the NAND gates NA_1 and NA_2, as well as the NOR gates NOR_1 and NOR_2, respectively receive the phase selection code P_SEL. <n-1:0>Or its inverse code P_SELB <n-1:0>And the inverting voltage VC is used to generate the first weighted control code SW_P1 <n-1:0>Second weight control code SW_P2 <n-1:0>Third weighted control code SW_N1 <n-1:0>and the fourth weight control code SW_N2 <n-1:0>However, please note that the weight control codes of this invention are not limited to those used in this invention. Figure 7 It is generated in the manner shown.

[0032] According to the foregoing embodiments, a simple circuit can be used to generate a phase interpolation signal, which can increase the linearity of the phase interpolation signal and improve the circuit power consumption and signal delay.

[0033] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention shall be covered by the present invention.

[0034] [Symbol Explanation]

[0035] 100-phase interpolation circuit

[0036] 700-weight control code generation circuit

[0037] C capacitor

[0038] CC_1 First Charging Circuit

[0039] CC_2 Second Charging Circuit

[0040] DC_1 First Discharge Circuit

[0041] DC_2 Second Discharge Circuit

[0042] INV inverter

[0043] MP1 <n-1:0>MP1, MP11, MP12, MP13, Type 1 Clock Switch Group

[0044] MP2 <n-1:0>MP2, MP21, MP22, MP23, Type I Weighted Switch Group

[0045] MP3 <n-1:0>MP3 Type II Clock Switch Group

[0046] MP4 <n-1:0>MP4 Type II Weighted Switch Group

[0047] MN1 <n-1:0>MN1 Type I Two-Weight Switch Group

[0048] MN2 <n-1:0>MN2 Type I Two Clock Switch Group

[0049] MN3 <n-1:0>MN3 Second type two-weighted switch group

[0050] MN4 <n-1:0>MN4 Type II Clock Switch Group

[0051] NA_1, NA_2 NAND gates

[0052] NOR_1 and NOR_2 gates.

Claims

1. A phase interpolation circuit for generating an interpolated clock signal, comprising: One capacitor; A first charging circuit, coupled to the capacitor, is used to selectively charge the capacitor according to a first clock signal and a first weight control code, wherein the first weight control code determines a first weight of the first clock signal in the interpolated clock signal. A second charging circuit, coupled to the capacitor, is used to selectively charge the capacitor according to a second clock signal and a second weight control code, wherein the second weight control code determines a second weight of the second clock signal in the interpolated clock signal. A first discharge circuit, coupled to the capacitor, is used to selectively discharge the capacitor according to the first clock signal and a third weight control code, wherein the third weight control code determines a third weight of the first clock signal in the interpolated clock signal. as well as A second discharge circuit, coupled to the capacitor, is used to selectively discharge the capacitor according to the second clock signal and a fourth weight control code, the fourth weight control code determining a fourth weight of the second clock signal in the interpolated clock signal.

2. The phase interpolation circuit as described in claim 1, The first charging circuit includes: A group of first-type-one clock switches, comprising at least one first-type-one clock switch, wherein the first-type-one clock switches are simultaneously turned on or simultaneously turned off according to the first clock signal; and A first type weighted switch group includes at least one first type weighted switch, which is turned on or off according to the first weighted control code; The second charging circuit includes: A group of second-type clock switches, comprising at least one second-type clock switch, wherein the second-type clock switches are simultaneously turned on or simultaneously turned off according to the second clock signal; and A second type of weighted switch group, comprising at least one second type of weighted switch, wherein the second type of weighted switch is turned on or off according to the second weighted control code.

3. The phase interpolation circuit as described in claim 2, wherein the first type-clock switch, the first type-weight switch, the second type-clock switch, and the second type-weight switch are all PMOS.

4. The phase interpolation circuit as described in claim 2, wherein each of the first type-clock switches is connected in series with different first type-weight switches, and each of the second type-clock switches is connected in series with different second type-weight switches.

5. The phase interpolation circuit as described in claim 1, The first discharge circuit includes: A group of first type II clock switches, comprising at least one first type II clock switch, wherein the first type II clock switches are simultaneously turned on or simultaneously turned off according to the first clock signal; and A first type two weighted switch group, comprising at least one first type two weighted switch, wherein the first type two weighted switch is turned on or off according to the third weighted control code; The second discharge circuit includes: A group of second-type-two clock switches, comprising at least one second-type-two clock switch, wherein the second-type-two clock switches are simultaneously turned on or simultaneously turned off according to the second clock signal; and A group of second-type two-weighted switches, comprising at least one second-type two-weighted switch, wherein the second-type two-weighted switch is turned on or off according to the fourth weighted control code.

6. The phase interpolation circuit as described in claim 5, wherein the first type two clock switch, the first type two weighted switch, the second type two clock switch, and the second type two weighted switch are all NMOS.

7. The phase interpolation circuit as described in claim 5, wherein each of the first type II clock switches is connected in series with different first type II weighted switches, and each of the second type II clock switches is connected in series with different second type II weighted switches.

8. The phase interpolation circuit as claimed in claim 1, wherein the first charging circuit and the first discharging circuit are connected in series, the second charging circuit and the second discharging circuit are connected in series, a first end of the capacitor is coupled to the coupling point of the first charging circuit and the first discharging circuit, and a second end of the capacitor is coupled to the coupling point of the second charging circuit and the second discharging circuit.

9. The phase interpolation circuit of claim 1, wherein the phase interpolation circuit further receives a phase selection code for determining the first weight, the second weight, the third weight, and the fourth weight.

10. A phase interpolation circuit for generating an interpolated clock signal, comprising: One capacitor; A first charging circuit, coupled to the capacitor, is used to selectively charge the capacitor according to a first clock signal and a first weighting control code. A second charging circuit, coupled to the capacitor, is used to selectively charge the capacitor according to a second clock signal and a second weighting control code. A first discharge circuit, coupled to the capacitor, is used to selectively discharge the capacitor according to the first clock signal and a third weighting control code. as well as A second discharge circuit, coupled to the capacitor, is used to selectively discharge the capacitor according to the second clock signal and a fourth weighting control code. The first charging circuit and the first discharging circuit are connected in series, the second charging circuit and the second discharging circuit are connected in series, and a first end of the capacitor is coupled to the coupling point of the first charging circuit and the first discharging circuit, and a second end of the capacitor is coupled to the coupling point of the second charging circuit and the second discharging circuit. The first charging circuit, the second charging circuit, the first discharging circuit, and the second discharging circuit each include switches connected in series. The first weight control code, the second weight control code, the third weight control code, and the fourth weight control code respectively control the number of switches turned on in the first charging circuit, the second charging circuit, the first discharging circuit, and the second discharging circuit.

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