DMOS gate voltage dynamic compensation method and system based on temperature feedback

Abstract

The application discloses a DMOS gate voltage dynamic compensation method and system based on temperature feedback, relates to the field of power electronic device thermal management, and comprises the following steps: periodically collecting temperature signals at multiple spatial positions of a DMOS device; projecting a temperature sequence in a short time window on a group of thermal response base functions to obtain a base coefficient set; calculating a fast protection index, and if the fast protection index exceeds a threshold value, performing proportional amplitude reduction of a gate driving voltage based on an analog channel; inputting the base coefficient set into a digital prediction channel to predict the spatial temperature evolution in the future, constructing an optimal gate voltage curve with temperature constraints; obtaining a preprocessing strategy, performing curve correction, and issuing a response strategy of an independent driving sub-area to execute partition compensation management. The application solves the technical problems that existing thermal management is not accurate in regulation and control and is difficult to maintain system performance while inhibiting temperature rise, and achieves the technical effects of accurately regulating and controlling a thermal field and maintaining system performance to the maximum extent while inhibiting temperature rise.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronic device thermal management, in particular to a DMOS gate voltage dynamic compensation method and system based on temperature feedback. BACKGROUND

[0002] The dynamic thermal management and reliability guarantee of power DMOS devices in operation are the core challenges of power electronic systems. If the instantaneous temperature rise is not controlled, it will directly lead to device thermal breakdown and even system failure. Existing solutions mainly use global shutdown protection based on fixed temperature threshold. By setting temperature sensors on DMOS devices, the device temperature is monitored in real time. When the temperature reaches the preset fixed threshold, the protection mechanism is triggered, such as reducing the gate drive voltage or directly shutting down the device, to prevent the device from being damaged due to overheating. However, due to the spatial and temporal non-uniformity of temperature distribution of DMOS devices during operation, the temperature change rate and peak temperature at different positions are different. The fixed threshold cannot accurately reflect the actual thermal state of each part of the device, which may trigger protection when the temperature in some areas has not reached a dangerous level, affecting the normal operation of the system. Moreover, this method can only respond passively to the overheating situation that has occurred, and cannot predict the temperature change trend in advance, so it cannot take effective preventive measures in time. When facing rapidly changing loads and complex working conditions, it is difficult to effectively suppress the instantaneous temperature rise, and the protection effect is not good.

[0003] At present, in the related technology, the DMOS device thermal management has the technical problems of inaccurate regulation and difficult to maintain system performance while suppressing temperature rise. SUMMARY

[0004] The present application provides a DMOS gate voltage dynamic compensation method and system based on temperature feedback. Temperature signals are periodically collected at multiple spatial positions of the DMOS device to construct a temperature sequence. The temperature sequence is projected with a thermal response basis function in a short time window to obtain a basis coefficient set, which represents the spatiotemporal thermal evolution characteristics. A fast protection index is calculated based on the basis coefficient set. If the index exceeds the threshold, the gate drive voltage is reduced through an analog channel to suppress the temperature rise. Then, the basis coefficient set is input into a digital prediction channel to predict the future temperature evolution, and an optimal gate voltage curve is constructed. After the analog channel preprocessing strategy is obtained, the optimal gate voltage curve is corrected, and an independent drive sub-region response strategy is issued to execute partition compensation management. The technical problems of inaccurate regulation and difficult to maintain system performance while suppressing temperature rise in existing DMOS device thermal management are solved, and the technical effects of precise regulation of thermal field and maximum maintenance of system performance while suppressing instantaneous temperature rise are achieved.

[0005] The application provides a DMOS gate voltage dynamic compensation method based on temperature feedback, comprising: periodically collecting temperature signals at multiple spatial positions of a DMOS device to construct a temperature sequence; projecting the temperature sequence in a short time window on a group of thermal response basis functions to obtain a basis coefficient set, which represents the time-space thermal evolution characteristics of the DMOS device; calculating a fast protection index based on the basis coefficient set, and if the fast protection index exceeds a preset threshold, performing proportional amplitude reduction of the gate driving voltage based on an analog channel to suppress the instantaneous temperature rise; inputting the basis coefficient set into a digital prediction channel, predicting the short-time future spatial temperature evolution by using a historical basis coefficient sequence and a basis function dictionary library, and constructing an optimal gate voltage curve with temperature constraints according to the prediction result and a preset time window; after obtaining the preprocessing strategy of the analog channel, executing the optimal gate voltage curve correction according to the preprocessing strategy, issuing a response strategy of an independent driving sub-area according to the correction result, and performing partition compensation management.

[0006] In a possible implementation, the optimal gate voltage curve correction is executed according to the preprocessing strategy, and the following processing is performed: the preprocessing strategy is sent to the digital prediction channel as additional data; an analog temperature fitting layer in the digital prediction channel is activated, spatial temperature influence analysis under the preprocessing strategy is performed by using the analog temperature fitting layer, and an influence fitting result is established; hysteresis verification data under the preprocessing strategy is read, after trend correction of the influence fitting result is performed according to the hysteresis verification data, trend correction result is used for short-time future spatial temperature evolution compensation, and the prediction result is updated; and the optimal gate voltage curve correction is completed by using the updated prediction result.

[0007] In a possible implementation, the basis coefficient set is input into the digital prediction channel, the short-time future spatial temperature evolution is predicted by using the historical basis coefficient sequence and the basis function dictionary library, and the following processing is performed: the digital prediction channel comprises a thermal feature coding unit, a time series prediction unit and a reconstruction mapping unit; the historical basis coefficient sequence is unfolded into a time series feature vector in the time dimension by using the thermal feature coding unit; the basis function dictionary library is a multi-dimensional response subspace constructed based on the DMOS structure topology and material thermal constants, and the time series prediction unit is used to predict dominant basis coefficients based on the time series feature vector and the basis function dictionary library under the feedback of the gate voltage dynamic component, wherein the feedback of the gate voltage dynamic component is used to realize thermal-electric dual-domain coupled prediction; the dominant basis coefficient prediction result is sent to the reconstruction mapping unit to generate a short-time temperature distribution matrix, so as to complete the spatial temperature evolution.

[0008] In a possible implementation, the temperature sequence is projected on a set of thermal response basis functions in a short time window to obtain a basis coefficient set, and the following processing is performed: the temperature sequence measured by each temperature measurement node of the DMOS device is divided by time and normalized in each sampling period; a preset thermal response basis function is called, and the thermal response basis function is composed of a plurality of sets of orthogonal functions with different time constants and spatial diffusion coefficients; the projection coefficients of the normalized temperature sequence on the thermal response basis function are calculated by using a sliding weighted least square projection algorithm, and the basis coefficient set is established, wherein the weighting factor is adaptively adjusted according to the local thermal gradient and the signal-to-noise ratio of the temperature measurement node.

[0009] In a possible implementation, a fast protection index is calculated based on the basis coefficient set, and the following processing is performed: the basis coefficient set in adjacent time windows is subjected to time differentiation operation to obtain a basis change rate matrix; the maximum change rate of a main basis component and the proportion of high-order basis energy in the basis change rate matrix are extracted, and a transient thermal stress coefficient is calculated according to the extraction result and in combination with the local thermal gradient distribution; and the fast protection index is constructed based on the transient thermal stress coefficient.

[0010] In a possible implementation, a proportional reduction amplitude of the gate drive voltage is performed based on the analog channel, and the following processing is performed: a gate voltage modulation layer of the analog channel is activated, the gate voltage modulation layer includes a proportional feedback unit, a hysteresis correction unit, and a transient amplitude limiting unit; a reduction amplitude proportional coefficient is calculated by using the proportional feedback unit according to the fast protection index, and the gate drive voltage reduction amplitude management is performed by using the reduction amplitude proportional coefficient; the hysteresis correction unit is used for smooth recovery constraint of the gate drive voltage reduction amplitude management process; and the transient amplitude limiting unit is used for gate voltage change amplitude constraint in a single cycle to complete the proportional reduction amplitude management.

[0011] In a possible implementation, a response strategy of an independent driving sub-region is issued according to the correction result, and partition compensation management is performed, and the following processing is performed: the gate drive network of the DMOS device is divided into N independent driving sub-regions according to the correction result, each independent driving sub-region corresponds to a local temperature observation node and an associated thermal coupling region; a partition compensation coefficient is calculated in each independent driving sub-region according to the basis coefficient component and the predicted temperature rise rate, and a cooperative adjustment model is established based on the thermal coupling strength of the independent driving sub-region; the partition compensation coefficient is used for compensation management, and the gate voltage adjustment amplitude of adjacent sub-regions is dynamically balanced through the cooperative adjustment model, to complete the partition compensation management.

[0012] In a possible implementation, the amplitude of the gate voltage adjustment of adjacent sub-regions is dynamically balanced by a cooperative adjustment model to complete the partition compensation management, and the following processing is performed: obtaining a global average temperature rise rate of a gate voltage adjustment process, establishing a focus compensation weight when any local temperature rise rate is higher than the global average temperature rise rate; performing hotspot focus compensation according to the focus compensation weight to complete the partition compensation management.

[0013] In a possible implementation, the partition compensation management is performed, and the following processing is further performed: establishing a contraction constraint collected periodically according to the response strategy; after adjusting the collection period by using the contraction constraint, the periodic temperature collection is continued.

[0014] The application also provides a DMOS gate voltage dynamic compensation system based on temperature feedback, comprising: a temperature signal collection module, configured to periodically collect temperature signals at a plurality of spatial positions of a DMOS device to construct a temperature sequence; a base coefficient set acquisition module, configured to project the temperature sequence in a short time window on a group of thermal response base functions to acquire a base coefficient set, the base coefficient set representing the space-time thermal evolution characteristics of the DMOS device; a fast protection index calculation module, configured to calculate a fast protection index based on the base coefficient set, and if the fast protection index exceeds a preset threshold, performing a proportional amplitude reduction of the gate driving voltage based on a simulation channel to suppress the instantaneous temperature rise; an optimal gate voltage curve construction module, configured to input the base coefficient set into a digital prediction channel, predict the spatial temperature evolution in the short future by using a historical base coefficient sequence and a base function dictionary library, and construct an optimal gate voltage curve of temperature constraint according to the prediction result and a preset time window; and a partition compensation management module, configured to execute optimal gate voltage curve correction according to a preprocessing strategy of the simulation channel after the preprocessing strategy is acquired, issue a response strategy of an independent driving sub-region according to the correction result, and perform partition compensation management.

[0015] The DMOS gate voltage dynamic compensation method and system based on temperature feedback provided in the application first periodically collects temperature signals at multiple spatial positions of the DMOS device, constructs a temperature sequence, then projects the temperature sequence in a short time window on a group of thermal response basis functions, obtains a basis coefficient set, the basis coefficient set represents the space-time thermal evolution characteristics of the DMOS device, then calculates a fast protection index based on the basis coefficient set, if the fast protection index exceeds a preset threshold, performs proportional amplitude reduction of the gate driving voltage based on the simulation channel to suppress the instantaneous temperature rise, then inputs the basis coefficient set to the digital prediction channel, predicts the future spatial temperature evolution in the short term by using the historical basis coefficient sequence and the basis function dictionary library, constructs an optimal gate voltage curve with temperature constraints according to the prediction result and a preset time window, finally, according to the preprocessing strategy of the simulation channel, executes the optimal gate voltage curve correction according to the correction result, issues the response strategy of the independent driving sub-area according to the correction result, and executes the partition compensation management. The technical effects of accurately regulating the thermal field and maintaining the system performance to the maximum while suppressing the instantaneous temperature rise are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings of the embodiments of the application will be briefly introduced below. In the present application, a flowchart is used to illustrate the operations performed by the system according to the embodiments of the application. It should be understood that the foregoing or the following operations are not necessarily performed in sequence. On the contrary, various steps can be processed in reverse order or simultaneously as needed. Meanwhile, other operations can be added to these processes, or a step or several steps can be removed from these processes.

[0017] Figure 1 The flowchart of the DMOS gate voltage dynamic compensation method based on temperature feedback provided by the embodiments of the application.

[0018] Figure 2 The structural schematic diagram of the DMOS gate voltage dynamic compensation system based on temperature feedback provided by the embodiments of the application.

[0019] The reference signs are explained as follows: temperature signal collection module 10, basis coefficient set acquisition module 20, fast protection index calculation module 30, optimal gate voltage curve construction module 40, and partition compensation management module 50. DETAILED DESCRIPTION

[0020] In order to further illustrate the technical means and effects adopted by the application to achieve the predetermined application purpose, the specific embodiments, structures, features and effects according to the application are described in detail below with reference to the drawings and preferred embodiments.

[0021] The embodiments of the application provide a DMOS gate voltage dynamic compensation method based on temperature feedback, as shown inFigure 1 The method comprises:

[0022] In step S100, temperature signals are periodically collected at multiple spatial positions of the DMOS device to construct a temperature sequence.

[0023] Specifically, the DMOS device is a double-diffused metal-oxide-semiconductor field-effect transistor used in a power switching circuit, and its on-resistance and switching loss cause the device to generate heat. Multiple temperature sensors are arranged near key regions on the surface or inside the DMOS chip, such as the drain, source, and gate. The temperature sensors can be PN junction temperature sensors, thermistors, or infrared temperature measurement units. The temperature sensors synchronously collect temperature values of each node at fixed time intervals, such as every 10 microseconds, to form a multi-channel temperature data arranged in time sequence, i.e., a temperature sequence, which is used to represent the change in the thermal state of the device at different positions over time.

[0024] In step S200, the temperature sequence is projected within a short time window with a set of thermal response basis functions to obtain a basis coefficient set, which represents the spatiotemporal thermal evolution characteristics of the DMOS device.

[0025] Specifically, a short time window, such as a 100-microsecond time period, is selected, and the temperature sequence collected within this window is projected with a pre-set set of thermal response basis functions. The thermal response basis function is a mathematical function used to describe the propagation pattern of heat in the device. Each basis represents a specific heat conduction path and time response characteristic. The projection operation can be performed by vector dot product or other methods to calculate the projection values of the temperature sequence in the direction of each thermal response basis function, thereby decomposing the complex temperature change into components in the direction of the basis functions. The set of these projection values is the basis coefficient set, which reflects the matching degree of the current temperature distribution with each thermal mode, i.e., the participation degree of the device under different thermal response modes, thereby representing the spatiotemporal thermal evolution characteristics of the device.

[0026] In one possible implementation, the temperature sequence is projected within a short time window with a set of thermal response basis functions to obtain a basis coefficient set, and step S200 further comprises step S210 of performing normalization processing on the temperature sequence measured by each temperature measurement node of the DMOS device after time division in each sampling period. Specifically, in each sampling period, the temperature data collected by each temperature measurement node is divided into multiple short time windows, such as one window per 100 milliseconds, and the temperature data in each window is normalized, such as subtracting the minimum temperature value in the segment and dividing by the temperature range obtained by subtracting the minimum temperature value from the maximum temperature value, so that the normalized data range is between 0 and 1, to eliminate the effects of dimension and baseline drift.

[0027] At step S220, a preset thermal response basis function is called, and the thermal response basis function is composed of a plurality of sets of orthogonal functions with different time constants and spatial diffusion coefficients. Specifically, a set of thermal response basis functions is pre-stored in the storage unit of the system, and the functions are composed of a plurality of orthogonal functions, such as Legendre polynomials, Fourier basis functions, etc., each basis function corresponding to a different thermal diffusion time constant and a spatial distribution mode, simulating the typical path of heat propagation inside the device. Among them, the orthogonality is used to ensure the independence between each function, so that the projection operation can accurately separate the components of the temperature sequence under different thermal response modes.

[0028] At step S230, the projection coefficients of the normalized temperature sequence on the thermal response basis function are calculated using the sliding weighted least squares projection algorithm, and a basis coefficient set is established, wherein the weighting factor is adaptively adjusted according to the local thermal gradient and the signal-to-noise ratio of the temperature measurement node. Specifically, the sliding weighted least squares projection is a method of fitting data by minimizing the weighted sum of squares of errors within a sliding time window. The sliding weighted least squares projection algorithm is adopted, and the algorithm assigns a weighting factor to the temperature data of each temperature measurement node when calculating the projection coefficients. The calculation of the weighting factor is adaptively adjusted according to the local thermal gradient and the signal-to-noise ratio around the temperature measurement node, and lower weights are given to areas with high thermal gradients or nodes with low signal-to-noise ratios to reduce noise interference, wherein the local thermal gradient can be obtained by calculating the temperature difference between adjacent temperature measurement nodes, reflecting the degree of temperature change; the signal-to-noise ratio is obtained by analyzing the fluctuation of the temperature data, reflecting the reliability of the data. Then, the projection coefficients of the temperature sequence on the thermal response basis function are calculated by the least squares method, and the basis coefficient set is obtained.

[0029] At step S300, a fast protection index is calculated based on the basis coefficient set, and if the fast protection index exceeds a preset threshold, a proportional reduction amplitude of the gate drive voltage is performed based on the simulation channel to suppress the transient temperature rise.

[0030] Specifically, the fast protection index is a quantitative parameter for evaluating the transient thermal risk of the device, which is calculated based on the basis coefficient change rate and the local thermal gradient. A threshold is pre-set, and when the calculated fast protection index exceeds this threshold, it indicates that the device may face an overheating risk. At this time, the reduction amplitude of the gate drive voltage is calculated according to the fast protection index through the simulation channel, and the gate drive voltage is adjusted in real time by reducing the gate drive voltage, thereby reducing the power loss of the device and suppressing the transient temperature rise to protect the device from damage. Among them, the simulation channel is a fast response path composed of analog circuits, containing corresponding circuits and logic, and does not depend on digital processing, which can achieve nanosecond-level response.

[0031] In a possible implementation, the fast protection index is calculated based on the set of base coefficients, and step S300 further includes step S310 of performing a time differentiation operation on the set of base coefficients in adjacent time windows to obtain a base change rate matrix. Specifically, the set of base coefficients in two adjacent time windows is selected, and the base coefficients at corresponding positions in the two sets are subjected to a time differentiation operation. It is assumed that the system stores all base coefficient data in a short historical time period at a current monitoring time. The data can be arranged in a table, each row of the table representing a specific thermal response mode, i.e., a coefficient change sequence of a base in the historical time period. Each column of the table represents a set of all base coefficients at a specific sampling time. The change rate of each row of data in the table, i.e., the coefficient sequence of each thermal response mode, is calculated, that is, the coefficient value of a base at the current time is subtracted from the coefficient value of the base at the previous time, and the difference is the change rate of the base at the current time. The calculation process is applied to each data point in the table, and finally a new table is generated. The new table no longer records the base coefficients, but records the change rate of each base at each time, i.e., the base change rate matrix, which shows the speed and direction of changes of various thermal modes in the recent period of time.

[0032] Step S320 extracts the maximum change rate of the principal base component and the proportion of high-order base energy in the base change rate matrix, and calculates the transient thermal stress coefficient according to the extraction result combined with the local thermal gradient distribution. Specifically, the principal base component is identified, that is, by calculation and comparison, the base with the strongest average energy in the last time period, i.e., the maximum sum of the square of the coefficient value, is found, which is the principal base. The principal base represents the most important and macroscopic thermal diffusion mode of the device. In the base change rate matrix, the row of data corresponding to the principal base component is found, which records the change rate of the principal base at each time in the recent period of time, the absolute value of the change rate is taken, i.e., the decline is ignored, and only the severity of the rise is concerned, and then the maximum value is found, which is the maximum change rate of the principal base component. If the maximum change rate of the principal base component suddenly and sharply increases, it indicates that the overall thermal state of the device is rapidly and globally deteriorating, which is a strong warning signal of thermal runaway.

[0033] All the bases are sorted according to the complexity of the thermal mode they represent from low to high, and the bases ranked in the last about 30% are defined as high-order bases, which correspond to local, fast-forming and changing tiny hot spots inside the device. The total energy of all the high-order base coefficients in the last complete time period, i.e. the sum of their squared coefficients, is calculated, and then this total energy is divided by the total energy of all the base coefficients to obtain a ratio, which is the high-order base energy ratio. The increase of the high-order base energy ratio indicates the presence of strong, local abnormal heating spots inside the device, which is a direct manifestation of local thermal overload.

[0034] The local thermal gradient is directly calculated from the readings of multiple temperature sensors arranged on the surface of the chip, i.e. the temperature difference between all adjacent sensor pairs is found, and then the maximum value of these differences is taken. The transient thermal stress coefficient is equal to the maximum rate of change of the primary bases multiplied by a weight, plus the high-order base energy ratio multiplied by another weight, plus the local thermal gradient multiplied by a third weight. Among them, the three weights are proportional constants determined by thermal testing of the device.

[0035] Step S330, constructing a fast protection index based on the transient thermal stress coefficient. Specifically, a reference stress value is preset, which is used to offset the inherent, harmless stress background during normal operation. The calculated transient thermal stress coefficient is subtracted by the reference stress value to obtain the net stress increment. The net stress increment is divided by a preset scaling coefficient to adjust the final index value to a range convenient for comparison with a fixed threshold. The value obtained after the final processing is the fast protection index.

[0036] In a possible implementation, based on the proportional reduction of the gate drive voltage of the analog channel, step S300 further includes step S340 of activating the gate voltage modulation layer of the analog channel, which includes a proportional feedback unit, a hysteresis correction unit and a transient amplitude limiting unit. Specifically, when the fast protection index exceeds the threshold value, a special circuit module, i.e. the gate voltage modulation layer, in the analog channel is immediately activated. This module is composed of analog electronic elements such as operational amplifiers, resistors, capacitors and comparators, etc., for achieving a nanosecond-level extremely fast response. The gate voltage modulation layer contains three core sub-units working cooperatively, among which the proportional feedback unit is an analog calculation circuit, whose output voltage has a preset proportional relationship with the input, i.e. the fast protection index; the hysteresis correction unit is a comparator circuit with hysteresis characteristics, which can prevent the gate voltage from frequently oscillating around the threshold point; the transient amplitude limiting unit is a clamping circuit for strictly limiting the maximum change amplitude of the output voltage within a single control period.

[0037] Step S350, the proportional feedback unit is used to calculate the amplitude reduction proportional coefficient according to the fast protection index, and the amplitude reduction proportional coefficient is used to perform the gate drive voltage amplitude reduction management. Specifically, the proportional feedback unit receives a voltage signal proportional to the fast protection index converted from the previous stage circuit. The unit internally presets a voltage-amplitude reduction coefficient relationship, for example, when the input voltage reaches 1 volt, the gate voltage needs to be reduced by 5%. The unit internally generates an analog control voltage proportional to the input voltage in real time through a resistance voltage dividing network and an operational amplifier circuit. The control voltage is the physical embodiment of the amplitude reduction proportional coefficient. The control voltage is directly sent to the voltage reference control pin of the gate drive chip or used to modulate the reference low level, thereby immediately and linearly reducing the actual drive voltage applied to the DMOS gate. By reducing the gate voltage, the conduction degree of the device is weakened, the current flowing through is reduced, and the power loss and temperature rise are inhibited.

[0038] Step S360, the hysteresis correction unit is used to perform the smooth recovery constraint of the gate drive voltage amplitude reduction management process. Specifically, when the temperature risk is removed and the fast protection index falls below the normal threshold, the hysteresis correction unit starts to work to avoid system jitter. The unit has a release threshold, which is lower than the triggered protection threshold. That is, only when the fast protection index falls below the release threshold from the high, the hysteresis correction unit outputs a signal to allow the proportional feedback unit to stop working, and the gate voltage starts to recover. If the index fluctuates between the release threshold and the protection threshold, the unit will maintain the original state unchanged. This hysteresis characteristic ensures that the gate voltage will not jump repeatedly due to the small and frequent fluctuations of the index, and realizes the smooth exit of the amplitude reduction management and the stable recovery of the system.

[0039] Step S370, the transient amplitude limiting unit is used to constrain the amplitude of the gate voltage change within a single cycle to complete the proportional amplitude reduction management. Specifically, the transient amplitude limiting unit is connected in series in the control signal path to prevent sudden changes in the gate voltage. The unit is a peak holding and voltage clamping circuit composed of a diode and a capacitor. Regardless of how large the theoretical amplitude calculated by the proportional feedback unit is, the transient amplitude limiting unit will limit the actual amplitude of the gate voltage within a single control cycle to a preset safe value, for example, the maximum change of the gate voltage is not more than 2% of its rated value. This is used to prevent problems such as current change, voltage overshoot or electromagnetic interference caused by sharp drop of the gate voltage, and to ensure the transient stability of the power system, thereby completing the proportional amplitude reduction management which is fast and smooth.

[0040] Step S400, the set of base coefficients is input to the digital prediction channel, the spatial temperature evolution in the short future is predicted using the historical base coefficient sequence and the base function dictionary library, and the optimal gate voltage curve constrained by temperature is constructed according to the prediction result and the preset time window.

[0041] Specifically, the digital prediction channel is a software algorithm module running on a digital signal processor or microcontroller, which combines the real-time acquired set of basis coefficients with the stored historical basis coefficient sequence and the basis function dictionary library. The historical basis coefficient sequence is a record of all basis coefficients in the past period of time. The basis function dictionary library is a database that stores various typical thermal response patterns, which are obtained in advance by modeling the physical structure and thermal properties of the DMOS device or a large number of experiments. The Kalman filter or long short-term memory network model analyzes the trend of the basis coefficients over time and predicts the most likely trajectory of the change of each basis coefficient in a very short period of time, such as 1 millisecond, in combination with the influence of the current gate voltage state on heat generation. Re-combining these predicted future basis coefficients with the corresponding basis functions generates a predicted temperature distribution map of the chip surface at the future time. With the predicted temperature map as a constraint condition, the optimal gate drive voltage adjustment curve that can optimize the system performance is calculated by solving the optimization algorithm under the premise of ensuring that the predicted temperature at any position does not exceed the upper limit of safety.

[0042] In one possible implementation, the set of basis coefficients is input to the digital prediction channel, and the historical basis coefficient sequence and the basis function dictionary library are used to predict the spatial temperature evolution in the short future. Step S400 further includes step S410, and the digital prediction channel includes a thermal feature encoding unit, a time series prediction unit, and a reconstruction mapping unit. The historical basis coefficient sequence is unfolded into a time series feature vector in the time dimension by using the thermal feature encoding unit. Specifically, the thermal feature encoding unit is a data preprocessing algorithm that concatenates the coefficient values of each basis at multiple sampling time points in the past into a long data sequence, i.e., a time series feature vector, in chronological order. The vector comprehensively represents the complete information of the recent evolution of the device thermal state, and is used to provide format-regularized input data for prediction.

[0043] At step S420, the base function dictionary library is a multi-dimensional response subspace constructed based on DMOS structure topology and material thermal constants. The time sequence prediction unit predicts the dominant base coefficients based on the time sequence feature vector and the base function dictionary library under the feedback of the gate voltage dynamic component, wherein the feedback of the gate voltage dynamic component is used to realize the thermal-electric dual-domain coupling prediction. Specifically, the base function dictionary library is a multi-dimensional response subspace established through theoretical analysis and experiments, which contains thermal response base functions under different DMOS structure topologies and material thermal constants, and can more accurately describe the thermal response characteristics of the device. The time sequence prediction unit receives the time sequence feature vector and queries the base function dictionary library, and receives the feedback signal of the gate voltage dynamic component from the gate drive circuit, which indicates the current or upcoming gate voltage adjustment strategy. The time sequence prediction unit learns and understands the thermal-electric coupling relationship between the gate voltage change and the base coefficient change through an internal model such as a trained neural network. On this basis, instead of predicting all base coefficients, the dominant base coefficients that have a decisive influence on the overall temperature field in the future period are predicted, which ensures prediction accuracy and reduces computational complexity.

[0044] At step S430, the dominant base coefficient prediction result is sent to the reconstruction mapping unit to generate a short-time temperature distribution matrix to complete the spatial temperature evolution. Specifically, the reconstruction mapping unit receives the dominant base coefficients at the future time output by the time sequence prediction unit, then multiplies these coefficients with the corresponding dominant base functions in the base function dictionary library and sums them up to reconstruct the temperature distribution of the entire DMOS chip in space at the future time, and outputs it in the form of a two-dimensional matrix, i.e., a short-time temperature distribution matrix, which shows the predicted future thermal map.

[0045] At step S500, after obtaining the pre-processing strategy of the analog channel, the optimal gate voltage curve correction is performed according to the pre-processing strategy, the response strategy of the independently driven sub-region is issued according to the correction result, and the partition compensation management is performed.

[0046] Specifically, the fast protection action performed by the analog channel, i.e., the pre-processing strategy, such as a 5% reduction in gate voltage, is used as prior information. Based on this fact, the digital prediction channel re-evaluates and corrects the calculated optimal gate voltage curve, and the corrected curve is more consistent with the actual situation, which can improve the accuracy of voltage adjustment. After correction, the gate drive network of the DMOS device is divided into multiple independently driven sub-regions according to the correction result, a corresponding response strategy is formulated for each sub-region, such as different gate drive voltage adjustment amplitudes, and partition compensation management is performed to improve the effect of temperature control.

[0047] In one possible implementation, the optimal gate voltage curve correction is performed according to the pre-processing strategy, and step S500 further includes step S510 of sending the pre-processing strategy as additional data to the digital prediction channel. Specifically, the analog channel sends the key parameters such as the gate voltage drop amplitude ratio, duration, and the like, which have been executed, to the input buffer of the digital prediction channel as a set of additional data packets through a system bus or a shared memory.

[0048] Step S520 activates the analog temperature fitting layer in the digital prediction channel, performs spatial temperature influence analysis under the pre-processing strategy by using the analog temperature fitting layer, and establishes an influence fitting result. Specifically, the analog temperature fitting layer is arranged in the digital prediction channel and includes a set of heat conduction equation solvers. When the pre-processing strategy is received, the analog temperature fitting layer is activated. After the layer is activated, the current temperature distribution and the chip thermal model are used as initial conditions, the pre-processing strategy of the analog channel is input as a boundary condition, the possible change of the chip temperature field after the execution of the strategy is quickly simulated and calculated, and a preliminary influence fitting result, for example, a relationship curve between the temperature change and the gate drive voltage adjustment, is output.

[0049] Step S530 reads the hysteresis verification data under the pre-processing strategy, performs trend correction on the influence fitting result according to the hysteresis verification data, performs spatial temperature evolution compensation in a short future by using the trend correction result, and updates the prediction result. Specifically, the historical hysteresis verification data related to the current pre-processing strategy are read from a storage unit. These data record the actual delay and inertia characteristics of the temperature response after the execution of the same gate voltage adjustment under similar working conditions in the past. The preliminary result of the analog temperature fitting layer is idealized, and the hysteresis verification data reflect the thermal inertia of the actual system. The preliminary fitting result is corrected by using these real data, for example, the predicted rate of temperature drop is slowed down, so that the prediction is closer to the physical reality. The short-time spatial temperature evolution prediction in step S400 is compensated by using the result after the trend correction, and an updated and more accurate prediction result is obtained.

[0050] Step S540 completes the optimal gate voltage curve correction by using the updated prediction result. Specifically, the updated and more accurate temperature prediction result is used as a new constraint condition, and the optimization calculation is performed again to fine-tune and update the previously planned optimal gate voltage curve, and the final corrected optimal gate voltage curve is generated.

[0051] In a possible implementation, the response strategy of the independent driving sub-area is issued according to the correction result, and the partition compensation management is performed, and step S500 further includes step S550. According to the correction result, the gate driving network of the DMOS device is divided into N independent driving sub-areas, and each independent driving sub-area corresponds to a local temperature observation node and an associated thermal coupling area. Specifically, according to the temperature distribution information revealed by the corrected optimal gate voltage curve, the entire DMOS gate is logically divided into N, for example, 4, sub-areas that can be independently controlled. The division is based on the hot spot distribution and thermal coupling characteristics of the chip, and specifically includes: using a gate driving chip with multi-channel output capability or grouping multiple single-channel driving chips, and independently addressing and controlling each driving channel through a digital address bus or a chip selection signal. A clustering algorithm is run to automatically divide the entire chip area into N clusters with similar thermal characteristics, each cluster being an independent driving sub-area. For each divided independent driving sub-area, a temperature sensor closest to the geometric center or the highest temperature point of the sub-area is designated as the local temperature observation node. At the same time, according to the thermal conductivity model of the chip, the chip area most significantly affected by the gate voltage adjustment of the sub-area is calculated, which is defined as the associated thermal coupling area of the sub-area.

[0052] Step S560, calculating the partition compensation coefficient in each independent driving sub-area according to the base coefficient component and the predicted temperature rise rate, and establishing a collaborative adjustment model based on the thermal coupling strength of the independent driving sub-area. Specifically, for each independent driving sub-area, from the global base coefficient set, several base coefficient components most related to the thermal behavior mode of the sub-area are selected. At the same time, from the predicted temperature distribution matrix, the average temperature change rate of the pixel points covered by the sub-area in the prediction time, that is, the predicted temperature rise rate, is extracted. A preset temperature rise-compensation lookup table is maintained, which is obtained through previous experimental calibration. The extracted related base coefficient component amplitude and the predicted temperature rise rate are input, and a partition compensation coefficient suitable for the sub-area is output in real time through lookup table or fitting calculation. The coefficient is a dimensionless scaling factor that determines the proportion of the gate voltage adjustment of the sub-area.

[0053] The thermal coupling strength matrix is pre-calculated and stored, which is based on the finite element thermal model of the chip, and is obtained by calculating the thermal resistance inverse between the center points of any two independently driven sub-regions or simulating the temperature rise of one sub-region when another sub-region is heated. Each element in the matrix quantifies the thermal interaction strength between the sub-regions. The collaborative adjustment model is a distributed optimal controller that receives the partition compensation coefficients and real-time temperature data of all sub-regions as inputs, and contains a target function inside, which minimizes the overall gate voltage adjustment energy while pursuing the uniformity of the temperature of each sub-region. The thermal coupling strength matrix is used as a parameter of the target function to ensure that the model can fully foresee and offset the thermal interference caused by one sub-region to its adjacent sub-regions when calculating the final adjustment instruction of the sub-region.

[0054] Step S570, the partition compensation management is performed by using the partition compensation coefficients, and the gate voltage adjustment amplitudes of adjacent sub-regions are dynamically balanced by the collaborative adjustment model to complete the partition compensation management. Specifically, the preliminary calculated partition compensation coefficients of each sub-region are distributed to the corresponding independently addressable gate driving channels through the digital bus. Each driving channel contains a digital-to-analog converter and a voltage reference source inside. The driving chip adjusts its output voltage reference through the internal digital-to-analog converter according to the received coefficients, so as to realize accurate and independent adjustment of the gate driving voltage of the sub-region. The collaborative adjustment model continuously runs to monitor the temperature feedback and gate voltage state of all sub-regions after the preliminary compensation is performed. When the model detects that the adjustment instructions of two adjacent sub-regions with high thermal coupling strength are in conflict, an iterative optimization process is started. For example, the gradient descent method is used to fine-tune the gate voltage adjustment amplitudes of the two sub-regions to find a balance point that optimizes the global target function. The process runs in real time in the processor, and its output is a small incremental adjustment value of the original partition compensation coefficient. The incremental values are superimposed on the original compensation coefficients in real time, and the setting values of the driving chip are dynamically updated through the bus. Through this dynamic balance, the thermal oscillation and new non-uniform hot spots generated between the sub-regions are avoided, and the uniformity of the temperature field of the whole chip and the stability of the system are ensured.

[0055] In a possible implementation, the adjustment range of the gate voltage of the adjacent sub-regions is dynamically balanced by the cooperative adjustment model to complete the partition compensation management, and step S570 further includes step S571 of obtaining a global average temperature rise rate of the gate voltage adjustment process, and a concern compensation weight is established when any local temperature rise rate is higher than the global average temperature rise rate. Specifically, the average value of the temperature change rate of all pixel points of the entire DMOS chip within a predicted time under the current partition gate voltage adjustment strategy, i.e., the global average temperature rise rate, is continuously calculated. Meanwhile, the local temperature rise rate of the region corresponding to each independent driving sub-region is calculated in parallel. The local temperature rise rate of each sub-region is compared with the global average temperature rise rate in real time, and once it is identified that the local temperature rise rate of a certain sub-region is continuously and significantly higher than the global average value, it is determined that the region is a potential hotspot risk region. For such a sub-region, a value greater than 1, i.e., a concern compensation weight, is dynamically assigned to the sub-region, and the specific value of the weight is positively correlated with the amplitude by which the local temperature rise rate exceeds the global average value, for example, the concern compensation weight is increased by 0.1 for each increase of 10% in the exceeding amplitude. This process is implemented by a comparator and a programmable gain amplifier circuit or by a comparison assignment statement in the processor.

[0056] Step S572, hotspot concern compensation is performed according to the concern compensation weight to complete the partition compensation management. Specifically, the basic partition compensation coefficient calculated for each sub-region in step S560 is multiplied by the concern compensation weight specially assigned to the hotspot sub-region in this step. The operation result is used as the final, enhanced gate voltage adjustment instruction of the hotspot sub-region. The enhanced instruction is issued to the corresponding gate drive channel through a digital bus for execution. Through this targeted hotspot concern compensation mechanism, the limited regulation and control resources are ensured to be preferentially and emphatically used in the region most in need of cooling, so that heat balance is more efficiently achieved on a global level.

[0057] In a possible implementation, the partition compensation management is performed, and the method further includes step S600 of establishing a contraction constraint according to the response strategy. Specifically, after the partition compensation management is implemented and the system thermal state tends to be stable, the current response strategy execution effect is comprehensively analyzed, including whether the temperature of each sub-region has converged to the target range, whether the temperature rise rate is effectively inhibited, and whether the gate voltage adjustment range enters a steady state. Based on the analysis, a contraction constraint decision rule is generated, and the logic of the rule is that when the system thermal state is evaluated as stable or low risk, the investment of monitoring resources is appropriately reduced. In a specific implementation, different thermal stability levels are preset in the system, and each level corresponds to a maximum allowed sampling period. For example, when the temperature rise rate of all sub-regions is lower than a certain low threshold and lasts for a period of time, it is determined that the high stability condition is met, and the contraction constraint rule corresponding to the condition is triggered, which allows the sampling period to be relaxed from 10 microseconds in a high-risk state to 50 microseconds.

[0058] After the acquisition period is adjusted by using the shrinkage constraint, the periodic temperature acquisition is continued in step S700. Specifically, according to the shrinkage constraint rule established in step S600, an instruction is dynamically sent to the controller of the temperature sensor array or the timer responsible for data acquisition to adjust the frequency of the sampling clock or the period of the timing interrupt. Specifically, by programming to rewrite the period register value of the timer module, the acquisition period of the temperature signal is adjusted from the previous shorter interval to the longer interval allowed by the shrinkage constraint. After successfully adjusting the acquisition period, the periodic temperature signal acquisition is continued at this new, lower frequency. This reduces the data throughput and the computational load of the subsequent signal processing module while ensuring that the device thermal state can be continuously monitored and the protection capability is maintained, thereby optimizing system resource consumption. The entire control flow forms an adaptive closed loop and continuously circulates.

[0059] The embodiment of the present application adopts periodic acquisition of temperature signals at multiple spatial positions of the DMOS device to construct a temperature sequence, projects the temperature sequence in a short time window with a thermal response basis function to obtain a basis coefficient set, characterizes the space-time thermal evolution characteristics, calculates a fast protection index based thereon, and reduces the gate drive voltage to suppress temperature rise through an analog channel when the index exceeds a threshold. Then, the basis coefficient set is input into a digital prediction channel to predict future temperature evolution, an optimal gate voltage curve is constructed, the optimal gate voltage curve is corrected after the analog channel pre-processing strategy is obtained, and an independent driving sub-region response strategy is issued to execute partition compensation management. The technical problems of inaccurate regulation and difficulty in maintaining system performance while suppressing temperature rise in existing DMOS device thermal management are solved, and the technical effects of accurately regulating the thermal field and maintaining system performance to the maximum extent while suppressing instantaneous temperature rise are achieved.

[0060] In the foregoing, the DMOS gate voltage dynamic compensation method based on temperature feedback according to the embodiments of the present application is described in detail. Next, the DMOS gate voltage dynamic compensation system based on temperature feedback according to the embodiments of the present application will be described with reference to the accompanying drawings. Figure 1 The DMOS gate voltage dynamic compensation system based on temperature feedback according to the embodiments of the present application is used to solve the technical problems of inaccurate regulation and difficulty in maintaining system performance while suppressing temperature rise in existing DMOS device thermal management, and achieve the technical effects of accurately regulating the thermal field and maintaining system performance to the maximum extent while suppressing instantaneous temperature rise. The DMOS gate voltage dynamic compensation system based on temperature feedback includes a temperature signal acquisition module 10, a basis coefficient set acquisition module 20, a fast protection index calculation module 30, an optimal gate voltage curve construction module 40, and a partition compensation management module 50. Figure 2

[0061] The DMOS gate voltage dynamic compensation system based on temperature feedback according to the embodiments of the present application is used to solve the technical problems of inaccurate regulation and difficulty in maintaining system performance while suppressing temperature rise in existing DMOS device thermal management, and achieve the technical effects of accurately regulating the thermal field and maintaining system performance to the maximum extent while suppressing instantaneous temperature rise. The DMOS gate voltage dynamic compensation system based on temperature feedback includes a temperature signal acquisition module 10, a basis coefficient set acquisition module 20, a fast protection index calculation module 30, an optimal gate voltage curve construction module 40, and a partition compensation management module 50.

[0062] ​The temperature signal collection module 10 is configured to periodically collect temperature signals at multiple spatial positions of the DMOS device to construct a temperature sequence; the base coefficient set acquisition module 20 is configured to project the temperature sequence in a short time window on a group of thermal response base functions to acquire a base coefficient set, and the base coefficient set represents the time-space thermal evolution characteristics of the DMOS device; the fast protection index calculation module 30 is configured to calculate a fast protection index based on the base coefficient set, and if the fast protection index exceeds a preset threshold, a proportional reduction of the gate drive voltage is performed based on the simulation channel to suppress the instantaneous temperature rise; the optimal gate voltage curve construction module 40 is configured to input the base coefficient set into a digital prediction channel, predict the spatial temperature evolution in the short future by using a historical base coefficient sequence and a base function dictionary library, and construct an optimal gate voltage curve with temperature constraints according to the prediction result and a preset time window; and the partition compensation management module 50 is configured to execute optimal gate voltage curve correction according to the preprocessing strategy after obtaining the preprocessing strategy of the simulation channel, issue a response strategy of an independent driving sub-area according to the correction result, and perform partition compensation management.

[0063] The partition compensation management module 50 is further configured to: a preprocessing strategy sending unit configured to send the preprocessing strategy as additional data to the digital prediction channel; a spatial temperature influence analysis unit configured to activate an analog temperature fitting layer in the digital prediction channel, perform spatial temperature influence analysis under the preprocessing strategy by using the analog temperature fitting layer, and establish an influence fitting result; a spatial temperature evolution compensation unit configured to read hysteresis verification data under the preprocessing strategy, perform trend correction of the influence fitting result according to the hysteresis verification data, perform spatial temperature evolution compensation in the short future by using the trend correction result, and update the prediction result; and an optimal gate voltage curve correction unit configured to complete optimal gate voltage curve correction by using the updated prediction result.

[0064] The detailed description of the specific configuration of the optimal grid voltage curve construction module 40 is as follows: as described above, the base coefficient set is input into the digital prediction channel to predict the short-time future spatial temperature evolution using the historical base coefficient sequence and the base function dictionary library. The optimal grid voltage curve construction module 40 can further include: a historical base coefficient sequence expansion unit for the digital prediction channel including a thermal feature coding unit, a time series prediction unit and a reconstruction mapping unit, the historical base coefficient sequence is expanded into a time series feature vector in the time dimension using the thermal feature coding unit; a dominant base coefficient prediction unit for the base function dictionary library being a multi-dimensional response subspace constructed based on the DMOS structure topology and material thermal constants, the time series prediction unit is used to perform dominant base coefficient prediction based on the time series feature vector and the base function dictionary library under the feedback of the grid voltage dynamic component, wherein the grid voltage dynamic component feedback is used to realize thermal-electric dual-domain coupled prediction; a short-time temperature distribution matrix generation unit for sending the dominant base coefficient prediction result to the reconstruction mapping unit to generate a short-time temperature distribution matrix to complete the spatial temperature evolution.

[0065] The detailed description of the specific configuration of the base coefficient set acquisition module 20 is as follows: as described above, the temperature sequence is projected on a group of thermal response base functions in a short-time window to obtain a base coefficient set. The base coefficient set acquisition module 20 can further include: a normalization processing unit for performing normalization processing on the temperature sequence measured by each temperature measurement node of the DMOS device after time division; a thermal response base function calling unit for calling a preset thermal response base function, the thermal response base function being composed of a plurality of groups of orthogonal functions with different time constants and spatial diffusion coefficients; a projection coefficient calculation unit for calculating the projection coefficient of the normalized temperature sequence on the thermal response base function using a sliding weighted least squares projection algorithm, and establishing a base coefficient set, wherein the weighting factor is adaptively adjusted according to the local thermal gradient and the signal-to-noise ratio of the temperature measurement node.

[0066] The detailed description of the specific configuration of the fast protection index calculation module 30 is as follows: as described above, the fast protection index is calculated based on the base coefficient set. The fast protection index calculation module 30 can further include: a time differentiation operation unit for performing time differentiation operation on the base coefficient set in adjacent time windows to obtain a base change rate matrix; a transient thermal stress coefficient calculation unit for extracting the maximum change rate of the main base component and the high-order base energy proportion in the base change rate matrix, and calculating the transient thermal stress coefficient according to the extraction result combined with the local thermal gradient distribution; a fast protection index construction unit for constructing the fast protection index based on the transient thermal stress coefficient.

[0067] Wherein, the fast protection index calculation module 30 can further include: a gate voltage modulation layer activation unit for activating the gate voltage modulation layer of the analog channel, the gate voltage modulation layer including a proportional feedback unit, a hysteresis correction unit, and a transient amplitude limiting unit; a gate drive voltage amplitude management unit for performing gate drive voltage amplitude management using the proportional feedback unit to calculate a proportional amplitude reduction coefficient according to the fast protection index calculation, and using the proportional amplitude reduction coefficient; a smooth recovery constraint unit for performing smooth recovery constraint of the gate drive voltage amplitude management process using the hysteresis correction unit; and a gate voltage change amplitude constraint unit for performing gate voltage change amplitude constraint within a single cycle using the transient amplitude limiting unit, to complete proportional amplitude reduction management.

[0068] Wherein, the system further includes: a shrinkage constraint establishment module for establishing shrinkage constraints for periodic collection according to the response strategy; and a collection period adjustment module for adjusting the collection period using the shrinkage constraints, and then continuing to perform periodic temperature collection.

[0069] Wherein, the gate voltage adjustment amplitude balancing unit can further include: an attention compensation weight establishment subunit for obtaining a global average temperature rise rate during the gate voltage adjustment process, and establishing an attention compensation weight when any local temperature rise rate is higher than the global average temperature rise rate; and a hot spot attention compensation subunit for performing hot spot attention compensation according to the attention compensation weight, to complete the partition compensation management.

[0070] Wherein, the system further includes: a shrinkage constraint establishment module for establishing shrinkage constraints for periodic collection according to the response strategy; and a collection period adjustment module for adjusting the collection period using the shrinkage constraints, and then continuing to perform periodic temperature collection.

[0071] The DMOS gate voltage dynamic compensation system based on temperature feedback provided by the embodiments of the present application can perform the DMOS gate voltage dynamic compensation method based on temperature feedback provided by any of the embodiments of the present application, and has the corresponding functional modules and beneficial effects of the execution method.

[0072] Although the present application makes various references to certain modules in the system according to the embodiments of the present application, however, any number of different modules can be used and run on the user terminal and / or server, the various units and modules are only divided according to the functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific name of each functional unit is only for easy mutual differentiation, and is not used to limit the protection scope of the present application.

[0073] The above is only the preferred embodiment of the present application, not any form of limitation on the present application, although the present application has been disclosed as above with the preferred embodiment, however, not to limit the present application, any person skilled in the art, without departing from the scope of the technical scheme of the present application, can make some changes or modifications for equivalent embodiments with the above disclosed technical content, but as long as it does not deviate from the technical scheme content of the present application, any modification, equivalent change and modification made on the above embodiments according to the technical essence of the present application, still belongs to the scope of the technical scheme of the present application.

Claims

1. A dynamic compensation method for DMOS gate voltage based on temperature feedback, characterized in that, The method includes: Temperature signals are periodically acquired at multiple spatial locations of the DMOS device to construct a temperature sequence; The temperature sequence is projected onto a set of thermal response basis functions within a short time window to obtain a set of basis coefficients, which characterize the spatiotemporal thermal evolution features of the DMOS device. A fast protection index is calculated based on the base coefficient set. If the fast protection index exceeds a preset threshold, the gate drive voltage is reduced proportionally based on the analog channel to suppress instantaneous temperature rise. The basis coefficient set is input into the digital prediction channel, and the spatial temperature evolution in the short term is predicted using the historical basis coefficient sequence and basis function dictionary. The optimal gate voltage curve with temperature constraints is constructed based on the prediction results and the preset time window. After obtaining the preprocessing strategy of the analog channel, the optimal gate voltage curve correction is performed according to the preprocessing strategy. Based on the correction result, the response strategy of the independent driving sub-region is issued and partition compensation management is performed. Based on the calibration results, a response strategy for the independent driver sub-region is issued, and partition compensation management is performed, including: Based on the calibration results, the gate drive network of the DMOS device is divided into N independent drive sub-regions, each of which corresponds to a local temperature observation node and an associated thermal coupling region. Within each independent driving sub-region, the partition compensation coefficient is calculated based on the base coefficient component and the predicted temperature rise rate, and a collaborative adjustment model is established based on the thermal coupling strength of the independent driving sub-region. Compensation management is performed using the partition compensation coefficient, and the grid voltage adjustment amplitude of adjacent sub-regions is dynamically balanced through the collaborative adjustment model to complete the partition compensation management. By dynamically balancing the gate voltage adjustment amplitude of adjacent sub-regions through collaborative adjustment models, zonal compensation management is achieved, including: Obtain the global average temperature rise rate during the gate voltage regulation process. If any local temperature rise rate is higher than the global average temperature rise rate, establish a focus compensation weight. Hotspot attention compensation is applied based on the aforementioned attention compensation weights to complete the zoning compensation management.

2. The dynamic compensation method for DMOS gate voltage based on temperature feedback as described in claim 1, characterized in that, Performing optimal gate voltage curve correction according to the preprocessing strategy includes: The preprocessing strategy is sent as additional data to the digital prediction channel; Activate the simulated temperature fitting layer in the digital prediction channel, and use the simulated temperature fitting layer to perform spatial temperature influence analysis under the preprocessing strategy to establish the influence fitting results. Read the hysteresis verification data under the preprocessing strategy, perform trend correction on the hysteresis verification data to affect the fitting results, and use the trend correction results to compensate for the short-term future spatial temperature evolution and update the prediction results. The optimal gate voltage curve is corrected using the updated prediction results.

3. The dynamic compensation method for DMOS gate voltage based on temperature feedback as described in claim 1, characterized in that, The basis coefficient set is input into a digital prediction channel, and short-term future spatial temperature evolution is predicted using historical basis coefficient sequences and a basis function dictionary, including: The digital prediction channel includes a hot feature encoding unit, a temporal prediction unit, and a reconstruction mapping unit; The historical basis coefficient sequence is expanded into a time-series feature vector using the aforementioned hot feature encoding unit. The basis function dictionary is a multidimensional response subspace constructed based on the DMOS structure topology and material thermal constants. The timing prediction unit uses the timing feature vector and the basis function dictionary to perform dominant basis coefficient prediction based on gate voltage dynamic component feedback. The gate voltage dynamic component feedback is used to realize thermal-electric dual-domain coupling prediction. The prediction results of the dominant basement coefficient are sent to the reconstruction mapping unit to generate a short-time temperature distribution matrix to complete the space temperature evolution.

4. The dynamic compensation method for DMOS gate voltage based on temperature feedback as described in claim 1, characterized in that, The temperature sequence is projected onto a set of thermal response basis functions within a short-time window to obtain a set of basis coefficients, including: In each sampling period, the temperature sequence measured by each temperature measurement node of the DMOS device is divided by time and then normalized. The preset thermal response basis function is invoked, which is composed of multiple sets of orthogonal functions with different time constants and spatial diffusion coefficients; The projection coefficients of the normalized temperature sequence onto the thermal response basis function are calculated using the sliding weighted least squares projection algorithm, and a basis coefficient set is established. The weighting factor is adaptively adjusted according to the local thermal gradient and signal-to-noise ratio of the temperature measurement node.

5. The dynamic compensation method for DMOS gate voltage based on temperature feedback as described in claim 1, characterized in that, The fast protection index is calculated based on the aforementioned base coefficient set, including: Perform time differentiation on the set of basis coefficients within adjacent time windows to obtain the basis rate of change matrix; The maximum rate of change of the main substrate component and the energy proportion of the higher-order substrate are extracted from the substrate change rate matrix. The transient thermal stress coefficient is calculated based on the extraction results and the local thermal gradient distribution. A rapid protection index is constructed based on the transient thermal stress coefficient.

6. The dynamic compensation method for DMOS gate voltage based on temperature feedback as described in claim 5, characterized in that, The proportional reduction of the gate drive voltage based on the analog channel execution includes: The gate voltage modulation layer of the analog channel is activated, and the gate voltage modulation layer includes a proportional feedback unit, a hysteresis correction unit, and a transient limiting unit; The proportional feedback unit calculates the reduction ratio coefficient based on the fast protection index, and uses the reduction ratio coefficient to perform gate drive voltage reduction management. Smooth recovery constraint of gate drive voltage drop management process using hysteresis correction unit; The transient limiting unit is used to constrain the gate voltage variation amplitude within a single cycle in order to complete the proportional derating management.

7. The dynamic compensation method for DMOS gate voltage based on temperature feedback as described in claim 1, characterized in that, Implementing zone compensation management also includes: Establish a contraction constraint for periodic acquisition based on the aforementioned response strategy; After adjusting the acquisition period using the aforementioned contraction constraint, the periodic temperature acquisition continues.

8. A DMOS gate voltage dynamic compensation system based on temperature feedback, characterized in that, The system is used to implement the temperature feedback-based dynamic compensation method for DMOS gate voltage as described in any one of claims 1-7, and the system comprises: The temperature signal acquisition module is used to periodically acquire temperature signals at multiple spatial locations of the DMOS device to construct a temperature sequence. The basis coefficient set acquisition module is used to project the temperature sequence onto a set of thermal response basis functions within a short time window to obtain the basis coefficient set, which characterizes the spatiotemporal thermal evolution characteristics of the DMOS device. The fast protection index calculation module is used to calculate the fast protection index based on the base coefficient set. If the fast protection index exceeds a preset threshold, the proportional reduction of the gate drive voltage is performed based on the analog channel to suppress the instantaneous temperature rise. The optimal gate voltage curve construction module is used to input the basis coefficient set into the digital prediction channel, use the historical basis coefficient sequence and basis function dictionary to predict the short-term future spatial temperature evolution, and construct the optimal gate voltage curve with temperature constraints based on the prediction results and preset time window. The partition compensation management module is used to perform optimal gate voltage curve correction according to the preprocessing strategy of the analog channel after obtaining the preprocessing strategy, and to issue the response strategy of the independent driving sub-region according to the correction result, and to perform partition compensation management.

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