Box dam for blocking solder of silicon circuit board

Abstract

According to the box dam for blocking the solder of the silicon circuit board, the overflow range of the solder is restrained, and the collapse thickness of a welding surface is accurately controlled; the method comprises the following steps: taking a silicon wafer; cleaning the silicon wafer; dehydrating and baking; photoresist is spin-coated; exposing and developing; evaporating titanium platinum and a metallization layer; stripping to form a metal circuit; annealing is conducted; photoresist is spin-coated; exposing and developing; vapor deposition of titanium nitride; performing stripping; carrying out passivating treatment; performing chemical vapor deposition on silicon dioxide; spin-coating photoresist, exposing and developing; etching the silicon dioxide to expose the metal bonding pad and the specified structure; performing cleaning; annealing is conducted; photoresist is spin-coated; exposing and developing; evaporating a titanium platinum welding layer; stripping to form a welding layer with a specified pattern; annealing is conducted; carrying out chemical vapor deposition on silicon dioxide; spin-coating photoresist, exposing and developing; etching the silicon dioxide to form a box dam with a specified structure; performing cleaning; annealing is conducted; photoresist is spin-coated; exposing and developing; magnetron sputtering of gold-tin solder is carried out; stripping to form a solder layer with a specified pattern; performing cleaning; and cleavage.

Description

Technical Field

[0001] This invention relates to optoelectronic communication technology and its equipment, specifically, to a dam for blocking solder on a silicon circuit board. Background Technology

[0002] In optoelectronic communication devices, metal housings / tubes are the mainstream hermetic packaging solution. Metal housings are generally made of Kovar alloy, with partial or complete nickel-gold plating. Kovar alloy is an iron-based alloy with a composition of nickel (28.5–29.5%), cobalt (16.8–17.8%), and the balance being iron and trace elements (C≤0.03%, Mn≤0.50%, Si≤0.30%, etc.). Within the temperature range of 20–450℃, its CTE is (4.6–5.6)×10⁻⁶. -6 / ℃, highly compatible with hard glass (such as borosilicate glass) and ceramics (such as 95% Al2O3), making it suitable for fixing optical windows and semiconductor laser heat sinks, but its thermal conductivity is at a medium level (17–21.4 W / (m·K)), and high-power scenarios require heat dissipation components such as oxygen-free copper; Kovar alloy has a resistivity of 0.46–0.48 μΩ·m, and its higher resistivity is beneficial for suppressing eddy current losses in high-frequency devices, but it requires an additional circuit carrier (such as a ceramic circuit board) as the signal loop and hermetic passage of the optoelectronic chip, while ceramics, as sintering materials, require appropriate volume and thickness to maintain structural strength during production and use; the material is easily corroded in acidic solutions and requires protection with gold or other plating.

[0003] The Kovar alloy process results in large package size, poor heat dissipation, complex assembly process, high manufacturing cost, high manufacturing threshold, and large scale, making it unsuitable for integrated and smaller-scale component-level packaging with lower thermal density. Furthermore, the hermeticity achieved through parallel sealing / laser welding or resistance welding with metal covers and caps exacerbates the large package size and high cost.

[0004] Therefore, it is necessary to provide a dam for blocking solder on silicon circuit boards to solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to provide a solder barrier for silicon circuit boards. By creating an inorganic barrier attached to the surface of the silicon circuit board, the overflow range of solder and the thickness of the solder surface collapse can be precisely controlled, achieving micron-level sealing. This invention is suitable for optoelectronic communication devices, high-frequency radio frequency devices, sensors, and aerospace electronic equipment with high reliability requirements.

[0006] The technical solution is as follows: A solder barrier dam for a silicon circuit board involves creating an inorganic barrier attached to the surface of the silicon circuit board to constrain the solder overflow range and precisely control the thickness of the solder surface collapse. The implementation steps include: Step 1: Obtain the silicon wafer; Step 2: Silicon wafer cleaning to remove organic contaminants; Step 3: Dehydrate and bake to remove surface moisture; Step 4: Spin-coating photoresist; Step 5, Exposure and Development; Step 6: Vaporize titanium-platinum to form a metallization layer. Step 7: Peel off to form metal circuitry; Step 8, annealing; Step 9: Spin-coating photoresist; Step 10, Exposure and Development; Step 11, vapor deposition of titanium nitride; Step 12, peeling; Step 13, passivation treatment; Step 14: Chemical vapor deposition of silicon dioxide; Step 15: Spin-coating photoresist, exposure and development; Step 16: Etch silicon dioxide to expose metal pads and the specified structure; Step 17, cleaning; Part 18, Annealing; Part 19, Spin-coating photoresist; Step 20, Exposure and Development; Step 21: Evaporate titanium-platinum welding layer; Step 22: Peel off the weld layer to form the specified pattern; Step 23, Annealing; Step 24: Chemical vapor deposition of silicon dioxide; Step 25: Spin-coating photoresist, exposure and development; Step 26: Etch silicon dioxide to form a dam with the specified structure; Step 27, cleaning; Step 28, Annealing; Part 29, Spin-coating photoresist; Step 30, Exposure and Development; Step 31: Magnetron sputtering of gold-tin solder; Step 32, peel off the solder layer to form the specified pattern; Step 33, cleaning; Step 34, solution.

[0007] Furthermore, the dam is a silica solder dam with micron-level precision, which restricts the extent of solder overflow and the degree of collapse after melting.

[0008] Furthermore, the passageway through the warehouse adopts a parallel stepped structure to reduce stress concentration and gas leakage paths.

[0009] Furthermore, the passivation layer material on the circuit surface is consistent with that of the dam, and its coefficient of thermal expansion matches that of silicon, allowing it to withstand a certain number of reheating cycles and slight hot melting of the solder.

[0010] Furthermore, the size of the sealing ring of complex optoelectronic communication devices is reduced from the millimeter level to the micrometer level, and the structure tends to be miniaturized and flattened, thereby freeing up more installation space and leaving room for the integration of more channel components, optical path integration and heat dissipation structure arrangement.

[0011] Compared with existing technologies, this invention achieves precise control of solder overflow range and solder surface collapse thickness by creating an inorganic dam attached to the surface of the silicon circuit board, thereby realizing micron-level sealing. It is suitable for optoelectronic communication devices, high-frequency radio frequency devices, sensors and aerospace electronic equipment with high reliability requirements. Attached Figure Description

[0012] Figure 1 This is one of the flowcharts of the present invention.

[0013] Figure 2 This is the second flowchart of the present invention.

[0014] Figure 3 This is a schematic diagram of steps 4 and 5 of the present invention: spin coating of photoresist, exposure, and development.

[0015] Figure 4 This is the sixth step of the present invention, a schematic diagram of titanium-platinum vapor deposition.

[0016] Figure 5 This is a schematic diagram of steps 7 and 8 of the present invention: peeling and annealing.

[0017] Figure 6 This is a schematic diagram of steps 9 and 10 of the present invention: spin coating of photoresist, exposure, and development.

[0018] Figure 7 This is the 11th step of the present invention, a schematic diagram of vapor deposition of titanium nitride.

[0019] Figure 8 This is a schematic diagram of steps 12 and 13 of the present invention: peeling and passivation treatment.

[0020] Figure 9 This is the 14th step of the present invention, a schematic diagram of silicon dioxide deposition.

[0021] Figure 10 This is the 15th step of the present invention, a schematic diagram of spin coating of photoresist, exposure and development.

[0022] Figure 11 This is the 16th step of the present invention, a schematic diagram of etching silicon dioxide.

[0023] Figure 12 This is step 17 of the present invention, a cleaning diagram.

[0024] Figure 13 This is step 18 of the present invention, a schematic diagram of spin coating of photoresist, exposure and development.

[0025] Figure 14 This is step 19 of the present invention, a schematic diagram of vapor deposition of titanium nitride.

[0026] Figure 15 These are schematic diagrams of steps 20 and 21 of the present invention, namely, peeling and annealing.

[0027] Figure 16 This is step 22 of the present invention, a schematic diagram of silicon dioxide deposition.

[0028] Figure 17 This is step 23 of the present invention, a schematic diagram of spin coating of photoresist, exposure and development.

[0029] Figure 18 This is step 24 of the present invention, a schematic diagram of spin coating of photoresist, exposure and development.

[0030] Figure 19 This is step 25 of the present invention, a schematic diagram of etching silicon dioxide.

[0031] Figure 20 This is a schematic diagram of step 26 of the present invention: cleaning and annealing.

[0032] Figure 21 This is step 27 of the present invention, a schematic diagram of spin coating of photoresist, exposure and development.

[0033] Figure 22 This is step 28 of the present invention, a schematic diagram of sputtering gold and tin.

[0034] Figure 23 This is step 29 of the present invention, a schematic diagram of the peeling process. Detailed Implementation Example:

[0035] Please see Figure 1-23 This embodiment demonstrates a solder barrier dam for a silicon circuit board, which involves creating an inorganic barrier attached to the surface of the silicon circuit board to constrain the solder overflow range and precisely control the thickness of the solder surface collapse; the implementation steps include: Step 1: Obtain the silicon wafer; Step 2: Silicon wafer cleaning to remove organic contaminants; Step 3: Dehydrate and bake to remove surface moisture; Step 4: Spin-coating photoresist; Step 5, Exposure and Development; Step 6: Vaporize titanium-platinum to form a metallization layer. Step 7: Peel off to form metal circuitry; Step 8, annealing; Step 9: Spin-coating photoresist; Step 10, Exposure and Development; Step 11, vapor deposition of titanium nitride; Step 12, peeling; Step 13, passivation treatment; Step 14: Chemical vapor deposition of silicon dioxide; Step 15: Spin-coating photoresist, exposure and development; Step 16: Etch silicon dioxide to expose metal pads and the specified structure; Step 17, cleaning; Part 18, Annealing; Part 19, Spin-coating photoresist; Step 20, Exposure and Development; Step 21: Evaporate titanium-platinum welding layer; Step 22: Peel off the weld layer to form the specified pattern; Step 23, Annealing; Step 24: Chemical vapor deposition of silicon dioxide; Step 25: Spin-coating photoresist, exposure and development; Step 26: Etch silicon dioxide to form a dam with the specified structure; Step 27, cleaning; Step 28, Annealing; Part 29, Spin-coating photoresist; Step 30, Exposure and Development; Step 31: Magnetron sputtering of gold-tin solder; Step 32, peel off the solder layer to form the specified pattern; Step 33, cleaning; Step 34, solution.

[0036] in: The dam is a silica solder dam with micron-level precision, which restricts the extent of solder overflow and the degree of collapse after melting.

[0037] The passageway through the warehouse adopts a parallel stepped structure to reduce stress concentration and gas leakage paths.

[0038] The passivation layer on the circuit surface is made of the same material as the dam, and its coefficient of thermal expansion matches that of silicon, allowing it to withstand a certain number of reheating cycles and slight hot melting of the solder.

[0039] By reducing the size of the sealing ring of complex optoelectronic communication devices from the millimeter level to the micrometer level, the structure tends to be miniaturized and flattened, thereby freeing up more installation space and leaving room for the integration of components with more channels, optical path integration, and heat dissipation structure arrangement.

[0040] Compared with existing technologies, this invention achieves precise control of solder overflow range and solder surface collapse thickness by creating an inorganic dam attached to the surface of the silicon circuit board, thereby realizing micron-level sealing. It is suitable for optoelectronic communication devices, high-frequency radio frequency devices, sensors and aerospace electronic equipment with high reliability requirements.

[0041] For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of this invention, and these all fall within the protection scope of this invention.

Claims

1. A dam for solder resist of a silicon circuit board, characterized by: To make inorganic dam attached to the surface of the silicon circuit board, to realize the solder overflow range constraint and the welding surface collapse thickness accurate control; implementation steps include: Step 1, take the silicon wafer; Step 2, silicon wafer cleaning, remove organic contaminants; Step 3, dehydration baking, eliminate surface moisture; Step 4, spin coating photoresist; Step 5, exposure and development; Step 6, titanium platinum gold evaporation, metal layer; Step 7, stripping, forming metal lines; Step 8, annealing; Step 9, spin coating photoresist; Step 10, exposure and development; Step 11, vapor deposition of titanium nitride; Step 12, stripping; Step 13, passivation treatment; Step 14, chemical vapor deposition of silicon dioxide; Step 15, spin coating photoresist, exposure and development; Step 16, etching of silicon dioxide, exposing metal pads and designated structure; Step 17, cleaning; Step 18, annealing; Step 19, spin coating photoresist; Step 20, exposure and development; Step 21, titanium platinum gold evaporation, welding layer; Step 22, stripping, forming designated pattern of welding layer; Step 23, annealing; Step 24, chemical vapor deposition of silicon dioxide; Step 25, spin coating photoresist, exposure and development; Step 26, etching of silicon dioxide, forming designated structure of dam; Step 27, cleaning; Step 28, annealing; Step 29, spin coating photoresist; Step 30, exposure and development; Step 31, magnetron sputtering of gold tin solder; Step 32, stripping, forming designated pattern of solder layer; Step 33, cleaning; Step 34, cleavage.

2. The solder resist dam for a silicon circuit board according to claim 1, characterized by: The dam is a micron level precision silicon dioxide solder dam, which can constrain the solder overflow range and collapse degree after melting.

3. The solder resist dam for a silicon circuit board according to claim 1, wherein: The parallel ladder structure of the channel reduces stress concentration and gas leakage path.

4. The solder barrier dam for a silicon circuit board of claim 1 wherein: The passivation layer material of the circuit surface is consistent with the dam, and the thermal expansion coefficient is matched with silicon, which can withstand a certain number of reheat and slight solder heat melting.

5. A solder barrier for a silicon circuit board according to claim 1, characterized in that: The size of the sealing ring of complex optoelectronic communication devices is reduced from millimeter level to micron level, and the structure tends to miniaturization and flattening, thereby releasing more installation space for more channel number of element integration, optical path integration and heat dissipation structure arrangement.

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