Frequency calibration circuit of oscillator and chip

Abstract

The invention provides a frequency calibration circuit of an oscillator and a chip, the oscillator comprises a first adjustable capacitor, the frequency calibration circuit is used for determining a target control signal for the first adjustable capacitor, and the target control signal is a control signal enabling the output frequency of the oscillator to reach a target value; the frequency calibration circuit comprises a control circuit and a second adjustable capacitor; the second adjustable capacitor and the first adjustable capacitor have the same capacitance value when controlled by the same control signal; the control circuit is used for outputting a first control signal to the second adjustable capacitor as a to-be-verified control signal; the second adjustable capacitor outputs a first voltage based on a charging current generated by a preset reference voltage under the action of the to-be-verified control signal; the control circuit is further used for determining the target control signal according to the first voltage and outputting the target control signal to the first adjustable capacitor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of electronic circuit, and more particularly, to an oscillator-based frequency calibration circuit and a chip. BACKGROUND

[0002] SPI communication protocol is a mainstream communication protocol, which is widely used in chip design due to its characteristics of fast transmission speed and less resource occupation. When using SPI protocol communication, the host and the selected chip interact when the chip select (CS) signal is low, and the transmission of clock signal and data is performed. When the chip select signal CS is pulled high, the host and the chip are completely disconnected. At this time, if the chip is to work normally, an oscillator needs to be integrated in the chip to provide a clock signal.

[0003] Due to the uncertainty of semiconductor manufacturing process, the components on different chips, such as resistors, capacitors, MOS tubes, etc., inevitably have a production error of more than 20% during manufacturing, which may cause the frequency of the clock signal output by the oscillator to be greatly different from the target value. SUMMARY

[0004] An object of embodiments of the present disclosure is to provide an oscillator frequency calibration circuit and a chip.

[0005] According to a first aspect of embodiments of the present disclosure, an oscillator frequency calibration circuit is provided, the oscillator comprising a first adjustable capacitor, the frequency calibration circuit being configured to determine a target control signal for the first adjustable capacitor, the target control signal being a control signal that makes the output frequency of the oscillator reach a target value.

[0006] The frequency calibration circuit comprises a control circuit and a second adjustable capacitor; the second adjustable capacitor and the first adjustable capacitor have the same capacitance value when controlled by the same control signal.

[0007] The control circuit is configured to output a first control signal as a to-be-verified control signal to the second adjustable capacitor.

[0008] The second adjustable capacitor outputs a first voltage based on a charging current generated by a preset reference voltage under the action of the to-be-verified control signal.

[0009] The control circuit is further configured to determine the target control signal according to the first voltage and output the target control signal to the first adjustable capacitor.

[0010] Optionally, the determination of the target control signal according to the first voltage comprises:

[0011] comparing the first voltage with the reference voltage to obtain a first comparison result;

[0012] determining the target control signal according to the first comparison result.

[0013] Optionally, the determining the target control signal according to the first comparison result comprises:

[0014] determining the first control signal as the target control signal in a case where the first comparison result meets a set condition;

[0015] outputting a second control signal as the to-be-verified control signal to the second adjustable capacitor in a case where the first comparison result does not meet the set condition.

[0016] Optionally, the set condition comprises:

[0017] the first comparison result corresponding to the first control signal is that the first voltage is equal to the reference voltage; or,

[0018] the first comparison result corresponding to the first control signal is that the first voltage is greater than the reference voltage, and the first comparison result corresponding to a third control signal is that the first voltage is less than the reference voltage; wherein the third control signal is a to-be-verified control signal output by the control circuit prior to the first control signal, or,

[0019] the first comparison result corresponding to the first control signal is that the first voltage is less than the reference voltage, and the first comparison result corresponding to a third control signal is that the first voltage is greater than the reference voltage.

[0020] Optionally, the outputting a second control signal as the to-be-verified control signal to the second adjustable capacitor in a case where the first comparison result does not meet the set condition comprises:

[0021] determining whether a switching number of switching to-be-verified control signals reaches a predetermined number in a case where the first comparison result does not meet the set condition;

[0022] outputting a second control signal as the to-be-verified control signal to the second adjustable capacitor in a case where the switching number does not reach the predetermined number.

[0023] Optionally, the control circuit is further configured to determine the to-be-verified control signal as the target control signal in a case where the switching number reaches the predetermined number.

[0024] Optionally, the second adjustable capacitor comprises a first terminal, a second terminal, a first capacitor, N second capacitors, and a first switch corresponding to each second capacitor, the first capacitor is connected between the first terminal and the second terminal, each second capacitor is connected in parallel between the first terminal and the second terminal after being connected in series with the corresponding first switch; the control signal to be verified is used to control the on-off state of the N first switches, so that the second adjustable capacitor has a corresponding capacitance value.

[0025] Optionally, the control circuit is configured to select a control signal from a plurality of control signals for making the second adjustable capacitor have different capacitance values as the first control signal, and output the first control signal to the second adjustable capacitor.

[0026] Optionally, the control circuit is configured to reselect a control signal from the plurality of control signals as the second control signal in a case where the first comparison result does not meet the set condition.

[0027] Optionally, the control circuit is configured to select the second control signal from the plurality of control signals according to the first comparison result, a set order of the plurality of control signals, and the first control signal; wherein the set order makes the capacitance value of the second adjustable capacitor monotonically change.

[0028] Optionally, in a case where the first comparison result is that the first voltage is greater than the reference voltage, a control signal adjacent to the first control signal and making the capacitance value of the second adjustable capacitor increase is selected from the plurality of control signals as the second control signal based on the set order.

[0029] Optionally, in a case where the first comparison result is that the first voltage is less than the reference voltage, a control signal adjacent to the first control signal and making the capacitance value of the second adjustable capacitor decrease is selected from the plurality of control signals as the second control signal based on the set order.

[0030] Optionally, the control circuit comprises a comparator configured to compare the first voltage and the reference voltage to obtain the first comparison result.

[0031] Optionally, a capacitance value of an (i+1)th second capacitor is twice a capacitance value of an ith second capacitor, wherein i is a positive integer less than N.

[0032] Optionally, the control circuit comprises an adder, the adder is configured to add one to the first N-bit binary value representing the first control signal as a second N-bit binary value representing the second control signal when the first comparison result is that the first voltage is greater than the reference voltage; or subtract one from the first N-bit binary value representing the first control signal as a second N-bit binary value representing the second control signal when the first comparison result is that the first voltage is less than the reference voltage.

[0033] Optionally, the control circuit further comprises N D flip-flops, the i th D flip-flop is configured to output an i th control signal in the second control signal to a corresponding first switch according to an i th bit of the second N-bit binary value, so as to control the on-off state of the i th first switch.

[0034] Optionally, the first voltage is a voltage output by the second adjustable capacitor after being charged for a predetermined time length based on the charging current under the action of the to-be-verified control signal after the second adjustable capacitor is completely discharged, wherein the predetermined time length is determined according to a target value of the output frequency of the oscillator.

[0035] Optionally, the frequency calibration circuit further comprises a current mirror circuit, the second adjustable capacitor is connected to an output branch of the current mirror circuit, and the current mirror circuit is configured to generate the charging current on the output branch based on the reference voltage to charge the second adjustable capacitor for a predetermined time length when the output branch is turned on.

[0036] Optionally, the oscillator further comprises a first resistor used in cooperation with the first adjustable capacitor, and the frequency calibration circuit further comprises a second resistor, a resistance value of the first resistor is the same as a resistance value of the second resistor.

[0037] Optionally, the second resistor is connected to an input branch of the current mirror circuit, and the current mirror circuit is configured to generate the charging current on the output branch based on a current generated on the input branch based on the reference voltage to charge the second adjustable capacitor.

[0038] Optionally, the frequency calibration circuit comprises a second switch, the second switch is connected in parallel with the second adjustable capacitor.

[0039] The second adjustable capacitor is discharged through the second switch when the second switch is turned on.

[0040] Optionally, the input branch of the current mirror circuit comprises a first PMOS tube and a first NMOS tube, the output branch of the current mirror circuit comprises a second PMOS tube and a second NMOS tube, the gate of the first PMOS tube is connected with the gate of the second PMOS tube, the drain of the first PMOS tube and the drain of the first NMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are both connected with the power supply end of the frequency calibration circuit, and the drain of the second PMOS tube is connected with the drain of the second NMOS tube; the source of the first NMOS tube is connected with the ground end of the frequency calibration circuit, and the source of the second NMOS tube is connected with the ground end.

[0041] Optionally, the frequency calibration circuit further comprises a bandgap reference source, the bandgap reference source is used to output a reference voltage, and the gate of the first NMOS tube is connected with the output end of the bandgap reference source.

[0042] Optionally, the frequency calibration circuit further comprises an operational amplifier, the gate of the first NMOS tube is connected with the output end of the operational amplifier; the non-inverting input end of the operational amplifier is connected with the output end of the bandgap reference source, and the inverting input end of the operational amplifier is connected with the source of the first NMOS tube.

[0043] According to a second aspect of the present disclosure, a chip is provided, comprising an oscillator and the frequency calibration circuit according to the first aspect of the present disclosure.

[0044] Through the frequency calibration circuit of the present embodiment, the control circuit determines the target control signal of the first adjustable capacitor of the oscillator based on the charging current output by the second adjustable capacitor under the action of the control signal to be verified and based on the preset reference voltage, so that the output frequency of the oscillator reaches the target value, and the precision of the oscillator can be improved. In addition, when the frequency calibration circuit of the present embodiment is used in the chip for setting the oscillator, the chip does not need to be calibrated outside the chip using a fuse or the like in the test stage, and the test steps of the oscillator can be reduced, and the production cost of the chip can be reduced.

[0045] Other features of the present application, and their advantages, will become apparent from the following detailed description of exemplary embodiments of the present application with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0047] Figure 1 is a circuit structure schematic diagram of an oscillator provided according to an embodiment of the present disclosure;

[0048] Figure 2is a block diagram of a frequency calibration circuit according to an embodiment of the present disclosure;

[0049] Figure 3 is a circuit structure schematic diagram of a second adjustable capacitor according to an embodiment of the present disclosure;

[0050] Figure 4 is a circuit structure schematic diagram of a frequency calibration circuit according to an embodiment of the present disclosure;

[0051] Figure 5 is a block diagram of a chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. Note that the relative arrangement, numerical expressions, and numerical values of components and steps set forth in these embodiments are illustrative only and do not limit the scope of the present application unless otherwise specifically stated.

[0053] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way limiting to the scope of the application and its applications or uses.

[0054] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art can not be discussed in detail herein. However, where appropriate, such techniques, methods, and apparatus can be considered part of the present application.

[0055] In all of the examples shown and discussed herein, any specific values should be interpreted as merely illustrative and not limiting. Other examples of the exemplary embodiments can have different values.

[0056] It should be noted that like references designate like items throughout the drawings, and that, where appropriate, a discussion of an item in one drawing can not be repeated in subsequent drawings.

[0057] Figure 1 is a circuit structure schematic diagram of an oscillator according to an embodiment of the present disclosure.

[0058] As shown in Figure 1 , the oscillator 100 includes a first RC network 110 for adjusting an output frequency, the first RC network 110 including a first resistance 111 and a first adjustable capacitor 112.

[0059] Further, as shown in Figure 1As shown, the oscillator 100 further includes a first current mirror circuit 120, a comparator 130, a voltage control oscillator (VCO) 140, a charging switch 151, a discharging switch 152, a first output terminal 161 and a second output terminal 162, the first resistor 111 is connected in a first branch of the first current mirror circuit 120, and the first adjustable capacitor 112 is connected in a second branch of the first adjustable capacitor 112.

[0060] The oscillation frequency of the voltage control oscillator 140 is controlled by the voltage VOUT output by the comparator 130, and the greater the voltage VOUT output by the comparator 130, the higher the frequency of the clock signal output by the voltage control oscillator 140.

[0061] The current input to the first resistor 111 and the first adjustable capacitor 112 is a reference current I REF , the voltage V IN- across the first resistor 111 is input to the negative input terminal of the comparator 130, the voltage V IN+ across the first adjustable capacitor 112 is input to the positive input terminal of the comparator 130, and V IN- = I REF *R, where R is the resistance of the first resistor 111.

[0062] The two clock signals OUT1 and OUR2 of the same frequency and opposite phase output by the voltage control oscillator 140 are input to the control terminals of the charging switch 151 and the discharging switch 152, respectively, to control the charging and discharging of the first adjustable capacitor, and the equivalent resistance of the first adjustable capacitor is where C is the capacitance of the first adjustable capacitor 112, and f is the frequency of the clock signal, i.e., the output frequency of the voltage control oscillator 140 and the oscillator 100, so

[0063] When the entire loop is stable, the voltages at the positive and negative input terminals of the comparator 130 are equal, i.e., V IN- = V IN+ , and the output frequency f can be obtained as

[0064] Due to the uncertainty of semiconductor manufacturing processes, the manufacturing of resistors and capacitors in different chips is not accurate, and the resistance of the same resistor and the capacitance of the same capacitor in different chips are not the same, so the capacitance of the first adjustable capacitor can be adjusted by the frequency calibration circuit provided in the embodiment, thereby improving the precision of the oscillator and making the output frequency of the oscillator reach the target value.

[0065] The embodiment provides a frequency calibration circuit based on an oscillator, and the oscillator includes a first adjustable capacitor. In one example, the oscillator can be the oscillator 100 described in the foregoing embodiments.

[0066] In this embodiment, the frequency calibration circuit is used to determine the target control signal for the first adjustable capacitor 112, which is a control signal that makes the output frequency of the oscillator 100 reach the target value.

[0067] Figure 2 This is a schematic diagram of the circuit structure of the frequency calibration circuit provided in an embodiment of the present disclosure.

[0068] like Figure 2 As shown, the frequency calibration circuit 200 includes a second adjustable capacitor 212 and a control circuit 220. The second adjustable capacitor 212 and the first adjustable capacitor 112 are controlled by the same control signal and have the same capacitance value.

[0069] The control circuit 220 is used to output a first control signal to the second adjustable capacitor 212 as a signal to be verified.

[0070] Under the action of the signal to be verified, the second adjustable capacitor 212 outputs a first voltage based on the charging current generated by the preset reference voltage.

[0071] The control circuit 220 is also used to determine the target control signal based on the first voltage and output the target control signal to the first adjustable capacitor 112.

[0072] In one embodiment of this disclosure, the control circuit 220 outputs a target control signal to the first adjustable capacitor 112. This can be either the control circuit 220 directly outputting the target control signal to the first adjustable capacitor 112, or the control circuit 220 controlling other circuits to output the target control signal to the first adjustable capacitor 112.

[0073] In one embodiment of this disclosure, when the control circuit 220 outputs a first control signal to the second adjustable capacitor 212, it may simultaneously output the first control signal to the first adjustable capacitor 112, or it may not output the first control signal to the first adjustable capacitor 112; this is not limited here.

[0074] Although semiconductor technology cannot fabricate perfectly precise devices, the relative deviations of similar devices on the same wafer are very small. Therefore, the capacitance values ​​of the first adjustable capacitor in the oscillator and the second adjustable capacitor in the frequency calibration circuit are equal. Thus, if the capacitance value of the second adjustable capacitor in the frequency calibration circuit is determined, the capacitance value of the first adjustable capacitor in the oscillator is also determined, and consequently, the output frequency of the oscillator can also be determined.

[0075] The frequency calibration circuit of the embodiment can determine the target control signal of the first adjustable capacitor of the oscillator according to the first voltage output by the charging current generated by the second adjustable capacitor under the action of the control signal to be checked and based on the preset reference voltage, so that the output frequency of the oscillator reaches the target value, and the precision of the oscillator can be improved. In addition, the frequency calibration circuit of the embodiment is used for frequency calibration in a chip in which the oscillator is arranged, and the chip does not need to be calibrated outside the chip by using a fuse or the like in a test stage, so that the test steps of the oscillator can be reduced, and the production cost of the chip can be reduced.

[0076] In the embodiment, the first adjustable capacitor 112 and the second adjustable capacitor 212 have the same structure.

[0077] In one example, as shown in Figure 3 The second adjustable capacitor 212 includes a first end 310, a second end 320, a first capacitor 330, N second capacitors 341-34N, and N first switches 351-35N corresponding to the N second capacitors respectively. The first capacitor 330 is connected between the first end 310 and the second end 320. Each second capacitor is connected in parallel between the first end 310 and the second end 320 after being connected in series with the corresponding first switch.

[0078] The first switches 351-35N can be provided by NMOS tubes, or can be provided by IGBTs or other controllable switch devices. The structures of the first switches 351-35N can be the same or different, which is not limited herein.

[0079] The control signal to be checked is used to control the on-off states of the N first switches 351-35N, so that the second adjustable capacitor 212 has a corresponding capacitance value.

[0080] On the basis of the embodiment, the control signal to be checked is an N-bit parallel control signal CTRL1-CTRLN. The i-th control signal CTRLi is used to control the switching state of the i-th first switch 35i, so as to select whether the i-th second capacitor 34i is used in the second adjustable capacitor 212. Therefore, the control circuit 220 can output different control signals to adjust the capacitance value of the second adjustable capacitor 212.

[0081] In the embodiment, the capacitance values of the capacitors in the corresponding positions of the first adjustable capacitor 112 and the second adjustable capacitor 212 are also the same.

[0082] The circuit structure of the second adjustable capacitor of the embodiment can facilitate the control circuit to output the first control signal to accurately control the capacitance value of the second adjustable capacitor, and thus the precision of the oscillator can be improved.

[0083] In one embodiment, the capacitance values of the N second capacitors 341-34N can be equal or unequal, which is not limited herein.

[0084] Further, the capacitance value of the i+1th second capacitor is twice the capacitance value of the ith second capacitor, where i is a positive integer less than N.

[0085] Through the setting of the capacitance values of the second capacitors in this embodiment, the efficiency of the control circuit in determining the target control signal can be improved.

[0086] In this embodiment, the precision of the output frequency of the oscillator can be determined by the number N of the second capacitors, and the precision is 1 / 2 N-1 .

[0087] In another example, the first adjustable capacitor 112 and the second adjustable capacitor 212 can also be other structures, for example, they can also be capacitors that change the capacitance value by changing the relative effective area between the poles or the distance between the poles. In one embodiment of the present disclosure, the first voltage is the voltage output by the second adjustable capacitor 212 after being fully discharged and then being charged for a predetermined time under the action of the control signal to be verified, where the predetermined time is determined according to the target value of the output frequency of the oscillator.

[0088] In one embodiment of the present disclosure, the oscillator further comprises a first resistor 111 used in cooperation with the first adjustable capacitor, and the frequency calibration circuit 200 further comprises a second resistor 211, the resistance value of the second resistor 211 being the same as that of the first resistor 111.

[0089] In one example, as shown in Figure 4 , the frequency calibration circuit 100 can further comprise a current mirror circuit 420, the second resistor 211 being connected to the input branch of the current mirror circuit 420, and the second adjustable capacitor 212 being connected to the output branch of the current mirror circuit 420. The current mirror circuit 420 is used to generate a charging current on the output branch based on a reference voltage to charge the second adjustable capacitor for a predetermined time in the case of the output branch being turned on.

[0090] For example, in the case where the target value of the output frequency is f0, the predetermined time t can be expressed as:

[0091] In one embodiment of the present disclosure, the frequency calibration circuit 200 is connected to an external host, and the current mirror circuit 420 charges the second adjustable capacitor 212 in the case of the host controlling the output branch to be turned on.

[0092] In one embodiment of the present disclosure, the current mirror circuit 420 is used to generate a charging current on the output branch based on the current generated on the input branch by the reference voltage to charge the second adjustable capacitor 212.

[0093] In one example, such as Figure 4 As shown, the frequency calibration circuit 100 may further include a second switch 410, which is connected in parallel with the second adjustable capacitor 212. The host is also connected to the control terminal of the second switch 410. When the host controls the second switch 410 to be turned on, the second adjustable capacitor 212 discharges through the second switch 410.

[0094] The second switch 410 can be provided by an NMOS transistor, an IGBT, or other controllable switching devices, and is not limited here.

[0095] In one embodiment of this disclosure, the host may output a discharge control signal DIS to the second switch 410. The discharge control signal DIS is used to control the switching state of the second switch 410 so that the second adjustable capacitor 212 is fully discharged based on the discharge control signal DIS.

[0096] In one embodiment of this disclosure, the input branch of the current mirror circuit 420 may include a first PMOS transistor 421 and a first NMOS transistor 423, and the output branch of the current mirror 420 may include a second PMOS transistor 422 and a second NMOS transistor 424. The gate of the first PMOS transistor 421 is connected to the gate of the second PMOS transistor 422, the drain of the first PMOS transistor 421, and the drain of the first NMOS transistor 423. The source of the first PMOS transistor 421 and the source of the second PMOS transistor 422 are both connected to the power supply terminal of the frequency calibration circuit 200, and the drain of the second PMOS transistor 422 is connected to the drain of the second NMOS transistor 424.

[0097] The source of the first NMOS transistor 423 and the source of the second NMOS transistor 424 are both connected to the ground terminal GND of the frequency calibration circuit 100.

[0098] In one example, such as Figure 4 As shown, the second resistor 212 can be connected between the source of the first NMOS transistor 423 and the ground terminal GND of the frequency calibration circuit 100, and the second adjustable capacitor 212 can be connected between the source of the second NMOS transistor 424 and the ground terminal GND of the frequency calibration circuit 100.

[0099] In another example, the second resistor 212 can also be connected between the drain of the first PMOS transistor 421 and the drain of the first NMOS transistor 423, and can also be connected between the source of the first PMOS transistor 421 and the power supply terminal of the frequency calibration circuit 100. The second adjustable capacitor 212 can also be connected between the drain of the second PMOS transistor 422 and the drain of the second NMOS transistor 424, and can also be connected between the source of the second PMOS transistor 422 and the power supply terminal of the frequency calibration circuit 100.

[0100] In one example, as shown in FIG. 4, the frequency calibration circuit 100 can further include a bandgap reference source 430 for outputting a reference voltage. The gate of the first NMOS transistor 423 can be connected with the output terminal of the bandgap reference source 430. Figure 4

[0101] In one example, as shown in FIG. 4, the frequency calibration circuit 100 can further include an operational amplifier 440, the non-inverting input terminal of which is connected with the bandgap reference source 430, the inverting input terminal of which is connected with the source of the first NMOS transistor 423, and the output terminal of which is connected with the gate of the first NMOS transistor 423. Figure 4

[0102] In one example, the gate of the second MOS transistor 424 is connected with a host. The host can output a charging control signal INT to the second MOS transistor 424, the charging control signal INT being used to control the on-off state of the output branch of the current mirror circuit 420, so that the second adjustable capacitor 212 is charged for a predetermined time length based on the charging control signal INT.

[0103] In the present embodiment, at most one of the second switch 410 and the second MOS transistor 424 is in the on state. The host can control the second MOS transistor 424 to be on while controlling the second switch 410 to be off, so that the output branch of the current mirror circuit 420 is turned on, or the host can control the second switch 410 to be on while controlling the second MOS transistor 424 to be off, so that the output branch of the current mirror circuit 420 is turned off. The host can also control both the second switch 410 and the second MOS transistor 424 to be off.

[0104] In one embodiment of the present disclosure, the host can first control the second switch 410 to be closed, so that the second adjustable capacitor 212 is discharged, and then control the second switch 410 to be opened when the voltage across the second adjustable capacitor 212 is zero, and then control the output branch of the current mirror circuit 420 to be on for a predetermined time length, so that the charging current generated by the current mirror circuit 420 charges the second adjustable capacitor 212 for a predetermined time length.

[0105] ​​In one embodiment of the present disclosure, the control circuit 220 is configured to select one control signal from the plurality of control signals as the first control signal and output the first control signal to the second adjustable capacitor 212, so as to make the second adjustable capacitor 212 have different capacitance values.

[0106] In the embodiment, the plurality of control signals have a set order, and the set order of the plurality of control signals can make the capacitance values of the second adjustable capacitors change monotonically.

[0107] Specifically, the capacitance value of the second adjustable capacitor corresponding to the control signal with a higher set order can be greater than the capacitance value of the second adjustable capacitor corresponding to the control signal with a lower set order; or the capacitance value of the second adjustable capacitor corresponding to the control signal with a higher set order can be less than the capacitance value of the second adjustable capacitor corresponding to the control signal with a lower set order.

[0108] In one embodiment of the present disclosure, the target control signal is determined according to the first voltage, including: determining a voltage difference between the first voltage and a reference voltage, in a case where the voltage difference is less than a voltage threshold, determining the first control signal as the target control signal; and in a case where the voltage difference is greater than or equal to the voltage threshold, outputting a second control signal to the second adjustable capacitor as a control signal to be verified.

[0109] In the embodiment, the voltage threshold can be determined according to a minimum value of a difference between the first voltage corresponding to each two of the plurality of control signals, and the voltage threshold can be less than or equal to the minimum value.

[0110] In one embodiment, in the case where the voltage difference is greater than or equal to the voltage threshold, the second N-bit binary value corresponding to the second control signal can be determined according to the voltage difference, and the second control signal can be output according to the second N-bit binary value.

[0111] A first comparison table reflecting a mapping relationship between the voltage difference and the N-bit binary value can be preset, the first comparison table can be searched according to the voltage difference between the first voltage and the reference voltage to obtain the N-bit binary value corresponding to the voltage difference as the second N-bit binary value. The first comparison table can be preset according to the capacitance values of the N second capacitors.

[0112] In a case where the first voltage is greater than the reference voltage, the control circuit 220 can determine a first N-bit binary value corresponding to the first control signal, a sum of N-bit binary values corresponding to the voltage difference, as a second N-bit binary value, and output a second control signal matching the second N-bit binary value as the to-be-verified control signal. In a case where the first voltage is less than the reference voltage, the control circuit 220 can determine a first N-bit binary value corresponding to the first control signal, a difference of N-bit binary values corresponding to the voltage difference, as a second N-bit binary value, and output a second control signal matching the second N-bit binary value as the to-be-verified control signal.

[0113] In another embodiment of the present disclosure, determining the target control signal according to the first voltage comprises: comparing the first voltage with the reference voltage to obtain a first comparison result; and determining the target control signal according to the first comparison result.

[0114] In one embodiment, as shown in FIG. 2, the control circuit 220 can comprise a comparator 221 configured to compare the first voltage with the reference voltage to obtain a first comparison result. Figure 4

[0115] In another embodiment, the control circuit 220 can also be implemented by a controller, which compares the first voltage with the reference voltage by an algorithm to obtain a first comparison result, and determines the target control signal according to the first comparison result.

[0116] In one embodiment of the present disclosure, determining the target control signal according to the first comparison result comprises: in a case where the first comparison result meets a set condition, determining the first control signal as the target control signal; and in a case where the first comparison result does not meet the set condition, outputting the second control signal to the second adjustable capacitor as the to-be-verified control signal.

[0117] In one embodiment of the present disclosure, the set condition comprises any one of the following:

[0118] The first comparison result corresponding to the first control signal is that the first voltage is equal to the reference voltage; or

[0119] The first comparison result corresponding to the first control signal is that the first voltage is greater than the reference voltage, and the first comparison result corresponding to the third control signal is that the first voltage is less than the reference voltage; or

[0120] The first comparison result corresponding to the first control signal is that the first voltage is less than the reference voltage, and the first comparison result corresponding to the third control signal is that the first voltage is greater than the reference voltage.

[0121] ​The third control signal is a to-be-verified control signal output by the control circuit before the first control signal. The setting order of the third control signal is adjacent to the setting order of the first setting control signal, and the setting order of the third control signal is in front of the setting order of the first setting control signal.

[0122] In the case where the first voltage is equal to the reference voltage, it indicates that the first adjustable capacitor has a capacitance value controlled by the first control signal, which can make the output frequency of the oscillator reach the target value, so that the first control signal can be directly used as the target control signal without switching the to-be-verified control signal.

[0123] In the embodiment in which the to-be-verified control signal is switched to make the capacitance value of the second adjustable capacitor monotonically decrease, in the case where the first comparison result corresponding to the first control signal is that the first voltage is greater than the reference voltage, and the first comparison result corresponding to the third control signal is that the first voltage is less than the reference voltage, it indicates that the first adjustable capacitor has a capacitance value controlled by the first control signal, which can make the output frequency of the oscillator close to the target value, so that the first control signal can be directly used as the target control signal without continuing to switch the to-be-verified control signal.

[0124] In the embodiment in which the to-be-verified control signal is switched to make the capacitance value of the second adjustable capacitor monotonically increase, in the case where the first comparison result corresponding to the first control signal is that the first voltage is less than the reference voltage, and the first comparison result corresponding to the third control signal is that the first voltage is greater than the reference voltage, it indicates that the first adjustable capacitor has a capacitance value controlled by the first control signal, which can make the output frequency of the oscillator close to the target value, so that the first control signal can be directly used as the target control signal without continuing to switch the to-be-verified control signal.

[0125] In one embodiment of the present disclosure, the control circuit 220 is configured to reselect a control signal from the plurality of control signals as a second control signal in the case where the first comparison result does not meet the set condition.

[0126] In one embodiment, the control circuit 220 can be configured to reselect a control signal from the plurality of control signals as a second control signal randomly in the case where the first comparison result does not meet the set condition.

[0127] In another embodiment, the control circuit 220 can be configured to select a second control signal from the plurality of control signals according to the first comparison result, the setting order of the plurality of control signals, and the first control signal; wherein the setting order is such that the capacitance value of the second adjustable capacitor monotonically changes.

[0128] In a case where the first comparison result is that the first voltage is greater than the reference voltage, a control signal adjacent to the first control signal and causing the capacitance value of the second adjustable capacitor to increase is selected as the second control signal from the plurality of control signals based on the set order.

[0129] In a case where the first comparison result is that the first voltage is less than the reference voltage, a control signal adjacent to the first control signal and causing the capacitance value of the second adjustable capacitor to decrease is selected as the second control signal from the plurality of control signals based on the set order.

[0130] The control circuit can determine the target control signal more quickly by selecting the second control signal in the manner provided in this embodiment.

[0131] In one embodiment of the present disclosure, in a case where the first comparison result does not meet the set condition, outputting the second control signal to the second adjustable capacitor as the control signal to be verified includes: in a case where the first comparison result does not meet the set condition, determining whether the switching number of the control signal to be verified reaches a predetermined number; and in a case where the switching number does not reach the predetermined number, outputting the second control signal to the second adjustable capacitor as the control signal to be verified.

[0132] In this embodiment, the predetermined number can be equal to the number of the plurality of control signals.

[0133] In a case where the structure of the second adjustable capacitor 212 is as shown in Figure 3 and the capacitance value of the i+1th second capacitor is twice the capacitance value of the ith second capacitor, the predetermined number and the number of the plurality of control signals can be 2 N-1 .

[0134] In a case where the structure of the second adjustable capacitor 212 is as shown in Figure 3 and the capacitance values of the N second capacitors are equal, the predetermined number and the number of the plurality of control signals can be N+1.

[0135] In one embodiment of the present disclosure, the control circuit 220 is further configured to: in a case where the switching number reaches the predetermined number, determine that the control signal to be verified is the target control signal.

[0136] In a case where the switching number does not reach the predetermined number, at least one of the plurality of control signals has not been output by the control circuit 220, and thus the second control signal can be output to the second adjustable capacitor as the control signal to be verified, and it is determined again whether the first comparison result corresponding to the second control signal meets the set condition.

[0137] In the embodiment in which the to-be-verified control signal is switched so as to monotonously change the capacitance value of the second adjustable capacitor, if the number of switching reaches the predetermined number, it indicates that the control circuit 220 has outputted each of the plurality of control signals, and the first comparison result corresponding to each control signal does not meet the set condition.

[0138] On this basis, if the number of switching of the to-be-verified control signal reaches the predetermined number, and the first comparison result corresponding to the first control signal still does not meet the set condition, it indicates that the first adjustable capacitor controlled by the first control signal has a capacitance value that can make the output frequency of the oscillator closest to the target value, so the first control signal can be directly used as the target control signal.

[0139] In the case where the charging voltage is greater than the reference voltage, the output second control signal can increase the capacitance value of the second adjustable capacitor. In the case where the charging voltage is less than the reference voltage, the output second control signal can decrease the capacitance value of the second adjustable capacitor.

[0140] In the embodiment in which the second adjustable capacitor 212 is as shown in the structure of Figure 3 In the embodiment in which the second adjustable capacitor 212 is as shown in the structure of

[0141] In one embodiment of the present disclosure, the control circuit 220 can be implemented by a controller, and the step of determining the target control signal according to the first voltage can be implemented by a computer program.

[0142] In another embodiment of the present disclosure, the control circuit 220 can be implemented by hardware circuit. When the first voltage is greater than the reference voltage, the control circuit 220 can be configured to add one to the first N-bit binary value corresponding to the first control signal to obtain a second N-bit binary value, and output a second control signal matching the second N-bit binary value as the to-be-verified control signal. When the first voltage is less than the reference voltage, the control circuit 220 can be configured to subtract one from the first N-bit binary value corresponding to the first control signal to obtain a second N-bit binary value, and output a second control signal matching the second N-bit binary value as the to-be-verified control signal.

[0143] In one embodiment of the present disclosure, as shown in FIG. 2, the control circuit 220 includes a comparator 221, an adder 222, and a D flip-flop 223 corresponding to each first switch. Figure 4

[0144] In this embodiment, the adder 222 can be configured to have a first input end, N second input ends, and N output ends. The positive input end of the comparator 221 is connected to the first end of the second adjustable capacitor 212, the negative input end of the comparator 221 is connected to the first input end of the second resistor 211, the output end of the comparator 221 is connected to the first input end of the adder 222, the adder 222 has N output ends, each output end is connected to the input end of the corresponding D flip-flop 223, and the output end of each D flip-flop 223 is further connected to the corresponding second input end of the adder 222.

[0145] The comparator 221 is configured to compare the first voltage and the reference voltage to obtain a first comparison result.

[0146] The adder 222 is configured to, when the first comparison result is that the first voltage is greater than the reference voltage, add one to the first N-bit binary value representing the first control signal as a second N-bit binary value representing the second control signal; and when the first comparison result is that the first voltage is less than the reference voltage, subtract one from the first N-bit binary value representing the first control signal as a second N-bit binary value representing the second control signal.

[0147] ​The i-th D flip-flop 223 is configured to output an i-th bit of the second control signal to the corresponding first switch according to an i-th bit of the second N-bit binary number, so as to control the on-off state of the i-th first switch. In this embodiment, the i-th D flip-flop 223 outputs a high-level control signal to the corresponding first switch when the i-th bit of the N-bit binary number is 1, and outputs a low-level control signal to the corresponding first switch when the i-th bit of the N-bit binary number is 0. Therefore, the N-bit binary number can also be used to represent the level state of the N-bit parallel control signal.

[0148] In this embodiment, the comparator 221 outputs a high level when the first voltage is greater than the reference voltage, and outputs a low level when the first voltage is less than the reference voltage.

[0149] The N-bit binary number is set to zero each time the frequency calibration circuit is powered on, so that each output terminal of the adder 222 outputs a low level 0. The adder 222 adjusts the N-bit binary number once each time the second adjustable capacitor 212 outputs the first voltage.

[0150] Specifically, the adder 222 can add one to the first N-bit binary number to obtain a second N-bit binary number when the comparator 221 outputs a high level, subtract one from the first N-bit binary number to obtain a second N-bit binary number when the comparator 221 outputs a low level, or use the first N-bit binary number as the second N-bit binary number.

[0151] When the i-th bit of the N-bit binary number is 1, the i-th output terminal of the adder 222 outputs a high level to the i-th D flip-flop 223, so as to control the i-th first switch 35i to be turned on, and the i-th second capacitor 34i is used in the second adjustable capacitor 212; when the j-th bit of the N-bit binary number is 0, the j-th output terminal of the adder 222 outputs a low level to the j-th D flip-flop 223, so as to control the j-th first switch 35j to be turned off, and the j-th second capacitor 34j is not used in the second adjustable capacitor 212; wherein i and j are positive integers less than or equal to N.

[0152] In this embodiment, the comparator operates based on a first clock signal, the adder operates based on a second clock signal, and the N D flip-flops operate based on a third clock signal. The first clock signal, the second clock signal, and the third clock signal can be provided by a host or obtained by the frequency calibration circuit based on a reference clock signal provided by the host.

[0153] In the embodiment, the control circuit composed of the comparator, the adder and the D flip-flop corresponding to each first switch can realize the function of outputting the second control signal as the to-be-verified control signal to the second adjustable capacitor in the case that the first comparison result does not meet the set condition.

[0154] In one example, the structure of the second adjustable capacitor 212 is as shown in Figure 3 The structure of the frequency calibration circuit 200 is as shown in Figure 4 When the oscillator and the frequency calibration circuit are powered on each time, the host first calibrates the frequency of the oscillator through the frequency calibration circuit. Specifically, the host can first send a high-level discharge control signal DIS to the second switch 410, and the second switch 410 is turned on to discharge the second adjustable capacitor 212. Then, the host sends a low-level discharge control signal DIS to the second switch 410, and the second switch 410 is turned off. At this time, the voltage across the second adjustable capacitor 212 is zero. The host then sends a high-level charging control signal INT to the second NMOS transistor 424 in the current mirror circuit 420, and the high-level duration of the charging control signal INT is a predetermined time length, so that the current mirror circuit 420 charges the second adjustable capacitor 212 for a predetermined time length.

[0155] The reference voltage output by the bandgap reference source is V REF , the reference voltage across the second resistor 211 is also V REF , the resistance value of the second resistor 211 is R, and the current I REF in the input branch of the current mirror circuit 420 is V REF / R. Then, the current that charges the second adjustable capacitor 212 in the output branch of the current mirror circuit 420 is also I REF , and the first voltage output by the second adjustable capacitor 212 is V cap = I REF *t / C, where C is the capacitance value of the second adjustable capacitor 212 controlled by the current first control signal.

[0156] For the second adjustable capacitor 212 as shown in Figure 3 , the larger the N-bit binary value is, the larger the capacitance value of the second adjustable capacitor 212 is. If the capacitance value of the second adjustable capacitor 212 is too large, the comparator can output a low level to reduce the capacitance value of the second adjustable capacitor 212; if the capacitance value of the second adjustable capacitor 212 is too small, the comparator can output a high level to increase the capacitance value of the second adjustable capacitor 212.

[0157] In the case that the first comparison result meets the set condition, the first voltage V cap is equal to the reference voltage V REF , that is,

[0158] Since the relationship between the set time t and the target value f0 of the output frequency can be expressed as Therefore, the output frequency of the oscillator can be stabilized to the target value f0.

[0159] In the embodiment, since the reference voltage generated by the bandgap reference source is an accurate voltage value, after the first voltage is determined, the capacitance value of the second adjustable capacitor is determined, and then the output frequency of the oscillator is stabilized to the accurate target value f0.

[0160] In the embodiment in which the first adjustable capacitor 112 and the second adjustable capacitor 212 are capacitive structures whose capacitance values are changed by changing the effective area between the poles or the distance between the poles, the first control signal can be a 1-bit signal, and the control circuit 220 can be configured to change the capacitance value of the second adjustable capacitor by adjusting the voltage or duty cycle of the first control signal.

[0161] In the embodiment, the control circuit 220 can adjust the voltage or duty cycle of the first control signal in a set step.

[0162] In one example, the set step can be a fixed value set in advance according to the accuracy of the output frequency of the oscillator.

[0163] In another example, the set step can also be determined according to the voltage difference between the first voltage and the reference voltage.

[0164] In the embodiment, mapping data reflecting the mapping relationship between the voltage difference and the step can be set in advance; the step corresponding to the current voltage difference is obtained as the set step according to the voltage difference between the first voltage and the reference voltage and the mapping data.

[0165] The mapping data can be a mapping function, a second lookup table, or the like, which is not limited herein.

[0166] For the mapping function, the dependent variable of the mapping function is the step, and the independent variable is the voltage difference, so that the set step corresponding to the voltage difference between the first voltage and the reference voltage can be obtained by substituting the voltage difference into the mapping function.

[0167] For the second lookup table, the set step corresponding to the voltage difference between the first voltage and the reference voltage can be found in the second lookup table. If the voltage difference between the first voltage and the reference voltage cannot be directly found in the second lookup table, two values adjacent to the voltage difference between the first voltage and the reference voltage can be found, and the set step corresponding to the voltage difference between the first voltage and the reference voltage can be obtained by interpolation according to the two values and the steps corresponding to the two values, respectively.

[0168] In a case where the first voltage is greater than the reference voltage, the control circuit 220 can increase the voltage or duty cycle of the first control signal by a set step size to increase the capacitance value of the second adjustable capacitor. In a case where the first voltage is less than the reference voltage, the control circuit 220 can decrease the voltage or duty cycle of the first control signal by a set step size to decrease the capacitance value of the second adjustable capacitor.

[0169] Through the embodiment, the control circuit can determine the target control signal more quickly, so that the output frequency of the oscillator can quickly reach the target value.

[0170] <Chip>

[0171] The embodiment provides a chip, as shown in the figure, the chip 500 can include an oscillator 510 and the frequency calibration circuit 200 of any of the foregoing embodiments. Figure 5

[0172] The oscillator 510 can include a first adjustable capacitor.

[0173] In an example, the oscillator 510 can further include a first resistor used in cooperation with the first adjustable capacitor.

[0174] Further, the oscillator 510 can further include a first adjustable capacitor. Figure 1

[0175] In an example, the chip 500 can be a chip that communicates with a host based on an SPI communication protocol.

[0176] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0177] ​​Computer readable storage media can be tangible storage media which can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0178] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0179] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0180] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0181] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other data storage device. When the computer readable program instructions are loaded into the computer and other programmable data processing apparatus, a series of operational steps are implemented that provide processes such that the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0182] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0183] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logic functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0184] Embodiments of the present disclosure have been described above, and the description is intended to be illustrative of the embodiments and not restrictive. Many modifications and variations of the described embodiments are possible and are within the scope of the disclosure. The selection of terms is intended to best describe the principles of the embodiments, the practical application, or technical improvements over the existing technology, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of the present disclosure is defined by the appended claims.

Claims

1. A frequency calibration circuit for an oscillator, characterized by The oscillator comprises a first adjustable capacitor, and the frequency calibration circuit is configured to determine a target control signal for the first adjustable capacitor, the target control signal being a control signal that causes an output frequency of the oscillator to reach a target value; The frequency calibration circuit comprises a control circuit and a second adjustable capacitor; the second adjustable capacitor and the first adjustable capacitor have the same capacitance value when controlled by the same control signal; The control circuit is configured to output a first control signal as a to-be-verified control signal to the second adjustable capacitor; The second adjustable capacitor generates a first voltage based on a charging current generated by a preset reference voltage under the action of the to-be-verified control signal; The control circuit is further configured to determine the target control signal according to the first voltage and output the target control signal to the first adjustable capacitor.

2. The frequency calibration circuit of claim 1, wherein, The determination of the target control signal according to the first voltage comprises: comparing the first voltage with the reference voltage to obtain a first comparison result; determining the target control signal according to the first comparison result.

3. The frequency calibration circuit of claim 2, wherein, The determination of the target control signal according to the first comparison result comprises: in a case where the first comparison result meets a set condition, determining that the first control signal is the target control signal; in a case where the first comparison result does not meet the set condition, outputting a second control signal as the to-be-verified control signal to the second adjustable capacitor.

4. The frequency calibration circuit of claim 3, wherein, The set condition comprises: the first comparison result corresponding to the first control signal is that the first voltage is equal to the reference voltage; or the first comparison result corresponding to the first control signal is that the first voltage is greater than the reference voltage, and the first comparison result corresponding to a third control signal is that the first voltage is less than the reference voltage; wherein the third control signal is a to-be-verified control signal output by the control circuit before the first control signal, or the first comparison result corresponding to the first control signal is that the first voltage is less than the reference voltage, and the first comparison result corresponding to a third control signal is that the first voltage is greater than the reference voltage.

5. The frequency calibration circuit of claim 3, wherein, In the case where the first comparison result does not meet the set condition, outputting a second control signal as the to-be-verified control signal to the second adjustable capacitor comprises: in the case where the first comparison result does not meet the set condition, determining whether a switching number of switching to-be-verified control signals reaches a predetermined number; in the case where the switching number does not reach the predetermined number, outputting a second control signal as the to-be-verified control signal to the second adjustable capacitor.

6. The frequency calibration circuit of claim 5, wherein, The control circuit is further configured to, in the case where the switching number reaches the predetermined number, determine that the to-be-verified control signal is the target control signal.

7. The frequency calibration circuit of claim 3, wherein, The second adjustable capacitor comprises a first end, a second end, a first capacitor, N second capacitors, and a first switch corresponding to each second capacitor; the first capacitor is connected between the first end and the second end; each second capacitor is connected in parallel between the first end and the second end after being connected in series with the corresponding first switch; and the control signal to be verified is used to control the on-off state of the N first switches, so that the second adjustable capacitor has a corresponding capacitance value.

8. The frequency calibration circuit of claim 7, wherein, The control circuit is configured to select a control signal from a plurality of control signals for making the second adjustable capacitor have different capacitance values as the first control signal, and output the first control signal to the second adjustable capacitor.

9. The frequency calibration circuit of claim 8, wherein, The control circuit is configured to reselect a control signal from the plurality of control signals as the second control signal in a case where the first comparison result does not meet the set condition.

10. The frequency calibration circuit of claim 9, wherein, The control circuit is configured to select the second control signal from the plurality of control signals according to the first comparison result, a set order of the plurality of control signals, and the first control signal; and the set order causes the capacitance value of the second adjustable capacitor to change monotonically.

11. The frequency calibration circuit of claim 10, wherein, In a case where the first comparison result is that the first voltage is greater than the reference voltage, a control signal adjacent to the first control signal and causing the capacitance value of the second adjustable capacitor to increase is selected from the plurality of control signals as the second control signal based on the set order.

12. The frequency calibration circuit of claim 10, wherein, In a case where the first comparison result is that the first voltage is less than the reference voltage, a control signal adjacent to the first control signal and causing the capacitance value of the second adjustable capacitor to decrease is selected from the plurality of control signals as the second control signal based on the set order.

13. The frequency calibration circuit of claim 3, wherein, The control circuit comprises a comparator configured to compare the first voltage and the reference voltage to obtain the first comparison result.

14. The frequency calibration circuit of claim 10, wherein, The capacitance value of an (i+1)th second capacitor is twice the capacitance value of an ith second capacitor, where i is a positive integer less than N.

15. The frequency calibration circuit of claim 14, wherein, The control circuit comprises an adder configured to, in a case where the first comparison result is that the first voltage is greater than the reference voltage, add one to a first N-bit binary value representing the first control signal to obtain a second N-bit binary value representing the second control signal; and in a case where the first comparison result is that the first voltage is less than the reference voltage, subtract one from the first N-bit binary value representing the first control signal to obtain the second N-bit binary value representing the second control signal.

16. The frequency calibration circuit of claim 15, wherein, The control circuit further comprises N D flip-flops, and an ith D flip-flop is configured to output an ith bit control signal in the second control signal to the corresponding first switch according to an ith bit binary value in the second N-bit binary value, to control the on-off state of the ith first switch.

17. The frequency calibration circuit of claim 1, wherein, The first voltage is a voltage output by the second adjustable capacitor after being fully discharged and then being charged for a predetermined time length under the action of the to-be-verified control signal, wherein the predetermined time length is determined according to a target value of the output frequency of the oscillator.

18. The frequency calibration circuit of claim 17, wherein, The frequency calibration circuit further comprises a current mirror circuit, and the second adjustable capacitor is connected to an output branch of the current mirror circuit, and the current mirror circuit is configured to generate the charging current on the output branch based on the reference voltage to charge the second adjustable capacitor for a predetermined time length when the output branch is turned on.

19. The frequency calibration circuit of claim 18, wherein, The oscillator further comprises a first resistor used in cooperation with the first adjustable capacitor, and the frequency calibration circuit further comprises a second resistor, and the first resistor has the same resistance value as the second resistor.

20. The frequency calibration circuit of claim 19, wherein, The second resistor is connected to an input branch of the current mirror circuit, and the current mirror circuit is configured to generate the charging current on the output branch based on a current generated on the input branch by the reference voltage to charge the second adjustable capacitor.

21. The frequency calibration circuit of claim 17, wherein, The frequency calibration circuit comprises a second switch connected in parallel with the second adjustable capacitor. The second adjustable capacitor is discharged through the second switch when the second switch is turned on.

22. The frequency calibration circuit of claim 18, wherein, The input branch of the current mirror circuit comprises a first PMOS tube and a first NMOS tube, the output branch of the current mirror circuit comprises a second PMOS tube and a second NMOS tube, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the first PMOS tube, and the drain of the first NMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are both connected to a power supply end of the frequency calibration circuit, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, the source of the first NMOS tube is connected to a ground end of the frequency calibration circuit, and the source of the second NMOS tube is connected to the ground end.

23. The frequency calibration circuit of claim 22, wherein, The frequency calibration circuit further comprises a bandgap reference source configured to output a reference voltage, and the gate of the first NMOS tube is connected to an output end of the bandgap reference source.

24. The frequency calibration circuit of claim 23, wherein, The frequency calibration circuit further comprises an operational amplifier, the gate of the first NMOS tube is connected to an output end of the operational amplifier, the non-inverting input end of the operational amplifier is connected to the output end of the bandgap reference source, and the inverting input end of the operational amplifier is connected to the source of the first NMOS tube.

25. A chip, characterized by The frequency calibration circuit comprises an oscillator and the frequency calibration circuit according to any one of claims 1 to 24.

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