Method for improving withstand voltage of transverse transistor device by irradiation

Abstract

The invention discloses a method for improving voltage resistance of a transverse transistor device by adopting irradiation. The method comprises the following steps: providing a silicon wafer as a substrate; forming a buried layer and a base deep well region on the substrate; pN junction isolation structures are formed on the two sides of the buried layer respectively, and a base deep junction well region connected with one end of the buried layer is formed; isolation grooves are formed between the emitter region and the collector regions on the two sides; filling an isolation medium in the isolation groove, and forming a thick field oxygen isolation structure on the base deep well region; completing the manufacturing of a base electrode, an emitter electrode and a collector electrode; a surface of the lateral transistor device is irradiated. According to the invention, a longitudinal base region current channel is formed through the isolation groove, electric leakage between an emitter and a collector of the device is greatly reduced, surface inversion of the device is reduced through irradiation of the surface of the transverse transistor device, CE voltage resistance of the device is further improved while CE spacing of the device is reduced, and the device is suitable for large-scale production. Therefore, the integration level of the transverse transistor high-power device can be improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication, and in particular relates to a method for improving the withstand voltage of lateral transistor devices by irradiation. Background Technology

[0002] In conventional bipolar processes, transistors are often fabricated using lateral transistor structures, such as lateral PNP transistors. Their voltage rating is directly related to the collector-emitter spacing (CE spacing) of the lateral PNP transistor. Therefore, in order to meet the voltage rating requirements of the device, the CE spacing is generally large, which is not conducive to the miniaturization of the device. If the CE spacing of the lateral PNP transistor is reduced, the voltage rating of the device will be significantly reduced, which is not conducive to large-scale integration. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a method for improving the withstand voltage of lateral transistor devices by irradiation.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A method for improving the breakdown voltage of a lateral transistor device using irradiation includes the following steps: S100, Provide a silicon wafer having a first conductivity type as a substrate; S200: A buried layer of a second conductivity type is formed in the middle of the substrate, and a base deep well region of the second conductivity type is formed above the buried layer, wherein the upper end of the buried layer is connected to the middle of the base deep well region. S300: A PN junction isolation structure is formed on both sides of the buried layer corresponding to the substrate, and a base deep junction well region of the second conductivity type connected to one end of the buried layer is formed in the base deep junction well region; a base region is defined in the area above the base deep junction well region, and an active region is defined on one side of the middle of the buried region corresponding to the base region, the active region including the emitter region in the middle and the collector regions located on both sides of the emitter region; S400, an isolation trench is formed by etching the base deep well region downward between the emission region and the collector regions on both sides; S500: Fill the isolation trench with an isolation medium and form a thick field oxygen isolation structure on the base deep well region using the LOCOS process; S600: Complete the fabrication of the base, emitter, and collector to obtain a lateral transistor device; S700, Irradiating the surface of a lateral transistor device.

[0005] Furthermore, the substrate is <111> Crystal orientation or <100> Crystal orientation.

[0006] Furthermore, the PN junction isolation structure includes a lower isolation island of a first conductivity type and an upper isolation island of a second conductivity type. The lower isolation island extends downward from the base deep well region into the substrate. The upper isolation island is formed above the lower isolation island and is connected to the lower isolation island.

[0007] Furthermore, step S300 includes the following sub-steps: S310. A first type of lower isolation island, extending downward from the base deep well region into the substrate, is formed on both sides of the buried layer by photolithography and ion implantation processes. S320. A base deep junction well region of the second conductivity type is formed above the corresponding buried layer on the substrate by photolithography and ion implantation, and the base deep junction well region is connected to one end of the buried layer. S330, A second type of upper isolation island is formed at the upper end of the lower isolation island and connected thereto by photolithography and ion implantation processes.

[0008] Furthermore, the lateral transistor device is a lateral PNP transistor, the first conductivity type is formed by P-type doping, and the second conductivity type is formed by N-type doping.

[0009] Furthermore, the depth of the isolation trench is 60% to 80% of the depth of the base deep junction well region.

[0010] Furthermore, the thick field oxygen isolation structure includes a first thick field oxygen located above and connected to the PN junction isolation structure, and a second thick field oxygen located on both sides of the active region.

[0011] Furthermore, step S500 includes the following sub-steps: S510. A thin oxide layer is deposited on the upper surface of the base deep well region and the wall of the isolation trench. S520, A SiN layer is deposited on the surface of the thin oxide layer; S530. A polysilicon layer is deposited on the surface of the SiN layer until the polysilicon layer fills the isolation trench. S540, Remove the polysilicon layer outside the isolation trench; S550, Remove the SiN layer in the region where a LOCOS isolation structure needs to be formed; S560: A thick field oxygen isolation structure is formed in the region where the SiN layer has been removed; S570, Remove the SiN layer outside the isolation trench.

[0012] Furthermore, step S600 includes the following sub-steps: S610. An emitter well region of the first conductivity type is formed in the emitter region by oxidation, photolithography and ion implantation processes, and a collector well region of the first conductivity type is formed in the collector region. S620. An emitter implantation region of the first conductivity type is formed in the emitter well region and a collector implantation region of the first conductivity type is formed in the collector well region through photolithography and ion implantation processes. S630. A base implantation region of a second conductivity type is formed on the upper part of the base deep junction well region by photolithography and ion implantation processes; the ion implantation concentration of the emitter implantation region is greater than the ion implantation concentration of the emitter well region, and the ion implantation concentration of the collector implantation region is greater than the ion implantation concentration of the collector well region. S640. A silicon oxide layer is deposited on the upper surface of the substrate, and a base contact hole is etched on the silicon oxide layer at the position corresponding to the base injection region, an emitter contact hole is etched at the position corresponding to the emitter injection region, and a collector contact hole is etched at the position corresponding to the collector injection region. S650. A metal contact is formed on the surface of the silicon oxide layer. The metal contact includes a base contact extending into the base contact hole and connected to the base injection region, an emitter contact extending into the emitter contact hole and connected to the emitter injection region, and a collector contact extending into the collector contact hole and connected to the collector injection region.

[0013] Furthermore, in step S700, the surface of the lateral transistor device is irradiated with X-rays or gamma rays at a dose rate ≤30 keV.

[0014] In this invention, by forming isolation trenches and filling them with an isolation dielectric, the direction of the base current flow in the lateral transistor is altered, creating a vertical base current channel. This significantly reduces leakage current between the emitter and collector, improving the device's withstand voltage performance. Irradiating the surface of the lateral transistor device reduces surface inversion, further improving the CE withstand voltage performance while decreasing the emitter-collector spacing, thereby enhancing the integration density of high-power lateral transistor devices. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of an embodiment of the method for improving the withstand voltage of lateral transistor devices using irradiation according to the present invention.

[0016] Figure 2 This is a schematic diagram of the structure after the buried layer and the base deep well region are formed on the substrate.

[0017] Figure 3 This is a schematic diagram of the structure after the lower isolation island is formed.

[0018] Figure 4 This is a schematic diagram of the structure after the base deep junction well region is formed.

[0019] Figure 5 This is a schematic diagram of the structure after the upper isolation island is formed.

[0020] Figure 6 This is a schematic diagram of the structure after the isolation trench is formed.

[0021] Figure 7 This is a schematic diagram of the structure after filling with the isolation medium and forming a thick-field oxygen isolation structure.

[0022] Figure 8 This is a schematic diagram of the isolation medium filling the isolation trench.

[0023] Figure 9 This is a schematic diagram of the structure after the collector-well region and emitter-well region are formed.

[0024] Figure 10 This is a schematic diagram of the structure after the collector injection region and emitter injection region are formed.

[0025] Figure 11 This is a schematic diagram of the structure after the base injection region is formed.

[0026] Figure 12 This is a schematic diagram of the structure after the silicon oxide layer is formed and the contact holes are etched.

[0027] Figure 13 This is a schematic diagram of the structure after metal contact is formed.

[0028] Figure 14 This is a graph showing the withstand voltage performance of the device before and after irradiation.

[0029] The diagrams in the instruction manual are labeled as follows: Substrate-100; Buried layer-110; Base deep well region - 200; PN junction isolation structure - 210; lower isolation island - 211; upper isolation island - 212; isolation trench - 220; isolation dielectric - 230; thin oxide layer - 231; SiN layer - 232; polysilicon layer - 233; First thickness field oxygen-310; Second thickness field oxygen-320; Base area -410; Collector area -420; Transmitter area -430; Base deep junction well region -510; Collector well region -520; Emitter well region -530; Base injection region - 610; Collector injection region - 620; Emitter injection region - 630; Silicon oxide layer - 700; base contact hole - 710; collector contact hole - 720; emitter contact hole - 730; Base contact - 810; Collector contact - 820; Emitter contact - 830. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0031] Please see Figure 1 , Figure 1 This is a flowchart of an embodiment of the method for improving the breakdown voltage of a lateral transistor device using irradiation according to the present invention. The method for improving the breakdown voltage of a lateral transistor device using irradiation in this embodiment includes the following steps: S100, a silicon wafer having a first conductivity type is provided as a substrate 100. The substrate 100 can be... <111> Crystal orientation or <100> Crystal orientation. For example, the lateral transistor device can be a lateral PNP transistor, in which case the first conductivity type is formed by P-type doping and the second conductivity type is formed by N-type doping.

[0032] S200, please refer to Figure 2 A second conductivity type buried layer 110 is formed in the middle of the substrate 100 by oxidation, photolithography, doping ion implantation, and annealing on the surface of the substrate 100; and a second conductivity type base deep well region 200 is formed above the buried layer 110 by photolithography, doping ion implantation, and annealing, with the upper end of the buried layer 110 connected to the middle of the base deep well region 200.

[0033] S300: PN junction isolation structures 210 are formed on both sides of the buried layer 110 on the substrate 100, and a second conductivity type base deep junction well region 510 connected to one end of the buried layer 110 is formed in the base deep junction well region 200. Then, a base region 410 is defined in the area above the base deep junction well region 510, and an active region is defined on one side of the buried region corresponding to the middle of the base region 410. The active region includes a central emitter region 430 and collector regions 420 located on both sides of the emitter region 430.

[0034] In this embodiment, the PN junction isolation structure 210 includes a lower isolation island 211 of a first conductivity type and an upper isolation island 212 of a second conductivity type. The lower isolation island 211 extends downward from the base deep well region 200 into the substrate 100; the upper isolation island 212 is formed above the lower isolation island 211 and connected to it. The process of forming the PN junction isolation structure 210 and the base deep well region 510 may include the following sub-steps: S310, please refer to Figure 3 A first conductivity type lower isolation island 211 is formed on both sides of the buried layer 110 by photolithography and ion implantation processes, extending downward from the base deep well region 200 into the substrate 100.

[0035] S320, please refer to Figure 4 A base deep junction well region 510 of a second conductivity type is formed on the substrate 100 above the buried layer 110 through photolithography and ion implantation processes, and the base deep junction well region 510 is connected to one end of the buried layer 110.

[0036] S330, please refer to Figure 5 An upper isolation island 212 of a second conductivity type is formed at the upper end of the lower isolation island 211 and connected thereto through photolithography and ion implantation processes.

[0037] S400, please refer to Figure 6 An isolation trench 220 is formed by etching the base deep well region 200 downwards between the emitter region 430 and the collector regions 420 on both sides. The pattern of the isolation trench 220 can be photolithographically etched on the surface of the base deep well region 200 first, and then the isolation trench 220 is formed by dry or wet etching. The width of the isolation trench 220 is generally ≤1μm; for example, the width of the isolation trench 220 can be 1μm, 0.9μm, 0.8μm, 0.7μm, 0.6μm, 0.5μm, 0.4μm, 0.3μm, 0.2μm, etc. The depth of the isolation trench 220 is generally 60% to 80% of the depth of the base deep junction well region 510. For example, the depth of the isolation trench 220 can be 2μm to 15μm.

[0038] S500, please refer to Figure 7An isolation dielectric 230 is filled in the isolation trench 220, and a thick field oxygen isolation structure is formed on the base deep well region 200 using the LOCOS (Local Oxidation of Silicon) process. By forming the isolation trench 220 and filling it with the isolation dielectric 230, a barrier can be formed between the emitter and collector of the lateral transistor, thereby changing the current flow direction of the base region 410 of the lateral transistor and forming a vertical base region 410 current channel. This significantly reduces the leakage current between the emitter and collector of the device under the same CE spacing, improving the device's breakdown voltage performance.

[0039] Please see Figure 8 The isolation medium 230 generally includes a thin oxide layer 231 deposited on the wall of the isolation trench 220, a SiN layer 232 deposited on the surface of the thin oxide layer 231, and a polysilicon layer 233 deposited on the surface of the SiN layer 232 and filling the isolation trench 220. In this embodiment, the thick field oxide isolation structure includes a first thick field oxide 310 located above the PN junction isolation structure 210 and connected to the upper isolation island 212 of the PN junction isolation structure 210, and a second thick field oxide 320 located on both sides of the active region.

[0040] This step may include the following sub-steps: S510, a thin oxide layer 231 is deposited on the upper surface of the base deep well region 200 and the wall of the isolation trench 220.

[0041] S520, a SiN layer 232 is deposited on the surface of the thin oxide layer 231.

[0042] S530, a polysilicon layer 233 is deposited on the surface of the SiN layer 232 until the polysilicon layer 233 fills the isolation trench 220.

[0043] S540, Remove the polysilicon layer 233 except for the isolation trench 220.

[0044] S550, Remove the SiN layer 232 in the region where the LOCOS isolation structure needs to be formed. The region where the LOCOS isolation structure needs to be formed includes the region above the upper isolation island 212 and the regions on both sides of the active region.

[0045] S560, a thick field oxygen isolation structure is formed in the region where the SiN layer 232 has been removed, including forming a first thick field oxygen 310 connected to the upper isolation island 212 in the region above the upper isolation island 212, and forming a second thick field oxygen 320 on both sides of the active region.

[0046] S570, Remove the SiN layer 232 outside of the isolation trench 220.

[0047] S600: Complete the fabrication of the base, emitter, and collector to obtain a lateral transistor device. This step may include the following sub-steps: S610, please refer to Figure 9 An emitter well region 530 of the first conductivity type is formed in the emitter region 430 through oxidation, photolithography, and ion implantation processes, and a collector well region 520 of the first conductivity type is formed in the collector region 420. The implanted ion concentrations of the emitter well region 530 and the collector well region 520 are generally on the same order of magnitude, but their specific implanted ion concentrations can be the same or different.

[0048] S620, please refer to Figure 10 An emitter implantation region 630 of a first conductivity type is formed in the emitter well region 530 and a collector implantation region 620 of a first conductivity type is formed in the collector well region 520 using photolithography and ion implantation processes. The ion implantation concentration of the emitter implantation region 630 is greater than that of the emitter well region 530, and the ion implantation concentration of the collector implantation region 620 is greater than that of the collector well region 520, thereby enabling a good ohmic contact between the emitter and the collector. For example, the ion implantation concentration of the emitter implantation region 630 can be one order of magnitude higher than that of the emitter well region 530, and the ion implantation concentration of the collector implantation region 620 can be one order of magnitude higher than that of the collector well region 520.

[0049] S630, please refer to Figure 11 A base implantation region 610 of a second conductivity type is formed on the upper part of the base deep junction well region 510 by photolithography and ion implantation processes.

[0050] S640, please refer to Figure 12 A silicon oxide layer 700 is deposited on the upper surface of the substrate 100, and a base contact hole 710 is etched on the silicon oxide layer 700 at the position corresponding to the base injection region 610, an emitter contact hole 730 is etched at the position corresponding to the emitter injection region 630, and a collector contact hole 720 is etched at the position corresponding to the collector injection region 620.

[0051] S650, please refer to Figure 13 Metal contacts are formed on the surface of the silicon oxide layer 700. The metal contacts include a base contact 810 that extends into the base contact hole 710 and connects to the base injection region 610, an emitter contact 830 that extends into the emitter contact hole 730 and connects to the emitter injection region 630, and a collector contact 820 that extends into the collector contact hole 720 and connects to the collector injection region 620.

[0052] S700. Irradiate the surface of the lateral transistor device. In this embodiment, the surface of the lateral transistor device is irradiated with X-rays or gamma rays, and the irradiation dose rate is ≤30keV.

[0053] While using trenching in lateral transistors can reduce the lateral CE spacing and increase the vertical CE spacing, thus achieving higher breakdown voltage, the etching process of silicon trenches (i.e., the etching of isolation trench 220) results in the formation of a certain number of dangling bonds at the Si interface. During subsequent oxidation, these bonds will form interface states and defects at the Si-SiO2 interface, leading to surface inversion, larger recombination current, and a significant reduction in CE breakdown voltage.

[0054] Therefore, it is necessary to solve the leakage problem of slotted lateral transistors. To address this, this embodiment introduces an irradiation scheme. When the lateral transistor device is irradiated, a large number of electron-hole pairs are generated in the SiO2 dielectric of the silicon oxide layer 700. Since the electron mobility is much greater than that of holes, electrons leave the silicon oxide layer 700, while holes remain in the silicon oxide layer 700 and are then transported to the SiO2-Si interface between the silicon oxide layer 700 and the substrate 100. There, they are trapped in a trap region of approximately 100 nm, forming interface trap charges. These trap charges neutralize the surface states induced by the etching of the isolation trench 220, reducing surface inversion. This reduces the CE spacing while increasing the CE breakdown voltage, thereby improving the integration density of high-power lateral transistor devices. Please refer to [link to relevant documentation]. Figure 14 The comparison shows the breakdown voltage of lateral transistor devices before and after total dose irradiation of 300K-1E-9. It can be seen that the breakdown voltage of lateral transistor devices is significantly improved after irradiation.

[0055] In this embodiment, by forming an isolation trench 220 and filling it with an isolation dielectric 230, the current flow direction of the base region 410 of the lateral transistor is changed, forming a vertical base region 410 current channel. This significantly reduces leakage current between the emitter and collector of the device and improves the device's withstand voltage performance. By irradiating the surface of the lateral transistor device, the surface inversion of the device can be reduced, further improving the CE withstand voltage performance of the device while reducing the CE spacing, thereby increasing the integration density of high-power lateral transistor devices.

[0056] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A method for improving the breakdown voltage of a lateral transistor device using irradiation, characterized in that, Includes the following steps: S100, Provide a silicon wafer having a first conductivity type as a substrate; S200: A buried layer of a second conductivity type is formed in the middle of the substrate, and a base deep well region of the second conductivity type is formed above the buried layer, wherein the upper end of the buried layer is connected to the middle of the base deep well region. S300: A PN junction isolation structure is formed on both sides of the buried layer corresponding to the substrate, and a base deep junction well region of the second conductivity type connected to one end of the buried layer is formed in the base deep junction well region; a base region is defined in the area above the base deep junction well region, and an active region is defined on one side of the middle of the buried region corresponding to the base region, the active region including the emitter region in the middle and the collector regions located on both sides of the emitter region; S400, an isolation trench is formed by etching the base deep well region downward between the emission region and the collector regions on both sides; S500: Fill the isolation trench with an isolation medium and form a thick field oxygen isolation structure on the base deep well region using the LOCOS process; S600: Complete the fabrication of the base, emitter, and collector to obtain a lateral transistor device; S700, Irradiating the surface of a lateral transistor device.

2. The method for improving the breakdown voltage of a lateral transistor device by irradiation as described in claim 1, characterized in that: The substrate is <111> Crystal orientation or <100> Crystal orientation.

3. The method for improving the breakdown voltage of a lateral transistor device by irradiation as described in claim 1, characterized in that: The PN junction isolation structure includes a lower isolation island of a first conductivity type and an upper isolation island of a second conductivity type. The lower isolation island extends downward from the base deep well region into the substrate. The upper isolation island is formed above the lower isolation island and is connected to the lower isolation island.

4. The method for improving the withstand voltage of a lateral transistor device by irradiation as described in claim 3, characterized in that, The S300 step includes the following sub-steps: S310. A first type of lower isolation island, extending downward from the base deep well region into the substrate, is formed on both sides of the buried layer by photolithography and ion implantation processes. S320. A base deep junction well region of the second conductivity type is formed on the substrate above the corresponding buried layer by photolithography and ion implantation processes, and the base deep junction well region is connected to one end of the buried layer. S330, A second type of upper isolation island is formed at the upper end of the lower isolation island and connected thereto by photolithography and ion implantation processes.

5. The method for improving the breakdown voltage of a lateral transistor device by irradiation as described in claim 1, characterized in that: The lateral transistor device is a lateral PNP transistor, the first conductivity type is formed by P-type doping, and the second conductivity type is formed by N-type doping.

6. The method for improving the breakdown voltage of a lateral transistor device by irradiation as described in claim 1, characterized in that: The depth of the isolation trench is 60% to 80% of the depth of the base deep junction well region.

7. The method for improving the breakdown voltage of a lateral transistor device by irradiation as described in claim 1, characterized in that: The thick field oxygen isolation structure includes a first thick field oxygen located above and connected to the PN junction isolation structure, and a second thick field oxygen located on both sides of the active region.

8. The method for improving the breakdown voltage of a lateral transistor device by irradiation as described in claim 1, characterized in that: The S500 step includes the following sub-steps: S510. A thin oxide layer is deposited on the upper surface of the base deep well region and the wall of the isolation trench. S520, A SiN layer is deposited on the surface of the thin oxide layer; S530. A polysilicon layer is deposited on the surface of the SiN layer until the polysilicon layer fills the isolation trench. S540, Remove the polysilicon layer outside the isolation trench; S550, Remove the SiN layer in the region where a LOCOS isolation structure needs to be formed; S560: A thick field oxygen isolation structure is formed in the region where the SiN layer has been removed; S570, Remove the SiN layer outside the isolation trench.

9. The method for improving the breakdown voltage of a lateral transistor device by irradiation as described in claim 1, characterized in that: The S600 step includes the following sub-steps: S610. An emitter well region of the first conductivity type is formed in the emitter region by oxidation, photolithography and ion implantation processes, and a collector well region of the first conductivity type is formed in the collector region. S620. An emitter implantation region of the first conductivity type is formed in the emitter well region and a collector implantation region of the first conductivity type is formed in the collector well region through photolithography and ion implantation processes. S630. A base implantation region of a second conductivity type is formed on the upper part of the base deep junction well region by photolithography and ion implantation processes; the ion implantation concentration of the emitter implantation region is greater than the ion implantation concentration of the emitter well region, and the ion implantation concentration of the collector implantation region is greater than the ion implantation concentration of the collector well region. S640. A silicon oxide layer is deposited on the upper surface of the substrate, and a base contact hole is etched on the silicon oxide layer at the position corresponding to the base injection region, an emitter contact hole is etched at the position corresponding to the emitter injection region, and a collector contact hole is etched at the position corresponding to the collector injection region. S650. A metal contact is formed on the surface of the silicon oxide layer. The metal contact includes a base contact extending into the base contact hole and connected to the base injection region, an emitter contact extending into the emitter contact hole and connected to the emitter injection region, and a collector contact extending into the collector contact hole and connected to the collector injection region.

10. The method for improving the breakdown voltage of a lateral transistor device by irradiation as described in any one of claims 1 to 9, characterized in that: In step S700, the surface of the lateral transistor device is irradiated with X-rays or gamma rays at a dose rate ≤30 keV.

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