Super-junction MOSFET structure and manufacturing method thereof

Abstract

The invention provides a super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, and the super-junction MOSFET structure comprises a semiconductor substrate, an epitaxial layer, a gate oxide layer, a gate electrode, a matrix region, a source region, a source electrode and a drain electrode. The semiconductor substrate comprises a front face and a back face, and the straight line direction from the front face to the back face is the vertical direction. The epitaxial layer is arranged on the front surface of the semiconductor substrate and comprises first and second conductive columns which vertically extend from the front surface to the back surface and are alternately arranged in the horizontal direction; the gate oxide layer is arranged on the surface of the first conductive column, the gate electrode is arranged on the gate oxide layer, the matrix region is arranged in the upper region of the second conductive column, and at least one source region is formed in the matrix region. The source electrode is formed on the base body region and electrically connected to at least one source region, the source electrode and the gate electrode are insulated and isolated, and the drain electrode is arranged on the back face of the semiconductor substrate. According to the super-junction MOSFET structure, the thick and thin gate oxide region design is adopted, the gate-drain capacitance is reduced, the turn-off delay is shortened, the transition loss is reduced, and the dynamic performance is optimized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a superjunction MOSFET structure and its manufacturing method. Background Technology

[0002] As power semiconductor devices evolve towards higher voltage withstand, higher frequency, and lower power consumption, traditional vertically diffused metal-oxide-semiconductor field-effect transistors (VDMOS) are gradually revealing a contradiction: "increased voltage withstand but simultaneously increased on-resistance." To address this, superjunction metal-oxide-semiconductor field-effect transistors (SJ MOSFETs) have emerged. SJ MOSFETs significantly increase the doping concentration of the N-type epitaxial layer (N-EPI) by periodically arranging vertical PN junctions between the drain (D) and source (S), while simultaneously utilizing the P-pillars embedded in the N-EPI to form a larger PN junction depletion region. When the device is reverse-biased, this depletion region rapidly expands and clamps off each other, thereby achieving a higher isolation voltage and breaking through the on-resistance limit of traditional vertically diffused metal-oxide-semiconductor field-effect transistors (VDMOS).

[0003] SJ MOSFETs, characterized by low conduction and switching losses, have become core components in high-efficiency, high-power-density systems such as server power supplies, communication power supplies, and charging piles. However, with the intensifying competition in the domestic production of power devices, higher performance requirements are being placed on SJ MOSFETs. Since SJ MOSFETs are designed for high-voltage, high-frequency applications, further reducing their power losses has become a very precise and urgent issue.

[0004] In high-frequency SJ MOSFET applications, the high operating frequency of the device means that excessively large parasitic capacitance will significantly increase the turn-off delay time. During this delay, the device continuously consumes a large amount of energy, causing heat generation, temperature rise, and ultimately failure. Therefore, reducing the power loss of high-frequency SJ MOSFETs is particularly critical.

[0005] The parasitic capacitance of an SJ MOSFET mainly consists of three parts:

[0006] 1) Input capacitance (Ciss) mainly consists of gate-source capacitance (Cgs) and gate-drain capacitance (Cgd);

[0007] 2) Output capacitance (Coss) is mainly composed of the drain-source capacitance (Cds) of the PN junction between the P-type body region (P-body) and the N-type epitaxial layer (N-EPI);

[0008] 3) Reverse transfer capacitance (Crss), mainly composed of gate-drain capacitance (Cgd).

[0009] Under high-frequency conditions, the gate-drain capacitance (Cgd) has the most significant impact on the turn-off delay time. Therefore, the gate-drain capacitance (Cgd) must be reduced to decrease the turn-off delay time, thereby reducing power loss.

[0010] The commonly used technical solution in the industry is to reduce the spacing between adjacent P-body regions to reduce the gate-drain capacitance (Cgd). However, reducing the spacing between the P-body regions will increase the resistance of the JFET region, which in turn will increase the overall on-resistance and thus increase the loss. Summary of the Invention

[0011] The purpose of this application is to provide a superjunction MOSFET structure and its manufacturing method, which adopts a thick and thin gate oxide region design to reduce gate-drain capacitance, shorten turn-off delay, reduce transition loss, and optimize dynamic performance.

[0012] In a first aspect, a superjunction MOSFET structure is provided, comprising a semiconductor substrate, an epitaxial layer, a gate oxide layer, a gate electrode, a substrate region, a source region, a source electrode, and a drain electrode. The semiconductor substrate includes a front side and a back side, with the straight line from the front side to the back side being the vertical direction. The epitaxial layer is disposed on the front side of the semiconductor substrate, and includes a first conductive pillar and a second conductive pillar extending vertically from the front side to the back side and alternately arranged in the horizontal direction. The gate oxide layer is disposed on the surface of the first conductive pillar, and the gate electrode is disposed on the gate oxide layer. The substrate region is disposed in the upper region of the second conductive pillar, and at least one source region is formed within the substrate region. The source electrode is formed on the substrate region and electrically connected to at least one source region. The source electrode and the gate electrode are insulated from each other, and the drain electrode is disposed on the back side of the semiconductor substrate.

[0013] In this configuration, the two ends of the gate electrode and the gate oxide layer in the horizontal direction overlap with portions of the substrate region and the source region in the vertical direction. The portion of the gate oxide layer that overlaps with the substrate region in the vertical direction is the thin gate oxide region, with a thickness of H1 in the vertical direction; the portion of the gate oxide layer located on the first conductivity pillar is the thick gate oxide region, with a maximum thickness of H2 in the vertical direction; wherein, H2 > H1.

[0014] In one feasible scheme, the ratio of the maximum thickness of the thick gate oxide region along the vertical direction to the thickness of the thin gate oxide region along the vertical direction satisfies: H2 / H1 = 6 to 9.

[0015] In one feasible approach, the thickness of the thick gate oxide region gradually decreases in the horizontal direction from the center to the edge along the vertical direction.

[0016] In one feasible embodiment, the thick gate oxide region includes an intermediate region and transition regions located on both sides of the intermediate region at horizontal distances; the thickness of the intermediate region in the vertical direction is H2; from the intermediate region to the thin gate oxide region in the horizontal direction, the thickness of the transition region in the vertical direction gradually decreases from H2 to H1.

[0017] In one feasible scheme, the transition regions on both sides of the middle region are symmetrically distributed; the total length of the thick gate oxide region along the horizontal direction is L, the length of the middle region along the horizontal direction is L1, and the length of the transition region along the horizontal direction is L2; ​​where L=L1+2*L2, L1 / L≥0.6.

[0018] In one feasible scheme, the height difference between the horizontal plane where the back side of the thin gate oxide region is located and the horizontal plane where the lowest point of the maximum thickness of the thick gate oxide region in the vertical direction is located is H3; where H3 / H2 < 0.5.

[0019] In one feasible scheme, the maximum thickness H2 of the thick gate oxide region along the vertical direction is 200–600 nm, and the thickness H1 of the thin gate oxide region along the vertical direction is 30–100 nm.

[0020] In one feasible embodiment, the semiconductor substrate is a heavily doped N-type substrate, the epitaxial layer is an N-type epitaxial layer, the first conductivity pillar is an N-type pillar, the second conductivity pillar is a P-type pillar, and the substrate region is a P-type body region.

[0021] Secondly, a method for manufacturing a superjunction MOSFET structure is also provided, comprising:

[0022] S1. Prepare a semiconductor substrate and form an epitaxial layer on its front side; wherein the straight line direction from the front side to the back side is the vertical direction;

[0023] S2. In the epitaxial layer, a first conductive pillar and a second conductive pillar are fabricated that extend vertically from the front side to the back side and are alternately arranged in the horizontal direction to form a superjunction structure.

[0024] S3. A thick gate oxide region is formed in the area near the middle of the front side of the first conductive pillar.

[0025] S4. Thin gate oxide regions are formed on both sides of the thick gate oxide region;

[0026] S5. A gate electrode is formed on the surface of the gate oxide layer, and a gate insulating layer is covered on the surface of the gate electrode.

[0027] S6. A matrix region is formed in the upper region of the second conductive column;

[0028] S7. Form at least one source region in the matrix region;

[0029] S8. A source electrode is formed to connect the source region, and the source electrode is covered by the gate insulating layer;

[0030] S9. A drain electrode is formed on the back side of the semiconductor substrate;

[0031] In this process, the thin gate oxide region of the gate electrode overlaps with a portion of the substrate region and the source region in the vertical direction; the thickness of the thin gate oxide region in the vertical direction is H1, and the maximum thickness of the thick gate oxide region in the vertical direction is H2, where H2 > H1.

[0032] In one feasible scheme, the ratio of the maximum thickness of the thick gate oxide region in the vertical direction to the thickness of the thin gate oxide region in the vertical direction satisfies: H2 / H1 = 6~9; and the thick gate oxide region includes an intermediate region and transition regions located on both sides of the intermediate region in the horizontal direction; the thickness of the intermediate region in the vertical direction is H2; from the intermediate region to the thin gate oxide region in the horizontal direction, the thickness of the transition region in the vertical direction gradually decreases from H2 to H1.

[0033] Compared with the prior art, the beneficial effects of this application include at least the following: In the superjunction MOSFET structure of this application, a thick gate oxide region (i.e., a thick gate oxide region is used on the surface of the accumulation region between the substrate region and the source region) covers the first conductivity pillar, and the gate oxide layer overlapping the substrate region and the source region in the vertical direction is a thin gate oxide region. By increasing the dielectric thickness between the gate and drain through the thick gate oxide region, the gate-drain capacitance (Cgd) is specifically reduced, thereby reducing the turn-off delay time. With the switching frequency unchanged, the reduction of the turn-off delay time directly reduces the transition loss during the switching process, thereby reducing the overall power loss and optimizing the dynamic performance of the device. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a cross-sectional schematic diagram of a superjunction MOSFET structure shown in an embodiment of this application.

[0036] Figure 2 for Figure 1 A magnified schematic diagram of the local structure at point A.

[0037] Figure 3 for Figure 1 Another enlarged schematic diagram of a local structure at point A.

[0038] Figure 4 for Figure 3 A magnified schematic diagram of the middle gate oxide layer.

[0039] Figure 5a and Figure 5b Micrograph of the gate oxide layer structure of the first superjunction MOSFET structure is provided for this application.

[0040] Figure 6a and Figure 6b Micrograph of the gate oxide layer structure of the second superjunction MOSFET structure is provided for this application.

[0041] Figure 7a and Figure 7b Micrographs of the gate oxide layer structure of the third superjunction MOSFET structure are provided for this application.

[0042] Figure 8a and Figure 8b Micrograph of the gate oxide layer structure of the fourth superjunction MOSFET structure is provided for this application.

[0043] Figure 9 This is a flowchart illustrating a method for manufacturing a superjunction MOSFET structure according to an embodiment of this application.

[0044] In the figure: 1. Semiconductor substrate; 2. Epitaxial layer; 21. First conductivity pillar; 22. Second conductivity pillar; 3. Gate oxide layer; 31. Thin gate oxide region; 32. Thick gate oxide region; 321. Intermediate region; 322. Transition region; 4. Gate electrode; 41. Gate insulating layer; 5. Substrate region; 6. Source region; 7. Source electrode; 8. Drain electrode. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0047] like Figure 1 As shown, this application embodiment first provides a superjunction MOSFET structure, including a semiconductor substrate 1, an epitaxial layer 2, a gate oxide layer 3, a gate electrode 4, a substrate region 5, a source region 6, a source electrode 7, and a drain electrode 8.

[0048] The semiconductor substrate 1 includes a front side and a back side, with the straight line from the front side to the back side being the vertical direction. The semiconductor substrate 1 can be a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. Group IV semiconductors include, but are not limited to, silicon (Si) substrates, germanium (Ge) substrates, or silicon-germanium (Si-Ge) substrates. Structurally, the semiconductor substrate 1 can be a bulk silicon wafer or an epitaxial layer grown on a bulk silicon wafer. In this embodiment, the semiconductor substrate 1 is specifically a highly doped N-type substrate.

[0049] An epitaxial layer 2 is disposed on the front side of the semiconductor substrate 1. The epitaxial layer 2 includes a first conductivity pillar 21 and a second conductivity pillar 22 extending vertically from the front side to the back side and alternately arranged in the horizontal direction to form a superjunction structure. The epitaxial layer is typically a single-crystal semiconductor with a crystal lattice matched to the semiconductor substrate 1. In this embodiment, the epitaxial layer 2 is a lightly doped N-type epitaxial layer. The first conductivity pillar 21 is formed by introducing N-type impurities into the epitaxial layer 2 to form N-type pillars, and the second conductivity pillar 22 is formed by introducing P-type impurities into the epitaxial layer 2 to form P-type pillars.

[0050] A gate oxide layer 3 is disposed on the surface of the first conductive post 21, and a gate electrode 4 is disposed on the gate oxide layer 3, which provides insulation. A gate insulating layer 41 is covered on the gate electrode 4, also for insulation from the subsequent source electrode 7.

[0051] A substrate region 5 is disposed in the upper region of the second conductive pillar 22, and at least one source region 6 is formed within the substrate region 5. The substrate region 5 is a P-type body region, and the source region 6 can be a high-concentration N-type impurity region. The substrate region 5 may have one or more source regions 6. In this embodiment, two source regions 6 are formed in the substrate region 5. By forming two source regions 6, current paths to the N-type pillars can be formed on both sides of each P-type pillar.

[0052] A source electrode 7 is formed on the substrate region 5 and electrically connected to at least one source region 6. The source electrode 7 is insulated from the gate electrode 4. A drain electrode 8 is formed on the back side of the semiconductor substrate 1.

[0053] In this configuration, the two ends of the gate electrode 4 and the gate oxide layer 3 in the horizontal direction overlap with a portion of the substrate region 5 and the source region 6 in the vertical direction. The overlapping portion of the gate oxide layer 3 and the substrate region 5 in the vertical direction is the thin gate oxide region 31, with a thickness of H1 in the vertical direction; the portion of the gate oxide layer 3 located on the first conductivity pillar 21 is the thick gate oxide region 32, with a maximum thickness of H2 in the vertical direction; wherein, H2 > H1.

[0054] Gate-drain capacitance (Cgd) is the parasitic capacitance formed between the gate electrode and the drain electrode in a MOSFET structure; it is an inherent capacitance parameter within the device. In this embodiment, from a structural perspective, its formation originates from the electric field coupling between the gate electrode 4 and the drain electrode 8. The gate electrode 4, through the gate oxide layer 3 (oxide dielectric), forms a structure similar to a parallel-plate capacitor with the semiconductor region where the drain electrode 8 is located (such as the first conductivity pillar 21 in a superjunction structure). Here, the gate oxide layer 3 is the dielectric, and the corresponding regions of the gate electrode 4 and the drain electrode 8 serve as two plates, thereby generating a capacitance effect.

[0055] During device operation, the characteristics of Cgd directly affect the switching performance of the MOSFET. For example, during the turn-off process, fluctuations in the drain voltage 8 can inject or extract charge into the gate electrode 4 through Cgd (also known as the "Miller effect"), causing a delay in the voltage change of the gate electrode 4, thereby prolonging the turn-off time.

[0056] In the superjunction MOSFET structure of this embodiment, a thick gate oxide region 32 (i.e., a thick gate oxide region 32 is used on the surface of the accumulation region between the substrate regions 5) covers the first conductivity pillar 21. The gate oxide layer 3 overlapping the substrate region 5 and the source region 6 in the vertical direction is a thin gate oxide region 31. By increasing the dielectric thickness between the gate and drain through the thick gate oxide region 32, the gate-drain capacitance (Cgd) is specifically reduced, thereby weakening the influence of the "Miller effect" and reducing the turn-off delay time. With the switching frequency unchanged, the reduction of the turn-off delay time directly reduces the transition loss during the switching process, thereby reducing the overall power loss and optimizing the dynamic performance of the device.

[0057] Furthermore, regarding on-resistance, the on-resistance of the superjunction MOSFET structure is mainly determined by the resistance of the first conductive pillar 21 between the base regions 5, and its resistance value is closely related to the spacing between the base regions 5 (i.e., the width of the first conductive pillar 21). When the spacing decreases, the cross-sectional area of ​​the first conductive pillar 21 decreases, and the on-resistance increases; conversely, the on-resistance decreases. In this structure, when a thick gate oxide region 32 and a thin gate oxide region 31 are configured, only the thickness distribution of the gate oxide layer 3 is changed, without adjusting the spacing between the base regions 5 (i.e., the alternating spacing of the first conductive pillar 21 and the second conductive pillar 22 in the horizontal direction remains unchanged). Therefore, the width of the first conductive pillar 21 and the cross-sectional area of ​​the overall current path do not change, and its resistance characteristics remain basically stable, making the overall on-resistance less affected by the gate oxide configuration, ensuring that the device can maintain good conduction performance while having low power loss.

[0058] In one embodiment, such as Figures 2 to 4 As shown, the ratio of the maximum thickness of the thick gate oxide region 32 along the vertical direction to the thickness of the thin gate oxide region 31 along the vertical direction satisfies: H2 / H1 = 6 to 9. In a more preferred embodiment, H2 / H1 = 6.5 to 8.5.

[0059] From the perspective of capacitance regulation, this range enables effective optimization of the gate-drain capacitance. In this embodiment, gate oxide thickness is a key factor affecting the gate-drain capacitance. Within this ratio range, the thick gate oxide region 32 can significantly weaken the electric field coupling between the gate electrode 4 and the extended region of the drain electrode 8, thereby reasonably reducing the gate-drain capacitance and providing favorable conditions for shortening the turn-off delay and reducing power loss. In terms of performance balance, this ratio range can take into account both the dynamic performance and conduction characteristics of the device. Within this range, the combination of the two can both improve the dynamic performance through the thick gate oxide region 32 and ensure that the thin gate oxide region 31 functions normally, keeping the on-resistance at a reasonable level.

[0060] From a process adaptation perspective, this ratio range meets the actual needs of industrial production. The preparation of gate oxide layer 3 needs to consider the controllability and stability of the oxidation process. The thickness parameters within this ratio range can match mature oxidation processes, facilitating precise control of the thickness deviation of gate oxide layer 3, reducing the process difficulty in the production process, and helping to ensure product consistency and yield.

[0061] If the ratio is outside this range, the following situations may be exacerbated. When the ratio is too small, the thickness of the thick gate oxide region 32 is relatively insufficient, resulting in limited reduction of gate-drain capacitance. This leads to strong gate-drain coupling, making it difficult to effectively shorten the turn-off delay, resulting in insignificant reduction in power loss and limited improvement in dynamic performance. Conversely, when the ratio is too large, the thickness of the thick gate oxide region 32 becomes excessive. On the one hand, this increases the difficulty of the oxidation process, making it difficult to precisely control the thickness and leading to a decrease in production yield. On the other hand, an excessively thick gate oxide layer 3 may affect the electric field modulation of the relevant region by the gate electrode 4, and may even cause a mismatch with the epitaxial layer structure, disrupting the charge balance of the superjunction structure and thus adversely affecting the overall performance of the device. At the same time, excessive reduction of gate-drain capacitance may also produce other unknown negative effects.

[0062] In one embodiment, the maximum thickness H2 of the thick gate oxide region 32 along the vertical direction is 200-600 nm, and the thickness H1 of the thin gate oxide region 31 along the vertical direction is 30-100 nm.

[0063] In one embodiment, such as Figure 2As shown, the thickness of the thick gate oxide region 32 gradually decreases from the center to the edge in the horizontal direction along the vertical direction. This gradual decrease in thickness from the center to the edge optimizes the electric field distribution of the gate oxide layer 3 and its surrounding area, improving the device's withstand voltage and operational reliability. Regarding capacitance, it allows for fine-tuning of the gate-drain capacitance. The thicker gate oxide in the center reduces the capacitance in the main coupling region to optimize dynamic performance, while the gradually thinning edge ensures the gate's control precision over adjacent areas, balancing multiple performance aspects. In terms of manufacturing process, this gradient structure is compatible with existing fabrication processes, reducing the manufacturing difficulty caused by abrupt thickness changes, improving product consistency, and thus reducing production costs.

[0064] In one embodiment, such as Figure 3 and Figure 4 As shown, the thick gate oxide region 32 includes an intermediate region 321 and transition regions 322 located on both sides of the intermediate region 321. The thickness of the intermediate region 321 in the vertical direction is H2. From the intermediate region 321 to the horizontal direction of the thin gate oxide region 31, the thickness of the transition region 322 in the vertical direction gradually decreases from H2 to H1.

[0065] In this embodiment, at the electric field optimization level, the near-constant thickness H2 of the intermediate region 321 can stably withstand the strong electric field above the first conductive pillar 21, while the gradient thickness design of the transition region 322 smoothly connects the electric field gradient between the thick gate oxide region 32 and the thin gate oxide region 31. If an abrupt thickness boundary is used, electric field concentration is likely to form at the junction, causing the local electric field intensity to exceed the tolerance limit of the gate oxide layer 3, leading to the risk of breakdown. The gradient structure of the transition region 322, through the continuously changing dielectric thickness, allows the electric field intensity to be gradually released along the horizontal direction, avoiding edge electric field distortion and significantly improving the device's withstand voltage capability and long-term operational reliability.

[0066] Regarding capacitance control, the thick gate oxide in the intermediate region 321 can maximize the reduction of the gate-drain capacitance in the region corresponding to the first conductivity pillar 21, directly optimizing dynamic performance. The gradual thickness change in the transition region 322 achieves a smooth transition of the gate-drain capacitance, avoiding voltage and current oscillations during switching caused by sudden capacitance changes. At the same time, the transition region 322 is close to the substrate region 5 and the source region 6, and its gradually thinning thickness can ensure precise control of the gate on / off of the channel, while taking into account the stability of the gate-source capacitance, making the device's response more balanced in high-frequency switching scenarios.

[0067] In one embodiment, such as Figure 4 As shown, the transition regions 322 on both sides of the intermediate region 321 are symmetrically distributed. The total length of the thick gate oxide region 32 along the horizontal direction is L, the length of the intermediate region 321 along the horizontal direction is L1, and the length of the transition region 322 along the horizontal direction is L2. Wherein, L=L1+2*L2, L1 / L≥0.6.

[0068] In this embodiment, from the perspective of electric field distribution, the symmetrically distributed transition region ensures that the electric field gradient on both sides of the thick gate oxide region 32 is uniform and symmetrical, avoiding unilateral electric field concentration caused by structural asymmetry. The length of the middle region 321 is not less than 0.6, which means that it can occupy the main area of ​​the thick gate oxide region 32, providing stable support for the strong electric field above the first conductive pillar 21, reducing the problem of insufficient electric field coverage caused by the middle region 321 being too short, and further improving the stability of the device's withstand voltage.

[0069] In terms of capacitance control, L1 / L≥0.6 ensures the proportion of the main low-capacitance region 321 in the middle area, which can fully utilize the effect of thick gate oxide to reduce gate-drain capacitance and lay the foundation for dynamic performance optimization. The symmetrical transition region makes the changing trend of gate-drain capacitance on both sides consistent, avoiding voltage and current imbalance during switching caused by sudden changes in capacitance on one side, and making the device response more stable when operating at high frequencies.

[0070] In one embodiment, such as Figure 4 As shown, the height difference between the horizontal plane where the back side of the thin gate oxide region 31 is located and the horizontal plane where the lowest point of the maximum thickness of the thick gate oxide region 32 in the vertical direction is located is H3. Where H3 / H2 < 0.5. In a further embodiment, 0.4 ≤ H3 / H2 < 0.5.

[0071] In this embodiment, from the perspective of electric field control, this ratio limit can avoid electric field distortion caused by an excessive vertical height difference between the back side of the thick gate oxide region 32 and the back side of the thin gate oxide region 31. The maximum thickness region of the thick gate oxide region 32 (the middle region 321) is the core that withstands the strong electric field. If H3 is too large (i.e., H3 / H2≥0.5), the vertical distance between the lowest point of the back side of the thin gate oxide region 31 and the back side of the thick gate oxide region 32 will be too wide, which will cause the electric field lines at the interface between the two to be distributed in a messy manner, forming a local high electric field region and increasing the risk of gate oxide layer 3 breakdown. On the other hand, H3 / H2<0.5 can shorten the vertical height difference, making the electric field transition more smoothly in the transition region and ensuring the breakdown voltage stability of the device.

[0072] At the capacitor optimization level, this range can balance the synergistic effect of gate-drain and gate-source capacitances. Thick gate oxide regions suppress gate-drain capacitance through H2, while thin gate oxide regions ensure gate-source control capability through H1. The ratio limit of H3 avoids capacitive coupling imbalance caused by excessive vertical position deviation between the two. Further limiting 0.4 ≤ H3 / H2 < 0.5 maintains a certain height difference to distinguish the functional boundaries of the two types of gate oxide regions, while also reducing capacitance regulation delay caused by excessive spacing through moderately close vertical positions. This results in more coordinated capacitance changes during switching and reduced dynamic losses.

[0073] like Figures 5a to 8b As shown in Table 1, this embodiment also provides several specific structural schemes for the gate oxide layer 3.

[0074] Table 1. Structural Dimensions of Different Gate Oxide Layer Schemes

[0075] Note: For ease of calculation and to meet accuracy requirements, the data in Table 1 are only rounded to two decimal places.

[0076] In the table, H1 represents the thickness of the thin gate oxide region 31 in the vertical direction;

[0077] H2 is the maximum thickness of the thick gate oxide region 32 in the vertical direction;

[0078] H3 is the height difference between the horizontal plane where the back side of the thin gate oxide region 31 is located and the horizontal plane where the lowest point of the maximum thickness of the thick gate oxide region 32 is located in the vertical direction.

[0079] L is the total length of the thick gate oxide region 32 along the horizontal direction;

[0080] L1 is the horizontal length of the intermediate section 321;

[0081] L2 is the length of the single-sided transition zone 322 along the horizontal direction.

[0082] This implementation tested the reverse recovery time Trr (i.e., the time it takes for the reverse current to decay from its peak to zero) of the power devices under each scheme in Table 1. It was found that after adopting the gate oxide layer 3 of the superjunction MOSFET structure of this application, Trr can be improved by about 13% compared with the gate oxide layer maintaining a uniform and thin thickness.

[0083] like Figure 9 As shown in the embodiments of this application, a method for manufacturing the aforementioned superjunction MOSFET structure is also provided, comprising:

[0084] S1. Prepare a semiconductor substrate 1 and form an epitaxial layer 2 on its front side;

[0085] S2. In the epitaxial layer 2, a first conductive pillar 21 (N-type pillar) and a second conductive pillar 22 (P-type pillar) extending vertically from the front to the back and alternating in the horizontal direction are fabricated to form a superjunction structure.

[0086] S3. A thick gate oxide region 32 of the gate oxide layer 3 is formed in the middle region on the front side of the first conductive pillar 21.

[0087] S4. Thin gate oxide regions 31 are formed on both sides of the thick gate oxide region 32;

[0088] S5. A gate electrode 4 is formed on the surface of the gate oxide layer 3, and a gate insulating layer 41 is covered on the surface of the gate electrode 4.

[0089] S6. A substrate region 5 is formed in the upper region of the second conductive pillar 22;

[0090] S7. Form at least one source region 6 in the matrix region 5;

[0091] S8. A source electrode 7 is formed to electrically connect the source region 6, and the source electrode 7 is covered by the gate insulating layer 41.

[0092] S9. A drain electrode 8 is formed on the back side of the semiconductor substrate 1;

[0093] In this process, the thin gate oxide region 31 of the gate electrode 4 overlaps with a portion of the substrate region 5 and the source region 6 in the vertical direction; the thickness of the thin gate oxide region 31 in the vertical direction is H1, and the maximum thickness of the thick gate oxide region 32 in the vertical direction is H2, where H2 > H1.

[0094] In one embodiment, in step S1, the semiconductor substrate 1 is a highly doped N-type substrate, which is cut, ground, and polished to obtain a substrate with a smooth surface. The epitaxial layer 2 is grown on the front side of the substrate using chemical vapor deposition (CVD) to form an N-type epitaxial layer (N-EPI). The substrate is placed in a reaction chamber, and silicon-containing source gases such as silane are introduced. At high temperature, silicon atoms grow epitaxially along the substrate lattice direction to form an epitaxial layer that matches the substrate lattice. This initial layer is a "dense epitaxial layer," with a doping concentration higher than that of subsequent supplementary layers, and serves as the basic N-type conductive channel for the superjunction structure. At this time, the epitaxial layer is entirely N-type without alternating pillars.

[0095] In one embodiment, in step S2, a superjunction structure can be formed by epitaxial growth layer by layer with simultaneous N-type and P-type doping. This is a conventional technique in the art and will not be described further.

[0096] In one embodiment, in step S2, trenches can be directly opened and filled, i.e., deep trench technology, to obtain a superjunction structure. This is a conventional technique in the art and will not be described further.

[0097] In one embodiment, in step S3, silicon nitride can be used as a mask. First, a pattern is created on the surface of the epitaxial layer 2 after step S2 using photolithography. Then, a silicon nitride thin film is deposited and etched so that the silicon nitride mask only covers the area near the center of the front side of the first conductive pillar 21 where the thick gate oxide region 32 needs to be formed, while other areas are exposed. Afterward, it is placed in a high-temperature oxidation furnace for oxidation treatment, and a gate oxide layer is grown in the area corresponding to the exposed first conductive pillar 21. Because silicon nitride has the property of blocking oxidation, no oxide layer grows in the area covered by it, while a thicker gate oxide layer (e.g., 200 nm to 500 mm) grows in the uncovered target area; this part is the thick gate oxide region 32.

[0098] In one embodiment, in step S4, after the growth of the thick gate oxide region 32 is completed, the silicon nitride mask and any sacrificial oxide film that may be formed need to be removed. Specifically, hot phosphoric acid can be used for this process. Hot phosphoric acid can etch and remove the silicon nitride mask, and at the same time, it will remove the sacrificial oxide film on the surface, exposing the area where the thin gate oxide region 31 needs to be grown. Subsequently, the sample is placed in an oxidation furnace again for oxidation. A gate oxide layer is grown in the area where no thick gate oxide layer was grown before and the mask has been removed (mainly the area above the substrate region 5 and the source region 6). The gate oxide layer grown this time is thinner (e.g., 100 nm), forming the thin gate oxide region 31.

[0099] Steps S5 to S9 are conventional technical methods, and their specific details can be found in existing technologies, so they will not be described in detail here.

[0100] In this embodiment, the ratio of the maximum thickness of the thick gate oxide region 32 in the vertical direction to the thickness of the thin gate oxide region 31 in the vertical direction satisfies: H2 / H1 = 6 to 9. Further, the thick gate oxide region 32 includes an intermediate region 321 and transition regions 322 located on both sides of the intermediate region 321 in the horizontal direction; the thickness of the intermediate region 321 in the vertical direction is H2; from the intermediate region 321 to the thin gate oxide region 31 in the horizontal direction, the thickness of the transition region 322 in the vertical direction gradually decreases from H2 to H1.

[0101] The above description is only a partial embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A superjunction MOSFET structure, characterized in that, include: A semiconductor substrate (1) includes a front side and a back side, with the straight line from the front side to the back side being the vertical direction; An epitaxial layer (2) is disposed on the front side of the semiconductor substrate (1). The epitaxial layer (2) includes a first conductive pillar (21) and a second conductive pillar (22) that extend vertically from the front side to the back side and are alternately arranged in the horizontal direction. A gate oxide layer (3) is disposed on the surface of the first conductive pillar (21); A gate electrode (4) is disposed on the gate oxide layer (3); The substrate region (5) is located in the upper region of the second conductive column (22); At least one source region (6) is formed within the substrate region (5); A source electrode (7) is formed on the substrate region (5) and electrically connected to at least one of the source regions (6), wherein the source electrode (7) is insulated from the gate electrode (4); The drain (8) is disposed on the back side of the semiconductor substrate (1); Wherein, the two ends of the gate electrode (4) and the gate oxide layer (3) in the horizontal direction overlap with a portion of the substrate region (5) and the source region (6) in the vertical direction; The overlapping portion of the gate oxide layer (3) and the substrate region (5) in the vertical direction is a thin gate oxide region (31), with a thickness of H1 in the vertical direction; the portion of the gate oxide layer (3) located on the first conductive pillar (21) is a thick gate oxide region (32), with a maximum thickness of H2 in the vertical direction; wherein, H2 > H1.

2. The superjunction MOSFET structure according to claim 1, characterized in that, The ratio of the maximum thickness of the thick gate oxide region (32) in the vertical direction to the thickness of the thin gate oxide region (31) in the vertical direction satisfies: H2 / H1 = 6~9.

3. The superjunction MOSFET structure according to claim 2, characterized in that, The thickness of the thick gate oxide region (32) gradually decreases in the horizontal direction from the middle to the edge along the vertical direction.

4. The superjunction MOSFET structure according to claim 2, characterized in that, The thick gate oxide region (32) includes an intermediate region (321) and a transition region (322) located on both sides of the intermediate region (321) at a horizontal level; The thickness of the intermediate region (321) in the vertical direction is H2; From the intermediate region (321) to the thin gate oxide region (31) in the horizontal direction, the thickness of the transition region (322) in the vertical direction gradually decreases from H2 to H1.

5. The superjunction MOSFET structure according to claim 4, characterized in that, The transition zones (322) on both sides of the intermediate zone (321) are symmetrically distributed; The total length of the thick gate oxide region (32) in the horizontal direction is L, the length of the intermediate region (321) in the horizontal direction is L1, and the length of the transition region (322) in the horizontal direction is L2. Where L = L1 + 2 * L2, L1 / L ≥ 0.

6.

6. The superjunction MOSFET structure according to claim 2, characterized in that, The height difference between the horizontal plane where the back side of the thin gate oxide region (31) is located and the horizontal plane where the lowest point of the maximum thickness of the thick gate oxide region (32) is located in the vertical direction is H3. Where H3 / H2 < 0.

5.

7. The superjunction MOSFET structure according to claim 1 or 2, characterized in that, The maximum thickness H2 of the thick gate oxide region (32) along the vertical direction is 200-600 nm, and the thickness H1 of the thin gate oxide region (31) along the vertical direction is 30-100 nm.

8. The superjunction MOSFET structure according to claim 1, characterized in that, The semiconductor substrate (1) is a heavily doped N-type substrate, the epitaxial layer (2) is an N-type epitaxial layer, the first conductive pillar (21) is an N-type pillar, the second conductive pillar (22) is a P-type pillar, and the substrate region (5) is a P-type body region.

9. A method for manufacturing a superjunction MOSFET structure, characterized in that, include: S1. Prepare a semiconductor substrate and form an epitaxial layer on its front side; wherein the straight line direction from the front side to the back side is the vertical direction; S2. In the epitaxial layer, a first conductive pillar and a second conductive pillar are fabricated that extend vertically from the front side to the back side and are alternately arranged in the horizontal direction to form a superjunction structure. S3. A thick gate oxide region is formed in the area near the middle of the front side of the first conductive pillar. S4. Thin gate oxide regions are formed on both sides of the thick gate oxide region; S5. A gate electrode is formed on the surface of the gate oxide layer, and a gate insulating layer is covered on the surface of the gate electrode. S6. A matrix region is formed in the upper region of the second conductive column; S7. Form at least one source region in the matrix region; S8. A source electrode is formed to connect the source region, and the source electrode is covered by the gate insulating layer; S9. A drain electrode is formed on the back side of the semiconductor substrate; Wherein, the thin gate oxide region of the gate electrode overlaps with a portion of the substrate region and the source region in the vertical direction; the thickness of the thin gate oxide region in the vertical direction is H1, and the maximum thickness of the thick gate oxide region in the vertical direction is H2, where H2 > H1.

10. The method for manufacturing a superjunction MOSFET structure according to claim 9, characterized in that, The ratio of the maximum thickness of the thick gate oxide region along the vertical direction to the thickness of the thin gate oxide region along the vertical direction satisfies: H2 / H1 = 6~9; Furthermore, the thick gate oxide region includes an intermediate region and transition regions located on both sides of the intermediate region at a horizontal level; The thickness of the intermediate region along the vertical direction is H2; From the intermediate region to the thin gate oxide region in the horizontal direction, the thickness of the transition region in the vertical direction gradually decreases from H2 to H1.

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