A network processor and chip

Abstract

This application relates to a network processor and chip, comprising: an instruction pipeline that receives and parses customer-defined instructions; reads a source data list and a command list from a storage module based on the instruction parsing information; and sends them to a finite state machine. In the finite state machine, a data buffer stores the source data and command execution results, a command buffer stores the command list, a state controller sequentially reads the target command from the command list, obtains the target source data from the data buffer based on the target command, generates a task request and sends it to the execution unit, receives the command result returned by the execution unit and writes it to the data buffer, and finally, after the command list is executed, generates a write-back data write-back storage module based on the data in the data buffer. This application enables customers to customize instructions according to their own needs during chip use and improves the utilization rate of the execution units in the instruction pipeline.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a network processor and chip. Background Technology

[0002] Currently, there are four main ways to define chip instructions:

[0003] The first type is where the instructions are entirely defined by the chip supplier;

[0004] The second type is where the IP vendor provides the instruction set determined by the IP vendor, and each customer uses the corresponding instruction set architecture according to their needs;

[0005] The third type is where public organizations determine the instruction set, and each IP vendor and customer chooses the instruction set they need based on their own requirements, such as the standard instruction set and extended instruction set of RISC-V.

[0006] The fourth type is where IP vendors or chip vendors provide custom instructions tailored to different application areas. Once the RT (Register-Transfer) is determined, the function of these custom instructions is fixed, and customers using the chip cannot further customize the instruction functions.

[0007] The functions of the instructions for the above four types of chips are already determined after they are manufactured into physical chips. However, these fixed standard instructions and custom instructions may still not meet the special scenarios or differentiated needs of customers using the chips. Since it is impossible to modify the instruction functions after the chips are manufactured, they cannot meet the further needs of customers. Summary of the Invention

[0008] The purpose of this application is to propose a network processor and chip that enables customers to customize custom instructions according to their own needs during chip use. In addition, the network processor improves computing performance, reduces instruction processing latency, and further increases the throughput of executed instructions.

[0009] To achieve the above objectives, according to a first aspect of this application, a network processor is provided, including an instruction pipeline, a storage module, and a finite state machine, wherein the finite state machine includes a data cache, a command cache, and a state controller;

[0010] The instruction pipeline is used to receive and parse custom instructions to obtain instruction parsing information, read the source data list and command list from the storage module according to the instruction parsing information, and send the instruction parsing information, source data list and command list to the finite state machine; the command list includes at least two commands, and the source data list includes the source data required to execute the at least two commands.

[0011] The data cache is used to store the source data list and the command results generated after executing each command in the command list;

[0012] The command cache is used to store the command list;

[0013] The state controller is used to read the target command to be executed from the command buffer, read the target source data from the data buffer according to the target command, generate a task request according to the target command and the target source data, send the task request to the target execution unit, receive the command result returned by the target execution unit after executing the task request, write the returned command result into the data buffer, and determine whether the command list has been executed. If so, it reads the write-back data from the data buffer according to the instruction parsing information and writes the write-back data into the storage module.

[0014] In some embodiments, the state controller includes a command counting unit, a command decoding unit, a state indication unit, and a state control unit;

[0015] The command counting unit is used to store a count value, which is the position index of the command being executed or about to be executed in the command list;

[0016] The status indication unit is used to store a status value, and the status value is used to instruct the status control unit to perform a corresponding operation.

[0017] The command decoding unit is used to decode the target command to obtain command decoding information;

[0018] The status control unit is used to set the status value according to the command execution status and perform corresponding operations according to the status value. The corresponding operations include: controlling the command buffer to output the command corresponding to the count value to the command decoding unit; reading the target source data from the data buffer according to the command decoding information; generating a task request according to the command decoding information and the target source data; sending the task request to the target execution unit; receiving the command result returned by the target execution unit after executing the task request; writing the returned command result into the data buffer; and determining whether the command list has been executed completely according to the count value. If yes, reading the write-back data from the data buffer according to the instruction parsing information and writing the write-back data into the storage module. If no, updating the count value to the current value plus one.

[0019] In some embodiments, the instruction parsing information includes a first index, a second index, a third index, a first quantity, and a second quantity; wherein, the storage module includes multiple storage units, the first index indicates the index of the storage unit in the storage module that stores the first source data in the source data list, the second index indicates the index of the storage unit in the storage module that stores the first command in the command list, the third index indicates the index of the storage unit in the storage module that stores the first data in the write-back data, the first quantity indicates the number of storage units in the storage module that store the write-back data, and the second quantity indicates the number of commands in the command list;

[0020] The instruction pipeline is used to read the source data list from the storage module according to the first index, and to read the command list from the storage module according to the second index and the second quantity;

[0021] The status controller is used to determine whether the command list has been executed completely based on the count value and the second quantity, read the write-back data from the data buffer based on the first quantity, and write the write-back data into the storage module based on the third index.

[0022] In some embodiments, the customer-defined instruction is one of a first custom instruction, a second custom instruction, and a third custom instruction;

[0023] The first custom instruction includes RS1 / RD field segment, RS2 field segment, RdNum field segment and CmdNum field segment. In the first custom instruction, RS1 / RD field segment is used to store the first index and the third index is equal to the first index, RS2 field segment is used to store the second index, RdNum field segment is used to store the first quantity and CmdNum field segment is used to store the second quantity.

[0024] The second custom instruction includes an RS1 domain segment, an RS2 / RD domain segment, an RdNum domain segment, and a CmdNum domain segment. In the first custom instruction, the RS1 domain segment is used to store the first index, the RS2 / RD domain segment is used to store the second index, and the third index is equal to the second index. The RdNum domain segment is used to store the first quantity, and the CmdNum domain segment is used to store the second quantity.

[0025] The third custom instruction includes RS1 field segment, RS2 field segment, RD field segment, RdNum field segment and CmdNum field segment. In the first custom instruction, RS1 field segment is used to store the first index, RS2 / RD field segment is used to store the second index, RD field segment is used to store the third index, RdNum field segment is used to store the first quantity, and CmdNum field segment is used to store the second quantity.

[0026] In some embodiments, the target source data includes first source data and second source data, and the command decoding information includes execution unit encoding, first source data index, second source data index, and command result index;

[0027] The data cache includes multiple storage units, the first source data index indicates the index of the storage unit in the data cache that stores the first source data, the second source data index indicates the index of the storage unit in the data cache that stores the second source data, and the command result index indicates the index of the storage unit in the data cache that stores the command result corresponding to the command.

[0028] The state controller is configured to read the target source data from the data cache according to the first source data index and the second source data index, generate the task request according to the execution unit code and the target source data, and write the returned command result into the data cache according to the command result index.

[0029] In some embodiments, the command is one of a first command, a second command, and a third command;

[0030] The first command includes an ExCode field, an SData1 / Dst field, and an SData2 field. In the first command, the ExCode field is used to store the execution unit code, the SData1 / Dst field is used to store the first source data index, and the command result index is equal to the first source data index. The SData2 field is used to store the second source data index.

[0031] The second command includes an ExCode field, an SData1 field, and an SData2 / Dst field. In the second command, the ExCode field is used to store the execution unit code, the SData1 field is used to store the first source data index, the SData2 / Dst field is used to store the second source data index, and the command result index is equal to the second source data index.

[0032] The third command includes the ExCode field, SData1 field, SData2 field, and Dst field. In the third command, the ExCode field is used to store the execution unit code, the SData1 field is used to store the first source data index, the SData2 field is used to store the second source data index, and the Dst field is used to store the command result index.

[0033] In some embodiments, the network processor includes an arbitration unit and a plurality of finite state machines, each finite state machine corresponding to a thread;

[0034] The customer-defined instruction carries a thread identifier, and the instruction pipeline is used to send the thread identifier, instruction parsing information, source data list, and command list to the arbitration unit.

[0035] The arbitration unit is used to send the instruction parsing information, source data list, and command list to the corresponding finite state machine according to the thread identifier.

[0036] In some embodiments, the system includes multiple execution units and multiple scheduling units, wherein each scheduling unit corresponds one-to-one with the multiple execution units, and the multiple execution units include multiple execution units inside the instruction pipeline and multiple FSM dedicated execution units outside the instruction pipeline.

[0037] The scheduling unit is used to schedule the task requests of at least one finite state machine when it receives a task request from at least one finite state machine, determine the task request to be processed, and send the task request to be processed to the corresponding execution unit.

[0038] The multiple execution units within the instruction pipeline are used to prioritize processing the task requests passed through the instruction pipeline; wherein, the task requests passed through the instruction pipeline have a higher priority than the task requests of the multiple finite state machines.

[0039] In some embodiments, the storage module includes a first storage component and a second storage component, each of which includes multiple storage cells for parallel reading or writing of data.

[0040] The storage module is used to prioritize the write-back requests transmitted through the instruction pipeline; wherein the write-back requests transmitted through the instruction pipeline have a higher priority than the write-back requests of the plurality of finite state machines.

[0041] According to a second aspect of this application, a chip is provided, including the network processor described in the first aspect of this application.

[0042] The network processor and chip proposed in this application have the following beneficial effects:

[0043] This application optimizes the design of the network processor and proposes a custom mechanism for complex instructions. The custom instructions include a command list, which contains multiple simple commands (micro-operations). Based on this network processor, when using the chip, customers only need to configure or change the content of the simple commands in the network processor's storage module to define complex instruction functions that meet specific needs. This makes the instruction functions no longer solely determined by the hardware design stage, but can be dynamically adjusted through software configuration, greatly improving the chip's flexibility and applicability.

[0044] In this embodiment, after the instruction pipeline parses the custom instruction and obtains the corresponding source data list and command list, it sends the instruction parsing information, source data list, and command list to the finite state machine of the corresponding thread. The execution process of the custom instruction is controlled by the thread-specific finite state machine. The execution unit in the instruction pipeline receives task requests from the instruction pipeline and the finite state machine through different data channels. This allows the execution unit to receive and process task requests from the finite state machine even when it does not receive a task request from the instruction pipeline. This helps reduce the idle time of the execution unit in the instruction pipeline, improves the utilization rate of the execution unit in the instruction pipeline, and enables the processor to execute more instructions in one cycle, thereby improving the processor's computing performance.

[0045] Other features and advantages of this application will be set forth in the following description. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings required in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the structure of a network processor in one embodiment of this application.

[0048] Figure 2 This is a schematic diagram of the structure of a finite state machine in one embodiment of this application.

[0049] Figure 3 This is a schematic diagram of the format of the first custom instruction in one embodiment of this application.

[0050] Figure 4 This is a schematic diagram of the format of the second custom instruction in one embodiment of this application.

[0051] Figure 5 This is a schematic diagram of the format of a third custom instruction in one embodiment of this application.

[0052] Figure 6 This is a schematic diagram of the format of the first command in one embodiment of this application.

[0053] Figure 7 This is a schematic diagram of the format of the second command in one embodiment of this application.

[0054] Figure 8 This is a schematic diagram of the format of the third command in one embodiment of this application.

[0055] Figure 9 This is a schematic diagram of the arbitration unit and multiple FSMs in one embodiment of this application.

[0056] Figure 10 This is a schematic diagram of the structure of multiple FSMs and FSM-specific execution units in one embodiment of this application.

[0057] Figure 11 This is a schematic diagram of the storage module in one embodiment of this application.

[0058] Marked in the image:

[0059] 1-Network processor;

[0060] 11 - Instruction pipeline, 111 - Instruction parsing module, 112 - Execution unit inside the instruction pipeline;

[0061] 12-Storage module, 121-First storage component, 122-Second storage component;

[0062] 13-Finite State Machine (FSM), 131-Data Buffer, 132-Command Buffer, 133-State Controller, 1331-Command Counting Unit, 1332-Command Decoding Unit, 1333-State Indication Unit, 1334-State Control Unit, 1335-Anomaly Detection Unit;

[0063] 14-FSM Dedicated Execution Unit;

[0064] 15-Arbitration Module;

[0065] 16-Scheduling Unit. Detailed Implementation

[0066] The detailed description of the accompanying drawings is intended to illustrate the present preferred embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be achieved by different embodiments intended to be included within the spirit and scope of this application.

[0067] Please see Figure 1 One embodiment of this application provides a network processor, including an instruction pipeline, a storage module, and a finite state machine (FSM), wherein the finite state machine includes a data cache, a command cache, and a state controller;

[0068] Specifically, the instruction pipeline is a core component of the network processor, used to receive, parse, and execute instructions, and write the execution results back to the storage module. In this embodiment, the storage module can be a register component. Unlike the storage module of a traditional network processor, the storage module in this embodiment stores not only the source data (operands) required to execute instructions, but also multiple simple commands (micro-operations) used to compose complex custom instructions. The content and storage location of these simple commands can be dynamically adjusted according to the user's needs, thereby defining complex instruction functions that meet specific requirements. The finite state machine is a sequential logic circuit that controls the system's operation flow through preset state transition rules. In this embodiment, the finite state machine is responsible for parsing and executing the command list of custom instructions (customer-defined complex instructions), ensuring that instructions are completed in sequence and efficiently. The finite state machine can only execute one custom instruction at a time.

[0069] The instruction pipeline is used to receive and parse customer-defined instructions to obtain instruction parsing information, read the source data list and command list from the storage module according to the instruction parsing information, and send the instruction parsing information, source data list and command list to the finite state machine; the command list includes at least two commands, and the source data list includes the source data required to execute the at least two commands.

[0070] Specifically, in the processor, the front-end device prefetches instructions from the instruction memory and then sends them to the instruction parsing module of the instruction pipeline for processing. For multi-threaded network processors, the instructions sent to the instruction pipeline include not only the instruction itself but also some additional information, such as a thread identifier, which indicates which thread will execute the instruction. The instruction parsing information includes the position indexes of the source data list and the command list in the storage module, as well as the position index of the write-back data to be written to the storage module after the execution of the customer-defined instruction. After receiving the source data list and command list returned by the storage module, the instruction pipeline sends the instruction parsing information, the source data list, and the command list to the finite state machine.

[0071] The data cache is used to store the source data list and the command results generated after executing each command in the command list;

[0072] The command cache is used to store the command list;

[0073] The state controller is used to read the target command to be executed from the command cache each time, read the target source data from the data cache according to the target command, generate a task request according to the target command and the target source data, send the task request to the target execution unit, receive the command result returned by the target execution unit after executing the task request, write the returned command result into the data cache, and determine whether the command list has been executed. If so, it reads the write-back data from the data cache according to the instruction parsing information and writes the write-back data into the storage module.

[0074] For example, suppose there is a custom instruction to calculate (A+B)*C. The source data list can contain three original values: A, B, and C. The command list can contain two commands: Command 1: Execute A+B, whose target source data is A and B; Command 2: Execute (the result of Command 1)*C, whose target source data is the intermediate result of Command 1 and C. The commands in the command list are executed sequentially.

[0075] The execution process of the custom instruction (A+B)*C is explained as follows:

[0076] (a1) When the FSM is in the first state, it is allowed to receive and process new custom commands, the source data list (A, B and C) is written to the data buffer, the command list (command 1 and command 2) is written to the command buffer, and the FSM is updated to the second state;

[0077] (a2) When FSM is in the second state, FSM first retrieves command 1 from the command buffer, retrieves source data A and B from the data buffer according to command 1, generates the corresponding task request, and requests the first execution unit (addition operation) to execute. FSM updates to the third state and waits for the confirmation of the first execution unit. At this time, the first execution unit may be busy and temporarily unable to respond.

[0078] (a3) The first execution unit returns an acknowledgment signal, the FSM is updated to the fourth state, and waits for the first execution unit to return the result of command 1;

[0079] (a4) The first execution unit returns the result of command 1, writes the result of command 2 back to the data buffer, and updates the FSM to the second state;

[0080] (a5) When the FSM is in the second state, the FSM determines whether the command list has been executed. If not, it continues to retrieve the next hop command, i.e., command 2, from the command buffer. Based on command 2, it retrieves the source data "result of command 1" and C from the data buffer, generates the corresponding task request, and requests the second execution unit (multiplication operation) to execute it. The FSM updates to the third state and waits for the confirmation of the second execution unit. At this time, the second execution unit may be busy and temporarily unable to respond.

[0081] (a6) The second execution unit returns an acknowledgment signal, the FSM is updated to the fourth state, and waits for the second execution unit to return the result of command 2;

[0082] (a7) The second execution unit returns the result of command 2, writes the result of command 2 back to the data buffer, and updates the FSM to the second state;

[0083] (a8) When the FSM is in the second state, the FSM determines whether the command list has been executed. If so, it obtains the write-back data based on the data in the data buffer. Finally, it writes the write-back data into the storage module based on the instruction parsing information, sets the data in the data buffer and command buffer to invalid, i.e., Valid signal = 0, and updates the FSM to the first state, ready to receive and process the next custom instruction.

[0084] As can be seen from the description of the above embodiments, this embodiment optimizes the design of the network processor of the chip processor and supports the processing of custom complex instructions. The custom instructions include a command list, which includes multiple simple commands (micro-operations). Based on this network processor, when using the chip, customers only need to configure or change the content of the simple commands in the storage module of the network processor to define complex instruction functions that meet specific needs. This makes the instruction functions no longer solely determined by the chip design stage, but can be dynamically adjusted through software-level configuration, greatly improving the flexibility and applicability of the chip.

[0085] In this embodiment, after the instruction pipeline parses the custom instruction and obtains the corresponding source data list and command list, it sends the instruction parsing information, source data list, and command list to the finite state machine of the corresponding thread. The execution process of the custom instruction is controlled by the thread-specific finite state machine. The execution unit (the smallest functional unit of execution, such as ALU, Mul, Max, Min, Test, DTCM, etc.) in the instruction pipeline receives task requests from the instruction pipeline and the finite state machine through different data channels. This allows the execution unit to receive and process task requests from the finite state machine even when it does not receive a task request from the instruction pipeline. This helps reduce the idle time of the execution unit in the instruction pipeline, improves the utilization rate of the execution unit in the instruction pipeline, and allows the processor to execute more instructions in one cycle, thereby improving the processor's computing performance.

[0086] In some embodiments, please refer to Figure 2 The status controller includes a command counting unit, a command decoding unit, a status indication unit, a status control unit, and an anomaly detection unit;

[0087] The command counting unit stores a count value, which represents the position index of the command being executed or about to be executed in the command list. Specifically, before the execution of the command list begins, the initial value of the count value is 0. For example, in the custom instruction (A+B)*C example listed above, when the FSM is in the first state, the count value is 0. The status indicator stores a status value, which indicates the corresponding operation performed by the status control unit. Specifically, the status value is, for example, the first, second, third, and fourth states in the custom instruction (A+B)*C example listed above. Of course, the status value of the FSM is not limited to the listed examples and can also include other states. For example, when the anomaly detection unit detects an anomaly event, the FSM is updated to the fifth state. The specific settings can be configured according to the execution process of the custom instruction.

[0088] The command decoding unit is used to decode the target command to obtain command decoding information. Specifically, the target command is a micro-operation, which differs from the chip's original non-custom instructions in that the result of the target command is written back to the data buffer in the FSM, while the result of the non-custom instructions is written back to the storage module of the network processing unit. The command decoding information includes the position index of the target source data in the data buffer and the position index of the command result written back to the data buffer.

[0089] The status control unit is used to set the status value according to the command execution status, and to perform corresponding operations according to the status value, the corresponding operations including:

[0090] (b1) Read the count value of the command counting unit and send the count value to the command buffer to control the command buffer to output the command corresponding to the count value to the command decoding unit;

[0091] (b2) The command decoding unit receives and parses the command output by the command buffer, obtains the command decoding information, and outputs it to the status control unit;

[0092] (b3) The status control unit reads the target source data from the data buffer according to the command decoding information, generates a task request according to the command decoding information and the target source data, sends the task request to the target execution unit, updates the status value of the status indicator unit (e.g., the third status), and waits for confirmation from the target execution unit;

[0093] (b4) Receive the confirmation signal returned by the target execution unit, update the status value of the status indicator unit (e.g., the fourth status) again, and wait for the target execution unit to return the command result;

[0094] (b5) Receive the command result returned by the target execution unit when executing the task request, write the returned command result into the data buffer, and update the status value (e.g., the second status) of the status indicator unit again.

[0095] (b6) Determine whether the command list has been executed completely based on the count value. If yes, read the write-back data from the data buffer according to the instruction parsing information, write the write-back data into the storage module, set the data in the data buffer and command buffer to invalid, i.e., Valid signal = 0, indicating that new data can be written to the data buffer and command buffer, and update the status value of the status indicator unit again (restore to the initial state, such as the first state); if no, update the count value to the current value plus one, and repeat the command execution process of (b1) to (b6) again.

[0096] The anomaly detection unit is used to detect abnormal events during command execution and report them to the status control unit so that the FSM can perform corresponding processing. For example, it can reset the FSM to the initial state to re-execute the instruction, or immediately stop the execution of the current instruction and enter the error handling state, or pass the abnormal information to the upper-layer software for processing. Specifically, the abnormal events are, for example, division by zero and invalid command. Division by zero means that if the divisor is zero when performing a division operation, a division by zero exception will be triggered. An invalid command means that when the FSM receives an unrecognized command, an invalid command exception will be triggered.

[0097] In some embodiments, the instruction parsing information includes a first index, a second index, a third index, a first quantity, and a second quantity; wherein, the storage module includes multiple storage units, the first index indicates the index of the storage unit in the storage module that stores the first source data in the source data list, the second index indicates the index of the storage unit in the storage module that stores the first command in the command list, the third index indicates the index of the storage unit in the storage module that stores the first data in the write-back data, the first quantity indicates the number of storage units in the storage module that store the write-back data (e.g., 0 represents one storage unit, 1 represents two storage units), and the second quantity indicates the number of commands in the command list (e.g., 0 represents one command, 1 represents two commands);

[0098] Specifically, the storage module includes a first storage component and a second storage component. The first storage component is used to store source data, and the second storage component is used to store commands (micro-operations). Both the first and second storage components include multiple storage units, and each storage unit has an index for reading and writing back data. One storage unit in the first storage component is used to store one or at least two source data, and one storage unit in the second storage component is used to store one or at least two commands (micro-operations).

[0099] The instruction pipeline is used to read the source data list from the storage module according to the first index, and to read the command list from the storage module according to the second index and the second quantity;

[0100] Specifically, the source data in the source data list is stored contiguously in the first storage component. The FSM executes only one custom instruction at a time. Therefore, when reading the source data list, it is only necessary to know the index of the starting storage unit (the first index). Then, based on the maximum storage capacity of the data cache in the FSM, the data range of the source data list to be read in the first storage component is determined. Then, the data output corresponding to the data range is read as the source data list. Simply put, assuming that the data cache can store n data, then n consecutive data are read starting from the first index as the source data list.

[0101] The commands in the command list are also stored contiguously in the second storage component. Therefore, when reading the command list, it is only necessary to know the index of the starting storage unit (second index) and the number of commands to be read (i.e., second quantity) to determine the data range of the command list to be read in the second storage component. Then, the data output corresponding to the data range is read as the command list.

[0102] The status controller is used to determine whether the command list has been executed completely based on the count value and the second quantity, read the write-back data from the data buffer based on the first quantity, and write the write-back data into the storage module based on the third index.

[0103] Specifically, the count value indicates the index of the currently executing / about-to-be-executed command in the command list. For example, a count value of 0 points to the first command at position 0 in the command list, a count value of 1 points to the second command at position 1, a count value of 2 points to the third command at position 2, and so on. The second quantity indicates the number of commands in the command list. For example, a second quantity of 0 indicates a command quantity of 1, a second quantity of 1 indicates a command quantity of 2, a second quantity of 2 indicates a command quantity of 3, and so on. Therefore, after receiving the command result returned by the execution unit and writing it to the data buffer, if the count value equals the second quantity, it is determined that the command list has been completed, and the data in the data buffer can be written back to the first storage component in the storage module.

[0104] After executing the command list, the write-back data is read from the data buffer according to the first quantity. For example, if the first quantity = 0, the data of the first storage unit (index 0) is read from the data buffer as write-back data; if the first quantity = 1, the data of the first storage unit (index 0) and the second storage unit (index 1) are read from the data buffer as write-back data; if the first quantity = 1, the data of the first storage unit (index 0), the second storage unit (index 1), and the third storage unit (index 2) are read from the data buffer as write-back data; and so on. When writing the write-back data to the storage module, the third index is used as the location index of the first storage unit in the storage module where the write-back data is stored, and the write-back data is written to the corresponding storage unit in the storage module.

[0105] In some embodiments, the customer-defined instruction is one of a first custom instruction, a second custom instruction, and a third custom instruction.

[0106] like Figure 3As shown, the first custom instruction includes RS1 / RD field segment, RS2 field segment, RdNum field segment and CmdNum field segment. In the first custom instruction, RS1 / RD field segment is used to store the first index, and the third index is equal to the first index. That is, the value in RS1 / RD field segment indicates both the first index and the third index, realizing the reuse of field segments and reducing the number of field segments. RS2 field segment is used to store the second index, RdNum field segment is used to store the first quantity, and CmdNum field segment is used to store the second quantity.

[0107] like Figure 4 As shown, the second custom instruction includes an RS1 field segment, an RS2 / RD field segment, an RdNum field segment, and a CmdNum field segment. In the first custom instruction, the RS1 field segment is used to store the first index, the RS2 / RD field segment is used to store the second index, and the third index is equal to the second index. That is, the value in the RS2 / RD field segment indicates both the second and third indices, realizing the reuse of field segments and reducing the number of field segments. The RdNum field segment is used to store the first quantity, and the CmdNum field segment is used to store the second quantity.

[0108] like Figure 5 As shown, the third custom instruction includes RS1 field segment, RS2 field segment, RD field segment, RdNum field segment and CmdNum field segment. In the first custom instruction, RS1 field segment is used to store the first index, RS2 / RD field segment is used to store the second index, RD field segment is used to store the third index, RdNum field segment is used to store the first quantity, and CmdNum field segment is used to store the second quantity.

[0109] In some embodiments, the target source data includes first source data and second source data, and the command decoding information includes execution unit encoding, first source data index, second source data index, and command result index; specifically, the execution unit encoding is the function code of the execution unit, and different execution units have different encodings. According to the execution unit encoding, it can be known what task needs to be performed, such as addition, multiplication, subtraction, etc.

[0110] The data cache includes multiple storage units, each of which has an index. The first source data index indicates the index of the storage unit in the data cache that stores the first source data, the second source data index indicates the index of the storage unit in the data cache that stores the second source data, and the command result index indicates the index of the storage unit in the data cache that stores the command result corresponding to the command.

[0111] The state controller is configured to read the target source data (first source data and second source data) from the data buffer according to the first source data index and the second source data index, generate the task request according to the execution unit code and the target source data, send the task request to the target execution unit, receive the command result returned by the target execution unit after executing the task request, and write the returned command result into the data buffer according to the command result index.

[0112] In some embodiments, the command is one of a first command, a second command, and a third command.

[0113] like Figure 6 As shown, the first command includes the ExCode field, the SData1 / Dst field, and the SData2 field. In the first command, the ExCode field is used to store the execution unit code, the SData1 / Dst field is used to store the first source data index, and the command result index is equal to the first source data index. That is, the value in the SData1 / Dst field simultaneously indicates the first source data index and the command result index, realizing the reuse of the field. The SData2 field is used to store the second source data index.

[0114] like Figure 7 As shown, the second command includes the ExCode field, the SData1 field, and the SData2 / Dst field. In the second command, the ExCode field is used to store the execution unit code, the SData1 field is used to store the first source data index, and the SData2 / Dst field is used to store the second source data index. The command result index is equal to the second source data index, that is, the value in the SData2 / Dst field simultaneously indicates the second source data index and the command result index, thus realizing the reuse of the field.

[0115] like Figure 8 As shown, the third command includes the ExCode field, SData1 field, SData2 field, and Dst field. In the third command, the ExCode field is used to store the execution unit code, the SData1 field is used to store the first source data index, the SData2 field is used to store the second source data index, and the Dst field is used to store the command result index.

[0116] In some embodiments, such as Figure 9 As shown, the network processor includes an arbitration unit and multiple finite state machines, each finite state machine corresponding to one thread;

[0117] The customer-defined instruction carries a thread identifier, and the instruction pipeline is used to send the thread identifier, instruction parsing information, source data list, and command list to the arbitration unit.

[0118] The arbitration unit is used to send the instruction parsing information, source data list, and command list to the corresponding finite state machine according to the thread identifier.

[0119] Specifically, in the network processor, multiple threads share hardware resources, such as execution units, and each also has its own dedicated hardware resources, such as the FSM and storage resources. The storage module allocates certain storage resources to each thread because different threads generally perform different tasks. Each thread has its own thread identifier to represent its identity. In addition to carrying the thread identifier, the client-defined instruction can also carry a custom instruction identifier (indicating the instruction is custom). The instruction pipeline parses the custom instruction using a custom instruction parsing method based on the client-defined instruction identifier, obtaining the thread identifier and instruction parsing information. Based on the relevant content in the instruction parsing information, it obtains the source data list and command list, and then packages the thread identifier, instruction parsing information, source data list, and command list together and sends them to the arbitration unit. The arbitration unit sends the corresponding data packet to the corresponding thread's FSM based on the thread identifier.

[0120] In some embodiments, such as Figure 10 As shown, the network processor includes multiple execution units and multiple scheduling units, with each scheduling unit corresponding to one of the multiple execution units. The multiple execution units include multiple execution units inside the instruction pipeline and multiple FSM dedicated execution units outside the instruction pipeline.

[0121] Specifically, the multiple execution units inside the instruction pipeline are, for example, ALU, MUL, DTCM, Max / Min / Test, etc. The characteristic of these execution units is that they do not block the execution of the instruction pipeline and do not require additional control processes. If these execution units encounter requests from the FSM and the instruction pipeline at the same time, the task requests passed by the instruction pipeline have an absolutely high priority to ensure that the instruction pipeline is not blocked.

[0122] The FSM dedicated execution unit is an execution unit dedicated to the Finite State Machine (FSM), such as Div / Rem, Float Unit, or Accelerator. These execution units are characterized by an uncertain number of execution cycles. If they are directly connected to the instruction pipeline and ordered execution is required, they will block the execution of the instruction pipeline. Therefore, they need to flow out of the instruction pipeline and enter the FSM control execution process.

[0123] The scheduling unit is used to schedule the task requests of at least one finite state machine when it receives a task request from at least one finite state machine, determine the task request to be processed, and send the task request to be processed to the corresponding execution unit.

[0124] Specifically, each execution unit can respond to task requests from multiple thread FSMs. Multiple thread FSMs may send task requests to an execution unit simultaneously. Therefore, it is necessary to schedule a task request from multiple task requests and then send it to the execution unit for processing. The scheduling algorithm can be based on round-robin scheduling, priority scheduling, or others.

[0125] The multiple execution units within the instruction pipeline are used to prioritize processing task requests passed through the instruction pipeline; wherein, the task requests passed through the instruction pipeline have a higher priority than the task requests of the multiple finite state machines.

[0126] Specifically, to ensure that the instruction pipeline is not blocked, the multiple execution units within the instruction pipeline will prioritize processing the task requests transmitted on the instruction pipeline. Only when they have no task requests from the instruction pipeline to process will they process the task requests submitted by the FSM. Therefore, it can be understood that the complex instruction functions customized by the customer in this embodiment are based on the original chip functions, and further utilize the idle execution units in the instruction pipeline to execute and implement them. This reduces the idle time of the execution units in the instruction pipeline, improves the utilization rate of the execution units in the instruction pipeline, and enables the processor to execute more instructions in one cycle, thereby improving the processor's computing performance.

[0127] In some embodiments, such as Figure 11 As shown, the storage module includes a first storage component and a second storage component. The first storage component includes n storage banks, and the second storage component includes m storage banks, which are used to implement parallel reading or writing of data.

[0128] Specifically, the multiple source data in the source data list are stored in different banks. When reading the source data list, data is read at the maximum capacity. Each bank in the first storage component can independently output the data of a storage unit. Then, the data output by these banks are reorganized in order from low bit to high bit to obtain the source data list.

[0129] It should be noted that traditional processors do not have a second storage component. The second storage component is proposed to implement customer-defined instructions and is used to store the command list of customer-defined instructions. A key to the implementation of customer-defined instructions is the order and content of the simple commands (micro-operations) in the command list, which determines the storage location of each simple command in the second storage component. These can be dynamically set by the customer at the software level. When reading the command list, each Bank in the second storage component can independently output a storage unit of data. Unlike reading the source data list, the command list is read according to the actual number of commands required, because each command needs to be executed, while reading the source data does not necessarily require it. Similarly, the command data output by each Bank also needs to be organized in order from low byte to high byte to obtain the command list.

[0130] The storage module is used to prioritize the write-back requests transmitted on the instruction pipeline; wherein, as mentioned above, the task requests transmitted on the instruction pipeline have an absolutely high priority to ensure that the instruction pipeline is not blocked. Therefore, the write-back requests transmitted on the instruction pipeline have a higher priority than the write-back requests of the multiple finite state machines.

[0131] Another embodiment of this application provides a chip including the network processor described in the above embodiments.

[0132] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many updates and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A network processor, characterized in that, It includes an instruction pipeline, a storage module, and a finite state machine, wherein the finite state machine includes a data buffer, an instruction buffer, and a state controller; The instruction pipeline is used to receive and parse customer-defined instructions to obtain instruction parsing information, read the source data list and command list from the storage module according to the instruction parsing information, and send the instruction parsing information, source data list and command list to the finite state machine; the command list includes at least two commands, and the source data list includes the source data required to execute the at least two commands. The data cache is used to store the source data list and the command results generated after executing each command in the command list; The command cache is used to store the command list; The state controller is used to read the target command to be executed from the command buffer, read the target source data from the data buffer according to the target command, generate a task request according to the target command and the target source data, send the task request to the target execution unit, receive the command result returned by the target execution unit after executing the task request, write the returned command result into the data buffer, and determine whether the command list has been executed. If so, it reads the write-back data from the data buffer according to the instruction parsing information and writes the write-back data into the storage module.

2. The network processor according to claim 1, characterized in that, The status controller includes a command counting unit, a command decoding unit, a status indication unit, and a status control unit; The command counting unit is used to store a count value, which is the position index of the command being executed or about to be executed in the command list; The status indication unit is used to store a status value, and the status value is used to instruct the status control unit to perform a corresponding operation. The command decoding unit is used to decode the target command to obtain command decoding information; The status control unit is used to set the status value according to the command execution status and perform corresponding operations according to the status value. The corresponding operations include: controlling the command buffer to output the command corresponding to the count value to the command decoding unit; reading the target source data from the data buffer according to the command decoding information; generating a task request according to the command decoding information and the target source data; sending the task request to the target execution unit; receiving the command result returned by the target execution unit after executing the task request; writing the returned command result into the data buffer; and determining whether the command list has been executed completely according to the count value. If yes, reading the write-back data from the data buffer according to the instruction parsing information and writing the write-back data into the storage module. If no, updating the count value to the current value plus one.

3. The network processor according to claim 2, characterized in that, The instruction parsing information includes a first index, a second index, a third index, a first quantity, and a second quantity; wherein, the storage module includes multiple storage units, the first index indicates the index of the storage unit in the storage module that stores the first source data in the source data list, the second index indicates the index of the storage unit in the storage module that stores the first command in the command list, the third index indicates the index of the storage unit in the storage module that stores the first data in the write-back data, the first quantity indicates the number of storage units in the storage module that store the write-back data, and the second quantity indicates the number of commands in the command list; The instruction pipeline is used to read the source data list from the storage module according to the first index, and to read the command list from the storage module according to the second index and the second quantity; The status controller is used to determine whether the command list has been executed completely based on the count value and the second quantity, read the write-back data from the data buffer based on the first quantity, and write the write-back data into the storage module based on the third index.

4. The network processor according to claim 3, characterized in that, The customer-defined instruction is one of the first custom instruction, the second custom instruction, and the third custom instruction; The first custom instruction includes RS1 / RD field segment, RS2 field segment, RdNum field segment and CmdNum field segment. In the first custom instruction, RS1 / RD field segment is used to store the first index and the third index is equal to the first index, RS2 field segment is used to store the second index, RdNum field segment is used to store the first quantity and CmdNum field segment is used to store the second quantity. The second custom instruction includes an RS1 domain segment, an RS2 / RD domain segment, an RdNum domain segment, and a CmdNum domain segment. In the first custom instruction, the RS1 domain segment is used to store the first index, the RS2 / RD domain segment is used to store the second index, and the third index is equal to the second index. The RdNum domain segment is used to store the first quantity, and the CmdNum domain segment is used to store the second quantity. The third custom instruction includes RS1 field segment, RS2 field segment, RD field segment, RdNum field segment and CmdNum field segment. In the first custom instruction, RS1 field segment is used to store the first index, RS2 / RD field segment is used to store the second index, RD field segment is used to store the third index, RdNum field segment is used to store the first quantity, and CmdNum field segment is used to store the second quantity.

5. The network processor according to claim 2, characterized in that, The target source data includes first source data and second source data, and the command decoding information includes execution unit encoding, first source data index, second source data index, and command result index; The data cache includes multiple storage units, the first source data index indicates the index of the storage unit in the data cache that stores the first source data, the second source data index indicates the index of the storage unit in the data cache that stores the second source data, and the command result index indicates the index of the storage unit in the data cache that stores the command result corresponding to the command. The state controller is configured to read the target source data from the data cache according to the first source data index and the second source data index, generate the task request according to the execution unit code and the target source data, and write the returned command result into the data cache according to the command result index.

6. The network processor according to claim 5, characterized in that, The command is one of the first command, the second command, and the third command; The first command includes an ExCode field, an SData1 / Dst field, and an SData2 field. In the first command, the ExCode field is used to store the execution unit code, the SData1 / Dst field is used to store the first source data index, and the command result index is equal to the first source data index. The SData2 field is used to store the second source data index. The second command includes an ExCode field, an SData1 field, and an SData2 / Dst field. In the second command, the ExCode field is used to store the execution unit code, the SData1 field is used to store the first source data index, the SData2 / Dst field is used to store the second source data index, and the command result index is equal to the second source data index. The third command includes the ExCode field, SData1 field, SData2 field, and Dst field. In the third command, the ExCode field is used to store the execution unit code, the SData1 field is used to store the first source data index, the SData2 field is used to store the second source data index, and the Dst field is used to store the command result index.

7. The network processor according to claim 1, characterized in that, The network processor includes an arbitration unit and multiple finite state machines, each finite state machine corresponding to one thread; The customer-defined instruction carries a thread identifier, and the instruction pipeline is used to send the thread identifier, instruction parsing information, source data list, and command list to the arbitration unit. The arbitration unit is used to send the instruction parsing information, source data list, and command list to the corresponding finite state machine according to the thread identifier.

8. The network processor according to claim 7, characterized in that, It includes multiple execution units and multiple scheduling units, with each scheduling unit corresponding to one of the multiple execution units. The multiple execution units include multiple execution units inside the instruction pipeline and multiple FSM dedicated execution units outside the instruction pipeline. The scheduling unit is used to schedule the task requests of at least one finite state machine when it receives a task request from at least one finite state machine, determine the task request to be processed, and send the task request to be processed to the corresponding execution unit. The multiple execution units within the instruction pipeline are used to prioritize processing the task requests passed through the instruction pipeline; wherein, the task requests passed through the instruction pipeline have a higher priority than the task requests of the multiple finite state machines.

9. The network processor according to any one of claims 1 to 8, characterized in that, The storage module includes a first storage component and a second storage component, each of which includes multiple storage cells for parallel reading or writing of data. The storage module is used to prioritize the write-back requests transmitted from the instruction pipeline; wherein the write-back requests transmitted from the instruction pipeline have a higher priority than the write-back requests of the plurality of finite state machines.

10. A chip, characterized in that, The network processor included in any one of claims 1 to 9.

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