Inter-chip interconnection unit proxy advance acknowledgement to cross-chip message communication

Abstract

The embodiment of the invention provides an advanced response of an inter-chip interconnection unit agent to cross-chip message communication, and relates to the field of integrated circuits. The inter-chip interconnection unit is coupled with the message bus and the inter-chip interconnection unit, and the inter-chip interconnection unit is coupled with the local chip and the far-end chip; the inter-chip interconnection unit proxy responds to the request message obtained from the message bus, generates a pseudo response message, and sends the pseudo response message to the message bus so as to send the pseudo response message to a sender of the request message, the pseudo response message replaces the receiver of the message to generate and send a response message of the sender of the message in response to the received request message; the inter-chip interconnection unit proxy responds to the request message obtained from the message bus and sends the request message to the inter-chip interconnection unit so as to send the request message to the far-end chip, the sender of the request message is located on the local chip and coupled to the message bus, and the receiver of the request message is located on the far-end chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular to early response of an inter-chip interconnect unit agent to cross-chip message communication. BACKGROUND

[0002] A system on chip (SoC) includes a plurality of components. For example, one or more CPU cores, memory interfaces, bus interfaces, etc. The prior art AMBA (Advanced Microcontroller Bus Architecture) bus architecture defines a plurality of buses, including AHB (Advanced High-Performance bus), ASB (Advanced System Bus), APB (Advanced Peripheral bus), AXI (Advanced eXtensible Interface), etc. The prior art SoC bus protocol also includes, for example, OCP (Open Core Protocol).

[0003] On AXI bus, a master accesses the address space provided by a slave through read transaction and write transaction. In a read transaction, the master issues a read address on a read address channel (for simplicity, the process is referred to as Read), and the slave responds with data corresponding to the address on a read data channel (the process is referred to as Read Response). In a write transaction, the master issues a write address on a write address channel and data to be written on a write data channel (the process is referred to as Write), and the slave responds with a response indicating the result of processing the Write on a write response channel (the process is referred to as Write Response). Thus, AXI bus is a bus based on Write / Write Response and Read / Read Response, and the communication model can be represented as <Write, Write Response> and <Read, Read Response> respectively. AXI write transaction is a bus transaction based on AXI protocol for writing data to a specified address, and Write response is a component of AXI write transaction, used to indicate the result of processing the AXI write transaction. The Write process of AXI write transaction carries a target address and data (denoted as AXI write<Addr, data>). AXI read transaction is a bus transaction based on AXI protocol for reading data from a specified address, and AXI Read response is a component of AXI read transaction, used to indicate the result of processing the AXI read transaction. The read process of AXI read transaction carries a target address (denoted as AXI read<Addr>). <addr>Each device connected to the AXI bus has its own bus address range.

[0004] Unlike the address-based access of the AXI bus, Chinese patents 202010461036.5 / 202010461038.4 / 201710213679.6 provide a messaging system for passing messages (also known as data packets) between multiple components within a chip. Figure 1 A schematic diagram of a messaging system is shown. Figure 1 As shown, the system-on-a-chip includes a messaging system 100 and one or more components coupled to the messaging system 100. The messaging system 100 provides point-to-point communication to the components coupled to the messaging system 100.<req,ack> Communication patterns. A request (req for short) refers to a message sent to or retrieved from the message bus, carrying the source ID, destination ID, and data (denoted as req).<source_ID,dest_ID,data> The message is a `req` message. `source_ID` refers to the source ID, the ID of the message sender. `dest_ID` refers to the destination ID, the ID of the message receiver. `ack` is the response message to `req`, indicating the processing result of the `req` message.

[0005] The system-on-a-chip (SoC) components include, for example, a CPU, an NVMe protocol processor, on-chip memory, and a message bus. On-chip memory includes, for example, DCCM (Data Close Coupled Memory). The CPU can be a CPU with different instruction set architectures such as ARM, MIPS, or ARC, and can have one or more CPU cores. The NVMe protocol processor is used to process the NVMe protocol. An example of an NVMe protocol processor is provided in Chinese patent application 201610505459.6. Other NVMe protocol processors available to those skilled in the art can also be applied to the message system. The SoC may also include other components. The SoC is also coupled to off-chip memory (DDR memory 124).

[0006] The messaging system 100 includes a message bus 108 and multiple proxies coupled to the message bus (CPU proxy, message proxy, cache proxy, and NVMe proxy; the proxies couple components of the messaging system to the message bus, enabling message communication between components through the proxies and the message bus). On-chip system components (CPU 102, CPU 104, NVMe protocol processor 152, etc.) are coupled to the messaging system through their respective proxies. Figure 1 In the illustrated message system, CPU agent 106, CPU agent 107, message agent 120, cache agent 109, and NVMe agent 151 are all instances of agents of the message system. CPU agent 106 is coupled to CPU 102, close-coupled memory 101, and message bus 108. CPU agent 107 is coupled to CPU 104, close-coupled memory 103, and message bus 108. NVMe subsystem 105 includes NVMe agent 151 and NVMe protocol handler 152. NVMe agent 151 is coupled to NVMe protocol handler 152 and message bus 108. DDR memory 124 is coupled to cache agent 109 through message bus 122. Cache agent 109 is coupled to message agent 108, message bus 122, and message bus 108. Message agent 120 is coupled to message bus 108 and cache agent 109.

[0007] In Figure 1 In the illustrated message system, messages sent by a sender are delivered to a receiver of the messages without the need to specify an address. Thus, multiple messages are sent to a receiver instantaneously without the need to assign addresses to the messages or to specify different addresses for the messages to avoid the overwriting of a preceding message by a following message. In a queue-based communication among chip components, it is advantageous to use a message system because enqueue and dequeue operations are always performed with respect to the tail and head of a queue without the need to concern the storage location of a queue entry in a memory, thus saving the overhead of maintaining a head pointer and a tail pointer needed in simulating a queue with a memory address space. In a producer-consumer model among chip components (e.g., component A generates a command and component B processes the command), it is also advantageous to use a message system. A message component sends its generated messages to a component as a consumer without the need to concern the respective storage locations of the messages. A message system includes a sender and a receiver of messages. The sender sends a message (referred to as request, req) that describes the identity of the sender and the identity of the receiver (e.g., sender ID, receiver ID, which is also referred to as target agent ID). The receiver receives the message and informs the sender of the result of the message reception (e.g., success or failure of the reception) (referred to as ack). In a message system, a request and an ack are used to represent a message communication process in the message system (the communication model is <request, ack>) and to distinguish from the communication process represented by Write / Write Response and Read / Read Response of an AXI bus.

[0008] The performance of an electronic device is limited by the performance of a chip, which is dependent on the number of transistors of the chip, and in turn is limited by the area of the chip / die. To further improve the performance, multiple chips are used in the electronic device to work cooperatively. To enable the cooperation and communication between the chips, chip-to-chip interconnect technology has been proposed. There are various standards and IP cores to provide high-speed interconnection between chips, such as chip-to-chip interconnect unit, FDI (Foveros Die Interconnect), INNOLINK, UCIe (Universal Chiplet Interconnect Express), etc. For example, Chinese patents 2023112407535 / 2023112408006 / 2023112408218 provide a technical solution based on chip-to-chip interconnect technology to enable two or more control components (chips) to work cooperatively to improve the IO processing capability of a storage device.

[0009] In the case where two chips are connected using the chip-to-chip interconnect technology, there are two message systems in the electronic device, and multiple components are coupled to each of the message systems. It is also desirable for the components belonging to the two message systems to communicate by messages. To this end, it is necessary to provide message-based communication capability between the different message systems belonging to different chips. SUMMARY

[0010] To solve the above technical problems or at least partially solve the above technical problems, embodiments of the present application provide a chip-to-chip interconnect unit agent, a chip, a data processing system, and a cross-chip communication method.

[0011] In a first aspect, embodiments of the present application provide a chip-to-chip interconnect unit agent, which is coupled to a message bus and coupled to a chip-to-chip interconnect unit, the chip-to-chip interconnect unit being configured to couple a local chip and a remote chip. The chip-to-chip interconnect unit agent is configured to, in response to obtaining a request message from the message bus, generate a pseudo response message and send the pseudo response message to the message bus to send the pseudo response message to a sender of the request message, wherein the pseudo response message replaces a response message generated by a receiver of the message in response to receiving the request message and sent to the sender of the message; and the chip-to-chip interconnect unit agent is configured to, in response to obtaining a request message from the message bus, send the request message to the chip-to-chip interconnect unit to send the request message to a remote chip, wherein the sender of the request message is located in a local chip and coupled to the message bus, the receiver of the request message is located in a remote chip, and the request message and the response message are messages defined by a transmission protocol of the message bus.

[0012] Optionally, the chip-to-chip interconnection unit agent does not process or discards the response message in response to obtaining the response message from the message bus.

[0013] Optionally, the chip-to-chip interconnection unit agent includes a pseudo response generation unit; the pseudo response generation unit generates a pseudo response message in response to the chip-to-chip interconnection unit agent obtaining a request message from the message bus, and sends the pseudo response message to the message bus to send the pseudo response message to a sender of the request message.

[0014] Optionally, the chip-to-chip interconnection unit agent further includes a forwarding decoder; the forwarding decoder is coupled with the message bus and the pseudo response generation unit respectively; the forwarding decoder sends the request message to the pseudo response generation unit in response to obtaining the request message from the message bus; and the forwarding decoder does not process or discards the response message in response to obtaining the response message from the message bus.

[0015] Optionally, the chip-to-chip interconnection unit agent further includes a message arbiter; the message arbiter is coupled with the pseudo response generation unit and the message bus respectively; the pseudo response generation unit sends the generated pseudo response message to the message arbiter; the message arbiter sends the pseudo response message to the message bus in response to receiving the pseudo response message to send the pseudo response message to the sender of the request message; and the message arbiter sends the request message to the message bus in response to receiving the request message.

[0016] Optionally, the chip-to-chip interconnection unit agent further includes a message receiving unit; the message receiving unit is coupled with the forwarding decoder and the message arbiter respectively; the forwarding decoder sends the response message to the message receiving unit in response to obtaining the response message from the message bus; the message receiving unit does not process or discards the response message in response to receiving the response message; and the message receiving unit sends the request message to the message arbiter in response to receiving the request message.

[0017] Optionally, the chip-to-chip interconnection unit agent further comprises a TX unit, a RX unit, a decoder and an arbiter; the decoder is coupled with the pseudo response generation unit and the TX unit; the pseudo response generation unit sends the request message to the decoder in response to receiving the request message; the decoder sends the request message to the TX unit in response to receiving the request message; the TX unit is coupled with the decoder and the chip-to-chip interconnection unit, and the TX unit sends the request message to the chip-to-chip interconnection unit in response to receiving the request message; the RX unit is coupled with the chip-to-chip interconnection unit and the arbiter, and the RX unit is configured to receive the request message sent by the chip-to-chip interconnection unit; the arbiter is coupled with the RX unit and the message receiving unit, and the arbiter sends the request message to the message receiving unit in response to obtaining the request message from the RX unit.

[0018] Optionally, the TX unit comprises at least one cache queue, and the at least one cache queue is coupled with the decoder; the decoder writes the request message into one of the at least one cache queue in response to receiving the request message; the pseudo response generation unit generates a first pseudo response message and sends the first pseudo response message to the message arbiter in response to the request message being successfully written into one of the at least one cache queue; and / or the pseudo response generation unit generates a second pseudo response message and sends the second pseudo response message to the message arbiter in response to the request message failing to be successfully written into one of the at least one cache queue, the second pseudo response message indicating the transmission of the request message to fail.

[0019] Optionally, the chip-to-chip interconnection unit agent further comprises a master device quota management unit; in response to the chip-to-chip interconnection unit agent being about to send a first message to the chip-to-chip interconnection unit, the master device quota management unit queries whether a quota managed by the master device quota management unit meets a preset condition; in response to the quota meeting the preset condition, the chip-to-chip interconnection unit agent sends the first message to the chip-to-chip interconnection unit to send the first message to a remote chip; wherein a sender of the first message is located in a local chip and coupled to the message bus, a receiver of the first message is a remote chip, and the quota is used to indicate an idle amount of resources in the remote chip for processing the first message.

[0020] Optionally, in response to the chip-to-chip interconnection unit agent determining to send the first message to the chip-to-chip interconnection unit, the master device quota management unit updates the quota managed by the master device quota management unit.

[0021] Optionally, the chip-to-chip interconnection unit agent further comprises a master device read transaction unit coupled with the chip-to-chip interconnection unit and the master device quota management unit; in response to the quota not satisfying the preset condition, the chip-to-chip interconnection unit agent temporarily does not send the first message to the chip-to-chip interconnection unit, and the master device quota management unit instructs the master device read transaction unit to generate a first bus read transaction; the master device read transaction unit generates the first bus read transaction and sends the first bus read transaction to the chip-to-chip interconnection unit, the first bus read transaction being used to read the free amount of resources in the remote chip for processing the first message; the master device read transaction unit, in response to receiving the first bus read response transaction sent by the chip-to-chip interconnection unit, sends the free amount of resources in the remote chip for processing the first message indicated by the first bus read response transaction to the master device quota management unit; the master device quota management unit, in response to receiving the free amount of resources in the remote chip for processing the first message, updates the quota managed thereby according to the free amount of resources in the remote chip for processing the first message, and determines whether the updated quota satisfies the preset condition.

[0022] Optionally, the chip-to-chip interconnection unit agent further comprises a slave device quota management unit and a slave device read transaction response unit.

[0023] The slave device read transaction response unit is coupled with the chip-to-chip interconnection unit and the slave device quota management unit, and in response to receiving a second bus read transaction from the chip-to-chip interconnection unit, instructs the slave device quota management unit to determine the free amount of resources in the local chip; the slave device quota management unit is coupled with the slave device read transaction response unit and is configured to determine the free amount of resources in the local chip for processing the second message and send the free amount of resources in the local chip for processing the second message to the slave device read transaction response unit; and the slave device read transaction response unit, according to the free amount of resources in the local chip for processing the second message sent by the slave device quota management unit, sends a second bus read response transaction to the chip-to-chip interconnection unit, the second bus read response transaction indicating the free amount of resources in the local chip for processing the second message.

[0024] Optionally, the first message is a request message or a response message, and the second message is a request message or a response message.

[0025] In a second aspect, the embodiments of the present application provide a chip, which comprises the chip-to-chip interconnection unit agent, the message bus and the chip-to-chip interconnection unit according to any of the embodiments of the present application.

[0026] In a third aspect, the embodiments of the present application provide a data processing system, comprising a first chip and a second chip;

[0027] The first chip comprises a first message bus, a first chip-to-chip interconnection unit agent, a first chip-to-chip interconnection unit, and at least one first component, the at least one first component being coupled with the first message bus, the first chip-to-chip interconnection unit agent being coupled with the first message bus and the first chip-to-chip interconnection unit respectively; the second chip comprises a second message bus, a second chip-to-chip interconnection unit agent, a second chip-to-chip interconnection unit, and at least one second component, the at least one second component being coupled with the second message bus, the second chip-to-chip interconnection unit agent being coupled with the second message bus and the second chip-to-chip interconnection unit respectively; the first chip-to-chip interconnection unit is coupled with the second chip-to-chip interconnection unit;

[0028] The first chip-to-chip interconnection unit agent generates a pseudo response message and sends the pseudo response message to the first message bus to send the pseudo response message to a sender of a request message in a case that the request message is obtained from the first message bus; and the second chip-to-chip interconnection unit agent generates a pseudo response message and sends the pseudo response message to the second message bus to send the pseudo response message to a sender of a request message in a case that the request message is obtained from the second message bus, wherein the pseudo response message replaces a response message generated by a receiver of the message in response to the request message and sent to the sender of the message, the request message and the response message being messages defined by a transmission protocol of a message bus.

[0029] Optionally, the first component sends a request message to the first message bus; the first chip-to-chip interconnection unit agent generates a pseudo response message and sends the pseudo response message to the first message bus to send the pseudo response message to a sender of a request message in response to obtaining the request message from the first message bus; and the first chip-to-chip interconnection unit agent sends the request message to the first chip-to-chip interconnection unit; the first chip-to-chip interconnection unit sends the request message to the second chip-to-chip interconnection unit in response to receiving the request message; the second chip-to-chip interconnection unit sends the request message to the second chip-to-chip interconnection unit agent in response to receiving the request message; the second chip-to-chip interconnection unit agent sends the request message to the second message bus in response to receiving the request message; and the second component obtains the request message from the second message bus.

[0030] Optionally, the second component generates a response message corresponding to the request message, and sends the response message to the second message bus; the second chip-to-chip interconnection unit agent does not process or discards the response message in response to obtaining the response message from the second message bus.

[0031] Optionally, the first chip-to-chip interconnection unit agent includes a first pseudo-response generation unit, and the second chip-to-chip interconnection unit agent includes a second pseudo-response generation unit; the first pseudo-response generation unit generates a pseudo-response message in response to the first chip-to-chip interconnection unit agent obtaining a request message from the first message bus, and sends the pseudo-response message to the first message bus to send the pseudo-response message to a sender of the request message.

[0032] Optionally, the first chip-to-chip interconnection unit agent further includes a first forwarding decoder, and the second chip-to-chip interconnection unit agent further includes a second forwarding decoder; the first forwarding decoder sends a request message to the first pseudo-response generation unit in response to obtaining the request message from the first message bus; and the second forwarding decoder does not process or discards a response message in response to obtaining the response message from the second message bus.

[0033] Optionally, the first chip-to-chip interconnection unit agent further includes a first message arbitrator, and the second chip-to-chip interconnection unit agent further includes a second message arbitrator; the first pseudo-response generation unit sends a generated pseudo-response message to the first message arbitrator; the first message arbitrator sends the pseudo-response message to the first message bus in response to receiving the pseudo-response message to send the pseudo-response message to a sender of the request message; and the second message arbitrator sends a request message to the second message bus in response to receiving the request message.

[0034] Optionally, the first chip-to-chip interconnection unit agent further includes a first message receiving unit, and the second chip-to-chip interconnection unit agent further includes a second message receiving unit; the second forwarding decoder sends a response message to the second message receiving unit in response to obtaining the response message from the second message bus; the second message receiving unit does not process or discards the response message in response to receiving the response message; and the second message receiving unit sends a request message to the second message arbitrator in response to receiving the request message.

[0035] Optionally, the first inter-chip interconnection unit agent further comprises a first TX unit, a first RX unit, a first decoder and a first arbiter, and the second inter-chip interconnection unit agent further comprises a second TX unit, a second RX unit, a second decoder and a second arbiter.

[0036] The first pseudo-response generating unit sends the request message to the first decoder in response to receiving the request message; the first decoder sends the request message to the first TX unit in response to receiving the request message; the first TX unit sends the request message to the first inter-chip interconnection unit in response to receiving the request message; the first inter-chip interconnection unit sends the request message to the second inter-chip interconnection unit in response to receiving the request message; the second RX unit receives the request message sent by the second inter-chip interconnection unit; and the second arbiter sends the request message to the second message receiving unit in response to obtaining the request message from the second RX unit.

[0037] Optionally, the first TX unit comprises at least one cache queue, and the at least one cache queue is coupled to the first decoder.

[0038] The first decoder writes the request message into one of the at least one cache queue in response to receiving the request message; the first pseudo-response generating unit generates a first pseudo-response message and sends the first pseudo-response message to the first message arbiter in response to the request message being successfully written into one of the at least one cache queue; the first message arbiter sends the first pseudo-response message to the first message bus; and / or the first pseudo-response generating unit generates a second pseudo-response message and sends the second pseudo-response message to the first message arbiter in response to the request message failing to be written into one of the at least one cache queue, the second pseudo-response message indicating that the request message fails to be transmitted to a sender of the request message; the first message arbiter sends the second pseudo-response message to the first message bus; and the first component sending the request message obtains the second pseudo-response message from the first message bus.

[0039] Optionally, the first component sending the request message confirms in advance that the communication corresponding to the request message is completed in response to obtaining the first pseudo-response message from the first message bus.

[0040] Optionally, the first component sending the request message obtains the second pseudo-response message from the first message bus, and confirms that the communication corresponding to the request message fails.

[0041] Optionally, the first chip-to-chip interconnection unit agent comprises a first master credit management unit; the second chip-to-chip interconnection unit agent comprises a second master credit management unit; a bandwidth occupied by the first component sending a message to the second component is controlled by a credit managed by the first master credit management unit, and a bandwidth occupied by the second component sending a message to the first component is controlled by a credit managed by the second master credit management unit.

[0042] Optionally, the first component in the first chip sends a first message to the first message bus; the first chip-to-chip interconnection unit obtains the first message from the first message bus; in response to the first chip-to-chip interconnection unit agent being about to send the first message to the first chip-to-chip interconnection unit, the first master credit management unit queries whether a credit managed by the first master credit management unit meets a preset condition; in response to the credit meeting the preset condition, the first chip-to-chip interconnection unit agent sends the first message to the first chip-to-chip interconnection unit; the first chip-to-chip interconnection unit sends the first message to the second chip-to-chip interconnection unit; the second chip-to-chip interconnection unit sends the first message to the second chip-to-chip interconnection unit agent in response to receiving the first message; the second chip-to-chip interconnection unit agent sends the first message to the second message bus in response to receiving the first message; and the second component obtains the first message from the second message bus.

[0043] Optionally, the first master credit management unit updates the credit managed by the first master credit management unit in response to the first chip-to-chip interconnection unit agent determining to send the first message to the first chip-to-chip interconnection unit.

[0044] Optionally, the first chip-to-chip interconnection unit agent further comprises a first master read transaction unit, and the second chip-to-chip interconnection unit agent further comprises a second master read transaction unit; in response to the credit managed by the first master credit management unit not satisfying the preset condition, the first chip-to-chip interconnection unit agent temporarily does not send the first message to the first chip-to-chip interconnection unit, and the first master credit management unit instructs the first master read transaction unit to generate a first bus read transaction; the master read transaction unit generates a first bus read transaction and sends the first bus read transaction to the first chip-to-chip interconnection unit, and the first bus read transaction is used to determine the free amount of resources in the second chip for processing the first message; the first chip-to-chip interconnection unit sends data carrying the first bus read transaction to the second chip-to-chip interconnection unit; the second chip-to-chip interconnection unit generates the second bus read transaction according to the data carrying the first bus read transaction and sends the second bus read transaction to the second chip-to-chip interconnection unit agent; the second chip-to-chip interconnection unit agent determines the free amount of resources in the second chip for processing the first message, and sends a second bus read response transaction to the second chip-to-chip interconnection unit according to the free amount of resources in the second chip for processing the first message; the second chip-to-chip interconnection unit sends data carrying the second bus read response transaction to the first chip-to-chip interconnection unit; the first chip-to-chip interconnection unit generates a first bus read response transaction according to the data carrying the second bus read response transaction and sends the first bus read response transaction to the first master read transaction unit; the first master read transaction unit sends the free amount of resources in the second chip for processing the first message indicated by the first bus read response transaction to the first master credit management unit in response to receiving the first bus read response transaction sent by the first chip-to-chip interconnection unit; and the first master credit management unit updates the credit managed thereby according to the free amount of resources in the second chip for processing the first message in response to receiving the free amount of resources in the second chip for processing the first message, and determines whether the updated credit satisfies the preset condition.

[0045] Optionally, the first chip-to-chip interconnection unit agent further comprises a first slave credit management unit and a first slave read transaction response unit; and the second chip-to-chip interconnection unit agent further comprises a second slave credit management unit and a second slave read transaction response unit.

[0046] The second slave device read transaction response unit, in response to receiving the second bus read transaction sent by the second inter-chip interconnection unit, instructs the second slave device credit management unit to determine the free amount of resources in the second chip for processing the first message; the second slave device credit management unit sends the determined free amount of resources in the second chip for processing the first message to the second slave device read transaction response unit; and the second slave device read transaction response unit sends a second bus read response transaction to the second inter-chip interconnection unit according to the free amount of resources in the second chip for processing the first message.

[0047] Optionally, the first message is a request message or a response message, and the second message is a request message or a response message.

[0048] In a fourth aspect, an embodiment of the present application provides a cross-chip communication method applied to a first chip and a second chip. The first chip includes a first message bus, a first inter-chip interconnection unit agent, a first inter-chip interconnection unit, and at least one first component. The at least one first component is coupled with the first message bus. The first inter-chip interconnection unit agent is coupled with the first message bus and the first inter-chip interconnection unit, respectively. The second chip includes a second message bus, a second inter-chip interconnection unit agent, a second inter-chip interconnection unit, and at least one second component. The at least one second component is coupled with the second message bus. The second inter-chip interconnection unit agent is coupled with the second message bus and the second inter-chip interconnection unit, respectively. The first inter-chip interconnection unit is coupled with the second inter-chip interconnection unit.

[0049] The method includes that the first component sends a request message to the first message bus; the first inter-chip interconnection unit agent, in response to obtaining the request message from the first message bus, generates a pseudo response message, sends the pseudo response message to the first message bus, and sends the pseudo response message to the sender of the request message; and the first inter-chip interconnection unit agent sends the request message to the first inter-chip interconnection unit; the first inter-chip interconnection unit, in response to receiving the request message, sends the request message to the second inter-chip interconnection unit; the second inter-chip interconnection unit, in response to receiving the request message, sends the request message to the second inter-chip interconnection unit agent; the second inter-chip interconnection unit agent, in response to receiving the request message, sends the request message to the second message bus; and the second component obtains the request message from the second message bus.

[0050] The chip interconnection unit agent provided by the embodiment of the present application generates a pseudo response message to replace the ack message provided by the receiver after the sender sends the req message and before the receiver feeds back the ack message, and provides the pseudo response message to the component that sends the req message. The pseudo response message has the same form as the ack message, so that the sender thinks that it has received the ack message. Therefore, the component that sends the req message can confirm the completion of the communication in advance after receiving the pseudo response message, so as to shorten the waiting time of the sender. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description only represent some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0052] Figure 1 A schematic diagram of a message system applied to a system on chip in the prior art is shown;

[0053] Figure 2A A structural schematic diagram of a message system provided by the embodiment of the present application is shown;

[0054] Figure 2B A structural schematic diagram of an electronic device applying the message system of the embodiment of the present application is shown;

[0055] Figure 3A A structural schematic diagram of a chip interconnection unit agent provided by an embodiment of the present application is shown;

[0056] Figure 3B A structural schematic diagram of an electronic device applying the chip interconnection unit agent of the embodiment of the present application is shown;

[0057] Figure 4A A flowchart of the electronic device processing the req message provided by the embodiment of the present application is shown;

[0058] Figure 4B A flowchart of the electronic device processing the ack message provided by the embodiment of the present application is shown;

[0059] Figure 5A A structural schematic diagram of a chip interconnection unit agent provided by another embodiment of the present application is shown;

[0060] Figure 5B A structural schematic diagram of an electronic device applying the chip interconnection unit agent of the embodiment of the present application is shown;

[0061] Figure 6 Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent;

[0062] Figure 7 Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent;

[0063] Figure 8A Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent;

[0064] Figure 8B and Figure 8C Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent;

[0065] Figure 9 Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent;

[0066] Figure 10A and Figure 10B Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent;

[0067] Figure 10C Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent;

[0068] Figure 11 Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent. DETAILED DESCRIPTION

[0069] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0070] Figure 2A Fig. 1 shows a flowchart of a process of a local chip interconnect unit agent;

[0071] As Figure 2A As shown, the system on chip includes a message system, one or more components coupled to the message system, and an inter-chip interconnect unit. The components of the system on chip include, for example, a CPU, an NVMe protocol processor, a media interface controller (NFI), etc. The message system includes a message bus, a plurality of agents coupled to the message bus, and an inter-chip interconnect unit agent. The plurality of agents coupled to the message bus include, for example, a CPU agent, an NVMe protocol processor agent (NVMe agent for short), a media interface controller agent (NFI agent for short), etc. Each component is coupled to the message bus through a corresponding agent. The inter-chip interconnect unit implements cross-chip communication through an inter-chip interconnect technology (for example, the inter-chip interconnect link provided by Chinese patent 2023112407535 / 2023112408006 / 2023112408218). The inter-chip interconnect unit is coupled to the message bus through the inter-chip interconnect unit agent.

[0072] The inter-chip interconnect unit agent couples the inter-chip interconnect unit to the message system, so that the inter-chip interconnect unit has the ability to communicate messages with the components locally coupled to the message bus through the message bus (message communication refers to communication based on the <req, ack> mode). Further, the inter-chip interconnect unit sends messages sent by the components locally coupled to the message bus to remote chip components, so that the components belonging to two message systems can communicate through messages. For example, the CPU locally coupled to the message bus sends a message to the local message bus, the local inter-chip interconnect unit agent obtains the message and sends the message to the local inter-chip interconnect unit, the local inter-chip interconnect unit sends the message to the inter-chip interconnect unit of another chip at a remote end, the inter-chip interconnect unit of the other chip sends the message to the message bus of the other chip, and then to the components of the other chip coupled to the message bus of the other chip.

[0073] Figure 2B A structural schematic diagram of an electronic device applying the system on chip of the embodiment of the present application is shown. As shown in the figure, Figure 2B The electronic device includes a system on chip 1 (chip 1) and a system on chip 2 (chip 2).

[0074] The chip 1 includes a message system 1, a plurality of components coupled to the message system 1, and an inter-chip interconnect unit 1. The components coupled to the message system 1 in the chip 1 include a CPU 1, an NVMe protocol processor 1 (NVMe_1 for short), and a media interface controller 1 (NFI_1 for short). The message system 1 includes a message bus 1 and a plurality of agents coupled to the message bus 1, and the agents communicate with each other through the message bus 1. The agents coupled to the message bus 1 in the chip 1 include a CPU agent 1, an NVMe agent 1, an NFI agent 1, and an inter-chip interconnect unit agent 1. The inter-chip interconnect unit 1 is coupled to the message bus 1 through the inter-chip interconnect unit agent 1.

[0075] Chip 2 includes a message system 2, a plurality of components coupled to the message system 2, and an inter-chip interconnect unit 2. The components in chip 2 coupled to the message system include: a CPU 2, an NVMe protocol processor 2 (abbreviated as NVMe_2), a media interface controller 1 (abbreviated as NFI_2). The message system 2 includes a message bus 2 and a plurality of agents coupled to the message bus 2. The agents in chip 2 coupled to the message bus 2 include: a CPU agent 2, an NVMe agent 2, an NFI agent 2, and an inter-chip interconnect unit agent 2, each of which communicates with each other through the message bus 2. The inter-chip interconnect unit 2 is coupled to the message bus 2 through the inter-chip interconnect unit agent 2.

[0076] Chip 1 and chip 2 are connected to each other through respective inter-chip interconnect units (e.g., inter-chip interconnect unit 1 and inter-chip interconnect unit 2), to implement inter-chip communication between chip 1 and chip 2. The components in chip 1 coupled to the message bus and the components in chip 2 coupled to the message bus implement message communication through inter-chip interconnect unit agents (e.g., inter-chip interconnect unit agent 1 and inter-chip interconnect unit agent 2).

[0077] The process of message communication between cross-chip components is described by taking an example of CPU 1 in chip 1 sending a message (req) to NVMe_2 in chip 2, and NVMe_2 feeding back a response (ack) to CPU 1. In this example, chip 1 is a local chip and chip 2 is a remote chip from the perspective of chip 1.

[0078] CPU 1 in chip 1 sends message 1 (message 1 is a req message, and message 1 carries the identity of CPU 1 and the identity of NVMe_2) to message bus 1 through CPU 1 agent. Inter-chip interconnect unit agent 1 obtains message 1 from message bus 1 and sends it to inter-chip interconnect unit 1. Inter-chip interconnect unit 1 sends message 1 to inter-chip interconnect unit 2. Inter-chip interconnect unit 2 sends message 1 to message bus 2 of message system 2 through inter-chip interconnect unit agent 2. NVMe agent 2 obtains message 1 from message bus 2 and sends it to NVMe_2.

[0079] NVMe_2 generates message 2 (message 2 is an ack message for message 1) in response to receiving message 1, and sends message 2 to message bus 2. Inter-chip interconnect unit agent 2 obtains message 2 from message bus 2 and sends it to inter-chip interconnect unit 2. Inter-chip interconnect unit 2 sends message 2 to inter-chip interconnect unit 1. Inter-chip interconnect unit 1 sends message 2 to message bus 1 through inter-chip interconnect unit agent 1. CPU agent 1 obtains message 2 from message bus 1 and sends it to CPU 1. Based on receiving the ack message, CPU 1 knows that the message 1 (req message) it sent before has been successfully received (by NVMe_2).

[0080] In the above embodiments, the operations performed by the inter-chip interconnect unit agent 1 include: since the recipient of message 1, NVMe_2, is located on a remote chip, message 1 is obtained from message bus 1 and sent to inter-chip interconnect unit 1; message 2 sent by chip 2 is obtained from inter-chip interconnect unit 1 and sent to message bus 1. The operations performed by the inter-chip interconnect agent 2 include: obtaining message 1 from inter-chip interconnect unit 2 and sending it to message bus 2; since the recipient of message 2, CPU1, is located on chip 1, message 2 is obtained from message bus 2 and sent to inter-chip interconnect unit 2.

[0081] When component 1 in chip 1 sends a message (e.g., a req message or an ack message) to component 2 in chip 2, the path through which the message flows is: component 1 in chip 1, message bus of chip 1, inter-chip interconnection unit agent 1, inter-chip communication link, inter-chip interconnection unit agent 2, message bus of chip 2, component 2 in chip 2.

[0082] exist Figure 2B In the illustrated embodiment, the communication bus between the components located in chip 1 and chip 2 respectively involves three types:

[0083] (1) Message Bus. Components in chip 1 coupled to message bus 1 communicate with each other via message bus 1. Components in chip 2 coupled to message bus 2 communicate with each other via message bus 2. Messages carry a sender identifier (denoted as source_ID) and a receiver identifier (denoted as dest_ID).

[0084] (2) AXI Bus. Inter-chip interconnect units act as AXI bus devices, and the AXI bus (…) Figure 2B (Not shown) Communication. Inter-chip interconnect unit 1 communicates with inter-chip interconnect unit agent 1 via an AXI bus. Inter-chip interconnect unit 2 communicates with inter-chip interconnect unit agent 2 via an AXI bus. It is understood that other devices can be coupled to the AXI bus, and these devices can communicate with the inter-chip interconnect units and inter-chip interconnect unit agents via the AXI bus. As an example, inter-chip interconnect unit 2 represents the AXI bus device of chip 2. Access sent from the AXI bus device of chip 1 to the AXI bus device of chip 2 is forwarded by the AXI bus to inter-chip interconnect unit 1 for processing (inter-chip interconnect unit 1 then forwards it to inter-chip interconnect unit 2). Inter-chip interconnect unit 1 also acts as a bus bridge, providing bridging between the AXI bus and the inter-chip communication link. Inter-chip interconnect unit 1 has an address space specified on the AXI bus, and the address spaces of the various AXI buses in chip 2 are allocated or mapped in the specified address space of inter-chip interconnect unit 1.

[0085] The chip interconnect unit agent 1 sends an AXI bus transaction to the chip interconnect unit 1 to carry the message passed in the message bus to the chip interconnect unit 1. The chip interconnect unit agent 1 converts or maps between the sender identifier or receiver identifier of the message bus and the AXI bus address. And in response to receiving the message of the message bus, the chip interconnect unit agent 1 acquires the corresponding AXI bus address according to, for example, the receiver identifier in the message, and sends an AXI bus transaction, and based on the AXI bus address, the chip interconnect unit 1 will process and respond to the AXI bus transaction. Since the AXI bus address of the AXI bus transaction corresponds to the AXI device of the chip 2, the chip interconnect unit 1 also sends the AXI bus transaction to the chip 2 via the chip intercommunication link, and the chip interconnect unit 1 also sends the response of the AXI bus transaction to the chip interconnect unit agent 1. It should be noted that the response of the AXI bus transaction represents the completion of the AXI bus transaction issued by the chip interconnect unit agent 1 according to the message of the message bus (req), and does not represent the ack message given to the req message of the message bus. The ack message given to the request message of the message bus is carried by another AXI bus transaction.

[0086] (3) Chip intercommunication link. The chip interconnect unit 1 and the chip interconnect unit 2 communicate via the chip intercommunication link, and the AXI bus transaction is carried on the chip intercommunication link.

[0087] The chip interconnect unit 2 provides a function equivalent to the chip interconnect unit 1.

[0088] Figure 3A A structural schematic diagram of the chip interconnect unit agent provided by the embodiment of the application is shown. Figure 3B A structural schematic diagram of an electronic device applying the chip interconnect unit agent of the embodiment of the application is shown. Figure 3B The electronic device shown includes a chip 1 and a chip 2. The chip 1 and the chip 2 both include Figure 3A a chip interconnect unit agent. For ease of description, in Figure 3B , components and functional modules in the chip 1 are identified with the suffix "1", and components and functional modules in the chip 2 are identified with the suffix "2".

[0089] As shown in Figure 3A , the chip interconnect unit agent includes an arbiter, a decoder, a TX unit and an RX unit. The TX unit is coupled to the decoder, the RX unit is coupled to the arbiter, and the decoder and the arbiter are respectively coupled to the message bus.

[0090] As shown in Figure 3A As shown, the TX unit includes a plurality of cache queues, a queue scheduling unit and an AXI master interface. The cache queues are used to cache messages (e.g. req messages or ack messages) sent by various components coupled to the local message system. Optionally, the cache queues correspond to the components coupled to the local message system one-to-one. As shown, Figure 3B As shown, the components in chip 1 coupled to message system 1 include CPU 1, NVMe_1, NFI_1, and the TX unit in chip 1 includes 3 cache queues, queue 1, queue 2, queue 3. Queue 1 corresponds to CPU 1 and caches messages sent by CPU 1. Queue 2 corresponds to NVMe_1 and caches messages sent by NVMe_1. Queue 3 corresponds to NFI_1 and caches messages sent by NFI_1. The components in chip 2 coupled to message system 2 include CPU 2, NVMe_2, NFI_2, and the TX unit in chip 2 includes 3 cache queues, queue 7, queue 8, queue 9. Queue 7 corresponds to CPU 2 and caches messages sent by CPU 2. Queue 8 corresponds to NVMe_2 and caches messages sent by NVMe_2. Queue 9 corresponds to NFI_2 and caches messages sent by NFI_2.

[0091] As shown, Figure 3A The queue scheduling unit is coupled to the plurality of cache queues in the TX unit and obtains messages from the cache queues to provide to the AXI master interface. The messages cached by the cache queues include an identification of the message sender (e.g. ID of the message sender, source_ID) and an identification of the message receiver (e.g. ID of the message receiver, dest_ID). The queue scheduling unit determines an AXI bus address (addr) according to the dest_ID in the message and generates data conforming to the AXI bus format based on the source_ID, dest_ID and the message content (data) in the message. In an optional embodiment, a mapping relationship between the address space on the AXI bus and all components in the chip coupled to the message bus is pre-established or configurable. For example Figure 3B As shown, a mapping relationship between the address space on the AXI bus and all components in chip 1 and chip 2 coupled to the message bus is pre-established, e.g. each component is mapped to one of the addresses in the bus address space, or several bus addresses are mapped to the same component.

[0092] As shown, Figure 3A The AXI master interface is connected to the local chip-to-chip interconnection unit through the AXI bus and generates an AXI write transaction (AXI write<addr, data>) according to the message to be transmitted. The address addr accessed by the AXI write transaction is mapped according to the dest_ID in the message.

[0093] As shown, Figure 3A As shown, the decoder couples the TX unit to the message bus. In response to receiving a message from the message bus, the decoder writes the message into the buffer queue in the TX unit corresponding to the sender identifier (e.g., source_ID) indicated by the message. For example... Figure 3B As shown, if CPU1 in chip 1 sends a message to message bus 1, decoder 1 in inter-chip interconnection unit agent 1 obtains the message from message bus 1 and adds the message to queue 1 in TX unit. Optionally, the decoder identifies that the message should be processed by itself based on the receiver identifier (dest_ID) indicated by the message, which represents a component located on a remote chip.

[0094] like Figure 3A As shown, the RX unit includes multiple buffer queues, a data scheduling unit, and an AXI slave interface. The buffer queues in the RX unit are used to buffer messages (e.g., req or ack messages) from remote chips. Optionally, the buffer queues in the RX unit correspond one-to-one with the components of the remote chip coupled to the messaging system. For example... Figure 3B As shown, the message system components coupled to chip 2 include CPU2, NVMe_2, and NFI_2. Chip 1's RX unit includes three cache queues: queue 4, queue 5, and queue 6. Queue 4 corresponds to CPU2 in chip 2, caching messages sent by CPU2. Queue 5 corresponds to NVMe_2 in chip 2, caching messages sent by NVMe_2. Queue 6 corresponds to NFI_2 in chip 2, caching messages sent by NFI_2. Chip 1 also includes the message system components coupled to CPU1, NVMe_1, and NFI_1. Chip 2's RX unit includes three cache queues: queue 10, queue 11, and queue 12. Queue 10 corresponds to CPU1 in chip 1, caching messages sent by CPU1. Queue 11 corresponds to NVMe_1 in chip 1, caching messages sent by NVMe_1. Queue 12 corresponds to NFI_1 in chip 1, caching messages sent by NFI_1.

[0095] like Figure 3A As shown, the AXI slave interface connects to the local inter-chip interconnect unit via the AXI bus, receives data carried by AXI write transactions, and sends it to the data scheduling unit. This AXI write transaction originates from the local inter-chip interconnect unit.

[0096] like Figure 3A As shown, the data scheduling unit is coupled with the AXI slave interface, generates a message (e.g., a req message or an ack message) in a specified format according to the data carried by the AXI write transaction, and adds the generated message in the specified format to a corresponding cache queue according to the sender identifier carried in the generated message. If the message sent by the remote chip is a req message, the data scheduling unit generates a req message according to the data carried by the AXI write transaction; if the message sent by the remote chip is an ack message, the data scheduling unit generates an ack message according to the data carried by the AXI write transaction. For example Figure 3B As shown, if CPU1 in chip 1 sends a message to CPU2 in chip 2, the message sent by CPU1 carries the identifier of CPU1 and the identifier of CPU2. The AXI write transaction carries the identifier of CPU1, the AXI slave interface 2 receives the AXI write transaction, and the data scheduling unit 2 in chip 2 receives the data carried by the AXI write transaction from the AXI slave interface 2 (the data includes the identifier of CPU1). The data scheduling unit 2 in chip 2 generates a message in a specified format according to the data carried by the AXI write transaction, and sends the message to the queue 10 corresponding to CPU1.

[0097] As shown in Figure 3A The arbiter is coupled with the cache queues in the RX unit. The arbiter is used to obtain access right of the message bus, and select to send the message cached in the selected cache queue to the message bus.

[0098] For ease of understanding, with reference to Figure 3A and Figure 3B , a req message is sent from CPU1 in chip 1 to NVMe_2 in chip 2, and an ack message is fed back from NVMe_2 to CPU1, as an example to illustrate the operations implemented by the inter-chip interconnection unit proxy 1 and the inter-chip interconnection unit proxy 2 in the communication process. Among them, from the perspective of chip 1, chip 1 is a local chip, and chip 2 is a remote chip.

[0099] Figure 4A A processing flow diagram of the req message is shown. Figure 4B A processing flow diagram of the ack message is shown.

[0100] As shown in Figure 4A The processing flow of the req message sent by CPU1 to NVMe_2 includes:

[0101] CPU1 in chip 1 sends a req message to message bus 1 through CPU1 proxy (indicated by (1.1) in Figure 4A ).

[0102] Decoder 1, based on the fact that the recipient of the request message is NVMe_2 located in chip 2, identifies from message bus 1 that the request message needs to be processed by itself, obtains the request message, and sends the request message to the cache queue corresponding to CPU1 in the TX unit (e.g., Figure 3A , Figure 4A Middle queue 1)( Figure 4A (As indicated by (1.2)).

[0103] Queue scheduling unit 1 retrieves the `req` message from queue 1, generates data conforming to the AXI bus format (denoted as `data 1`), and provides the generated `data 1` to AXI master interface 1. Figure 4A (As indicated by (1.3)).

[0104] AXI master interface 1 sends an AXI write transaction, which sends data 1 received from queue scheduling unit 1 to inter-chip interconnect unit 1. Figure 4A (Instructions from (1.4)).

[0105] Inter-chip interconnect unit 1 sends data representing an AXI write transaction (denoted as data 2) to inter-chip interconnect unit 2 via the inter-chip interconnect link. Figure 4A (Instructions from (1.5)).

[0106] In response to sending data 2 to Interconnect Unit 2, Interconnect Unit 1 sends an AXI write response transaction to AXI Master Interface 1. Figure 4A (1.6) indicates that the AXI master interface 1 has been informed that its previously issued AXI write transaction has been completed in a manner specified by the AXI protocol.

[0107] Inter-chip interconnect unit 2, in response to receiving data 2 from inter-chip interconnect unit 1, generates an AXI write transaction carrying data 2 and provides it to the AXI slave interface 2 of inter-chip interconnect unit agent 2. Figure 4B (As indicated by (1.7)). Data 2 is the same as or corresponds to Data 1.

[0108] AXI provides the data 2 carried by the AXI write transaction to the data scheduling unit 2 from the device interface 2. Figure 4A (As indicated by (1.8)).

[0109] In response, AXI slave interface 2 provides data 2 carrying the AXI write transaction to data scheduling unit 2, and sends an AXI Write Response transaction to inter-chip interconnect unit 2. Figure 4A (1.9) indicates that the chip interconnect unit 2 has been informed that its previously issued AXI write transaction has been completed in a manner specified by the AXI protocol.

[0110] Data scheduling unit 2 receives data 2, converts data 2 into a req message, and writes the req message into the cache queue corresponding to CPU 1 (e.g., ...). Figure 3A , Figure 4A Middle queue 10)( Figure 4A (As indicated by (1.10)).

[0111] After gaining access to message bus 2, arbitrator 2 retrieves the req message from queue 10 and sends it to message bus 2. Figure 4A (As indicated by (1.11)). The req message carries the receiver identifier, such as the NVMe_2 ID.

[0112] NVMe Agent 2 retrieves the req message from message bus 2 based on the recipient identifier NVMe_2 carried in the req message and forwards it to NVMe_2. Figure 4A (As indicated by (1.12)).

[0113] At this point, the process of CPU1 sending the req message to NVMe_2 is complete. Next, according to the message bus protocol, NVMe_2, upon receiving the req message, must send an ack message to CPU1 as a response to receiving the req message.

[0114] like Figure 4B As shown, the process of NVMe_2 sending an ACK message to CPU1 includes:

[0115] In chip 2, NVMe_2 responds to the received req message by generating an ack message and sends the ack message to message bus 2 through NVMe agent 2. Figure 4B (2.1) indicates.

[0116] The decoder 2 of the inter-chip interconnect unit agent 2 obtains the ack message from the message bus 2 based on the message bus device CPU1, whose receiver is identified as chip 1 in the ack message, and adds the ack message to the cache queue corresponding to NVMe_2 in the TX unit 2 (e.g., Figure 3A , Figure 4B Middle queue 8)( Figure 4B (As indicated by (2.2)).

[0117] In TX unit 2, queue scheduling unit 2 obtains the ACK message from queue 8, generates data conforming to the AXI bus format (denoted as data 3), and provides the generated data 3 to AXI master interface 2. Figure 4B (Instructions from (2.3)).

[0118] AXI master interface 2 sends an AXI write transaction, which sends the data 3 received from queue scheduling unit 2 to inter-chip interconnect unit 2. Figure 4B (Instructions from (2.4)).

[0119] Inter-chip interconnect unit 2 sends data representing an AXI write transaction (denoted as data 4) to inter-chip interconnect unit 1 via the inter-chip interconnect link. Figure 4B (Instructions from (2.5)).

[0120] Inter-chip interconnect unit 2, in response to sending data 4 representing an AXI write transaction to inter-chip interconnect unit 1, sends an AXI write response transaction to AXI master interface 2. Figure 4B (2.6) indicates that the AXI master interface 2 has been informed that its previously issued AXI write transaction has been completed in a manner specified by the AXI protocol.

[0121] Inter-chip interconnect unit 1, in response to receiving data 4 from inter-chip interconnect unit 2, generates an AXI write transaction carrying data 4 and provides it to AXI slave interface 1. Figure 4B (Indicated by (2.7)). Data 4 is the same as or corresponds to data 3.

[0122] Chip 1 receives data 4 carried by the AXI write transaction from the AXI slave interface 1 and provides data 4 to the data scheduling unit 1. Figure 4B (Instructions from (2.8)).

[0123] In response, AXI slave interface 1 provides the data 4 carried by the AXI write transaction to data scheduling unit 1, and sends the AXI write response transaction to inter-chip interconnect unit 1. Figure 4B (2.9) indicates that the chip interconnect unit 1 has been informed that its previously issued AXI write transaction has been completed in a manner specified by the AXI protocol.

[0124] Data scheduling unit 1 receives data 4 carried by the AXI write transaction, converts data 4 into an ack message, and writes the ack message into the cache queue corresponding to NVMe_2 (e.g., Figure 3A , Figure 4A Middle queue 5)( Figure 4B (As indicated by (2.10)).

[0125] After gaining access to message bus 1, arbitrator 1 retrieves an ACK message from queue 5 and sends it to message bus 1. Figure 4B The ack message carries the receiver identification, such as the ID of CPU1.

[0126] The CPU agent 1 acquires the ack message from the message bus 1 and provides it to the CPU 1 according to the receiver identification carried by the ack message, which is the ID of CPU1. Figure 4B The process of sending the ack message by NVMe_2 to CPU1 is thus completed.

[0127] The CPU 1 knows according to the ack message that the req message (see Figure 4A ) it sent before has been received by NVMe_2 of chip 2, thus completing the cross-chip message transmission based on the message system.

[0128] Referring to the embodiments shown in Figure 4A and Figure 4B , the operations implemented by the inter-chip interconnect unit agent 1 include:

[0129] (1) In response to receiving a message from the message bus 1 of chip 1 (the receiver of the message is a component in chip 2 coupled to the message system 2), generate an AXI write carrying the message and send it to the inter-chip interconnect unit 1, so that the inter-chip interconnect unit 1 sends the message to the inter-chip interconnect unit agent 2 through the inter-chip interconnect link.

[0130] (2) Receive and process the AXI write transaction from the inter-chip interconnect unit 1, generate a corresponding AXI write response and provide it to the inter-chip interconnect unit 1. Obtain the message (req or ack) of the message system from the AXI write transaction, and send the message to the message bus 1.

[0131] Referring to the embodiments shown in Figure 4A and Figure 4B , the operations implemented by the inter-chip interconnect unit agent 2 include:

[0132] (1) Receive and process the AXI write transaction from the inter-chip interconnect unit 2, generate a corresponding AXI write response and provide it to the inter-chip interconnect unit 2. Obtain the message (req or ack) of the message system from the AXI write transaction, and send the message to the message bus 2.

[0133] (2) In response to receiving a message from the message bus 2 of chip 2 (the receiver of the message is a component in chip 1 coupled to the message system 1), generate an AXI write carrying the message and send it to the inter-chip interconnect unit 2, so that the inter-chip interconnect unit 2 sends the message to the inter-chip interconnect unit agent 1 through the inter-chip interconnect link.

[0134] In optional embodiments, multiple components in one chip can access the same component in another chip, for example Figure 4A The CPU1, NVMe_1, NFI_1, etc. in chip 1 can all access NVMe_2 in chip 2; the CPU2, NVMe_2, NFI_2, etc. in chip 2 can all access NVMe_1 in chip 1. Since the components communicate through the message bus, when multiple components in one chip access the same component in another chip, the corresponding agents of the multiple components send messages to the message bus with the same receiver identifier, and the AXI addresses (addr) in the corresponding AXI Write are the same. For example, in FIG. 4, CPU1 in chip 1 sends data1 (for example, as req or ack) to NFI_2 in chip 2 through CPU agent 1, and NVMe_1 sends data2 to NFI_2 in chip 2 through NVMe agent 1. Since both are sending data to NFI_2 in chip 2, the message sent by the CPU1 agent to the message bus is recorded as Req1<source_ID_1,dest_ID_1,data1>, where source_ID_1 indicates CPU1 in chip 1 and dest_ID_1 indicates NFI_2 in chip 2. The message sent by the NVMe_1 agent in chip 1 to the NFI agent 2 in chip 2 is recorded as Req2<source_ID_2,dest_ID_2data2>, where source_ID_2 indicates NVMe_1 in chip 1 and dest_ID_2 indicates the NFI_2 agent in chip 2. The dest_ID_1 indicated by Req1 and the dest_ID_2 indicated by Req2 are the same.

[0135] The AXI Master interface 1 in chip 1 converts dest_ID_1 in Req1 to AXI bus address addr1 to generate AXI Write1(addr1, data1); and converts dest_ID_2 in Req2 to AXI bus address addr2 to generate AXI Write2(addr2, data2); since dest_ID_1 and dest_ID_2 are the same, addr1 and addr2 in AXI Write1(addr1, data1) and AXI Write2(addr2, data2) generated by the AXI Master are the same.

[0136] In some cases, multiple components of a chip in an electronic device need to send req messages to another chip, and the multiple components contend with each other for bandwidth of an inter-chip communication link, causing available bandwidth of one or more components to fluctuate and affecting communication performance and quality of service between the components. On the other hand, a component in one chip frequently accesses a component in another chip, for example, CPU1 in chip 1 frequently accesses a component in chip 2. If a buffer queue corresponding to CPU1 in an RX unit of an inter-chip interconnect agent 2 of chip 2 is full, the RX unit of the inter-chip interconnect agent 2 of chip 2 will not be able to process a corresponding AXI Write transaction. To solve this technical problem, a sender (a chip sending a req message or an ack message) can query free space of a corresponding queue in an inter-chip interconnect agent of a receiver (a chip receiving the req message or the ack message) before sending an AXI Write transaction carrying the message. If the free space of the corresponding queue can carry the message, the sender sends the message to the receiver. If the free space is insufficient to carry the message, the sender suspends sending the message to the receiver. However, the RX unit in the inter-chip interconnect agent of the sender and the receiver is located in different chips, and the sender needs to obtain the size of the free space of the buffer queue of the RX unit in the inter-chip interconnect agent of the receiver through inter-chip communication. Compared with the time required for reading data through an AXI bus within a chip, the sender needs a longer time to obtain the size of the free space of the buffer queue of the RX unit in the inter-chip interconnect agent of the receiver, which reduces the efficiency of inter-chip communication.

[0137] Therefore, in an embodiment of the present application, a component for managing credits is arranged in an inter-chip interconnect agent of a sender, and the size of the free space of a buffer queue of an RX unit in an inter-chip interconnect agent of a receiver is represented by the managed credits. The sender locally queries the value of the managed credits before sending a message, to estimate the size of the free space of a corresponding buffer queue in the RX unit of the receiver. Compared with querying the size of the free space of the buffer queue of the RX unit of the receiver across chips, the embodiment of the present application locally queries the value of the credit representing the size of the free space of the buffer queue of the RX unit in the inter-chip interconnect agent of the receiver, shortens the time required for querying the free space of the buffer queue of the RX unit in the inter-chip interconnect agent of the receiver across chips, and improves the efficiency of inter-chip message communication.

[0138] Figure 5A An embodiment of the present application provides an inter-chip interconnect agent. Figure 5B An embodiment of the present application provides an electronic device including an inter-chip interconnect agent. Figure 5B The electronic device shown includes chip 1 and chip 2, and chip 1 and chip 2 each include Figure 5A The inter-chip interconnect agent shown. For ease of description, Figure 5B In the figure, components and functional modules in chip 1 are identified with suffix "1", and components and functional modules in chip 2 are identified with suffix "2".

[0139] As shown in Figure 5A , the inter-chip interconnection unit agent includes a decoder, an arbiter, a TX unit, and an RX unit. The functions of the arbiter and the decoder can refer to Figure 3A , 3B , which will not be described here in detail. Compared with the inter-chip interconnection unit agent shown in Figure 3A , 3B , the TX unit of the inter-chip interconnection unit agent shown in Figure 5A further includes a master credit management unit and a master read transaction unit, and the RX unit further includes a slave credit management unit and a slave read transaction response unit.

[0140] As shown in Figure 5A , the master credit management unit is coupled with an AXI master interface, a queue scheduling unit, and a master read transaction unit. The master credit management unit is configured to manage a credit corresponding to a cache queue in the RX unit of the remote chip. Optionally, the credit is used to represent the size of the free space of the cache queue in the RX unit of the remote chip. Since the cache queue of the RX unit in the inter-chip interconnection unit agent of the remote chip corresponds to a message sender of the message system of the local chip one-to-one, the credit managed by the master credit management unit also corresponds to the message sender of the message system of the chip (the local chip) where the master credit management unit is located, thereby realizing the management of the message sent by the message sender based on the credit. In short, if the credit of the message sender is sufficient, the message sender is allowed to send the message; if the credit of the message sender is insufficient, the message sender is not allowed to send the message.

[0141] Optionally, the number of master credit management units is the same as the number of cache queues in the RX unit of the remote chip, and the master credit management unit corresponds to the cache queue in the RX unit of the remote chip one-to-one. For example, as shown in Figure 5B , the master credit management unit 1 manages the credit corresponding to the cache queue of the RX unit 2 in the chip 2, and the master credit management unit 2 manages the credit corresponding to the cache queue of the RX unit 1 in the chip 1. Figure 5B One master credit management unit is schematically shown, and it can be understood that in an optional embodiment, the TX unit 1 includes three master credit management units corresponding to the cache queues of the RX unit 2, and the TX unit 2 includes three master credit management units corresponding to the cache queues of the RX unit 1. Still optionally, a single master credit management unit is used to maintain the credits of the multiple cache queues of the multiple RXs of the remote chip.

[0142] As shown in Figure 5A As shown, the master read transaction unit is coupled with the AXI master interface, the inter-chip interconnect unit, and the master credit management unit. Before the AXI master interface issues an AXI Write transaction, the master credit management unit checks whether the credit of the buffer queue corresponding to the data carried by the AXI Write transaction is sufficient to support the issuance of the transaction. The credit indicates whether the message sender of the data corresponding to the AXI Write transaction has the credit to send the message, or the credit indicates the size of the free space of the buffer queue corresponding to the data carried by the AXI Write transaction. If the master credit management unit checks that the credit of the corresponding buffer queue is sufficient, the AXI master interface issues the AXI Write transaction. In response to the AXI master interface issuing the AXI Write transaction, the master credit management unit updates the credit it manages, for example, deducts the credit corresponding to the amount of data carried by the AXI Write transaction. If the master credit management unit checks that the credit of the corresponding buffer queue is insufficient, the master credit management unit instructs the master read transaction unit to generate an AXI read transaction to read the current free space size of the corresponding buffer queue in the RX unit of the inter-chip interconnect unit agent in the remote chip, and to update the credit in the master credit management unit according to the current free space size. Accordingly, a slave credit management unit and a slave read transaction response unit are provided in the inter-chip interconnect unit agent of the remote chip as a slave on the AXI bus to respond to the read transaction. For example, referring to Figure 5B , the master read transaction unit 1 in the inter-chip interconnect unit agent 1 generates an AXI read transaction to read the free space of the buffer queue corresponding to the data carried by the AXI Write transaction in the RX unit 2 of the inter-chip interconnect unit agent 2. A slave credit management unit 2 and a slave read transaction response unit 2 are provided in the inter-chip interconnect unit agent 2 as a slave on the AXI bus to respond to the AXI read transaction. The value read by the master read transaction unit 1 represents the current free space size of the corresponding buffer queue in the RX unit 2. The master read transaction unit 1 updates the credit managed by the master credit management unit according to the read value. If the updated credit of the master credit management unit 1 is still insufficient, the AXI master interface 1 still suspends the issuance of the AXI Write transaction, and the master read transaction unit 1 generates the AXI read transaction again, repeating the above process of obtaining the credit, until there is sufficient credit to issue the AXI Write transaction.

[0143] As shown in Figure 5A , the slave credit management unit is coupled with the AXI slave interface and the slave read transaction response unit. The slave credit management unit is used to obtain the size of the free space of each buffer queue in the RX unit of the inter-chip interconnect unit agent.

[0144] As Figure 5A indicated, the slave read transaction response unit is coupled with the inter-chip interconnect unit and the slave quota management unit. The slave read transaction response unit receives the AXI read transaction issued by the master read transaction unit of the inter-chip interconnect unit agent of the remote chip, acquires the free space size of the specified cache queue through the slave quota management unit, takes the data to be read by the AXI read transaction, and generates an AXI read response transaction to feed back the free space size of the specified cache queue to the master read transaction unit of the inter-chip interconnect unit agent of the remote chip. The master quota management unit updates the quota it manages according to the data read by the master read transaction unit through the AXI read transaction and its response. Among them, the slave read transaction response unit determines the specified cache queue according to the address carried by the AXI read transaction.

[0145] For ease of understanding, with reference to Figure 6 , take an example of that CPU1 in chip1 sends a req message to NVMe_2 in chip2, and NVMe_2 feeds back an ack message to CPU1 to illustrate the function of the inter-chip interconnect unit agent. Among them, from the perspective of chip1, the inter-chip interconnect unit agent 1 in chip1 is the local inter-chip interconnect unit agent, and the inter-chip interconnect unit agent 2 in chip2 is the remote inter-chip interconnect unit agent.

[0146] Figure 6 The processing flow diagram of the local inter-chip interconnect unit agent is shown. As Figure 6 indicated, the processing flow of the req message includes:

[0147] CPU1 in chip1 sends a req message to message bus1 through CPU agent1 (indicated in (3.1) in Figure 6 ).

[0148] The decoder 1 identifies from the message bus 1 that the req message needs to be processed by itself, acquires the req message, and sends the req message to the queue 1 corresponding to CPU1 in the TX unit (indicated in (3.2) in Figure 6 ).

[0149] The queue scheduling unit 1 acquires the req message from the queue 1, generates data (denoted as data 5) conforming to the AXI bus format, and provides the generated data 1 to the AXI master interface 1 (indicated in (3.3) in Figure 6 ).

[0150] Before sending an AXI write transaction, the master device quota management unit 1 queries whether the quota value it manages corresponding to the sender of the req message (CPU1) is greater than or equal to a preset value. The preset value is, for example, the quota value consumed by sending an AXI write transaction. The master device quota management unit 1 manages quotas corresponding to the free space size of queue 10 (corresponding to CPU1), queue 11 (corresponding to NVMe_1), and queue 12 (corresponding to NFI_1), respectively. The initial value of the quota can be, for example, the size of each queue. Each time the AXI master device interface 1 sends an AXI write transaction, the master device quota management unit 1 updates the quota value corresponding to the queue carrying the data of that AXI write transaction. In this embodiment, taking the example that the quota value managed by the master device quota management unit 1 corresponding to queue 10 is less than the preset value required for the current AXI write transaction, the master device quota management unit 1, in response to finding that the quota value corresponding to queue 10 is less than the preset value, instructs the master device read transaction unit 1 to generate an AXI read transaction. Figure 6 (3.4) Instruction) and instruct AXI master interface 1 to suspend sending AXIwrite transactions. For cases where the quota value managed by master quota management unit 1 corresponding to queue 10 is greater than or equal to a preset value, refer to the following description of master quota management unit 1 instructing AXI master interface 1 to send an AXI write transaction to inter-chip interconnect unit 1 ( Figure 6 (3.13) instructions).

[0151] When AXI master interface 1 suspends sending AXI write transactions, master read transaction unit 1 sends an AXI read transaction to inter-chip interconnect unit 1. Figure 6 (3.5) indicates that the size of the free space in queue 10 of RX unit 2 is read.

[0152] Inter-chip interconnect unit 1 sends the AXI read transaction to inter-chip interconnect unit 2 via the inter-chip interconnect link. Figure 6 (3.6) instructions).

[0153] In response to receiving data representing an AXI read transaction, the inter-chip interconnection unit 2 transmits the AXI read transaction to the slave device read transaction response unit 2. Figure 6 (3.7) instructions).

[0154] In response to receiving an AXI read transaction, the device read transaction response unit 2 instructs the device quota management unit 2 to obtain the current free space size of queue 10. Figure 6 (3.8) instructions).

[0155] The slave read transaction response unit 2 sends an AXI read response transaction to the inter-chip interconnect unit 2, which carries the size of the current free space of the queue 10 (3.9). Figure 6

[0156] The inter-chip interconnect unit 2 sends data representing the AXI read response transaction to the inter-chip interconnect unit 1 in response to the AXI read response transaction (3.10). Figure 6

[0157] The inter-chip interconnect unit 1 delivers the AXI read response transaction to the master read transaction unit 1 in response to receiving the data representing the AXI read response transaction (3.11). Figure 6

[0158] The master read transaction unit 1 delivers the data carried in the AXI read response transaction to the master credit management unit 1, which instructs the master credit management unit 1 to update the credit value corresponding to the queue 10 (3.12). Figure 6

[0159] The master credit management unit 1 updates the credit value corresponding to the queue 10 to the credit value corresponding to the current free space of the queue 10. The master credit management unit 1 identifies whether the updated credit value is greater than or equal to a preset value. The master credit management unit 1 instructs the AXI master interface to send an AXI write transaction (3.13) to deliver data 5 in response to the updated credit value being greater than or equal to the preset value. Figure 6

[0160] The AXI master interface sends the AXI write transaction to the inter-chip interconnect unit 1 (3.14). Figure 6

[0161] The master credit management unit 1 updates the credit value corresponding to the queue 10 in response to the AXI master interface sending, such as deducting the credit value required for sending the AXI write transaction.

[0162] The following processing process is consistent with the processing process shown in Figure 4A The inter-chip interconnect unit 1 sends data (denoted as data 6) carrying the AXI write transaction to the inter-chip interconnect unit 2 through the inter-chip interconnect link (1.5). Figure 4A

[0163] ​​​​​​​The inter-chip interconnect unit 1, in response to sending the data 6 to the inter-chip interconnect unit 2, sends an AXI write response transaction to the AXI master interface 1 (refer to (1.6) in FIG. 4A) to inform the AXI master interface 1 that the AXI write transaction it previously issued has been processed in the manner prescribed by the AXI protocol.

[0164] The inter-chip interconnect unit 2, in response to receiving the data 6 from the inter-chip interconnect unit 1, generates an AXI write transaction carrying the data 6 and provides the AXI slave interface 2 of the inter-chip interconnect unit agent 2 (refer to (1.7) in FIG. 4B). Figure 4B The data 6 is the same as or corresponds to the data 5.

[0165] The AXI slave interface 2 provides the data 6 carried by the AXI write transaction to the data scheduling unit 2 (refer to (1.8) in FIG. 4B). Figure 4A

[0166] The AXI slave interface 2, in response to providing the data 6 carried by the AXI write transaction to the data scheduling unit 2, sends an AXI write response transaction to the inter-chip interconnect unit 2 (refer to (1.9) in FIG. 4B) to inform the inter-chip interconnect unit 2 that the AXI write transaction it previously issued has been processed in the manner prescribed by the AXI protocol. Figure 4A

[0167] The data scheduling unit 2 receives the data 6, converts the data 6 into a req message, and writes the req message to the queue 10 corresponding to the CPU 1 (refer to (1.10) in FIG. 4B). Figure 4A

[0168] The arbiter 2, upon obtaining the right to use the message bus 2, obtains the req message from the queue 10 and sends it to the message bus 2 (refer to (1.11) in FIG. 4B). The req message carries a recipient identifier, such as the ID of NVMe_2. Figure 4A

[0169] The NVMe_2 agent, according to the recipient identifier carried by the req message, which is the ID of NVMe_2, obtains the req message from the message bus 2 and hands it over to NVMe_2 (refer to (1.12) in FIG. 4B). Figure 4A

[0170] NVMe_2 in the chip 2, in response to receiving the req message, generates an ack message and sends it to the message bus 2 through the NVMe_2 agent (refer to (2.1) in FIG. 4B). Figure 4B

[0171] ​​​​​​The decoder 2 of the inter-chip interconnect unit agent 2 obtains the ack message from the message bus 2 based on the message bus device CPU1, whose receiver is identified as chip 1 in the ack message, and adds the ack message to the queue 8 corresponding to NVMe_2 in the TX unit 2 (see reference). Figure 4B (2.2)).

[0172] In TX unit 2, queue scheduling unit 2 retrieves the ACK message from queue 8, generates data conforming to the AXI bus format (denoted as data 7), and provides the generated data 7 to AXI master interface 2 (reference). Figure 4B (2.3)).

[0173] AXI master interface 2 sends an AXI write transaction, transmitting data 7 received from queue scheduling unit 2 to inter-chip interconnect unit 2 (reference). Figure 4B (2.4)

[0174] Inter-chip interconnect unit 2 sends data representing an AXI write transaction (denoted as data 7) to inter-chip interconnect unit 1 (reference) via the inter-chip interconnect link. Figure 4B (2.5) instructions).

[0175] Inter-chip interconnect unit 2, in response to sending data 7 representing an AXI write transaction to inter-chip interconnect unit 1, sends an AXI write response transaction to AXI master interface 2 (see reference). Figure 4B In (2.6), the AXI master interface 2 is notified that its previously issued AXI write transaction has been completed in a manner specified by the AXI protocol.

[0176] In response to receiving data 7 from inter-chip interconnect unit 2, chip interconnect unit 1 generates an AXI write transaction carrying data 7 and provides it to AXI slave interface 1 (reference). Figure 4B (2.7)). Data 7 is the same as or corresponds to data 6.

[0177] Chip 1 receives data 7 carried by the AXI write transaction from the AXI slave device interface 1 and provides data 7 to the data scheduling unit 1 (reference). Figure 4B (2.8)

[0178] In response, AXI slave interface 1 provides the data 7 carried by the AXI write transaction to data scheduling unit 1, and sends an AXI write response transaction to inter-chip interconnect unit 1 (see reference). Figure 6 In (2.9), the chip interconnection unit 1 is notified in the manner specified by the AXI protocol that its previously issued AXI write transaction has been processed.

[0179] Reference Figure 6 In the embodiment shown, the master credit management unit 1 in the inter-chip interconnect unit agent 1 uses the managed credit to represent the free space size of the RX unit 2 buffer queue in the inter-chip interconnect unit agent 2. Before the AXI master interface 1 in the inter-chip interconnect unit agent 1 sends an AXI write transaction, the master credit management unit 1 locally queries the managed credit value to estimate the free space size of the RX unit 2 buffer queue in the inter-chip interconnect unit agent 2, without the need to cross-chip query the free space size of the RX unit 2 buffer queue in the inter-chip interconnect unit agent 2. Compared to cross-chip querying the free space size of the RX unit buffer queue in the inter-chip interconnect unit agent, the chip 1 locally queries the credit representing the free space size of the RX unit 2 buffer queue in the inter-chip interconnect unit agent 2, shortens the query time, and improves the efficiency of message communication between chips.

[0180] It needs to be pointed out that first, in more cases, the credit value required by the AXI master interface 1 when sending an AXI Write transaction is sufficient, so that the required credit can be obtained only through the master credit management unit 1, without the need to read the free space size of the RX unit 2 queue in the inter-chip interconnect unit agent 2 through the master read transaction unit 1. For example, in 10 times of sending AXI Write transactions, the credit value required in 9 times is sufficient, without the need to update the credit value through time-consuming inter-chip data transmission, and only for 1 time of AXI Write transaction, the credit value is updated through the cross-chip AXI read transaction.

[0181] Second, for the remote chip (for example, chip 2), the inter-chip interconnect unit agent 2 continuously sends data in the RX unit 2 queue to the corresponding component on the message bus, so that the space of the RX unit 2 queue can be released in time to form sufficient free space, so that the AXI Read transaction sent by the master read transaction interface 1 can probably read a sufficient number of free space values to update the credit of the master credit management unit 1. Even if the queue free space is not much when the AXI Read transaction is occasionally received from the device read transaction response unit 2, so that the updated credit value is still insufficient, after the AXI Read transaction is sent again through the master read transaction interface 1, a sufficient number of free space values can usually be read. Therefore, the master read transaction interface 1 does not need to frequently send AXI Read transactions.

[0182] Third, the remote chip (e.g. chip 2), the inter-chip interconnect unit agent 2 continuously sends data in the queue of RX unit 2 to the corresponding component on the message bus, but the occurrence of this event does not and need not notify the inter-chip interconnect unit agent 1 of chip 1 (because the overhead of cross-chip data transmission is relatively high). Thus, the credit maintained by the master credit management unit 1 is an estimate of the free space of the queue of RX unit 2 of chip 2, rather than reflecting the true value. Thus, when the master credit management unit 1 reports that the credit is insufficient, there can be sufficient free space in the queue of RX unit 2 of chip 2, but this does not affect the effectiveness of the embodiments of the present application, because for most AXI Write transactions to be sent, sufficient credit values can be obtained through the master credit management unit 1.

[0183] Fourth, the master read transaction interface 1 reads the free space size of the queue of the RX unit of the inter-chip interconnect unit agent of the remote chip, which is equivalent to synchronizing the free space size of the queue of the RX unit of the remote chip with the corresponding credit value of the local chip. Alternatively, other means of synchronization between the remote chip and the local chip can also be applicable. For example, the synchronization can be achieved by means of an ack message corresponding to a req message. In response to the inter-chip interconnect unit agent of the local chip receiving the ack message, the credit value managed by the master credit management unit is updated (e.g. increased). For another example, the inter-chip interconnect unit agent of the remote chip actively sends an AXI Write transaction to transmit the free space size of the queue of its RX unit to the inter-chip interconnect unit agent of the local chip, and the credit value managed by the master credit management unit is updated (e.g. increased) accordingly.

[0184] Fifth, the credit value managed by the master credit management unit and the free space size of the queue can have the same or different units. When the units are the same, the queue free size obtained through the AXI Read transaction can be directly used as the credit value. When the units are different, the queue free size obtained through the AXI Read transaction can be used as the credit value after conversion.

[0185] Sixth, the master credit management unit maintains a credit for each message sender that sends messages to the remote chip. The credit is used to manage the bandwidth of the inter-chip transmission link that can be used by each message sender within a certain time. When the credit of a message sender is exhausted, the messages sent by the message sender will not be converted into AXI Write transactions, thereby temporarily limiting the occupation of the bandwidth of the inter-chip transmission link by the message sender. Thus, a single message sender will not occupy the entire bandwidth of the inter-chip transmission link within a short time due to the limitation of the available credit, thereby also ensuring that the sending behavior of a certain message sender will not significantly affect the use of the inter-chip transmission link by other message senders.

[0186] Reference Figure 7 The timing of updating the credit managed by the master device credit management unit in the embodiment of the present application includes: when the local chip interconnect unit agent (the party sending the AXI write transaction) sends the AXI write, and after receiving the AXI read response sent by the remote chip interconnect unit agent (the party receiving the AXI write transaction).

[0187] The queue scheduling unit of the local chip interconnect unit agent provides the message (such as the req message or the ack message) obtained from the TX unit cache queue to the AXI master interface; the AXI master interface generates the AXI write transaction based on the information carried by the message. The local chip interconnect unit agent checks whether the credit value in the master device credit management unit meets the requirement of the AXI write transaction before the AXI master interface sends the AXI write transaction; if it meets, instructs the AXI master interface to send the AXI write transaction, and in response to the AXI master interface sending the AXI write transaction, updates the credit value managed by the master device credit management unit, and the updated credit value = the credit value before updating- the credit value required by the AXI write transaction; for example, the credit value before updating is 10, and the credit required by the AXI write is 5, then the updated credit value is 5 = 10-5.

[0188] In response to the credit value in the master device credit management unit being insufficient to send the AXI write transaction, instructing the AXI master interface to suspend sending the AXI write transaction; generating and issuing the AXI read transaction by the master device read transaction unit. The remote chip interconnect unit agent receives the AXI read transaction, and generates the AXI read response transaction. The local chip interconnect unit agent receives the AXI read response transaction, and updates the credit value (credit) managed by the master device credit management unit according to the current free space size of the destination cache queue indicated by the AXI read response transaction. For example, the credit value managed by the master device credit management unit is 2, the current free space size of the destination cache queue is 5, and the master device credit management unit updates the credit value corresponding to the destination cache queue to 5.

[0189] Figure 7 A schematic diagram of the chip interconnect unit agent updating the credit provided by an embodiment of the present application is shown. As shown in Figure 5B , Figure 7 The initial quota value for CPU1 is 20, which means that the initial space of queue 10 in RX unit 2 of inter-chip interconnect unit agent 2 is 20 units. The initial quota value for NVMe_1 is 10, which means that the initial space of queue 11 in RX unit 2 of inter-chip interconnect unit agent 2 is 10 units. For each message sent by CPU1, the corresponding AXIwrite transaction consumes 5 quotas; for each message sent by NVMe_1, the corresponding AXIwrite transaction consumes 2 quotas.

[0190] like Figure 7 As shown, at time t1, CPU1 sends two messages, AXI master interface 1 sends two AXI write transactions, consuming 10 credits. Inter-chip interconnect unit agent 1 updates the corresponding credit value for CPU1, leaving a remaining credit value of 10. At time t2, CPU1 sends two messages, AXI master interface 1 sends two AXI write transactions, consuming 10 credits. Inter-chip interconnect unit agent 1 updates the corresponding credit value for CPU1, leaving a remaining credit value of 0. At time t3, CPU1 needs to send two messages. Inter-chip interconnect unit agent 1 queries the credit value; the current credit value is 0, meaning the current credit value does not support CPU1 sending messages. Inter-chip interconnect unit agent 1 sends an AXI read transaction to update the corresponding credit value for CPU1, resulting in an updated credit value of 5. At time t4, CPU1 sends two messages. Inter-chip interconnect unit agent 1 queries the current credit limit value and determines that the current credit limit only supports sending one message. CPU1 sends one message and pauses sending the other message. Inter-chip interconnect unit agent 1 updates the credit limit value corresponding to CPU1, with a remaining credit limit value of 0. At time t5, NVMe_1 sends one message, AXI master interface 1 sends an AXI write transaction, which consumes 2 credit limits. Inter-chip interconnect unit agent 1 updates the credit limit value corresponding to NVMe_1, with a remaining credit limit value of 8.

[0191] exist Figure 5B In the illustrated embodiment, CPU1 has a large amount of data transmission, which requires frequent use of the bandwidth of the inter-chip transmission link to send messages. Its corresponding quota will be quickly exhausted, thereby preventing CPU1 from continuously transmitting data, so that the bandwidth of the inter-chip transmission link required by NVMe_1 will not be squeezed out by the frequent data transmission of CPU1.

[0192] In the embodiment, the local chip-to-chip interconnect unit agent represents the size of the free space of the buffer queue in the RX unit of the remote chip-to-chip interconnect unit agent for buffering the message sent by the sender by using the locally managed credit value, so that the local chip-to-chip interconnect unit agent does not need to query the size of the free space of the buffer queue in the RX unit of the remote chip-to-chip interconnect unit agent across the chip, saving time and improving the communication efficiency between chips. If the local chip-to-chip interconnect unit agent queries that the locally managed credit value is greater than or equal to the credit value required for sending the AXI write transaction, the buffer queue of the RX unit in the remote chip-to-chip interconnect unit agent can certainly accommodate the current AXI write transaction; if the local chip-to-chip interconnect unit agent queries that the locally managed credit value is less than the credit value required for sending the AXI write transaction, the buffer queue of the RX unit in the remote chip-to-chip interconnect unit agent can not be able to accommodate the current AXI write transaction, or can be able to accommodate the current AXI write transaction (because the RX unit of the remote chip-to-chip interconnect unit agent is continuously sending the data in the buffer queue to the message bus, so the free space of the buffer queue in the RX unit can be greater than the locally managed credit value). In response to the locally managed credit value being less than the credit value required for sending the AXI write transaction, the local chip-to-chip interconnect unit agent acquires the size of the free space of the buffer queue of the RX unit of the remote chip-to-chip interconnect unit agent through the AXI read transaction, to determine whether the AXI write transaction can be sent. Thus, the local chip-to-chip interconnect unit agent does not need to always query the size of the free space of the buffer queue of the RX unit in the remote chip-to-chip interconnect unit agent across the chip when sending the AXI write transaction, shortening the processing delay.

[0193] Reference Figure 6 and Figure 8A , the other components in chip 1 coupled to message bus 1 send messages to components in chip 2 coupled to message bus 2, e.g. NVMe_1 sends a message to CPU2. Before AXI master interface sends AXI write transaction, master credit management unit 1 queries the credit value corresponding to queue 11 it manages. If master credit management unit 1 queries that the credit value corresponding to queue 11 is greater than or equal to the credit value required for sending AXI write transaction, it instructs AXI master interface 1 to send AXI write transaction to deliver the message sent by NVMe_1 to CPU2. AXI read transaction sent by inter-chip interconnect unit agent 1 to query the size of free space of queue 10 is independent of AXI write transaction sent by inter-chip interconnect unit agent 1 to deliver the message sent by NVMe_1, and inter-chip interconnect unit agent 1 does not need to wait for the response of AXI read transaction for querying queue 10. If master credit management unit 1 queries that the credit value corresponding to queue 11 is less than the credit value required for sending AXI write transaction, it instructs master read transaction unit 1 to send AXI read transaction to query the size of free space of queue 11. AXI read transaction sent by inter-chip interconnect unit agent 1 to query the size of free space of queue 10 is independent of AXI read transaction sent by inter-chip interconnect unit agent 1 to query the size of free space of queue 11, and inter-chip interconnect unit agent 1 does not need to wait for the response of AXI read transaction for querying queue 10.

[0194] Figure 8A A flow chart is shown for inter-chip interconnect unit agent 1 processing AXI write transaction. As shown in Figure 8B , inter-chip interconnect unit agent 1 gets a message (denoted as message 1) from the cache queue (e.g. queue 1) of TX unit 1, determines the designated cache queue in RX unit of inter-chip interconnect unit agent 2 corresponding to message 1, and instructs master credit management unit 1 to query whether the credit value it manages corresponding to the sender of message 1 meets the requirement of sending AXI write transaction.

[0195] If the master credit management unit 1 finds that the credit value corresponding to the sender of message 1 satisfies the requirement of sending AXI write transaction, it instructs the AXI master interface 1 to send AXI write transaction to deliver message 1 to the chip interconnect unit agent 2. In response to the AXI master interface 1 sending AXI write transaction, the master credit management unit 1 updates the credit value corresponding to the sender of message 1. The chip interconnect unit agent 1 receives AXI write response sent by the chip interconnect unit 1 to inform the chip interconnect unit agent 1 that the AXI write transaction it sent before has been processed. The chip interconnect unit agent 1 continues to get message (denoted as message 2) from the cache queue (e.g., queue 1 or queue 2) of the TX unit 1 and repeats the above process.

[0196] If the master credit management unit 1 finds that the credit value corresponding to the sender of message 1 does not satisfy the requirement of sending AXI write transaction, it instructs the master read transaction unit 1 to send AXI read transaction to get the size of the free space of the cache queue corresponding to the sender of message 1 in the RX unit of the chip interconnect unit agent 2.

[0197] Figure 8B A flow chart of the chip interconnect unit agent 1 updating the credit value through AXI read transaction is shown. As shown in Figure 8C , the master read transaction unit 1 sends AXI read transaction to get the size of the free space of the specified cache queue in the RX unit of the chip interconnect unit agent 2. The chip interconnect unit agent 1 receives AXI read response transaction to get the size of the free space of the specified cache queue in the RX unit of the chip interconnect unit agent 2. The master credit management unit 1 updates the credit value corresponding to the specified cache queue in the RX unit of the chip interconnect unit agent 2.

[0198] Figure 8C A flow chart of the chip interconnect unit agent 2 processing AXI read transaction is shown. As shown in Figure 8A , the slave read transaction response unit 2 of the chip interconnect unit agent 2 receives AXI read transaction. The slave read transaction response unit 2 determines the specified cache queue in the RX unit 2 based on the address to be accessed by the AXI read transaction, gets the size of the free space of the specified cache queue from the slave credit management unit 2 and returns it to the slave read transaction response unit 2. The slave read transaction response unit 2 generates AXI read response transaction according to the size of the free space of the specified cache queue in the RX unit 2.

[0199] Figure 8B 、 Figure 8C With Figures 2A-8C The processing flows shown occur independently and can be processed in parallel by their respective hardware units.

[0200] refer to Figure 9 In the illustrated embodiment, the inter-chip interconnect unit agent transmits messages sent by components locally coupled to the message bus to remote chip components, enabling communication between components belonging to two different message systems via messages. Communication between components of a message system via messages refers to...<req,ack> The communication pattern is as follows: The sender generates a `req` message and sends it to the receiver via the inter-chip interconnect unit (ICU). Upon receiving the `req` message, the receiver generates an `ack` message and sends it back to the sender via the ICU. Upon receiving the `ack` message, the sender acknowledges the completion of the message communication. However, in the embodiments of this application, the sender and receiver are two separate chips, and the message transmission is cross-chip. This significantly increases the message delivery delay compared to message communication between two components within the same chip. Consequently, the sender needs a considerable amount of time to receive the `ack` message after sending the `req` message. The sender needs to spend a long time polling for the arrival of the `ack` message or requires complex task scheduling logic (e.g., frequent task scheduling) to handle the waiting time between sending the `req` message and receiving the `ack` message.

[0201] In view of this, in this embodiment of the application, after the sender sends the req message and before the receiver sends the ack message, the sender's own inter-chip interconnect unit generates a pseudo-response message to replace the ack message that should be provided by the receiver and provides it to the component that sent the req message. The pseudo-response message optionally has the same form as the ack message, so that from the sender's perspective, it appears that it has received the ack message. Therefore, the component that sent the req message can confirm the completion of communication in advance upon receiving the pseudo-response message, thereby shortening the sender's waiting time.

[0202] Figure 9 A schematic diagram of the structure of an inter-chip interconnect unit proxy according to an embodiment of this application is shown. Figure 3A As shown, the inter-chip interconnection unit agent includes a decoder, arbitrator, RX unit, TX unit, forward decoder, pseudo-response generation unit, message arbitrator, and message receiving unit. The decoder, arbitrator, RX unit, and TX unit can be referenced from [reference needed]. Figure 3B , Figure 5A , Figure 5B and Figure 9 The embodiments shown are not described again here to avoid repetition.

[0203] like Figure 9 As shown, the forwarding decoder is coupled to the message bus, the pseudo-response generation unit, and the message receiving unit. The forwarding decoder obtains messages from the message bus, such as a `req` message or an `ack` message. Optionally, in response to obtaining a `req` message from the message bus, the forwarding decoder sends the `req` message to the pseudo-response generation unit. Optionally, in response to obtaining an `ack` message from the message bus, the forwarding decoder either does not perform further processing on the `ack` message (e.g., discards the `ack` message) or sends the `ack` message to the message receiving unit for processing (e.g., discarding the `ack` message).

[0204] like Figure 9 As shown, the pseudo-response generation unit is coupled to the forwarding decoder, the decoder, and the message arbitrator. In response to receiving a `req` message from the forwarding decoder, the pseudo-response generation unit sends the `req` message to the decoder. Furthermore, in response to the decoder writing the `req` message into the corresponding buffer queue in the TX unit, the pseudo-response generation unit generates a pseudo-response message 1 corresponding to the `req` message (this pseudo-response message 1 is, for example, the same as the `ack` message returned by the receiver after receiving the `req` message). This pseudo-response message 1 is then sent to the message arbitrator, which transmits the pseudo-response message to the message bus, and further to the sender of the `req` message, thereby notifying the sender of the `req` message in advance that communication is complete.

[0205] Optionally, in response to the translator failing to successfully write the req message into the corresponding buffer queue in the TX unit (e.g. the buffer queue in the TX unit corresponding to the sender of the req message is full), a pseudo response message 2 (indicating that the sending of the req message is unsuccessful) is generated and sent to the message arbiter, so that the message arbiter sends the pseudo response message to the message bus and further to the sender of the req message, thereby informing the sender of the req message that the req message is not sent to the receiver. In the background art message system, the message receiver feeds back an ack message to the message sender based on receiving the req message, which only represents that the receiver successfully receives the req message (same as the semantic of the pseudo response message 1 mentioned above); when the message receiver fails to receive the req message, it does not feed back any message, thereby in the view of the message sender, it always fails to receive the ack message corresponding to the req message. Thus, the message sender in the background art can only identify that the req message is successfully received through the ack message, and additionally needs a mechanism such as a timeout detection mechanism to identify whether the req message is sent unsuccessfully. However, when the sender and the receiver of the message belong to different chips, the time delay from the sending of the req message to the receiving of the corresponding ack message is significantly increased, and causes the timeout detection mechanism in the background art to fail. Moreover, in some cases, the sender and the receiver of the message belong to the same chip, and if the way of increasing the timeout threshold is adopted, the efficiency of the timeout detection in such cases is greatly reduced.

[0206] In embodiments according to the present application, the receiver of the message (whether it is located in the local chip or the remote chip) still only feeds back the ack message when receiving the ack message, and still does not feed back any message when failing to receive the ack message or receiving the ack message unsuccessfully, but the inter-chip interconnection unit agent generates a pseudo response message 2 different from the ack message. The generation of the pseudo response message 2 is irrelevant to the behavior or state of the message receiver. The pseudo response message 2 is generated by the pseudo response generation unit located in the same chip as the message sender, so that the sender of the req message can obtain the result that the req message is sent unsuccessfully as early as possible, thereby performing subsequent remediation. For example, in response to receiving the pseudo response message 2, the message sender re-sends the req message. Thus, whether the receiver of the message is located in the local chip or the remote chip, the message sender can adopt the same timeout detection mechanism to identify whether the req message is successfully received by the receiver, and whether the req message needs to be re-sent.

[0207] As Figure 9 As shown, the message receiving unit is coupled with the arbitrator, the message arbitrator, and the forwarding decoder, respectively. The message receiving unit, in response to receiving the req message sent by the arbitrator, delivers the req message to the message arbitrator. Optionally, the message receiving unit, in response to receiving the ack message sent by the forwarding decoder, does not process (e.g., discards) the ack message. According to the embodiments of the present application, the pseudo response generated by the pseudo response generating unit located in the same chip as the message sender is provided to the message sender, and thus the ack message generated by the real message receiver is intercepted by the forwarding decoder located in the same chip as the message receiver and discarded by the forwarding decoder itself, or is forwarded to the message receiving unit and discarded by the message receiving unit. Thus, the message sender is prevented from receiving the ack message from the receiver after receiving the pseudo response (from the perspective of the message sender, this will be receiving two identical ack messages).

[0208] As shown in Figure 10A , the message arbitrator is coupled with the message receiving unit, the pseudo response generating unit, and the message bus, respectively. The message arbitrator, in response to receiving the req message sent by the message receiving unit, sends the req message to the message bus. Alternatively, the message arbitrator, in response to receiving the pseudo response message 1 or the pseudo response message 2 sent by the pseudo response generating unit, sends the pseudo response message 1 or the pseudo response message 2 to the message bus to send the pseudo response message 1 or the pseudo response message 2 to the sender of the req message.

[0209] Figure 10A A processing flow diagram of the req message is shown. Figure 9 The electronic device shown includes chip 1 and chip 2, and both chip 1 and chip 2 include Figure 10A The inter-chip interconnection unit agent is shown. For ease of description, in Figure 3A , components and functional modules in chip 1 are identified with the suffix "1", and components and functional modules in chip 2 are identified with the suffix "2". The structures and functions of the TX unit 1, the RX unit 1, the TX unit 2, and the RX unit 2 can be referred to the embodiments shown in Figure 3B , Figure 5A , Figure 5B and Figure 10A for details, which will not be described here again to avoid repetition.

[0210] In the embodiment shown in Figure 10A , the CPU 1 in chip 1 sends a req message to the NVMe_2 in chip 2, and the decoder 1 successfully writes the req message into the corresponding cache queue in the TX unit 1, which is taken as an example for description. As shown in Figure 10A , the processing flow of the req message includes:

[0211] The CPU 1 in chip 1 sends a req message to the message bus 1 through the CPU 1 agent ( Figure 10A (4.1) instructions).

[0212] In response to receiving a req message from message bus 1, forward decoder 1 sends the req message to pseudo-response generation unit 1. Figure 10A (4.2) instructions).

[0213] In response to the req message sent by the receive-forward decoder 1, the pseudo-response generation unit 1 sends the req message to the decoder 1. Figure 3A (4.3) instructions).

[0214] Decoder 1, in response to receiving the req message from pseudo-response generation unit 1, writes the req message into the cache queue corresponding to CPU 1 in TX unit 1 (e.g., Figure 5A , Figure 10A Middle queue 1)( Figure 10A (4.4) instructions).

[0215] In response to decoder 1 successfully writing the req message into queue 1 of TX unit 1, pseudo-response generation unit 1 generates pseudo-response message 1 and sends it to message arbitrator 1. Figure 10A (4.5) instructions).

[0216] In response to receiving pseudo-response message 1 from pseudo-response generation unit 1, message arbitrator 1 sends pseudo-response message 1 to message bus 1. Figure 10A (4.6) instructions).

[0217] CPU1 agent receives pseudo-response message 1 from message bus 1 and sends it to CPU1 ( Figure 10A (4.7) Instructions). Upon receiving the pseudo response message 1, CPU1 assumes that the previously sent req message has been successfully received. It is understandable that the actual recipient of the req message (NVMe_2) may not have received the req message at this time, but it will eventually receive the req message.

[0218] The TX unit retrieves the req message from queue 1 and sends an AXI write transaction to inter-chip interconnection unit agent 1. Figure 10A (4.8) indicates this. It is understandable that the process of TX unit 1 sending the AXI write transaction to the inter-chip interconnection unit agent 1 and the process of pseudo-response generation unit 1 generating pseudo-response message 1 are independent of each other. TX unit 1 does not need to wait for the pseudo-response generation unit to generate pseudo-response message 1. Although (4.8) indicates the AXI write transaction and (4.7) indicates the pseudo-response message 1 in the figure, it does not mean that the occurrence of the AXI write transaction is necessarily later than the CPU 1 receiving the pseudo-response message 1.

[0219] The inter-chip interconnect unit 1 sends data (denoted as data 8) representing an AXI write transaction to the inter-chip interconnect unit 2 Figure 10A as indicated in (4.9).

[0220] The inter-chip interconnect unit 2, in response to receiving the data 8 sent by the inter-chip interconnect unit, sends an AXI write transaction carrying the data 8 to the RX unit 2 Figure 3A as indicated in (4.10).

[0221] The RX unit 2, in response to receiving the AXI write transaction sent by the inter-chip interconnect unit 2, converts the data 8 carried by the AXI write transaction into a req message, writes the req message into a cache queue (e.g. Figure 5A , Figure 10A queue 10) corresponding to the CPU 1, and sends an AXI write response transaction to the inter-chip interconnect unit 2 Figure 10A as indicated in (4.11).

[0222] The arbiter 2, in response to obtaining the req message from the queue 10, sends the req message to the message receiving unit 2 Figure 10A as indicated in (4.12). It can be understood that the obtaining of the req message indicated in (4.11) does not have to be later than the transmission of the AXI write response transaction indicated in (4.10).

[0223] The message receiving unit 2, in response to receiving the req message sent by the arbiter 2, sends the req message to the message arbiter 2 Figure 10A as indicated in (4.13).

[0224] The message arbiter 2, in response to receiving the req message sent by the message receiving unit 2, sends the req message to the message bus 2 Figure 10A as indicated in (4.14). The req message carries an identifier of a receiving party, such as the ID of NVMe_2.

[0225] The NVMe agent 2 obtains the req message from the message bus 2 and sends it to the NVMe_2 Figure 10B as indicated in (4.15).

[0226] Figure 10B A schematic diagram of the processing flow of the req message is shown. In the embodiment shown in Figure 10B , an example is taken in which the req message is not successfully written into the corresponding cache queue of the TX unit 1 by the decoder 1.

[0227] As shown in Figure 10B , the processing flow of the req message includes:

[0228] In chip 1, CPU1 sends a req message to message bus 1 through CPU1 agent. Figure 10B (5.1) instructions).

[0229] In response to receiving a req message from message bus 1, forward decoder 1 sends the req message to pseudo-response generation unit 1. Figure 10B (5.2) instructions).

[0230] In response to the req message sent by the receive-forward decoder 1, the pseudo-response generation unit 1 sends the req message to the decoder 1. Figure 10B (5.3) instructions).

[0231] Decoder 1, in response to receiving the req message sent by pseudo-response generation unit 1, attempts to write the req message into queue 1 corresponding to CPU1 in TX unit 1, but the write fails.

[0232] In response to the decoder 1's failure to successfully write the req message into queue 1 of TX unit 1, pseudo-response generation unit 1 generates pseudo-response message 2 and sends it to message arbitrator 1. Figure 10A (5.4) instructions).

[0233] In response to receiving the pseudo-response message 2 sent by the pseudo-response generation unit 1, message arbitrator 1 sends the pseudo-response message 1 to message bus 2. Figure 10A (5.5) instructions).

[0234] CPU1 agent receives pseudo-response message 2 from message bus 1 and sends it to CPU1 ( Figure 10C (5.6) Instruction). CPU1 responds to receiving the spurious response message 2 and knows that the req message was not successfully sent.

[0235] Figure 10A This diagram illustrates the flow of chip 2 responding to the received req message. Figure 10C In the illustrated embodiment, NVMe_2 in chip 2 receives a `req` message sent by CPU1 in chip 1. In response, NVMe_2 generates a corresponding `ack` message. Figure 10C As shown, the processing flow diagram of chip 2 includes:

[0236] In response to receiving the req message from CPU1 in chip 1, NVMe_2 generates an ack message according to the same processing method in the background art, and sends the ack message to message bus 2 through NVMe agent 2. Figure 10C (6.1) instructions).

[0237] Forwarder-decoder 2 responds to receiving an ACK message from message bus 2. Figure 10C (6.2) indicates that the ACK message should be discarded. Alternatively, the forwarding decoder 2 may discard the ACK message in response to receiving it from the message bus 2. Figure 10C (6.1) indicates that the ack message will be sent to message receiving unit 2. Figure 10A (6.3) instructions).

[0238] In response to receiving an ack message sent by forwarding decoder 2, message receiving unit 2 either does not process the ack message or discards the ack message.

[0239] refer to Figure 10B , Figure 10C and Figure 11 In this embodiment of the application, after the sender sends the `req` message and before receiving the `ack` message from the receiver, the sender's own inter-chip interconnect unit generates a pseudo-response message and provides it to the component that sent the `req` message. Upon receiving the pseudo-response message, the component that sent the `req` message can confirm the completion of message communication in advance, thereby shortening the sender's waiting time without adding complex task scheduling logic.

[0240] Figure 11 This illustration shows a flowchart of an electronic device processing req and ack messages according to another embodiment of this application. Figure 11 As shown, the electronic device includes chip 1 and chip 2. Components and functional modules in chip 1 are identified by the suffix "1", and components and functional modules in chip 2 are identified by the suffix "2". For example, chip 1 includes an inter-chip interconnection unit agent 1, which includes TX unit 1, RX unit 1, decoder 1, arbitrator 1, pseudo-response generation unit 1, forwarding decoder 1, message receiving unit 1, and message arbitrator 1. TX unit 1 includes a master device quota management unit 1, an AXI master device interface 1, a master device read transaction unit 1, a queue scheduling unit 1, and queue 1 (…). Figure 11 An example of a cache queue is shown, but the number of cache queues included in TX unit 1 is the same as the number of components of the messaging system coupled to message bus 1. RX unit 1 includes a slave device quota management unit 1, an AXI slave device interface 1, a slave device read transaction response unit 1, a data scheduling unit 1, and queue 4 ( Figure 11 An example of a buffer queue is shown, but the number of buffer queues included in RX unit 1 is the same as the number of components of the messaging system coupled to message bus 2.

[0241] Chip 2 includes an inter-chip interconnect unit agent 2, which includes a TX unit 2, an RX unit 2, a decoder 2, an arbiter 2, a fake response generation unit 2, a forwarding decoder 2, a message receiving unit 2, a message arbiter 2. TX unit 2 includes a master credit management unit 2, an AXI master interface 2, a master read transaction unit 2, a queue scheduling unit 2, and a queue 7 Figure 11 One cache queue is exemplarily shown, but the number of cache queues included in TX unit 2 is the same as the number of components of the message system coupled to message bus 2). RX unit 2 includes a slave credit management unit 2, an AXI slave interface 2, a slave read transaction response unit 2, a data scheduling unit 2, and a queue 10 Figure 4A One cache queue is exemplarily shown, but the number of cache queues included in RX unit 2 is the same as the number of components of the message system coupled to message bus 1).

[0242] Referring to Figure 4B , Figure 6 , Figure 10A , Figure 10C and Figure 6 , the message communication process between chip 1 and chip 2 includes:

[0243] CPU 1 in chip 1 sends a req message to message bus 1 through CPU agent 1 (as an example, the receiver of the message is NVMe_2) (refer to Figure 10A (3.1)).

[0244] Forwarding decoder 1 sends the req message to fake response generation unit 1 in response to obtaining the req message from message bus 1 (refer to Figure 10A (4.2)).

[0245] Fake response generation unit 1 sends the req message to decoder 1 in response to receiving the req message sent by forwarding decoder 1 (refer to Figure 10A (4.3)).

[0246] Decoder 1 writes the req message sent by fake response generation unit 1 into queue 1 corresponding to CPU 1 in TX unit 1 in response to receiving the req message (refer to Figure 6 (4.4) or Figure 10A (3.2)).

[0247] Fake response generation unit 1 generates a fake response message 1 in response to decoder 1 successfully writing the req message into queue 1 in TX unit 1, and sends the fake response message 1 to message arbiter 1 (refer to Figure 6 (4.5)).

[0248] The queue scheduling unit 1 acquires the req message from the queue 1, and generates data (denoted as data 5) conforming to the AXI bus format, and provides the generated data 1 to the AXI master interface 1 (refer to Figure 6 (3.3)) so that the AXI master interface 1 generates an AXI write transaction based on the data 5.

[0249] Before the AXI master interface 1 sends the AXI write transaction, the master credit management unit 1 queries whether the credit value it manages corresponding to the sender (CPU 1) of the req message is greater than or equal to a preset value. The master credit management unit 1 instructs the AXI master interface 1 to send an AXI write transaction to the inter-chip interconnection unit 1 (refer to Figure 6 (3.13)) in response to the credit value it manages (e.g., corresponding to the queue 10) being greater than or equal to the preset value. For the case where the credit value managed by the master credit management unit 1 is less than the preset value, the operations (3.4)-(3.12) in Figure 6 may be referred to for brevity.

[0250] The AXI master interface sends an AXI write transaction to the inter-chip interconnection unit 1 (refer to Figure 10A (3.14)). The master credit management unit 1 updates the credit value corresponding to the queue 10 in response to the AXI master interface sending the AXI write transaction, e.g., deducts the credit value required for sending the AXI write transaction.

[0251] The message arbiter 1 sends the pseudo response message 1 sent by the pseudo response generation unit 1 to the message bus 1 (refer to Figure 10A (4.6)) in response to receiving the pseudo response message 1.

[0252] The CPU 1 proxy acquires the pseudo response message 1 from the message bus 1 and sends it to the CPU 1 (refer to Figure 4A (4.7) for instructions). The CPU 1 considers that the req message it previously sent has been successfully received in response to receiving the pseudo response message 1.

[0253] The process of transmitting the req message to NVMe_2 next is consistent with the processing process shown in Figure 10A or Figure 10C for brevity.

[0254] The NVMe_2 generates an ack message according to the same processing manner in the background art in response to receiving the req message sent by the CPU 1 in chip 1, and sends the ack message to the message bus 2 through the NVMe proxy 2 (refer to Figure 10C (6.1)).

[0255] The forwarding decoder 2 discards the ack message in response to having fetched the ack message from the message bus 2 (cf. (6.2) in Fig. 6). Alternatively, the forwarding decoder 2 sends the ack message to the message receiving unit 2 in response to having fetched the ack message from the message bus 2 (cf. (6.1) in Fig. 6). Figure 10C Figure 10C ​

[0256] The message receiving unit 2 does not process the ack message in response to having received the ack message sent by the forwarding decoder 2, or the message receiving unit 2 discards the ack message.

[0257] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the preferred embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to encompass within their scope all such variations and modifications as are included within the scope of the application. It should be apparent that the application is not limited to the specific embodiments described herein, but can be practiced with modification within the scope of the application. Accordingly, the specification is to be regarded as merely illustrative of the broad application and the scope of the application is indicated by the appended claims, rather than by the foregoing description.​​​< / addr>

Claims

1. An inter-chip interconnect unit proxy, comprising: The chip interconnect unit agent is coupled with a message bus and a chip interconnect unit for coupling a local chip with a remote chip; The chip interconnect unit agent, in response to obtaining a request message from the message bus, generates a pseudo response message and sends the pseudo response message to the message bus to send the pseudo response message to a sender of the request message, wherein the pseudo response message replaces a response message generated and sent by a receiver of the message to the sender of the message in response to receiving the request message; The chip interconnect unit agent, in response to obtaining a request message from the message bus, sends the request message to the chip interconnect unit to send the request message to a remote chip, wherein a sender of the request message is located at a local chip and coupled to the message bus, a receiver of the request message is located at a remote chip, and the request message and the response message are messages defined by a transmission protocol of the message bus.

2. The chip interconnect unit agent of claim 1, wherein The chip interconnect unit agent, in response to obtaining a response message from the message bus, does not process or discard the response message.

3. The inter-chip interconnect unit proxy of claim 2, wherein, The chip interconnect unit agent comprises a pseudo response generation unit; The pseudo response generation unit, in response to the chip interconnect unit agent obtaining a request message from the message bus, generates a pseudo response message and sends the pseudo response message to the message bus to send the pseudo response message to a sender of the request message.

4. The inter-chip interconnect unit proxy of claim 3, wherein, The chip interconnect unit agent further comprises a forwarding decoder, which is coupled with the message bus and the pseudo response generation unit respectively; The forwarding decoder, in response to obtaining a request message from the message bus, sends the request message to the pseudo response generation unit; The forwarding decoder, in response to obtaining a response message from the message bus, does not process or discard the response message. The chip interconnect unit agent further comprises a message arbiter, which is coupled with the pseudo response generation unit and the message bus respectively; 5. The chiplet interconnect unit agent of claim 3 or 4, wherein, The pseudo response generation unit sends the generated pseudo response message to the message arbiter, and the message arbiter, in response to receiving the pseudo response message, sends the pseudo response message to the message bus to send the pseudo response message to a sender of the request message; The message arbiter, in response to receiving a request message, sends the request message to the message bus. The chip interconnect unit agent further comprises a message receiving unit, which is coupled with the forwarding decoder and the message arbiter respectively; The forwarding decoder, in response to obtaining a response message from the message bus, sends the response message to the message receiving unit; 6. The inter-chip interconnect unit agent of claim 5, wherein, The message receiving unit, in response to receiving the response message, does not process or discard the response message; The message receiving unit, in response to receiving the response message, does not process or discard the response message; ​ ​ The message receiving unit sends the request message to the message arbitrator in response to receiving the request message.

7. The chiplet interconnect unit agent of any of claims 1-6, wherein, The chip-to-chip interconnection unit agent further comprises a master device quota management unit; In response to the chip-to-chip interconnection unit agent sending a first message to the chip-to-chip interconnection unit, the master device quota management unit queries whether the quota managed by the master device quota management unit meets a preset condition; In response to the quota meeting the preset condition, the chip-to-chip interconnection unit agent sends the first message to the chip-to-chip interconnection unit to send the first message to a remote chip; wherein the sender of the first message is located in a local chip and is coupled to the message bus, the receiver of the first message is a remote chip, and the quota is used to indicate the idle amount of resources in the remote chip for processing the first message.

8. A chip, characterized by The chip comprises the chip-to-chip interconnection unit agent, the message bus and the chip-to-chip interconnection unit according to any one of claims 1-7.

9. A data processing system, characterized by The data processing system comprises a first chip and a second chip; The first chip comprises a first message bus, a first chip-to-chip interconnection unit agent, a first chip-to-chip interconnection unit and at least one first component, the at least one first component is coupled to the first message bus, and the first chip-to-chip interconnection unit agent is coupled to the first message bus and the first chip-to-chip interconnection unit respectively; The second chip comprises a second message bus, a second chip-to-chip interconnection unit agent, a second chip-to-chip interconnection unit and at least one second component, the at least one second component is coupled to the second message bus, and the second chip-to-chip interconnection unit agent is coupled to the second message bus and the second chip-to-chip interconnection unit respectively; The first chip-to-chip interconnection unit is coupled to the second chip-to-chip interconnection unit; In the case that the first chip-to-chip interconnection unit agent obtains a request message from the first message bus, the first chip-to-chip interconnection unit agent generates a pseudo response message and sends the pseudo response message to the first message bus to send the pseudo response message to the sender of the request message; In the case that the second chip-to-chip interconnection unit agent obtains a request message from the second message bus, the second chip-to-chip interconnection unit agent generates a pseudo response message and sends the pseudo response message to the second message bus to send the pseudo response message to the sender of the request message, wherein the pseudo response message replaces the response message generated by the receiver of the message in response to receiving the request message and sent to the sender of the message, and the request message and the response message are messages defined by the transmission protocol of the message bus.

10. A method of cross-chip communication, the method comprising: The application is applied to a first chip and a second chip, the first chip comprises a first message bus, a first chip-to-chip interconnection unit agent, a first chip-to-chip interconnection unit and at least one first component, the at least one first component is coupled to the first message bus, and the first chip-to-chip interconnection unit agent is coupled to the first message bus and the first chip-to-chip interconnection unit respectively; The second chip comprises a second message bus, a second chip-to-chip interconnection unit agent, a second chip-to-chip interconnection unit and at least one second component, the at least one second component is coupled with the second message bus, the second chip-to-chip interconnection unit agent is coupled with the second message bus and the second chip-to-chip interconnection unit respectively; The first chip-to-chip interconnection unit is coupled with the second chip-to-chip interconnection unit; The method comprises: The first component sends a request message to the first message bus; The first chip-to-chip interconnection unit agent generates a pseudo response message in response to obtaining the request message from the first message bus, sends the pseudo response message to the first message bus, and sends the pseudo response message to the sender of the request message; And the first chip-to-chip interconnection unit agent sends the request message to the first chip-to-chip interconnection unit; The first chip-to-chip interconnection unit sends the request message to the second chip-to-chip interconnection unit in response to receiving the request message; The second chip-to-chip interconnection unit sends the request message to the second chip-to-chip interconnection unit agent in response to receiving the request message; The second chip-to-chip interconnection unit agent sends the request message to the second message bus in response to receiving the request message; The second component obtains the request message from the second message bus.

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