Sysml-based design method and apparatus for resistive superconducting current limiter

Abstract

The application discloses a kind of resistance type superconducting current limiter design method and device based on SysML, the method comprises the following steps: S1, the design requirement of resistance type superconducting current limiter is obtained and requirement analysis is carried out;S2, according to design requirement, the function logic architecture of resistance type superconducting current limiter is analyzed;S3, the physical architecture of resistance type superconducting current limiter is obtained by converting through design parameter and function logic architecture;S4, the design result of resistance type superconducting current limiter is output and obtained by physical architecture and the set thermoelectric analogy algorithm.The application solves the technical problems that the complexity of finite element simulation and numerical simulation in the prior art is too high, and the design process requirement analysis and architecture design are insufficient, can quickly design resistance type superconducting current limiter and improve the accuracy and consistency of its design result.

Description

Technical Field

[0001] This invention belongs to the field of data processing technology of next-generation information technology, and specifically relates to a design method and device for a resistive superconducting current limiter based on SysML. Background Technology

[0002] Resistive superconducting current limiters utilize the principle of quenching failure caused by phase transition in superconducting tape to suppress short-circuit fault currents in the power grid. They are characterized by minimal impact on the power grid, fast response speed, and strong current limiting effect, and are widely used in the power industry. Common design methods for resistive superconducting current limiters mainly include finite element simulation and mathematical model simulation. Finite element simulation uses multiphysics simulation software such as COMSOL to construct an electrothermal coupling model of the resistive superconducting current limiter coil, simulating the current impact process under short-circuit faults and calculating key design parameters such as temperature distribution, resistance change, and voltage-current change of the superconducting tape. Mathematical model simulation uses tools such as Matlab / Simuink to construct simulation models such as resistance-unit heat and electric field strength-current density exponent, analyzing changes in parameters such as peak current, current limiting impedance, and temperature change.

[0003] However, existing design methods for resistive superconducting current limiters have the following drawbacks: (1) Finite element simulation takes too long, and the finite element simulation software is difficult to couple with the power system; (2) The joint simulation of mathematical model simulation software and circuit simulation software is too complex and takes a relatively long time, making it impossible to quickly analyze the superconducting quench and recovery characteristics under different short-circuit currents; (3) The design process does not start from system-level requirements, refine and decompose downwards, and compare and verify the design results with the requirements. Overall, existing design methods focus on the physical characteristic analysis of resistive superconducting current limiters, the simulation process is complex and time-consuming, and the requirements decomposition and architecture design are insufficient, making it difficult to meet the accuracy and consistency requirements of resistive superconducting current limiter system design involving multiple fields, multiple levels, and multiple stages. In summary, there is room for improvement in existing technologies. Summary of the Invention

[0004] This invention provides a SysML-based design method and apparatus for resistive superconducting current limiters, which at least solves the technical problems of excessive complexity in finite element simulation and numerical simulation, and insufficient requirements analysis and architecture design in the design process.

[0005] According to one aspect of the present invention, a design method for a resistive superconducting current limiter based on SysML is provided, comprising the following steps: S1, obtaining the design requirements of the resistive superconducting current limiter and conducting requirement analysis; S2, based on the design requirements, analyzing the relationship between the resistive superconducting current limiter and the external environment through use case diagrams in SysML, analyzing the operational flow of the resistive superconducting current limiter through activity diagrams in SysML, and analyzing the functional logic architecture of the resistive superconducting current limiter through module definition diagrams in SysML; S3, analyzing the physical architecture and physical parameters of the resistive superconducting current limiter through module definition diagrams in SysML, based on the design parameters and functional logic architecture; S4, using the physical architecture and the established thermoelectric analogy algorithm, outputting the resistance-time curve, the limiting current-time curve, the voltage-time curve, and the temperature-time curve of the resistive superconducting current limiter.

[0006] Furthermore, the functional logic architecture includes a superconducting current limiting unit, a cryogenic refrigeration system, a high-voltage output unit, and an online monitoring system. The physical architecture is generated using a module definition diagram. The superconducting current limiting unit consists of a substrate layer, BSCCO-2212 superconducting tape, a metal connection layer, and a Cu-Ni shunt resistor. The cryogenic refrigeration system consists of liquid nitrogen and a liquid nitrogen storage tank. The high-voltage output unit consists of current limiting unit electrodes and a high-voltage insulating bushing. The online monitoring system consists of a temperature sensor and a control cabinet.

[0007] Furthermore, in step S1, the design requirements are obtained by importing CSV or Excel files, and the requirements analysis is conducted by constructing a requirements analysis model using a requirements diagram.

[0008] Furthermore, in step S4, the resistance of the resistive superconducting current limiter in the thermoelectric analogy algorithm... The expression is:

[0009]

[0010] Where l is the length of the resistive superconducting current limiter. , , These represent the width, thickness, and resistivity of the superconducting tape, respectively. ( , Critical electric field strength of superconducting layer , It is the current in the superconducting tape. It is the superconducting critical current, T sp It is the temperature of the superconducting tape, T c It is the critical temperature, and n is the characteristic constant of the superconducting tape; , , These are the width, thickness, and resistivity of the shunt resistor, respectively. , , These are the width, thickness, and resistivity of the substrate layer, respectively. , , These represent the width, thickness, and resistivity of the metal interconnect layer, respectively.

[0011] Furthermore, in step S4, the short-circuit current I in the thermoelectric analogy algorithm t The calculation expression is:

[0012]

[0013] Among them, V o It is the grid voltage, R c L c These are the equivalent resistance and inductance during a power grid short circuit, respectively, and t is the fault current time.

[0014] Furthermore, the temperature calculation expression in the thermoelectric analogy algorithm is as follows:

[0015]

[0016] Among them, the heat capacity of the base layer , It is the mass of the basal layer. It refers to the specific heat capacity of the substrate; the heat capacity of the superconducting tape. , It is the mass ratio of superconducting tape. It refers to the specific heat capacity of the superconducting tape; the heat capacity of the metal bonding layer. , It is the mass of the metal bonding layer. It is the specific heat capacity of the metal bonding layer; the shunt resistance heat capacity. , It is the ratio of shunt resistance to mass. It is the specific heat capacity of the shunt resistor; , , , These are the substrate temperature, superconducting tape temperature, metallic bonding layer temperature, and shunt resistance temperature; superconducting tape power. , It is the superconducting tape current; the metal interconnect layer power. , It is the current in the metal interconnect layer; the power of the shunt resistor. , It is the shunt resistor current; It is the temperature of liquid nitrogen; , , , , , The first proportionality coefficient, This is the second proportionality coefficient. The third proportionality coefficient, It is the fourth proportionality coefficient. h is the fifth proportionality coefficient. c It is the convective heat transfer coefficient. , , , These are the thermal conductivity of the substrate, the thermal conductivity of the superconducting tape, the thermal conductivity of the metal bonding layer, and the thermal conductivity of the shunt resistance.

[0017] Furthermore, the workflow of the resistive superconducting current limiter, as determined by the activity diagram analysis, includes: when a short-circuit fault occurs during normal grid operation, the resistive superconducting current limiter detects the short-circuit current and determines whether the short-circuit current exceeds the threshold current; when the threshold current is exceeded, the resistive superconducting current limiter triggers a quench phase transition, and the resistance of the superconducting current limiting unit increases to suppress the short-circuit current; when the grid returns to normal, the resistive superconducting current limiter returns to the superconducting state.

[0018] Furthermore, the physical parameters include the length l of the resistive superconducting current limiter and the width of the superconducting tape. The thickness of the superconducting tape Width of the base layer Thickness of the base layer , width of shunt resistor Thickness of shunt resistor Width of the metal bonding layer Thickness of the metal bonding layer Peak grid voltage V m , grid voltage frequency f, grid voltage phase The equivalent resistance R during a power grid short circuit c The equivalent inductance L during a power grid short circuit c liquid nitrogen temperature Fault current time t.

[0019] According to another aspect of the present invention, a SysML-based resistive superconducting current limiter design device is provided, comprising:

[0020] The requirements elicitation and analysis module is used to convert CSV and Excel files into requirements analysis models in the requirements diagram.

[0021] The Functional Logic Architecture Analysis Module is used to generate a functional logic architecture model of the resistive superconducting current limiter using use case diagrams, activity diagrams, and module definition diagrams in SysML, and to analyze the relationship between the resistive superconducting current limiter and the external environment and its workflow.

[0022] The physical architecture analysis module is used to generate a physical architecture model of a resistive superconducting current limiter from a module definition diagram, including the physical architecture components and physical parameters.

[0023] The simulation demonstration module is used to output the design results of the resistive superconducting current limiter, including the current limiting curve, temperature change curve, resistance change curve and voltage change curve.

[0024] According to another aspect of the present invention, an electronic device is provided, characterized in that it includes a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that the processor executes the computer program to implement the SysML-based resistive superconducting current limiter design method as described above.

[0025] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a processing program is stored, which, when executed by a processor, implements the SysML-based resistive superconducting current limiter design method as described above.

[0026] The SysML-based resistive superconducting current limiter design method and apparatus provided by this invention can include the following beneficial effects: (1) By applying the SysML-based resistive superconducting current limiter design method and apparatus, according to design requirements, the relationship between the resistive superconducting current limiter and the external environment is analyzed through use case diagrams in SysML, the working process of the resistive superconducting current limiter is analyzed through activity diagrams in SysML, and the functional logic architecture of the resistive superconducting current limiter is analyzed through module definition diagrams in SysML; through design parameters and functional logic architecture, through The module definition diagram in SysML analyzes the physical architecture and physical parameters of the resistive superconducting current limiter; through the physical architecture and the set thermoelectric analogy algorithm, the design results of the resistive superconducting current limiter are output, which can realize the rapid design of the resistive superconducting current limiter system-subsystem-equipment level multi-level, demand-function-logic-physical multi-stage, electrical-thermal-materials multi-disciplinary; (2) the design process is driven by the system requirements of the resistive superconducting current limiter, and the design results are used to check whether the system requirements are met, which can improve the accuracy and consistency of the design results.

[0027] Furthermore, additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings. These illustrative embodiments and their descriptions are intended to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0029] Figure 1 This is a flowchart of a SysML-based resistive superconducting current limiter design method according to an embodiment of the present invention;

[0030] Figure 2 This is a demand analysis diagram of a resistive superconducting current limiter according to an embodiment of the present invention;

[0031] Figure 3 This is an analysis diagram of a resistive superconducting current limiter according to an embodiment of the present invention;

[0032] Figure 4 This is a flowchart illustrating the working process of a resistive superconducting current limiter according to an embodiment of the present invention.

[0033] Figure 5 This is a logic architecture diagram of a resistive superconducting current limiter according to an embodiment of the present invention;

[0034] Figure 6 This is a diagram of the physical architecture of a resistive superconducting current limiter according to an embodiment of the present invention;

[0035] Figure 7 These are two diagrams illustrating the physical architecture of a resistive superconducting current limiter according to an embodiment of the present invention;

[0036] Figures 8a to 8d This is a design result diagram of a resistive superconducting current limiter according to an embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram of the composition structure of a resistive superconducting current limiter design device according to an embodiment of the present invention.

[0038] Figure 10 This is a schematic diagram of the composition structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0039] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them.

[0040] The following is for reference. Figure 1 This paper describes a SysML-based design method for a resistive superconducting current limiter according to embodiments of the present invention. Figure 1 As shown, the SysML-based resistive superconducting current limiter design method according to an embodiment of the present invention includes the following steps:

[0041] S1. Obtain the design requirements for the resistive superconducting current limiter and conduct a requirements analysis.

[0042] S2. Based on the design requirements, analyze the functional logic architecture of the resistive superconducting current limiter;

[0043] S3, through design parameters and functional logic architecture, transforms to obtain the physical architecture of the resistive superconducting current limiter;

[0044] S4 outputs the design results of the resistive superconducting current limiter through the physical architecture and the set thermoelectric analogy algorithm.

[0045] The SysML-based design method for resistive superconducting current limiters according to the present invention enables rapid design of resistive superconducting current limiters and improves the accuracy and consistency of the design results.

[0046] According to an embodiment of the SysML-based design method for resistive superconducting current limiters, in step S1, the functional and performance requirements of the resistive superconducting current limiter are obtained by importing CSV and Excel files, such as... Figure 2 As shown.

[0047] Specifically, the functional requirements of the resistive superconducting current limiter include fault current detection, fast quench triggering, and fault current suppression, with ID numbers FR-01, FR-02, and FR-03, respectively. Among them, fault current detection requires real-time monitoring of grid current and identification of short-circuit fault events; fast quench triggering requires triggering the superconducting strip to quench when a fault occurs, realizing a resistance jump; and fault current suppression requires generating high impedance in the quench state to suppress the peak fault current.

[0048] Specifically, the performance requirements for resistive superconducting current limiters include response time, current limiting effect, and thermal stability, with ID numbers PR-01, PR-02, and PR-03, respectively. The response time requirement is less than 5ms from the detection of a short circuit to the establishment of the current limiting impedance; the current limiting effect requirement is that the peak current limiting value during a fault is suppressed by more than 60%; and the thermal stability requirement is that the maximum temperature of the superconducting tape during a short circuit is less than 300K.

[0049] According to an embodiment of the present invention, the SysML-based design method for resistive superconducting current limiters includes, in step S2, analyzing the relationship between the resistive superconducting current limiter and the external environment through use case diagrams, analyzing the working process of the resistive superconducting current limiter through activity diagrams, and analyzing the logical composition architecture of the resistive superconducting current limiter through module definition diagrams.

[0050] Specifically, use case diagram analysis reveals an interaction between the resistive superconducting current limiter and the power grid. The power grid short-circuit current limiting use case can be further subdivided into cryogenic environment maintenance, fault current detection, and short-circuit current limiting, such as... Figure 3 As shown.

[0051] Specifically, the workflow of the resistive superconducting current limiter, as determined by activity diagram analysis, includes: When a short-circuit fault occurs during normal grid operation, the resistive superconducting current limiter detects the short-circuit current and determines whether it exceeds a threshold current. When the threshold current is exceeded, the resistive superconducting current limiter triggers a quench phase transition, and the resistance of the superconducting current-limiting unit increases to suppress the short-circuit current. When the grid returns to normal, the resistive superconducting current limiter returns to its superconducting state, as... Figure 4 As shown.

[0052] Furthermore, the logical architecture of the resistive superconducting current limiter is obtained through the module definition diagram, including the superconducting current limiting unit, the cryogenic refrigeration system, the high-voltage output unit, and the online monitoring system, such as... Figure 5 As shown.

[0053] According to an embodiment of the present invention, a SysML-based design method for resistive superconducting current limiters generates the physical architecture of the resistive superconducting current limiter in step S3 by using specific design parameters and functional logic architecture.

[0054] Specifically, the design parameters in the SysML-based resistive superconducting current limiter design method of one embodiment of the present invention are described in detail with reference to Table 1, as shown in Table 1:

[0055] Table 1

[0056]

[0057] Furthermore, based on the specific design parameters and functional logic architecture described above, a physical architecture is generated using a module definition diagram, such as... Figure 6 As shown. The superconducting current-limiting unit consists of a substrate layer, BSCCO-2212 superconducting tape, a metal connecting layer, and a Cu-Ni shunt resistor. The cryogenic refrigeration system consists of liquid nitrogen and a liquid nitrogen storage tank. The high-voltage output unit consists of current-limiting unit electrodes and a high-voltage insulating bushing. The online monitoring system consists of a temperature sensor and a control cabinet.

[0058] Furthermore, the physical parameters in the physical architecture, such as the length l of the resistive superconducting current limiter and the width of the superconducting tape, are... The thickness of the superconducting tape Width of the base layer Thickness of the base layer , width of shunt resistor Thickness of shunt resistor Width of the metal bonding layer Thickness of the metal bonding layer Peak grid voltage V m , grid voltage frequency f, grid voltage phase The equivalent resistance R during a power grid short circuit c The equivalent inductance L during a power grid short circuitc liquid nitrogen temperature The fault current time t is used as the input to the thermoelectric analogy algorithm, such as... Figure 7 As shown.

[0059] Furthermore, the resistance of the resistive superconducting current limiter was calculated:

[0060]

[0061] Among them, the resistivity of the shunt resistor Substrate resistivity resistivity of metal bonding layer Superconducting tape resistivity ( , Characteristic constant n of superconducting tape, critical electric field strength of superconducting layer Superconducting critical current Critical temperature T c Superconducting tape temperature T sp All of these have been pre-set in the thermoelectric analogy algorithm and do not need to be used as input.

[0062] Furthermore, the short-circuit current I of the resistive superconducting current limiter was calculated. t :

[0063]

[0064] The temperature of the resistive superconducting current limiter was calculated as follows:

[0065]

[0066] Among them, the heat capacity of the base layer , It is the mass of the basal layer. It refers to the specific heat capacity of the substrate; the heat capacity of the superconducting tape. , It is the mass ratio of superconducting tape. It refers to the specific heat capacity of the superconducting tape; the heat capacity of the metal bonding layer. , It is the mass of the metal bonding layer. It is the specific heat capacity of the metal bonding layer; the shunt resistance heat capacity. , It is the ratio of shunt resistance to mass. It is the specific heat capacity of the shunt resistor; , , , These are the substrate temperature, superconducting tape temperature, metallic bonding layer temperature, and shunt resistance temperature; superconducting tape power. , It is the superconducting tape current; the metal interconnect layer power. , It is the current in the metal interconnect layer; the power of the shunt resistor. , It is the shunt resistor current; It is the temperature of liquid nitrogen; , , , , , The first proportionality coefficient, This is the second proportionality coefficient. The third proportionality coefficient, It is the fourth proportionality coefficient. h is the fifth proportionality coefficient. c It is the convective heat transfer coefficient. , , , These are the thermal conductivity of the substrate, the thermal conductivity of the superconducting tape, the thermal conductivity of the metal bonding layer, and the thermal conductivity of the shunt resistor. Besides the external input l, , , , , , , , Apart from that, all other physical quantities have been preset and calculated in the thermoelectric analogy algorithm.

[0067] Furthermore, the resistance versus time curve, the limiting current versus time curve, the voltage versus time curve, and the temperature versus time curve of the resistive superconducting current limiter were obtained, as shown below. Figures 8a to 8d As shown. When a short-circuit fault occurs at t=0s, the resistive superconducting current limiter identifies the short-circuit fault event and quickly triggers the superconducting tape to lose quench, causing a jump in resistance and generating high impedance, which suppresses the fault current peak and meets the functional requirements of FR-01, FR-02, and FR-03.

[0068] Specifically, the resistive superconducting current limiter takes 2ms from detecting a short circuit to establishing the current-limiting impedance, suppressing the original short-circuit current peak from 123kA to 8.4kA with a suppression efficiency of 93%. The resistive superconducting current limiter has a maximum temperature of 110K during the short circuit period, meeting the performance requirements of PR-01, PR-02, and PR-03.

[0069] Therefore, compared with traditional technologies, the SysML-based resistive superconducting current limiter design method of the present invention enables rapid design of resistive superconducting current limiters while improving the accuracy and consistency of the design results with the design requirements.

[0070] This invention also provides a SysML-based design device for a resistive superconducting current limiter, including a requirement acquisition and analysis module 901, a functional logic architecture analysis module 902, a physical architecture analysis module 903, and a simulation demonstration module 904, such as... Figure 9 As shown.

[0071] The module includes: a requirement acquisition and analysis module 901, which converts CSV and Excel files into requirement analysis models in the requirement diagram; a functional logic architecture analysis module 902, which generates a functional logic architecture model of the resistive superconducting current limiter through use case diagrams and activity diagrams, and analyzes the relationship between the resistive superconducting current limiter and the external environment and its workflow; a physical architecture analysis module 903, which generates a physical architecture model of the resistive superconducting current limiter through module definition diagrams, including physical architecture components and physical parameters; and a simulation demonstration module 904, which outputs the design results of the resistive superconducting current limiter, including but not limited to current limiting curves, temperature change curves, and resistance change curves.

[0072] On the other hand, the present invention also provides an electronic device, such as Figure 10 As shown. The electronic device includes a processor 1001, a communication bus 1002, a display screen 1003, a memory 1004, and a communication interface 1005. The processor 1001 provides computational and control capabilities for the SysML-based resistive superconducting current limiter design method. The communication bus 1002 provides a communication channel for the processor 1001, display screen 1003, memory 1004, and communication interface 1005. The display screen 1003 is a liquid crystal display (LCD) or an e-ink display screen, used to display the design results output by the SysML-based resistive superconducting current limiter design method. The memory 1004 includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs, and the internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface 1005 is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi or other technologies.

[0073] In another aspect, the present invention also provides a computer-readable storage medium having a processing program stored thereon, which, when executed by a processor, implements the steps in the SysML-based resistive superconducting current limiter design method as described in any of the preceding claims.

[0074] In summary, the SysML-based design method and device for resistive superconducting current limiters can achieve rapid design across multiple levels (system-subsystem-equipment), multiple stages (requirement-function-logic-physics), and multiple disciplines (electrical-thermal-materials). By driving the design process through the requirements of the resistive superconducting current limiter system and verifying whether the system requirements are met through the design results, the accuracy and consistency of the design results can be improved.

[0075] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0076] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A design method for a resistive superconducting current limiter based on SysML, characterized in that, Includes the following steps: S1. Obtain the design requirements for the resistive superconducting current limiter and conduct a requirements analysis. S2. Based on the design requirements, the relationship between the resistive superconducting current limiter and the external environment is analyzed through use case diagrams in SysML, the working process of the resistive superconducting current limiter is analyzed through activity diagrams in SysML, and the functional logic architecture of the resistive superconducting current limiter is analyzed through module definition diagrams in SysML. S3 analyzes the physical architecture and physical parameters of the resistive superconducting current limiter by designing parameters and functional logic architecture and using the module definition diagram in SysML. S4, through the physical architecture and the set thermoelectric analogy algorithm, outputs the resistance-time curve, the limiting current-time curve, the voltage-time curve, and the temperature-time curve of the resistive superconducting current limiter.

2. The design method for a resistive superconducting current limiter based on SysML according to claim 1, characterized in that, The functional logic architecture includes a superconducting current limiting unit, a cryogenic refrigeration system, a high-voltage output unit, and an online monitoring system. The physical architecture is generated using a module definition diagram. The superconducting current limiting unit consists of a substrate layer, BSCCO-2212 superconducting tape, a metal connection layer, and a Cu-Ni shunt resistor. The cryogenic refrigeration system consists of liquid nitrogen and a liquid nitrogen storage tank. The high-voltage output unit consists of current limiting unit electrodes and a high-voltage insulating bushing. The online monitoring system consists of a temperature sensor and a control cabinet.

3. The design method for a resistive superconducting current limiter based on SysML according to claim 2, characterized in that, In step S1, the design requirements are obtained by importing CSV or Excel files, and the requirements analysis is conducted by constructing a requirements analysis model using a requirements diagram.

4. The design method for a resistive superconducting current limiter based on SysML according to any one of claims 1 to 3, characterized in that, In step S4, the resistance of the resistive superconducting current limiter in the thermoelectric analogy algorithm... The expression is: Where l is the length of the resistive superconducting current limiter. , , These represent the width, thickness, and resistivity of the superconducting tape, respectively. ( , Critical electric field strength of superconducting layer , It is the current in the superconducting tape. It is the superconducting critical current, T sp It is the temperature of the superconducting tape, T c It is the critical temperature, and n is the characteristic constant of the superconducting tape; , , These are the width, thickness, and resistivity of the shunt resistor, respectively. , , These are the width, thickness, and resistivity of the substrate layer, respectively. , , These represent the width, thickness, and resistivity of the metal interconnect layer, respectively.

5. The SysML-based resistive superconducting current limiter design method according to claim 4, characterized in that, In step S4, the short-circuit current I in the thermoelectric analogy algorithm t The calculation expression is: , where V o It is the grid voltage, R c L c These are the equivalent resistance and inductance during a power grid short circuit, respectively, and t is the fault current time.

6. The design method for a resistive superconducting current limiter based on SysML according to claim 5, characterized in that, The temperature calculation expression in the thermoelectric analogy algorithm is as follows: Among them, the heat capacity of the base layer , It is the mass of the basal layer. It refers to the specific heat capacity of the substrate; the heat capacity of the superconducting tape. , It is the mass ratio of superconducting tape. It refers to the specific heat capacity of the superconducting tape; the heat capacity of the metal bonding layer. , It is the mass of the metal bonding layer. It is the specific heat capacity of the metal bonding layer; the shunt resistance heat capacity. , It is the ratio of shunt resistance to mass. It is the specific heat capacity of the shunt resistor; , , , These are the substrate temperature, superconducting tape temperature, metallic bonding layer temperature, and shunt resistance temperature; superconducting tape power. , It is the superconducting tape current; the metal interconnect layer power. , It is the current in the metal interconnect layer; the power of the shunt resistor. , It is the shunt resistor current; It is the temperature of liquid nitrogen; , , , , , The first proportionality coefficient, This is the second proportionality coefficient. The third proportionality coefficient, It is the fourth proportionality coefficient. h is the fifth proportionality coefficient. c It is the convective heat transfer coefficient. , , , These are the thermal conductivity of the substrate, the thermal conductivity of the superconducting tape, the thermal conductivity of the metal bonding layer, and the thermal conductivity of the shunt resistance.

7. The design method for a resistive superconducting current limiter based on SysML according to claim 6, characterized in that, The workflow of the resistive superconducting current limiter, as determined by the activity diagram analysis, includes: when a short-circuit fault occurs during normal grid operation, the resistive superconducting current limiter detects the short-circuit current and determines whether the short-circuit current exceeds the threshold current; when the threshold current is exceeded, the resistive superconducting current limiter triggers a quench phase transition, and the resistance of the superconducting current limiting unit increases to suppress the short-circuit current; when the grid returns to normal, the resistive superconducting current limiter returns to the superconducting state.

8. A SysML-based resistive superconducting current limiter design device, characterized in that, include: The requirements elicitation and analysis module is used to convert CSV and Excel files into requirements analysis models in the requirements diagram. The Functional Logic Architecture Analysis Module is used to generate a functional logic architecture model of the resistive superconducting current limiter using use case diagrams, activity diagrams, and module definition diagrams in SysML, and to analyze the relationship between the resistive superconducting current limiter and the external environment and its workflow. The physical architecture analysis module is used to generate a physical architecture model of a resistive superconducting current limiter from a module definition diagram, including the physical architecture components and physical parameters. The simulation demonstration module is used to output the design results of the resistive superconducting current limiter, including the current limiting curve, temperature change curve, resistance change curve and voltage change curve.

9. An electronic device, characterized in that, The device includes a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that when the processor executes the computer program, it implements the SysML-based resistive superconducting current limiter design method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a processing program that, when executed by a processor, implements the SysML-based resistive superconducting current limiter design method as described in any one of claims 1 to 7.

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