Control method of SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory

Abstract

The invention discloses a control method of an SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory. The method comprises the steps that after an erasure instruction is completed, a corresponding block is obtained according to the number of times of power-on; obtaining programmed blocks according to the corresponding blocks; screening out a programming state storage unit in the programmed block; detecting whether the threshold voltage of the programming state storage unit is reduced to be below the verification voltage or not; and determining whether to refresh the data in the SONOS memory or not according to the detection result. The method can effectively solve the problems of data errors and data loss caused by the reduction of the threshold voltage of the storage unit in the SONOS memory, is easy to implement, low in cost and high in refreshing speed, does not need to increase extra storage capacity, and enables the SONOS memory to be longer in data retention time and better in programming interference resistance so as to meet the application requirements of higher specifications.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and more particularly to a control method of a SONOS memory. BACKGROUND

[0002] With the development of big data analysis technology, the demand for data storage and processing is increasing, and therefore the demand for non-volatile memories is also increasing. In non-volatile memories, FLASH memories with SONOS structures are widely used in various electronic products due to their low operating voltage, fast erase-write speed, large capacity, and other advantages. In the existing SONOS memories, the threshold voltage of the storage unit is prone to decrease in the programming state, resulting in errors in the information stored therein.

[0003] Currently, there are mainly two solutions to solve the above problems. One is to optimize the performance of the storage unit from the perspective of process, relying on the physical characteristics of the storage unit itself to ensure the reliability of data storage to a certain extent. However, process optimization requires a long development time and high cost, and when higher operating temperatures or cycle erase-write times are required, it is still difficult to ensure the reliability of data storage, and optimization needs to be performed again. The second is to use an ECC error correction scheme. However, in this scheme, additional storage capacity is required to store the check code in the ECC error correction algorithm, which increases the chip area. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the present application provides a control method of a SONOS memory, which can effectively solve the data errors and data loss caused by the decrease of the threshold voltage of the storage unit in the SONOS memory, is easy to implement and low in cost, has a fast refresh speed and does not require additional storage capacity, makes the data retention time of the SONOS memory longer, and has better anti-programming interference performance to meet higher specification application requirements.

[0005] To achieve the above purpose, the present application provides a control method of a SONOS memory, comprising: obtaining a corresponding block according to the number of power-on after the completion of an erase instruction; obtaining a programmed block according to the corresponding block; screening out a programmed-state storage unit in the programmed block; detecting whether the threshold voltage of the programmed-state storage unit has decreased below a check voltage; and determining whether to refresh the data in the SONOS memory according to the detection result.

[0006] In some embodiments, obtaining the corresponding block according to the number of power-on comprises: setting a non-volatile memory, recording the number of power-on using the non-volatile memory, and obtaining the check address of the corresponding block according to the number of power-on.

[0007] In some embodiments, the power-on number is recorded by using a non-volatile memory, and the corresponding block check address is obtained according to the power-on number, which includes: setting a content addressable memory; loading data in the content addressable memory when the SONOS memory is powered on; judging whether the data in the content addressable memory is full; performing an erase operation on the content addressable memory when the data in the content addressable memory is full; performing an operation on the data in the content addressable memory when the data in the content addressable memory is not full; decoding the data in the content addressable memory to obtain the corresponding block check address.

[0008] In some embodiments, when the content addressable memory is full, the data in the content addressable memory is all 0; when the content addressable memory is empty, the data in the content addressable memory is all 1; when the data in the content addressable memory is all 0, an erase operation is performed on the content addressable memory so that the data in the content addressable memory is all 1; when the data in the content addressable memory is not all 0, the data in the content addressable memory is incremented by 1 so that the data in the content addressable memory is increased by one bit and written as 0.

[0009] In some embodiments, the programmed block is obtained according to the corresponding block, which includes: judging whether the corresponding block is a programmed block; and obtaining the programmed block as the corresponding block when the corresponding block is a programmed block.

[0010] In some embodiments, the programmed block is obtained according to the corresponding block, which includes: taking the corresponding block as a starting block, and screening out a programmed block from the starting block to obtain the programmed block as the first programmed block detected from the corresponding block.

[0011] In some embodiments, the programmed state storage unit in the programmed block is screened out, which includes: reading data in the programmed block by using a read voltage, and if the read data is 1, it indicates that the storage unit is in an erase state; and if the read data is 0, it indicates that the storage unit is in a programmed state.

[0012] In some embodiments, the threshold voltage of the programmed state storage unit is detected whether it has dropped below the check voltage, which includes: setting the check voltage to be greater than the read voltage; reading data of the programmed state storage unit by using the check voltage, and if the read data is 0, it indicates that the threshold voltage of the programmed state storage unit has not dropped below the check voltage; and if the read data is 1, it indicates that the threshold voltage of the programmed state storage unit has dropped below the check voltage.

[0013] In some embodiments, according to the detection result, it is determined whether to refresh the data in the SONOS memory, which includes: refreshing the data in the SONOS memory when there is a programmed state storage unit whose threshold voltage has dropped below the check voltage.

[0014] In some embodiments, the refreshing of the data in the SONOS memory comprises: starting from the first page, using the read voltage to read and re-write data page by page until all the data of all the pages are re-written.

[0015] Compared with the prior art, the above technical solutions conceived by the present application have the following beneficial effects: the check voltage is increased, the check voltage is greater than the read voltage, and the data in the SONOS memory is refreshed after it is detected that the threshold voltage of the storage unit in the programming state is lower than the check voltage; the number of power-on is recorded by using the non-volatile memory, the data in the block corresponding to the address is detected according to the number of power-on, the programmed block is obtained, and the storage unit in the programming state in the block is further screened out; the number of power-on is recorded by using a special count code, and a 0 is written into the count code every time the number is increased by 1, and the number of power-on can be determined according to the number of 0 in the count code, so that the address of the block can be obtained by decoding the count code. The data of the SONOS memory is refreshed when the threshold voltage of the storage unit in the programming state meets certain conditions, effectively solving the problem of threshold voltage reduction of the storage unit caused by programming interference and easily occurring after programming, avoiding data errors and data loss, greatly improving the reliability of the SONOS memory, and meeting the application scenarios with higher requirements. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a typical SONOS memory device structure schematic diagram;

[0017] Figure 2 is a schematic diagram of the embodiment of the present application for monitoring the threshold voltage drop of the storage unit in the programming state by using the check voltage;

[0018] Figure 3 is a flowchart of the control method of the SONOS memory of the embodiment of the present application;

[0019] Figure 4 is a method flowchart of the embodiment of the present application for obtaining the corresponding block according to the number of power-on;

[0020] Figure 5 is a method flowchart of the embodiment of the present application for refreshing the data in the SONOS memory. DETAILED DESCRIPTION

[0021] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0022] As shown in FIG. 1, a typical SONOS memory device includes a plurality of memory cells arranged in a first direction to form a plurality of rows and arranged in a second direction to form a plurality of columns. For example, memory cell Cell0, memory cell Cell1, and other memory cells are arranged in the first direction to form a first row, and memory cell Cell2 and memory cell Cell3, and other memory cells are arranged in the first direction to form a second row. For another example, memory cell Cell0, memory cell Cell2, and other memory cells are arranged in the second direction to form a first column, and memory cell Cell1, memory cell Cell3, and other memory cells are arranged in the second direction to form a second column. Figure 1

[0023] The control gates of the memory tubes of the same row are connected to the same program line (PL), and the gates of the select tubes of the same row are connected to the same word line (WL). The drains of the memory tubes of the same column are connected to the same bit line (BL), and the sources of the select tubes of the same column are connected to the same source line (SL) as the sources of the select tubes of the adjacent column. For example, the control gates of the memory tubes of memory cell Cell0 and memory cell Cell1 are connected to the same program line PL0, and the control gates of the memory tubes of memory cell Cell2 and memory cell Cell3 are connected to the same program line PL1. The gates of the select tubes of memory cell Cell0 and memory cell Cell1 are connected to the same word line WL0, and the gates of the select tubes of memory cell Cell2 and memory cell Cell3 are connected to the same word line WL1. For another example, the drains of the memory tubes of memory cell Cell0 and memory cell Cell2 are connected to the same bit line BL0, and the drains of the memory tubes of memory cell Cell1 and memory cell Cell3 are connected to the same bit line BL1. The sources of the select tubes of memory cell Cell0 and memory cell Cell2 and the sources of the select tubes of memory cell Cell1 and memory cell Cell3 are connected to the same source line SL.

[0024] ​In one aspect, when a programming operation is performed on a memory cell Cell0, other memory cells are disturbed by the programming operation. For example, memory cell Cell1 and memory cell Cell2 are disturbed by FN (Fowler-Nordheim) disturbance, and memory cell Cell3 is disturbed by BTBT (Band-to-Band Tunneling) disturbance. After a number of program-erase cycles, the threshold voltage of the disturbed memory cells can decrease, which can cause the stored information to be incorrect or lost.

[0025] In another aspect, after a memory is programmed, for example, after memory cell Cell0 is programmed, the trapped electrons in the nitride layer of memory cell Cell0 are lost slowly, which causes the threshold voltage of memory cell Cell0 to decrease. When the memory operates at a high temperature, the speed of electron loss increases, which can cause the information stored in the memory to change over time.

[0026] Therefore, it is necessary to design a data refresh scheme to address the problem of the decrease in the threshold voltage of a memory cell caused by programming disturbance and the decrease in the threshold voltage of a memory cell after programming. The data refresh scheme automatically refreshes the stored data when the threshold voltage of the memory cell satisfies certain conditions, which ensures the high reliability of the SONOS memory, and is particularly suitable for SONOS embedded flash (eFlash).

[0027] In a SONOS memory, the threshold voltage of a memory cell in an erased state is different from the threshold voltage of a memory cell in a programmed state. Generally, the threshold voltage in the programmed state is higher than the threshold voltage in the erased state. Figure 2 The threshold voltage curve 201 in the erased state and the threshold voltage curve 203 in the programmed state are shown. The read voltage is between the threshold voltage in the erased state and the threshold voltage in the programmed state. Generally, when the threshold voltage is higher than the read voltage, the read data is 0, and when the threshold voltage is lower than the read voltage, the read data is 1. Normally, the threshold voltage in the programmed state is higher than the read voltage, and the read data is 0. However, when the memory cell in the programmed state is disturbed by programming or the trapped charge in the nitride layer is lost over time, the threshold voltage decreases, for example, from the threshold voltage curve 203 in the programmed state to the threshold voltage curve 205. Further, when the threshold voltage decreases to be lower than the read voltage, the read data of the memory cell in the programmed state changes from 0 to 1, which causes the stored data to be incorrect.

[0028] To solve this problem, an embodiment of the present application adds a check voltage, which is greater than the read voltage. When it is detected that the threshold voltage of the memory cell in the programmed state is lower than the check voltage, the data in the SONOS memory is refreshed, which avoids the read error of the data caused by the further decrease in the threshold voltage.

[0029] As Figure 3 shown, the control method of the SONOS memory of the embodiment of the present application comprises:

[0030] Step S301: After the erasing instruction is completed, the corresponding block is acquired according to the power-on times.

[0031] In some embodiments, a non-volatile memory is set, the power-on times are recorded by using the non-volatile memory, and the check address of the corresponding block is acquired according to the power-on times.

[0032] In some embodiments, the non-volatile memory is a content-addressable memory (CAM).

[0033] As Figure 4 shown, acquiring the corresponding block according to the power-on times further comprises:

[0034] Step S401: When the SONOS memory is powered on, the data in the CAM is loaded.

[0035] Step S403: It is judged whether the data state in the CAM is full.

[0036] Step S405: When the data in the CAM is full, the erasing operation is performed on the CAM.

[0037] Step S407: When the data in the CAM is not full, the operation operation is performed on the data in the CAM.

[0038] Step S409: The data in the CAM is decoded to acquire the check address of the corresponding block.

[0039] In some embodiments, when the CAM is defined as full, the data in the CAM is all 0; when the CAM is empty, the data in the CAM is all 1. Specifically, when the data in the CAM is all 0, it is judged that the data in the CAM is full, the erasing operation is performed on the CAM, and the data in the CAM is all 1. When the data in the CAM is not all 0, it is judged that the data in the CAM is not full, the data in the CAM is added by 1, and the data in the CAM is increased by one bit written as 0.

[0040] Table 1

[0041] Count bit 62 bit 61 bit 60 … bit 3 bit 2 bit 1 bit 0 0 1 1 1 … 1 1 1 1 1 1 1 1 … 1 1 1 0 2 1 1 1 … 1 1 0 0 3 1 1 1 … 1 0 0 0 … … … … … … … … … 61 1 1 0 … 0 0 0 0 62 1 0 0 … 0 0 0 0 63 0 0 0 … 0 0 0 0

[0042] As shown in Table 1, taking 64 blocks in the SONOS memory as an example, there are 63 bits of data in the CAM, which are bit0 to bit62. When the power-on number is 0, the data of bit0 to bit62 are all 1, the number of 0 in the data in the CAM is 0, and the corresponding count value is 0. When the power-on number is 1, the data of bit0 changes from 1 to 0, the data of bit1 to bit62 remains 1, the number of 0 in the data in the CAM is 1, and the corresponding count value is 1. In this way, when the power-on number is 62, the data of bit0 to bit61 are all 0, and the data of bit62 remains 1. The number of 0 in the data in the CAM is 62, and the corresponding count value is 62. When the power-on number is 63, the data of bit0 to bit62 are all 0, and the number of 0 in the data in the CAM is 63. At this time, it is considered that the data in the CAM is full, and the corresponding count value is 63. When the power-on number is 63, the data in the CAM is full, and the data in the CAM is full. The data in the CAM is full, and the data in the CAM is full.

[0043] Through this count encoding mode, the number of 0 in the data in the CAM is recorded according to the power-on number of the SONOS memory, and the corresponding block is obtained by decoding.

[0044] Next, the programmed block is obtained according to the corresponding block, and the programmed state storage unit in the programmed block is screened out.

[0045] Specifically, in some embodiments, steps S303 and S305 are performed.

[0046] Step S303: Determine whether the corresponding block is a programmed block.

[0047] In some embodiments, the data in the corresponding block is read using a read voltage. If there is no 0 in the read data, it indicates that the corresponding block is not a programmed block; if there is 0 in the read data, it indicates that the corresponding block is a programmed block.

[0048] Step S305: When the corresponding block is a programmed block, the programmed block is obtained as the corresponding block, and the programmed state storage unit in the corresponding block is screened out.

[0049] In some embodiments, the data in the corresponding block is read using a read voltage. If the read data is 1, it indicates that the storage unit is in an erased state; if the read data is 0, it indicates that the storage unit is in a programmed state.

[0050] In some other embodiments, steps S307 and S309 are performed.

[0051] Step S307: Taking the corresponding block as a starting block, screening the programmed blocks from the starting block, and obtaining the first programmed block detected from the corresponding block.

[0052] In some embodiments, taking the starting block as a current block, reading the data in the current block using the read voltage, if there is no 0 in the read data, it indicates that the current block is not a programmed block, adding 1 to the address of the current block, and taking the next block as the current block; continue to read the data in the current block using the read voltage until there is 0 in the read data, and obtain that the current block is a programmed block.

[0053] Step S309: Screening the programmed-state storage unit in the programmed block.

[0054] In some embodiments, reading the data in the programmed block using the read voltage, if the read data is 1, it indicates that the storage unit is in the erased state; if the read data is 0, it indicates that the storage unit is in the programmed state.

[0055] Step S311: Detecting whether the threshold voltage of the programmed-state storage unit has dropped below the check voltage.

[0056] In some embodiments, reading the data of the programmed-state storage unit using the check voltage, and judging whether the threshold voltage of the programmed-state storage unit has dropped below the check voltage according to the read data.

[0057] In some embodiments, the check voltage is greater than the read voltage. In some embodiments, the check voltage is a preset value. In some embodiments, the check voltage can be adjusted according to actual needs.

[0058] In some embodiments, reading the data of the programmed-state storage unit using the check voltage, if the read data is 0, it indicates that the threshold voltage of the programmed-state storage unit has not dropped below the check voltage; if the read data is 1, it indicates that the threshold voltage of the programmed-state storage unit has dropped below the check voltage.

[0059] Further, according to the detection result of step S311, it is determined whether to refresh the data in the programmed block.

[0060] In some embodiments, step S313 is performed: when the threshold voltage of the programmed-state storage unit drops below the check voltage, the data in the SONOS memory is refreshed. That is, as long as there is a programmed-state storage unit whose threshold voltage drops below the check voltage, the data in the SONOS memory is refreshed. It is suitable for scenarios with high reliability requirements for SONOS memory.

[0061] In some embodiments, the following step is performed: when the number of programmed memory cells whose threshold voltage has dropped below the verify voltage reaches a predetermined value, the data in the SONOS memory is refreshed. In some embodiments, the following step is performed: when the number of programmed memory cells whose threshold voltage has dropped below the verify voltage is continuously detected to reach a predetermined value, the data in the SONOS memory is refreshed. This is suitable for scenarios where the reliability requirement of the SONOS memory is not high.

[0062] In some embodiments, as shown in FIG. 5, the refreshing of the data in the SONOS memory includes starting from the first page, using the read voltage to read and re-write the data page by page until all the data of all the pages are re-written. Specifically, it includes: Figure 5

[0063] Step S501: Take the first page as the current page.

[0064] Step S503: Use the read voltage to read the data in the current page and cache the read data into the page buffer.

[0065] Step S505: Re-write the data in the page buffer into the current page through programming operation.

[0066] Step S507: Judge whether the writing of the data of the last page is completed.

[0067] Step S509: When the writing of the data of the last page is not completed, add 1 to the current page address, take the next page as the current page, and return to step S503.

[0068] Step S511: When the writing of the data of the last page is completed, judge whether the refreshing of the data is completed.

[0069] Step S315: When the corresponding block is not the programmed block or the threshold voltage of the programmed memory cell has not dropped below the verify voltage, do not perform the refreshing operation.

[0070] ​The application increases the check voltage, the check voltage is greater than the read voltage, after detecting that the threshold voltage of the storage unit in the programming state is lower than the check voltage, the data in the SONOS memory is refreshed; the number of power-on is recorded by using the non-volatile memory, the data in the block of the corresponding address is detected according to the number of power-on, the programmed block is obtained, and the storage unit in the programming state in the block is further screened out; the number of power-on is recorded by using a special counting code, one 0 is written into the counting code every time 1 is added, the number of power-on can be determined according to the number of 0 in the counting code, and the address of the block can be obtained by decoding the counting code. When the threshold voltage of the storage unit in the programming state meets certain conditions, the data of the SONOS memory is refreshed, the problem of the threshold voltage reduction of the storage unit caused by the programming interference of the SONOS memory and the problem of the threshold voltage reduction of the storage unit after programming are effectively solved, data errors and data loss are avoided, the reliability of the SONOS memory is greatly improved, and higher requirement application scenarios can be met.

[0071] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0072] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one feature. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0073] Any process or method descriptions in flow charts or described elsewhere herein can be understood as representing code modules, segments, or portions of code that include one or more executable instructions for performing specific logic functions or steps in the process. And the scope of preferred embodiments of the present application includes additional implementation in which the functions described in the illustrated or discussed order are not performed in the order shown or discussed, including functions performed in substantially simultaneous or in reverse order according to the functions involved.

[0074] The logic and / or steps represented in the flow diagrams and / or otherwise described herein, for example, can be embodied in non-transitory computer-readable media, executed by an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions, or in conjunction with which the instructions can be executed.

[0075] It should be understood that each part of the present application can be realized by hardware, software, firmware or a combination thereof. In the above embodiments, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the above-mentioned embodiment method can be instructed by a program to complete the relevant hardware, and the program can be stored in a computer readable storage medium, and the program includes one of the steps of the method embodiment or a combination thereof when executed.

[0076] In addition, each functional unit in each embodiment of the present application can be integrated in one processing module, or each unit can be physically present separately, or two or more units can be integrated in one module. The above-mentioned integrated module can be realized in the form of hardware or in the form of a software functional module. The above-mentioned integrated module, if realized in the form of a software functional module and sold or used as an independent product, can also be stored in a computer readable storage medium. The storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

[0077] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of various changes or replacements within the technical scope disclosed in the present application, and these should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A control method for a SONOS memory, characterized in that, include: After the erase command is completed, the corresponding block is obtained based on the number of power-on cycles; Retrieve the programmed block based on the corresponding block; Filter out the programmed state storage units in the programmed block; Check whether the threshold voltage of the programmed memory cell has dropped below the verification voltage; Based on the test results, a decision will be made as to whether to refresh the data in the SONOS memory.

2. The control method for the SONOS memory as described in claim 1, characterized in that, Obtaining the corresponding block based on the number of power-on cycles includes: setting up non-volatile memory, using non-volatile memory to record the number of power-on cycles, and obtaining the verification address of the corresponding block based on the number of power-on cycles.

3. The control method for the SONOS memory as described in claim 2, characterized in that, The number of power-on cycles is recorded using non-volatile memory, and the corresponding block's check address is obtained based on the number of power-on cycles, including: Set content-addressable memory; When the SONOS memory is powered on, it loads the data in the addressable memory. Determine whether the content-addressable memory is full; When the content-addressable memory is full, an erase operation is performed on the content-addressable memory; When the content-addressable memory is not full, perform operations on the data in the content-addressable memory; The data in the content-addressable memory is decoded to obtain the check address of the corresponding block.

4. The control method for the SONOS memory as described in claim 3, characterized in that, When the content-addressable memory is full, all data in the content-addressable memory is 0; when the content-addressable memory is empty, all data in the content-addressable memory is 1; when all data in the content-addressable memory is 0, an erase operation is performed on the content-addressable memory to make all data in the content-addressable memory 1. When the data in the content-addressable memory is not all zeros, add 1 to the data in the content-addressable memory, so that the data in the content-addressable memory is increased by one bit and written as 0.

5. The control method for the SONOS memory as described in claim 1, characterized in that, Obtaining the programmed block based on the corresponding block includes: determining whether the corresponding block is a programmed block; if the corresponding block is programmed, obtaining the programmed block as the corresponding block.

6. The control method for the SONOS memory as described in claim 1, characterized in that, Obtaining the programmed block based on the corresponding block includes: taking the corresponding block as the starting block, filtering out programmed blocks starting from the starting block, and obtaining the programmed block as the first programmed block detected starting from the corresponding block.

7. The control method for the SONOS memory as described in claim 1, characterized in that, The process of filtering out programmed storage cells in a programmed block involves: reading data from the programmed block using a read voltage; if the read data is 1, it indicates that the storage cell is in an erased state; if the read data is 0, it indicates that the storage cell is in a programmed state.

8. The control method for the SONOS memory as described in claim 1, characterized in that, Detecting whether the threshold voltage of the programmed memory cell has dropped below the verification voltage includes: setting the verification voltage to be greater than the read voltage; using the verification voltage to read the data of the programmed memory cell; if the read data is 0, it indicates that the threshold voltage of the programmed memory cell has not dropped below the verification voltage; if the read data is 1, it indicates that the threshold voltage of the programmed memory cell has dropped below the verification voltage.

9. The control method for the SONOS memory as described in claim 1, characterized in that, Based on the test results, the decision on whether to refresh the data in the SONOS memory includes: refreshing the data in the SONOS memory when there is a programmed memory cell whose threshold voltage drops below the verification voltage.

10. The control method for the SONOS memory as described in any one of claims 1 to 9, characterized in that, Refreshing data in the SONOS memory involves reading and rewriting data page by page, starting from the first page, using a read voltage, until all pages have been rewritten.

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