A semiconductor test structure

Abstract

The embodiment of the present disclosure provides a semiconductor test structure, comprising: a first metal layer and a second metal layer filled with a dielectric layer; a first test chain and a second test chain distributed in the first metal layer and the second metal layer respectively; the first test chain comprises a first main chain and a plurality of first branch chains, the first branch chains extend in a first direction and a second direction in sequence and semi-enclose the plurality of first branch chains, a first end of the first branch chain is connected with the first main chain and a second end is free; the second test chain comprises a second main chain and a plurality of second branch chains, the second branch chains extend in the first direction and the second direction in sequence and semi-enclose the plurality of second branch chains, a first end of the second branch chain is connected with the second main chain and a second end is free; the first main chain and the second main chain jointly form a surrounding area and are located in the surrounding area, two sides of the first branch chain are the second branch chain and the free end is close to the second main chain, two sides of the second branch chain are the first branch chain and the free end is close to the first main chain.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor test structure. BACKGROUND

[0002] Intermetal dielectric layer test structure (IMD Test Structure) is a kind of semiconductor test structure which is crucial, and its design aims to evaluate the quality of IMD. The most classic and widely used IMD test structure is metal-dielectric layer-metal capacitor structure, which is usually composed of two groups of parallel metal plates staggered at different metal layers, separated by the dielectric layer to be tested.

[0003] The existing IMD test structure is generally a comb-shaped cross capacitor structure, including same layer and stacked layer structures. In the stacked layer structure, when the via is displaced, the dielectric layer will be thinned, and the dielectric layer will be broken down in advance. The existing IMD test structure only monitors the displacement of the via in one direction, and the reliability evaluation of the dielectric layer is not comprehensive enough. On the other hand, the existing IMD test structure is a long comb-shaped symmetrical structure, which cannot monitor the dielectric layer breakdown in advance caused by the concentration of metal end electric field. Therefore, there is an urgent need for a semiconductor test structure that can monitor the dielectric layer breakdown in advance caused by the concentration of metal end electric field and multi-directional via displacement. SUMMARY

[0004] The semiconductor test structure provided by the embodiments of the present disclosure comprises:

[0005] The first metal layer and the second metal layer are distributed in a stacked manner, and the first metal layer and the second metal layer are filled with a dielectric layer;

[0006] The semiconductor test structure comprises a first test chain and a second test chain, the first test chain is distributed in the first metal layer and the second metal layer, and the second test chain is distributed in the first metal layer and the second metal layer;

[0007] The first test chain comprises a first main chain and a plurality of first branch chains, and the first branch chains extend in a meandering manner along a first direction and a second direction in sequence; the first main chain semi-encloses a plurality of the first branch chains, a first end of each of the first branch chains is connected to the first main chain, and a second end of each of the first branch chains is free;

[0008] The second test chain comprises a second main chain and a plurality of second branch chains, and the second branch chains extend in a meandering manner along a first direction and a second direction in sequence; the second main chain semi-encloses a plurality of the second branch chains, a first end of each of the second branch chains is connected to the second main chain, and a second end of each of the second branch chains is free;

[0009] Wherein, the first direction and the second direction intersect.

[0010] The first main chain and the second main chain jointly form a surrounding area, and the first branch chain and the second branch chain are located in the surrounding area, two sides of each first branch chain are the second branch chains, two sides of each second branch chain are the first branch chains, a free end of the first branch chain is close to the second main chain, and a free end of the second branch chain is close to the first main chain.

[0011] In some embodiments, the first branch chain located in the first metal layer includes a plurality of first connection lines extending in a first direction and a plurality of second connection lines extending in a second direction, so that the first branch chain extends in a meandering manner in the first direction and the second direction.

[0012] The first branch chain located in the second metal layer includes a plurality of first connection lines extending in a first direction and a plurality of second connection lines extending in a second direction, so that the first branch chain extends in a meandering manner in the first direction and the second direction.

[0013] In some embodiments, the second branch chain located in the first metal layer includes a plurality of first connection lines extending in a first direction and a plurality of second connection lines extending in a second direction, so that the second branch chain extends in a meandering manner in the first direction and the second direction.

[0014] The second branch chain located in the second metal layer includes a plurality of first connection lines extending in a first direction and a plurality of second connection lines extending in a second direction, so that the second branch chain extends in a meandering manner in the first direction and the second direction.

[0015] In some embodiments, for the same first branch chain of the same metal layer, the first connection lines do not overlap in projection in the first direction, and the second connection lines do not overlap in projection in the second direction.

[0016] For the same second branch chain of the same metal layer, the first connection lines do not overlap in projection in the first direction, and the second connection lines do not overlap in projection in the second direction.

[0017] In some embodiments, the first test chain is connected with a first test pad, and the second test chain is connected with a second test pad.

[0018] In some embodiments, the first main chain further includes a third connection line extending in the first direction and a fourth connection line extending in the second direction.

[0019] The second main chain further includes a fifth connection line extending in the first direction and a sixth connection line extending in the second direction.

[0020] The third connection line, the fourth connection line, the fifth connection line and the sixth connection line in the first metal layer are connected with the third connection line, the fourth connection line, the fifth connection line and the sixth connection line in the second metal layer through a plurality of through holes respectively.

[0021] In some embodiments, the portion of the first test chain located in the first metal layer and the portion of the first test chain located in the second metal layer are coincident in projection along a third direction;

[0022] The portion of the second test chain located in the first metal layer and the portion of the second test chain located in the second metal layer are coincident in projection along a third direction;

[0023] The third direction is perpendicular to the first direction and perpendicular to the second direction.

[0024] In some embodiments, the first connection line in the first metal layer is connected with the first connection line in the second metal layer through a through hole;

[0025] The second connection line in the first metal layer is connected with the second connection line in the second metal layer through a through hole.

[0026] In some embodiments, the first main chain located in the first metal layer has a plurality of first connection points, the first main chain located in the second metal layer has a plurality of second connection points, one first connection point is connected with one second connection point through one through hole, and the portion of the first main chain located between adjacent first connection points is connected with the portion of the first main chain located between adjacent second connection points through at least one through hole.

[0027] The second main chain located in the first metal layer has a plurality of first connection points, the second main chain located in the second metal layer has a plurality of second connection points, one first connection point is connected with one second connection point through one through hole, and the portion of the second main chain located between adjacent first connection points is connected with the portion of the second main chain located between adjacent second connection points through at least one through hole.

[0028] In some embodiments, the semiconductor test structure satisfies one or more of the following conditions:

[0029] (1) the widths of the first test chain and the second test chain are equal;

[0030] (2) the widths of the first connection line, the second connection line, the third connection line, the fourth connection line, the fifth connection line and the sixth connection line are equal;

[0031] (3) the lengths of the first connection line and the second connection line are equal;

[0032] (4) the widths of the first branch in the first test chain and the second branch in the second test chain are equal.

[0033] The semiconductor test structure provided by the embodiment of the present disclosure comprises: a first metal layer and a second metal layer which are distributed in a stack, and the first metal layer and the second metal layer are filled with a dielectric layer; the semiconductor test structure comprises a first test chain and a second test chain, the first test chain is distributed in the first metal layer and the second metal layer, and the second test chain is distributed in the first metal layer and the second metal layer; the first test chain comprises a first main chain and a plurality of first branch chains, and the first branch chains extend in a first direction and a second direction in sequence; the first main chain semi-surrounds the plurality of first branch chains, a first end of each first branch chain is connected to the first main chain, and a second end of each first branch chain is free; the second test chain comprises a second main chain and a plurality of second branch chains, and the second branch chains extend in the first direction and the second direction in sequence; the second main chain semi-surrounds the plurality of second branch chains, a first end of each second branch chain is connected to the second main chain, and a second end of each second branch chain is free; wherein the first direction and the second direction intersect; the first main chain and the second main chain jointly form a surrounding area, and the first branch chains and the second branch chains are located in the surrounding area, two sides of each first branch chain are both the second branch chains, two sides of each second branch chain are both the first branch chains, the free end of the first branch chain is close to the second main chain, and the free end of the second branch chain is close to the first main chain. Here, the first metal layer and the second metal layer in the test chain are distributed in a stack, the first branch chains in the first test chain and the second branch chains in the second test chain are staggered, one end of the first branch chain and one end of the second branch chain are free, the dielectric layer breakdown caused by the electric field concentration at the metal end can be monitored, and the multi-directional via displacement can be monitored, thereby improving the comprehensiveness of the reliability evaluation of the dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A same-layer structure diagram of a semiconductor test structure provided by the related art;

[0035] Figure 2 A stack structure diagram of a semiconductor test structure provided by the related art;

[0036] Figure 3 A first partial structure diagram of a semiconductor test structure provided by the embodiment of the present disclosure;

[0037] Figure 4 A second partial structure diagram of a semiconductor test structure provided by the embodiment of the present disclosure;

[0038] Figure 5 A third partial structure diagram of a semiconductor test structure provided by the embodiment of the present disclosure;

[0039] Figure 6 A semiconductor test structure diagram provided by the embodiment of the present disclosure;

[0040] Figure 7 This is a side view schematic diagram of a semiconductor test structure provided in an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic flowchart of a semiconductor testing method provided in an embodiment of the present disclosure. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining the relevant disclosure and not for limiting the disclosure. It should also be noted that, for ease of description, only the parts related to the relevant disclosure are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third, fourth" involved in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third, fourth" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] Existing IMD test structures are generally capacitive structures formed by comb-like cross-sections, including single-layer and multi-layer structures. Single-layer structures include... Figure 1 As shown, test chain 001 and test chain 002 are distributed in the same metal layer. Test chain 001 is connected to the first pad 003, and test chain 002 is connected to the second pad 004; the stacked structure is as follows. Figure 2 As shown, test chains 001 and 002 are distributed in metal layers 005 and 006 respectively, which are connected by vias 007. Test chain 001 is connected to the first pad 003, and test chain 002 is connected to the second pad 004. In a multilayer structure, when vias shift, the dielectric layer thins, causing premature breakdown. Existing IMD test structures can generally only monitor via shift in one direction, and cannot monitor via shift in multiple directions simultaneously, resulting in an insufficiently comprehensive assessment of dielectric layer reliability. In addition, existing IMD test structures are all long comb-shaped symmetrical structures, which cannot detect premature breakdown of the dielectric layer caused by electric field concentration at the metal ends.

[0044] Hereinafter, the semiconductor test structure in the embodiments of the present disclosure will be described in detail with reference to the drawings.

[0045] In some embodiments of the present disclosure, see Figure 3 , which shows a first partial structure diagram of a semiconductor test structure 10 provided by an embodiment of the present disclosure. As Figure 3 shown, the semiconductor test structure 10 includes a first metal layer 100 and a second metal layer 200 distributed in layers, and the first metal layer 100 and the second metal layer 200 are filled with a dielectric layer; the semiconductor test structure 10 includes a first test chain 101 and a second test chain 201, the first test chain 101 is distributed in the first metal layer 100 and the second metal layer 200, and the second test chain 201 is distributed in the first metal layer 100 and the second metal layer 200; the first test chain 101 includes a first main chain 102 and a plurality of first branch chains 103, the first branch chains 103 extend in a first direction and a second direction in turn; the first main chain 102 semi-surrounds the plurality of first branch chains 103, the first end of each first branch chain 103 is connected to the first main chain 102, and the second end of each first branch chain 103 is free; the second test chain 201 includes a second main chain 202 and a plurality of second branch chains 203, the second branch chains 203 extend in the first direction and the second direction in turn; the second main chain 202 semi-surrounds the plurality of second branch chains 203, the first end of each second branch chain 203 is connected to the second main chain 202, and the second end of each second branch chain 203 is free; wherein the first direction and the second direction intersect; the first main chain 102 and the second main chain 202 jointly form a surrounding area, and the first branch chain 103 and the second branch chain 203 are located in the surrounding area, the two sides of each first branch chain 103 are the second branch chains 203, the two sides of each second branch chain 203 are the first branch chains 103, the free end of the first branch chain 103 is close to the second main chain 202, and the free end of the second branch chain 203 is close to the first main chain 102.

[0046] It should be noted that the metal interconnection lines deposited in different layers are separated by dielectric layers, and the metal interconnection lines in the same layer are separated by dielectric layers, and the insulating material layer is used to realize electrical isolation. In the early stage, silicon dioxide was mainly used, which was formed by chemical vapor deposition process, and low dielectric constant materials such as carbon-doped silicon oxide and porous silicon dioxide were introduced to reduce the parasitic capacitance between the interconnection lines. The dielectric layer physically separates and electrically insulates the adjacent metal interconnection lines above and below and the metal interconnection lines in the same layer, prevents short circuit between them, and ensures that the signal can only be connected vertically through the specially designed via; by using low dielectric constant materials, the parasitic capacitance between the metal interconnection lines is effectively reduced, thereby reducing signal transmission delay and dynamic power consumption; the dielectric layer also provides a solid and flat substrate for the metal layer above, and the surface of the dielectric layer is planarized by chemical mechanical polishing (CMP) to ensure the accuracy and uniformity of subsequent metal photolithography, preventing defects caused by surface undulations; in addition, a high-quality dielectric layer can suppress electromigration and reduce leakage current under voltage stress, significantly improving the overall reliability, performance and yield of the chip.

[0047] It should also be noted that the widths of the first test chain 101 and the second test chain 201 are equal, and the widths of the first branch 103 in the first test chain 101 and the second branch 203 in the second test chain 201 are equal.

[0048] Here, the first branch 103 in the first test chain 101 and the second branch 203 in the second test chain 201 are sequentially extended in the first direction and the second direction, so that the first branch 103 and the second branch 203 present a polyline, which facilitates monitoring of dielectric layer breakdown caused by metal tip end electric field concentration. At the same time, the second end of each first branch 103 in the first test chain 101 is free, and one end of each second branch 203 in the second test chain 201 has multiple free ends, and the free ends of the branches are more susceptible to electric field concentration caused by discharge.

[0049] Further, the first main chain 102 in the first test chain 101 and the second main chain 202 in the second test chain 201 form a surrounding area to surround the first branch 103 and the second branch 203, and the plurality of first branches 103 in the first test chain 101 and the plurality of second branches 203 in the second test chain 201 are staggered, that is, each first branch 103 has a second branch 203 on both sides, and each second branch 203 has a first branch 103 on both sides, which can more accurately monitor the displacement of the metal layer in different directions.

[0050] In the embodiment, the number of the first branch 103 in the first test chain 101 and the second branch 203 in the second test chain 201 is not limited, as long as the number of the first branch 103 in the first test chain 101 and the second branch 203 in the second test chain 201 is consistent, and the length and width of the first branch 103 in the first test chain 101 and the second branch 203 in the second test chain 201 are matched.

[0051] In some embodiments of the present disclosure, please continue to refer to Figure 3 As shown in the drawings, the first branch 103 in the first metal layer 100 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the first branch 103 extends in the first direction and the second direction in a meandering manner; the first branch 103 in the second metal layer 200 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the first branch 103 extends in the first direction and the second direction in a meandering manner. Figure 3 As shown in the drawings, the first branch 103 in the first metal layer 100 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the first branch 103 extends in the first direction and the second direction in a meandering manner; the first branch 103 in the second metal layer 200 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the first branch 103 extends in the first direction and the second direction in a meandering manner.

[0052] It should be noted that the width of the first connection line 401 and the second connection line 402 is equal, and the length of the first connection line 401 and the second connection line 402 is equal.

[0053] Here, the first metal layer 100 and the second metal layer 200 both have the first branch 103, and the first connection line 401 and the second connection line 402 in the first branch 103 extend in the first direction and the second direction respectively, so that the first branch 103 is interleaved between the first metal layer 100 and the second metal layer 200 and presents a polyline trace, which facilitates monitoring of dielectric layer breakdown caused by metal tip end electric field concentration.

[0054] In some embodiments of the present disclosure, please continue to refer to Figure 3 As shown in the drawings, the first branch 103 in the first metal layer 100 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the first branch 103 extends in the first direction and the second direction in a meandering manner; the first branch 103 in the second metal layer 200 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the first branch 103 extends in the first direction and the second direction in a meandering manner.

[0055] Here, in the same first branch chain 103 of the same metal layer, the first connection line 401 does not overlap in the projection along the first direction, and the second connection line 402 does not overlap in the projection along the second direction; in the same second branch chain 203 of the same metal layer, the first connection line 401 does not overlap in the projection along the first direction, and the second connection line 402 does not overlap in the projection along the second direction. Wherein, the first connection line 401 and the second connection line 402 have conductivity, belong to metal interconnection lines, and the metal interconnection lines are separated by a dielectric layer.

[0056] In the embodiments of the present disclosure, the first metal layer 100 and the second metal layer 200 both have the second branch chain 203, and the first connection line 401 and the second connection line 402 in the second branch chain 203 extend along the first direction and the second direction respectively, so that the second branch chain 203 is interleaved between the first metal layer 100 and the second metal layer 200 and presents a zigzag trace. This zigzag trace facilitates monitoring of dielectric layer breakdown caused by metal tip end electric field concentration, and facilitates judgment of the displacement of the metal layer.

[0057] In some embodiments of the present disclosure, please refer to Figure 4 , which shows a second partial structure diagram of a semiconductor test structure 10 provided by an embodiment of the present disclosure. As shown in Figure 4 , the first main chain 102 further includes a third connection line 403 extending along the first direction and a fourth connection line 404 extending along the second direction; the second main chain 202 further includes a fifth connection line 405 extending along the first direction and a sixth connection line 406 extending along the second direction; the third connection line 403, the fourth connection line 404, the fifth connection line 405 and the sixth connection line 406 in the first metal layer 100 are connected with the third connection line 403, the fourth connection line 404, the fifth connection line 405 and the sixth connection line 406 in the second metal layer 200 through a plurality of vias 301.

[0058] Here, the first test chain 101 is connected with the first test pad 302, and the second test chain 201 is connected with the second test pad 303.

[0059] It should be noted that the second test pad 303 is defined as a ground pad, and the first test pad 302 is defined as a power pad. Based on this electrical connection setting, in the second test chain 201 connected with the second test pad 303, the structures of the vias 301 between the different layer metal layers are all applied with 0V voltage, i.e. at the ground potential; the structures of the vias 301 between the different layer metal layers in the first test chain 101 connected with the first test pad 302 are applied with a certain positive voltage.

[0060] Specifically, for any one via 301, there is a voltage difference between it and the nearest four vias around it.

[0061] It should be further noted that the third connection line 403 and the fifth connection line 405 are a line extending in the second direction, and the fourth connection line 404 and the sixth connection line 406 are a line extending in the first direction. In the embodiment, the number of the third connection line 403, the fourth connection line 404, the fifth connection line 405 and the sixth connection line 406 is not limited, and only the width of the third connection line 403, the fourth connection line 404, the fifth connection line 405 and the sixth connection line 406 is equal, and the width of the third connection line 403, the fourth connection line 404, the fifth connection line 405, the sixth connection line 406 and the first connection line 401, the second connection line 402 is matched.

[0062] In some embodiments of the present disclosure, please continue to refer to Figure 4 , the part of the first test chain 101 located in the first metal layer 100 and the part of the first test chain 101 located in the second metal layer 200 are projected to coincide in the third direction; the part of the second test chain 201 located in the first metal layer 100 and the part of the second test chain 201 located in the second metal layer 200 are projected to coincide in the third direction; wherein the third direction is perpendicular to the first direction, and the third direction is perpendicular to the second direction.

[0063] In the embodiment of the present disclosure, the first connection line 401 in the first metal layer 100 and the first connection line 401 in the second metal layer 200 are connected through the via hole 301; the second connection line 402 in the first metal layer 100 and the second connection line 402 in the second metal layer 200 are connected through the via hole 301.

[0064] Here, the first metal layer 100 and the second metal layer 200 belong to different layers, and the connection lines between different metal layers are connected by the via hole through the stack structure between the metal layers, and the first metal layer 100 and the second metal layer 200 are completely symmetrical and coincide in the third direction.

[0065] In some embodiments of the present disclosure, please refer to Figure 5 , which shows a third part structure diagram of a semiconductor test structure 10 provided by an embodiment of the present disclosure. As Figure 5As shown, the first main chain 102 in the first metal layer 100 has a plurality of first connection points, the first main chain 102 in the second metal layer 200 has a plurality of second connection points, one first connection point is connected to one second connection point through one via hole 301, and the part of the first main chain 102 between adjacent first connection points is connected to the part of the first main chain 102 between adjacent second connection points through at least one via hole 301; the second main chain 202 in the first metal layer 100 has a plurality of first connection points, the second main chain 202 in the second metal layer 200 has a plurality of second connection points, one first connection point is connected to one second connection point through one via hole 301, and the part of the second main chain 202 between adjacent first connection points is connected to the part of the second main chain 202 between adjacent second connection points through at least one via hole 301.

[0066] Here, by connecting the plurality of first connection points in the first main chain 102 of the first metal layer 100 with the plurality of second connection points in the first main chain 102 of the second metal layer 200 through the via holes 301, after the first main chain 102 is connected with each first branch 103, there are still via holes 301 between the connection points to connect the remaining first connection points on the first main chain 102 of the first metal layer 100 with the corresponding second connection points on the first main chain 102 of the second metal layer 200, further, the connection line in the second branch 203 that is consistent with the extension direction of the third connection line 403 or the fourth connection line 404 of the first main chain 102 and close to the first main chain 102 can more accurately monitor the offset of the via holes 301 in different directions on the connection line. By connecting the plurality of first connection points in the second main chain 202 of the first metal layer 100 with the plurality of second connection points in the second main chain 202 of the second metal layer 200 through the via holes 301, after the second main chain 202 is connected with each second branch 203, there are still via holes 301 between the connection points to connect the remaining first connection points on the second main chain 202 of the first metal layer 100 with the corresponding second connection points on the second main chain 202 of the second metal layer 200, further, the connection line in the first branch 103 that is consistent with the extension direction of the fifth connection line 405 and the sixth connection line 406 of the second main chain 202 and close to the second main chain 202 can more accurately monitor the offset of the via holes 301 in different directions on the connection line.

[0067] In summary, the present disclosure provides a semiconductor test structure, in a specific example, please see Figure 6The semiconductor test structure 10 comprises: a first metal layer 100 and a second metal layer 200 which are distributed in a stack, and the first metal layer 100 and the second metal layer 200 are filled with a dielectric layer; the semiconductor test structure 10 comprises a first test chain 101 and a second test chain 201, the first test chain 101 is distributed in the first metal layer 100 and the second metal layer 200, and the second test chain 201 is distributed in the first metal layer 100 and the second metal layer 200; the first test chain 101 comprises a first main chain 102 and a plurality of first branch chains 103, and the first branch chains 103 extend in a first direction and a second direction in sequence; the first main chain 102 semi-surrounds the plurality of first branch chains 103, a first end of each first branch chain 103 is connected to the first main chain 102, and a second end of each first branch chain 103 is free; the second test chain 201 comprises a second main chain 202 and a plurality of second branch chains 203, and the second branch chains 203 extend in the first direction and the second direction in sequence; the second main chain 202 semi-surrounds the plurality of second branch chains 203, a first end of each second branch chain 203 is connected to the second main chain 202, and a second end of each second branch chain 203 is free; wherein the first direction and the second direction intersect; the first main chain 102 and the second main chain 202 jointly form a surrounding area, and the first branch chains 103 and the second branch chains 203 are located in the surrounding area, two sides of each first branch chain 103 are the second branch chains 203, two sides of each second branch chain 203 are the first branch chains 103, the free end of the first branch chain 103 is close to the second main chain 202, and the free end of the second branch chain 203 is close to the first main chain 102.

[0068] Here, the first metal layer 100 and the second metal layer 200 are distributed in a stack, and the first metal layer 100 and the second metal layer 200 are filled with a dielectric layer, and the first metal layers 100 which are distributed in the same layer and the second metal layers 200 which are distributed in the same layer are also filled with a dielectric layer.

[0069] The first branch 103 in the first metal layer 100 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the first branch 103 extends in the first direction and the second direction in a meandering manner; the first branch 103 in the second metal layer 200 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the first branch 103 extends in the first direction and the second direction in a meandering manner. The second branch 203 in the first metal layer 100 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the second branch 203 extends in the first direction and the second direction in a meandering manner; the second branch 203 in the second metal layer 200 includes a plurality of first connection lines 401 extending in the first direction and a plurality of second connection lines 402 extending in the second direction, so that the second branch 203 extends in the first direction and the second direction in a meandering manner.

[0070] The first main chain 102 further includes a third connection line 403 extending in the first direction and a fourth connection line 404 extending in the second direction; the second main chain 202 further includes a fifth connection line 405 extending in the first direction and a sixth connection line 406 extending in the second direction; the third connection line 403, the fourth connection line 404, the fifth connection line 405 and the sixth connection line 406 in the first metal layer 100 are connected with the third connection line 403, the fourth connection line 404, the fifth connection line 405 and the sixth connection line 406 in the second metal layer 200 through a plurality of through holes 301. The first test chain 101 is connected with the first test pad 302, and the second test chain 201 is connected with the second test pad 303.

[0071] The portion of the first test chain 101 in the first metal layer 100 and the portion of the first test chain 101 in the second metal layer 200 project in the third direction and coincide; the portion of the second test chain 201 in the first metal layer 100 and the portion of the second test chain 201 in the second metal layer 200 project in the third direction and coincide; wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0072] The first connection line 401 in the first metal layer 100 is connected with the first connection line 401 in the second metal layer 200 through the through hole 301; the second connection line 402 in the first metal layer 100 is connected with the second connection line 402 in the second metal layer 200 through the through hole 301.

[0073] It should be noted that the first metal layer 100 and the second metal layer 200 belong to different layers. The material of the first test chain 101 can be a material with strong conductivity, for example, the material can be copper, aluminum, tungsten, or other materials with strong conductivity, which are not listed one by one here. The material of the dielectric layer can be an insulating material, for example, the material can be silicon oxide or silicon oxynitride. The material of the second test chain 201 can also be a material with strong conductivity, for example, the material can be copper, aluminum, tungsten, or other materials with strong conductivity, which are not listed one by one here.

[0074] Here, there are multiple free ends in the first test chain 101 and the second test chain 201 respectively, and through the free ends in the test chain, the discharge caused by the electric field concentration can be monitored.

[0075] It should be noted that the first test chain 101 and the second test chain 201 are not electrically connected; the second test pad 303 is defined as a ground pad, and the first test pad 302 is defined as a power supply pad. Based on this electrical connection setting, in the second test chain 201 connected to the second test pad 303, the metal layers in different layers and the through holes 301 structure between them are all applied with 0V voltage, that is, at the ground potential; the first test chain 101 connected to the first test pad 302 is applied with a certain positive voltage.

[0076] Specifically, for any one through hole 301, there is a voltage difference between it and the nearest four surrounding through holes.

[0077] As shown in the embodiment of the present disclosure, Figure 6 As shown in the embodiment of the present disclosure,

[0078] When testing the semiconductor, a positive voltage is applied to the first test pad 302 until the capacitor is broken down, and the breakdown voltage is recorded. If there is an electric field concentration of the metal tip, the breakdown voltage can be less than the preset voltage value; if the through hole 301 is offset, the distance between the capacitors (i.e. the width of the dielectric layer) becomes smaller, which will also cause the breakdown voltage to be smaller.

[0079] The first main chain 102 in the first metal layer 100 has a plurality of first connection points, the first main chain 102 in the second metal layer 200 has a plurality of second connection points, one first connection point is connected to one second connection point through one via hole 301, the part of the first main chain 102 between adjacent first connection points is connected to the part of the first main chain 102 between adjacent second connection points through at least one via hole 301; the second main chain 202 in the first metal layer 100 has a plurality of first connection points, the second main chain 202 in the second metal layer 200 has a plurality of second connection points, one first connection point is connected to one second connection point through one via hole 301, the part of the second main chain 202 between adjacent first connection points is connected to the part of the second main chain 202 between adjacent second connection points through at least one via hole 301.

[0080] In an example, the side view of the semiconductor test structure from the connection point A to the connection point A' in the second direction and from the connection point B to the connection point B' in the first direction is shown as Figure 7 As can be seen from the figure, the first test chain 101 and the second test chain 201 are distributed in the first metal layer 100 and the second metal layer 200, at the connection points, the first metal layer 100 and the second metal layer 200 in the first test chain 101 are connected through the via hole 301; at the connection points, the first metal layer 100 and the second metal layer 200 in the second test chain 201 are also connected through the via hole 301; at the positions where no connection points are arranged, the first metal layer 100 and the second metal layer 200 are not connected through the via hole 301.

[0081] Here, the first metal layer 100 and the second metal layer 200 are arranged perpendicular to each other and completely coincide in the third direction, any one of the first metal layer 100 and the second metal layer 200 in the test chain is connected through the via hole 301; the via hole 301 is used to realize the signal transmission between different metal layers and is a vertical conductive channel.

[0082] Since the first test chain 101 and the second test chain 201 are respectively composed of the first metal layer 100 and the second metal layer 200 distributed in the form of a laminated structure, the first branch chain 103 in the first test chain 101 and the second branch chain 203 in the second test chain 201 present a cross structure and are respectively connected to the first test pad 302 and the second test pad 303, the alternating distribution of the electric potential is realized, and a multi-dimensional electric field sensitive area is also formed, so that the semiconductor test structure 10 can monitor the insulation reliability of the dielectric layer between the metal layers in the same layer and the withstand voltage capability of the dielectric layer between the metal layers in adjacent layers; the electric field concentration and dielectric discharge caused by the tip structure of the metal layer under bias voltage can also be monitored; in addition, the shift of the via hole 301 in the first direction and the second direction can also be monitored.

[0083] In an example, for via hole 301-1, there are metal layers in the first direction Y, the first direction Y', and the second direction X, so the semiconductor test structure 10 can monitor the shift of the via hole 301-1 in the first direction and the second direction.

[0084] In an example, for via hole 301-2, there are metal layers in the first direction Y, the second direction X, and the second direction X', so the semiconductor test structure 10 can monitor the shift of the via hole 301-2 in the first direction and the second direction.

[0085] In an example, for via hole 301-3, there are metal layers in the first direction Y and the second direction X, so the semiconductor test structure 10 can monitor the shift of the via hole 301-3 in the first direction and the second direction.

[0086] The disclosure also provides a test method of the semiconductor test structure 10 described above, Figure 8 A flowchart of a semiconductor test method provided by an embodiment of the disclosure is shown in FIG. 10. As shown in the figure, the method comprises the following steps. Figure 8

[0087] S210: The first test pad of the semiconductor test structure is grounded, the second test pad is applied with a voltage, and the voltage is continuously increased until the current monitored by the first test pad or the second test pad is greater than a preset current value, then it is considered that the dielectric layer is broken down, and the breakdown voltage is recorded.

[0088] S220: The breakdown voltage is compared with a preset voltage value, when the breakdown voltage is greater than or equal to the preset voltage value, the shift of the via hole or the width of the intermetallic dielectric layer is less than or equal to a preset deviation range, and the electrical performance of the semiconductor structure meets the requirements.

[0089] S230: The breakdown voltage is compared with a preset voltage value, when the breakdown voltage is less than the preset voltage value, the shift of the via hole or the width of the intermetallic dielectric layer is greater than the preset deviation range, and the electrical performance of the semiconductor structure does not meet the requirements.

[0090] It should be noted that the embodiments of the disclosure take the semiconductor test structure 10 shown in FIG. 10 as an example for description, and the test processes of semiconductor test structures 10 of other structures can be understood with reference to the above embodiments, which will not be described here. Figure 6

[0091] The above is only a preferred embodiment of the disclosure, and is not used to limit the protection scope of the disclosure.

[0092] ​​It should be noted that in the present disclosure, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0093] The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0094] The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

[0095] The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0096] The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0097] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A semiconductor test structure, characterized by, The semiconductor test structure comprises a first metal layer and a second metal layer, and a dielectric layer is arranged between the first metal layer and the second metal layer; The semiconductor test structure comprises a first test chain and a second test chain, the first test chain is arranged on the first metal layer and the second metal layer, and the second test chain is arranged on the first metal layer and the second metal layer; The first test chain comprises a first main chain and a plurality of first branch chains, the first branch chains extend in a first direction and a second direction in sequence, the first main chain semi-surrounds the plurality of first branch chains, a first end of each first branch chain is connected to the first main chain, and a second end of each first branch chain is free; The second test chain comprises a second main chain and a plurality of second branch chains, the second branch chains extend in a first direction and a second direction in sequence, the second main chain semi-surrounds the plurality of second branch chains, a first end of each second branch chain is connected to the second main chain, and a second end of each second branch chain is free; The first direction and the second direction intersect each other; The first main chain and the second main chain jointly form a surrounding area, and the first branch chains and the second branch chains are located in the surrounding area, two sides of each first branch chain are the second branch chains, two sides of each second branch chain are the first branch chains, the free end of the first branch chain is close to the second main chain, and the free end of the second branch chain is close to the first main chain.

2. The semiconductor test structure according to claim 1, wherein the first branch chain on the first metal layer comprises a plurality of first connection lines extending in the first direction and a plurality of second connection lines extending in the second direction, so that the first branch chain extends in the first direction and the second direction in sequence.

3. The semiconductor test structure according to claim 1, wherein the second branch chain on the first metal layer comprises a plurality of first connection lines extending in the first direction and a plurality of second connection lines extending in the second direction, so that the second branch chain extends in the first direction and the second direction in sequence.

4. The semiconductor test structure according to claim 2, wherein for the same first branch chain on the same metal layer, the first connection lines do not overlap in the first direction, and the second connection lines do not overlap in the second direction.

5. The semiconductor test structure according to claim 1, wherein ​ ​ ​ ​ ​ ​ ​ The first test chain is connected with a first test pad, and the second test chain is connected with a second test pad. 6.The semiconductor test structure of claim 1, wherein, the first main chain further comprises a third connection line extending in the first direction and a fourth connection line extending in the second direction; the second main chain further comprises a fifth connection line extending in the first direction and a sixth connection line extending in the second direction; the third connection line, the fourth connection line, the fifth connection line and the sixth connection line in the first metal layer are connected with the third connection line, the fourth connection line, the fifth connection line and the sixth connection line in the second metal layer through the plurality of through holes, respectively. 7.The semiconductor test structure of claim 1, wherein, the portion of the first test chain in the first metal layer and the portion of the first test chain in the second metal layer are overlapped in projection along a third direction; the portion of the second test chain in the first metal layer and the portion of the second test chain in the second metal layer are overlapped in projection along the third direction; wherein the third direction is perpendicular to the first direction and perpendicular to the second direction. 8.The semiconductor test structure of claim 1, wherein, the first connection line in the first metal layer is connected with the first connection line in the second metal layer through a through hole; the second connection line in the first metal layer is connected with the second connection line in the second metal layer through a through hole. 9.The semiconductor test structure of claim 1, wherein, the first main chain in the first metal layer has a plurality of first connection points, the first main chain in the second metal layer has a plurality of second connection points, one first connection point is connected with one second connection point through one through hole, and the portion of the first main chain between adjacent first connection points is connected with the portion of the first main chain between adjacent second connection points through at least one through hole; the second main chain in the first metal layer has a plurality of first connection points, the second main chain in the second metal layer has a plurality of second connection points, one first connection point is connected with one second connection point through one through hole, and the portion of the second main chain between adjacent first connection points is connected with the portion of the second main chain between adjacent second connection points through at least one through hole.

10. A semiconductor test structure according to any one of claims 1 to 9, wherein, The semiconductor test structure satisfies one or more of the following conditions: (1) the width of the first test chain is equal to the width of the second test chain; (2) the width of the first connection line, the second connection line, the third connection line, the fourth connection line, the fifth connection line and the sixth connection line are equal; (3) the length of the first connection line is equal to the length of the second connection line; (4) the width of the first branch in the first test chain is equal to the width of the second branch in the second test chain.

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