Physical layer link response time measurement method, electronic device, and storage medium

Abstract

Embodiments of the present application provide a physical layer link response time measurement method, an electronic device and a computer readable storage medium. The method comprises: based on a master chip controlling a first physical layer chip and a second physical layer chip to complete initialization; based on the master chip controlling a reset signal of the first physical layer chip or the second physical layer chip to change, and marking a time as a first time node; based on the master chip detecting a working state of the second physical layer chip, and in the case that the second physical layer chip produces a working state change matching the change of the reset signal, marking a time as a second time node; and based on the first time node and the second time node, performing difference processing to obtain a physical layer link response time. According to the scheme of the embodiments of the present application, the physical layer link response time measurement can be more convenient, fast and efficient.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a physical layer link response time measurement method, electronic device, and computer-readable storage medium. Background Technology

[0002] With the continuous development of science and technology, fields such as industrial automation, robotics, and vehicle communication have placed higher standards and requirements on Ethernet technology. Besides common technical parameters such as Ethernet communication speed and latency, the link response time of the Physical Layer (PHY) is also receiving attention. In EtherControlAutomationTechnology (EtherCAT) and other industrial real-time Ethernet bus slave stations, the technical characteristics include two or more PHYs, and explicitly specified link response time requirements to ensure deterministic device response. Traditional link response time measurement requires obtaining relevant data using specialized equipment such as oscilloscopes to calculate the link response time; however, this method suffers from problems such as complex measurement processes, low efficiency, and high measurement costs. Summary of the Invention

[0003] The embodiments of this application are intended to at least solve one of the technical problems existing in the prior art.

[0004] Therefore, this application proposes a physical layer link response time measurement method, which makes physical layer link response time measurement simpler, faster and more efficient.

[0005] This application also proposes an electronic device that applies the above-described physical layer link response time measurement method.

[0006] This application also proposes a computer-readable storage medium that applies the above-described physical layer link response time measurement method.

[0007] The physical layer link response time measurement method according to the first aspect of the present application is applied to a physical layer link measurement system. The physical layer link measurement system includes a main control chip, a first physical layer chip, and a second physical layer chip. Both the first physical layer chip and the second physical layer chip are connected to the main control chip. The first physical layer chip is also signal-connected to the second physical layer chip. The method includes:

[0008] The main control chip controls the first physical layer chip and the second physical layer chip to complete the initialization.

[0009] The main control chip controls the reset signal of the first physical layer chip or the second physical layer chip to change, and the time is marked as the first time node;

[0010] The main control chip detects the working state of the second physical layer chip, and when the second physical layer chip generates a working state change that matches the change in the reset signal, the time is marked as the second time node.

[0011] The physical layer link response time is obtained by subtracting the first time node and the second time node.

[0012] According to some embodiments of this application, the reset control pins of both the first physical layer chip and the second physical layer chip are connected to the main control chip. The initialization process, controlled by the main control chip, includes:

[0013] The main control chip sends a reset signal to the reset control pins of the first physical layer chip and the second physical layer chip, so that the first physical layer chip and the second physical layer chip complete initialization.

[0014] According to some embodiments of this application, the step of sending a reset signal from the main control chip to the reset control pins of the first physical layer chip and the second physical layer chip to enable the first physical layer chip and the second physical layer chip to complete initialization includes:

[0015] The main control chip sends a low-level signal to the reset control pin of the first physical layer chip and the second physical layer chip, and maintains it for a first preset time threshold, so that the first physical layer chip and the second physical layer chip complete initialization.

[0016] According to some embodiments of this application, the signal state detection pins of both the first physical layer chip and the second physical layer chip are connected to the main control chip. The step of sending a reset signal from the main control chip to the reset control pins of the first physical layer chip and the second physical layer chip to enable the first physical layer chip and the second physical layer chip to complete initialization includes:

[0017] The main control chip sends a high-level signal to the reset control pins of the first physical layer chip and the second physical layer chip, and maintains it for a second preset time threshold.

[0018] The main control chip performs signal detection on the signal status detection pins of the first physical layer chip and the second physical layer chip until it is detected that both the first physical layer chip and the second physical layer chip are in a normal link state, so that the first physical layer chip and the second physical layer chip complete the initialization.

[0019] According to some embodiments of this application, the step of controlling the reset signal of the first physical layer chip or the second physical layer chip based on the main control chip changes, and marking the time as a first time node, includes:

[0020] The main control chip sends a high-level signal to the reset control pin of the first physical layer chip and maintains it for a third preset time threshold so that the first physical layer chip enters a normal working state.

[0021] The main control chip controls the reset control pin of the second physical layer chip to switch from low level to high level, and the time is marked as the first time node.

[0022] According to some embodiments of this application, the step of controlling the reset signal of the first physical layer chip or the second physical layer chip based on the main control chip changes, and marking the time as a first time node, includes:

[0023] The main control chip controls the reset control pin of the first physical layer chip to switch from high level to low level, so that the first physical layer chip enters the reset state and the time is marked as the first time node.

[0024] According to some embodiments of this application, the signal state detection pins of both the first physical layer chip and the second physical layer chip are connected to the main control chip. The step of detecting the operating state of the second physical layer chip based on the main control chip, and marking a second time node when the second physical layer chip generates an operating state change matching the reset signal change, includes:

[0025] The main control chip performs signal detection on the signal status detection pin of the second physical layer chip.

[0026] When the second physical layer chip is detected to have switched from a link failure state to a link normal state, the time is marked as the second time node.

[0027] According to some embodiments of this application, the step of detecting the operating state of the second physical layer chip based on the main control chip, and marking the time as a second time node when the second physical layer chip generates an operating state change that matches the change in the reset signal, includes:

[0028] The main control chip performs signal detection on the signal status detection pin of the second physical layer chip.

[0029] When the second physical layer chip is detected to have switched from a normal link state to a link failure state, the time is marked as the second time node.

[0030] An electronic device according to a second aspect of the present application includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the physical layer link response time measurement method as described above.

[0031] According to a third aspect of the present application, a computer-readable storage medium stores computer-executable instructions that, when executed by a control processor, implement the physical layer link response time measurement method as described above.

[0032] The physical layer link response time measurement method according to the embodiments of this application has at least the following beneficial effects: In the process of measuring the physical layer link response time, firstly, the first and second physical layer chips of the physical layer link measurement system are initialized based on the control chip; then, the reset signal of the first or second physical layer chip changes based on the control chip, and the time is marked as a first time node; next, the working state of the second physical layer chip is detected based on the control chip, and when the second physical layer chip generates a working state change matching the reset signal change, the time can be marked as a second time node; finally, the difference between the first and second time nodes is calculated to obtain the physical layer link response time. Through the above technical solution, physical layer link response time measurement can be achieved simply, quickly, and efficiently, without the need for an oscilloscope as in the past, thus significantly saving measurement costs. Attached Figure Description

[0033] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0034] Figure 1This is a system architecture diagram of a method for performing physical layer link response time measurement provided in one embodiment of this application;

[0035] Figure 2 This is a flowchart of a physical layer link response time measurement method provided in one embodiment of this application;

[0036] Figure 3 yes Figure 1 Step S100 method sub-flowchart;

[0037] Figure 4 yes Figure 3 Step S110 method sub-flowchart;

[0038] Figure 5 yes Figure 3 Another method flowchart for step S110;

[0039] Figure 6 yes Figure 1 Step S200 method sub-flowchart;

[0040] Figure 7 yes Figure 1 Another method flowchart for step S200;

[0041] Figure 8 yes Figure 1 Step S300 method sub-flowchart;

[0042] Figure 9 yes Figure 1 Another method flowchart for step S300;

[0043] Figure 10 This is a schematic diagram illustrating the signal changes during the measurement of the PHY's link-up time.

[0044] Figure 11 This is a schematic diagram illustrating the signal changes during the measurement of the PHY's link down time;

[0045] Figure 12 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the embodiments of this application and are not intended to limit the embodiments of this application.

[0047] In the description of the embodiments of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first" or "second" is used in the description, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0048] In the description of the embodiments of this application, unless otherwise expressly limited, terms such as setting, installing, and connecting should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in the embodiments of this application in combination with the specific content of the technical solution.

[0049] This application provides a method, electronic device, and computer-readable storage medium for measuring physical layer link response time. The method includes: firstly, initialization processing of a first physical layer chip and a second physical layer chip in a physical layer link measurement system controlled by a main control chip; then, a change in the reset signal of either the first or second physical layer chip controlled by the main control chip, and marking the time as a first time node; next, detection processing of the operating state of the second physical layer chip by the main control chip, and marking the time as a second time node when the second physical layer chip generates an operating state change matching the reset signal change; finally, subtraction between the first and second time nodes to obtain the physical layer link response time. This technical solution enables simple, fast, and efficient measurement of physical layer link response time, eliminating the need for an oscilloscope as in the past, thus significantly reducing measurement costs.

[0050] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0051] like Figure 1 As shown, Figure 1 This is a schematic diagram of the architecture of a physical layer link measurement system provided in one embodiment of this application. The physical layer link measurement system includes a main control chip 300, a first physical layer chip 100, and a second physical layer chip 200; wherein, both the first physical layer chip 100 and the second physical layer chip 200 are connected to the main control chip 300, and the first physical layer chip 100 is also connected to the second physical layer chip 200; through the above settings, both the first physical layer chip 100 and the second physical layer chip 200 can be signal connected to the main control chip 300, and the first physical layer chip 100 and the second physical layer chip 200 can also be signal connected to each other.

[0052] Specifically, both the first physical layer chip 100 and the second physical layer chip 200 are provided with reset control pins. The reset control pin of the first physical layer chip 100 is connected to the main control chip 300, and the reset control pin of the second physical layer chip 200 is also connected to the main control chip 300. Both the first physical layer chip 100 and the second physical layer chip 200 are also provided with signal status detection pins. The signal status detection pin of the first physical layer chip 100 is connected to the main control chip 300, and the signal status detection pin of the second physical layer chip 200 is also connected to the main control chip 300. Through the above configuration, the main control chip 300 can send a reset signal through the reset control pin of the first physical layer chip 100 to control the operating state of the first physical layer chip 100; similarly, the main control chip 300 can also send a reset signal through the reset control pin of the second physical layer chip 200 to control the operating state of the second physical layer chip 200. The main control chip 300 can also detect and process the link status of the first physical layer chip 100 through the signal status detection pin of the first physical layer chip 100; similarly, the main control chip 300 can also detect and process the link status of the second physical layer chip 200 through the signal status detection pin of the second physical layer chip 200. Specifically, the main control chip 300 can send a reset signal 0 to the reset control pin of the first physical layer chip 100, and a reset signal 1 to the reset control pin of the second physical layer chip 200, so that the main control chip 300 can control the operating status of the first physical layer chip 100 and the second physical layer chip 200; the first physical layer chip 100 can send a link status signal 0 to the main control chip 300 through the signal status detection pin, and the second physical layer chip 200 can send a link status signal 1 to the main control chip 300 through the signal status detection pin, thereby enabling the main control chip 300 to detect and process the link status of the first physical layer chip 100 and the second physical layer chip 200.

[0053] It is worth noting that the first physical layer chip 100 and the second physical layer chip 200 can be connected via a network cable; the first physical layer chip 100 and the second physical layer chip 200 are Ethernet physical layer transceiver chips, which connect the main control chip 300 to the network cable interface. The use of the first physical layer chip 100 and the second physical layer chip 200 is merely to distinguish different physical layer chip objects for clarity in subsequent embodiment descriptions, and does not imply any difference in their attributes or properties.

[0054] Specifically, in practical application scenarios, the first physical layer chip 100 and the main control chip 300 belong to the measurement tool, while the second physical layer chip 200 belongs to the device under test. Alternatively, in EtherCAT industrial bus slave devices, the system of the device under test usually contains the main control chip 300 and two physical layer chips, in which case there is no need for external measurement tools, and the physical layer link measurement system can be built directly using the existing system.

[0055] The system architecture and application scenarios described in this application are intended to more clearly illustrate the technical solutions of this application and do not constitute a limitation on the technical solutions provided in this application. Those skilled in the art will understand that as system architectures evolve and new application scenarios emerge, the technical solutions provided in this application are also applicable to similar technical problems.

[0056] It will be understood by those skilled in the art that Figure 1 The system architecture shown does not constitute a limitation on the embodiments of this application. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0057] Based on the above system architecture, various embodiments of the physical layer link response time measurement method of this application are proposed.

[0058] like Figure 2 As shown, Figure 2 This is a flowchart of a physical layer link response time measurement method. The method includes, but is not limited to, steps S100, S200, S300, and S400:

[0059] Step S100: Initialization is completed by controlling the first physical layer chip and the second physical layer chip based on the main control chip.

[0060] Step S200: Based on the change in the reset signal of the first physical layer chip or the second physical layer chip controlled by the main control chip, and mark the time as the first time node;

[0061] Step S300: Based on the main control chip, the working state of the second physical layer chip is detected, and when the second physical layer chip generates a working state change that matches the change of the reset signal, the time is marked as the second time node.

[0062] Step S400: Perform a difference operation based on the first time node and the second time node to obtain the physical layer link response time.

[0063] It should be noted that in the process of measuring the physical layer link response time, the first and second physical layer chips of the physical layer link measurement system are first initialized by the main control chip. Then, the reset signal of either the first or second physical layer chip changes, and the time is marked as the first time node. Next, the operating state of the second physical layer chip is detected by the main control chip, and when the second physical layer chip produces an operating state change that matches the reset signal change, the time is marked as the second time node. Finally, the difference between the first and second time nodes is calculated to obtain the physical layer link response time. This technical solution allows for simple, fast, and efficient measurement of the physical layer link response time, eliminating the need for an oscilloscope as in the past and significantly reducing measurement costs.

[0064] It is worth noting that the main control chip needs to control the first and second physical layer chips to complete the initialization process, which prepares for subsequent physical layer link response time measurement. Specifically, during the initialization process, the main control chip can either keep the reset signals input to the first and second physical layer chips low to measure the response time of physical layer link reconnection, or keep the reset signals high to measure the response time of physical layer link disconnection.

[0065] It is worth noting that after the first physical layer chip and the second physical layer chip complete initialization, the main control chip can be used to control the reset signal of the first physical layer chip or the second physical layer chip to change, and record the time node when the reset signal changes as the first time node. Specifically, in the process of measuring the response time of physical layer link reconnection, it is necessary to control the reset signal of the second physical layer chip to change; in the process of measuring the response time of physical layer link disconnection, it is necessary to control the reset signal of the first physical layer chip to change.

[0066] It is worth noting that after the reset signal controlling the first or second physical layer chip changes, the operating state of the second physical layer chip can be detected. When a change in the operating state of the second physical layer chip due to the reset signal change is detected, this time point can be recorded as the second time point. Finally, the difference between the second time point and the first time point can be calculated to obtain the physical layer link response time, making the measurement of the physical layer link response time simpler and faster. The first and second time points can be marked using a timer inside the main control chip, further simplifying the timing process.

[0067] Additionally, in one embodiment, such as Figure 3 As shown, the initialization is completed by the main control chip controlling the first physical layer chip and the second physical layer chip, which may include, but is not limited to, step S110:

[0068] Step S110: The main control chip sends a reset signal to the reset control pins of the first physical layer chip and the second physical layer chip so that the first physical layer chip and the second physical layer chip complete the initialization.

[0069] It should be noted that during the initialization process controlled by the main control chip to complete the first and second physical layer chips, a reset signal can be sent from the main control chip to the reset control pins of the first and second physical layer chips. For example, the reset signal input to the first and second physical layer chips can be set to a low level to measure the response time of subsequent physical layer link reconnection; alternatively, the reset signal input to the first and second physical layer chips can be set to a high level to measure the response time of subsequent physical layer link disconnection.

[0070] It is worth noting that for different physical layer link response time measurements, the reset signals input to the first physical layer chip and the second physical layer chip can be controlled to be in a low-level state or a high-level state to prepare for subsequent physical layer link response time measurements.

[0071] Additionally, in one embodiment, such as Figure 4 As shown, the process involves the main control chip sending a reset signal to the reset control pins of the first physical layer chip and the second physical layer chip to initialize them. This can include, but is not limited to, step S111.

[0072] Step S111: The main control chip sends a low-level signal to the reset control pins of the first physical layer chip and the second physical layer chip, and maintains it for a first preset time threshold, so that the first physical layer chip and the second physical layer chip complete the initialization.

[0073] It should be noted that during the measurement of the response time for physical layer link reconnection, the main control chip can send a low-level signal to the reset control pins of the first and second physical layer chips and maintain it for a first preset time threshold, thereby enabling the first and second physical layer chips to complete initialization. The first preset time threshold can be set according to actual needs.

[0074] For example, during the measurement of the response time for physical layer link reconnection, the main control chip can send a low-level signal to the reset control pins of the first physical layer chip and the second physical layer chip and hold it for 100ms, thereby enabling the first physical layer chip and the second physical layer chip to complete the reset.

[0075] Additionally, in one embodiment, such as Figure 5 As shown, the process of the main control chip sending a reset signal to the reset control pins of the first physical layer chip and the second physical layer chip to enable the first physical layer chip and the second physical layer chip to complete initialization may include, but is not limited to, steps S112 and S113:

[0076] Step S112: The main control chip sends a high-level signal to the reset control pins of the first physical layer chip and the second physical layer chip, and maintains it for a second preset time threshold.

[0077] Step S113: Based on the main control chip, the signal status detection pins of the first physical layer chip and the second physical layer chip are detected until it is found that both the first physical layer chip and the second physical layer chip are in a normal link state, so that the first physical layer chip and the second physical layer chip complete the initialization.

[0078] It should be noted that during the measurement of the response time for physical layer link disconnection, the main control chip first sends a high-level signal to the reset control pins of the first and second physical layer chips, maintaining this signal for a second preset time threshold. Then, the main control chip performs signal detection on the signal status detection pins of the first and second physical layer chips until both chips are detected to be in a normal link state, thus completing the initialization of the first and second physical layer chips. The second preset time threshold can also be set according to actual needs.

[0079] For example, during the measurement of the response time of physical layer link disconnection, the main control chip can send a high-level signal to the reset control pins of the first physical layer chip and the second physical layer chip and maintain it for 100ms; then the main control chip can perform signal detection on the signal status detection pins of the first physical layer chip and the second physical layer chip until both the first physical layer chip and the second physical layer chip are in the physical layer link connection state, thereby enabling the first physical layer chip and the second physical layer chip to complete the initialization.

[0080] Additionally, in one embodiment, such as Figure 6 As shown, the change in the reset signal of the first physical layer chip or the second physical layer chip controlled by the main control chip, and the marking time as the first time node, may include, but is not limited to, steps S210 and S220:

[0081] Step S210: Based on the main control chip sending a high-level signal to the reset control pin of the first physical layer chip and maintaining it for a third preset time threshold, so that the first physical layer chip enters a normal working state.

[0082] Step S220: Based on the main control chip, the reset control pin of the second physical layer chip is controlled to change from low level to high level, and the time is marked as the first time node.

[0083] It should be noted that, in the process of the main control chip controlling the reset signal of the second physical layer chip to change and marking the time as the first time node, the main control chip first sends a high-level signal to the reset control pin of the first physical layer chip and maintains it for a third preset time threshold so that the first physical layer chip enters the normal working state; then, the main control chip can control the reset control pin of the second physical layer chip to change from low level to high level and mark the time as the first time node, in order to prepare for the response time measurement of physical layer link restoration.

[0084] It is worth noting that the third preset time threshold can be set according to actual needs.

[0085] Additionally, in one embodiment, such as Figure 7 As shown, the change in the reset signal of the first physical layer chip or the second physical layer chip controlled by the main control chip, and the marking time as the first time node, may include, but is not limited to, step S230:

[0086] Step S230: Based on the main control chip, the reset control pin of the first physical layer chip is controlled to change from high level to low level, so that the first physical layer chip enters the reset state, and the time is marked as the first time.

[0087] It should be noted that during the process of the reset signal of the first physical layer chip controlled by the main control chip changing and the time being marked as the first time node, the reset control pin of the first physical layer chip controlled by the main control chip changes from high level to low level and the time is marked as the first time node, in order to prepare for the measurement of the response time of physical layer link disconnection.

[0088] Additionally, in one embodiment, such as Figure 8 As shown, the main control chip detects the working state of the second physical layer chip, and when the second physical layer chip generates a working state change that matches the change in the reset signal, the time is marked as the second time node. This may include, but is not limited to, steps S310 and S320:

[0089] Step S310: Perform signal detection on the signal status detection pin of the second physical layer chip based on the main control chip;

[0090] Step S320: When the second physical layer chip is detected to have switched from a link failure state to a link normal state, the time is marked as the second time node.

[0091] It should be noted that, based on the main control chip's detection of the second physical layer chip's operating status, and when the second physical layer chip generates an operating status change that matches the reset signal change, the process of marking the time as the second time node begins. First, the main control chip performs signal detection on the signal status detection pin of the second physical layer chip. When it is detected that the second physical layer chip has switched from a link failure state to a link normal state because the reset control pin of the second physical layer chip has changed from a low level to a high level, the time can be marked as the second time node. Subsequently, the difference between the second time node and the first time node can be calculated to determine the physical layer link response time.

[0092] Additionally, in one embodiment, such as Figure 9 As shown, the main control chip detects the working state of the second physical layer chip, and when the second physical layer chip generates a working state change that matches the change in the reset signal, the time is marked as the second time node. This may include, but is not limited to, steps S330 and S340:

[0093] Step S330: Perform signal detection on the signal status detection pin of the second physical layer chip based on the main control chip;

[0094] Step S340: When the second physical layer chip is detected to have switched from a normal link state to a failed link state, the time is marked as the second time node.

[0095] It should be noted that, based on the main control chip detecting the working state of the second physical layer chip, and when the second physical layer chip generates a working state change that matches the reset signal change, the time is marked as the second time node. First, the main control chip detects the signal state detection pin of the second physical layer chip. When it is detected that the second physical layer chip switches from a normal link state to a link failure state because the reset control pin of the first physical layer chip changes from a high level to a low level, the time can also be marked as the second time node. Subsequently, the difference between the second time node and the first time node can be calculated to determine the physical layer link response time.

[0096] It is worth noting that the physical layer link response time includes the response time for switching from a normal link state to a failed link state and the response time for switching from a failed link state to a normal link state. For different situations, the reset signals of the first physical layer chip and the second physical layer chip can be flexibly adjusted to complete the corresponding response time measurement process, making the determination of the physical layer link response time more flexible, convenient and fast.

[0097] To more clearly illustrate the process of the physical layer link response time measurement method provided in this application embodiment, specific examples are given below.

[0098] Note: This application embodiment includes a measuring tool and a device under test (DUT). The measuring tool includes a main control chip and a general-purpose PHY0, and the DUT includes the device under test (PHY1). The reset signal and link status signal of both PHY0 and PHY1 need to be connected to the main control chip. PHY0 and PHY1 are connected via a network cable. reset0 represents the reset signal of PHY0, and reset1 represents the reset signal of PHY1.

[0099] The main control chip controls the PHY to switch between two operating states: reset and normal operation, via a reset signal. Simultaneously, the main control chip can obtain the PHY's link status via a link signal. Furthermore, a timer is enabled in the main control chip to clock the control and state transitions. The link response time can be obtained by the time difference between the link state change and the control output. This embodiment can be tested using simple measurement tools or the existing main control chip and PHY in the system, without requiring external professional measurement equipment.

[0100] like Figure 10As shown, the link-up time of the PHY is measured. First, system initialization is performed by starting a timer with a timing step of t, where t must be less than or equal to 100ns and the maximum timing duration must be greater than 3s. The master controller controls reset0 and reset1 to low level for 100ms to ensure the PHY completes reset and initialization. Then, the master controller controls reset0 to high level and waits for more than 200ms for PHY0 to enter normal operating state. Next, the master controller controls reset1 to transition from low to high level, at which point the timer count value T1 is acquired. Finally, the master controller continuously acquires the link1 status until it is pulled high, recording the timer count value T2 at this point. The PHY link-up time is equal to (T2-T1)t. The link-up time is the response time for switching from a link failure state to a link normal state.

[0101] like Figure 11 As shown, the link down time of the PHY is measured. First, system initialization is performed by starting a timer with a timing step of t, where t must be less than or equal to 100ns and the maximum timing duration must be greater than 3s. The master controller controls reset0 and reset1 to low level for 100ms. Then, the master controller controls reset0 and reset1 to high level to acquire the PHY link status. Initialization is complete when both link0 and link1 are in the link up state. Next, the master controller controls reset0 to low level, putting PHY0 into a reset state, and the timer count value T3 is recorded at this time. Finally, the master controller continuously acquires the link1 status until it is pulled low, and the timer count value T4 is recorded at this time. The PHY link down time is equal to (T4-T3)t. Here, the link down time is the response time for the link to switch from a normal state to a link failure state.

[0102] This completes the measurement of the PHY's link response time, including link up time and link down time.

[0103] Through the above technical solution, the embodiments of this application can achieve high-precision PHY link response time by using existing systems or simple measurement tools. The measurement is simple and can save measurement costs and speed up the measurement process.

[0104] In some embodiments of this application, such as Figure 12As shown, one embodiment of this application also provides an electronic device 700, including: a memory 720, a processor 710, and a computer program stored in the memory 720 and executable on the processor 710. When the processor 710 executes the computer program, it implements the physical layer link response time measurement method in the above embodiment.

[0105] In some embodiments of this application, one embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or controller, for example, by a processor in the above-described device embodiment, causing the processor to perform the physical layer link response time measurement method in the above-described embodiment.

[0106] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0107] The above is a detailed description of the preferred embodiments of this application. However, the embodiments of this application are not limited to the above-described implementation methods. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the embodiments of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of the embodiments of this application.

Claims

1. A method for measuring physical layer link response time, characterized in that, An application is made in a physical layer link measurement system, the physical layer link measurement system including a main control chip, a first physical layer chip, and a second physical layer chip, both the first physical layer chip and the second physical layer chip being connected to the main control chip, and the first physical layer chip also being signal-connected to the second physical layer chip, the method comprising: The main control chip controls the first physical layer chip and the second physical layer chip to complete the initialization. The main control chip controls the reset signal of the first physical layer chip or the second physical layer chip to change, and the time is marked as the first time node; The main control chip detects the working state of the second physical layer chip, and when the second physical layer chip generates a working state change that matches the change in the reset signal, the time is marked as the second time node. The physical layer link response time is obtained by performing a difference operation based on the first time node and the second time node. The physical layer link response time includes the response time for switching from a normal link state to a failed link state and the response time for switching from a failed link state to a normal link state; the reset control pins of the first physical layer chip and the second physical layer chip are both connected to the main control chip, and the initialization of the first physical layer chip and the second physical layer chip based on the main control chip includes: The main control chip sends the reset signal to the reset control pin of the first physical layer chip and the second physical layer chip so that the first physical layer chip and the second physical layer chip can complete the initialization. The step of sending a reset signal from the main control chip to the reset control pins of the first physical layer chip and the second physical layer chip to enable the first physical layer chip and the second physical layer chip to complete initialization includes: Regarding the response time for switching from a link failure state to a link normal state, the main control chip sends a low-level signal to the reset control pin of the first physical layer chip and the second physical layer chip, and maintains it for a first preset time threshold, so that the first physical layer chip and the second physical layer chip can complete initialization. Alternatively, regarding the response time for switching from a normal link state to a failed link state, the main control chip sends a high-level signal to the reset control pins of the first physical layer chip and the second physical layer chip, and maintains it for a second preset time threshold. The main control chip then performs signal detection on the signal status detection pins of the first physical layer chip and the second physical layer chip until it is detected that both the first physical layer chip and the second physical layer chip are in a normal link state, so that the first physical layer chip and the second physical layer chip complete initialization.

2. The physical layer link response time measurement method according to claim 1, characterized in that, The step of controlling the reset signal of the first physical layer chip or the second physical layer chip based on the main control chip to change, and marking the time as the first time node, includes: The main control chip sends a high-level signal to the reset control pin of the first physical layer chip and maintains it for a third preset time threshold so that the first physical layer chip enters a normal working state. The main control chip controls the reset control pin of the second physical layer chip to switch from low level to high level, and the time is marked as the first time node.

3. The physical layer link response time measurement method according to claim 1, characterized in that, The step of controlling the reset signal of the first physical layer chip or the second physical layer chip based on the main control chip to change, and marking the time as the first time node, includes: The main control chip controls the reset control pin of the first physical layer chip to switch from high level to low level, so that the first physical layer chip enters the reset state and the time is marked as the first time node.

4. The physical layer link response time measurement method according to claim 2, characterized in that, The signal state detection pins of both the first physical layer chip and the second physical layer chip are connected to the main control chip. The step of detecting the operating state of the second physical layer chip based on the main control chip, and marking a second time node when the second physical layer chip generates an operating state change matching the reset signal change, includes: The main control chip performs signal detection on the signal status detection pin of the second physical layer chip. When the second physical layer chip is detected to have switched from a link failure state to a link normal state, the time is marked as the second time node.

5. The physical layer link response time measurement method according to claim 3, characterized in that, The step of detecting the operating state of the second physical layer chip based on the main control chip, and marking the time as the second time node when the second physical layer chip generates an operating state change that matches the change in the reset signal, includes: The main control chip performs signal detection on the signal status detection pin of the second physical layer chip. When the second physical layer chip is detected to have switched from a normal link state to a link failure state, the time is marked as the second time node.

6. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the physical layer link response time measurement method as described in any one of claims 1 to 5.

7. A computer-readable storage medium storing computer-executable instructions, characterized in that, When the computer-executable instructions are executed by the control processor, they implement the physical layer link response time measurement method as described in any one of claims 1 to 5.

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