Storage control module, memory controller and three-dimensional stacked memory

Abstract

The invention provides a memory control module, a memory controller and a three-dimensional stacked memory, which can process the execution time sequence of a plurality of operation instructions when managing the execution of a plurality of operation instructions of a corresponding memory unit (comprising a plurality of stacked memory array bodies, and each memory array body is provided with a latch circuit) in a memory stack body. Under the condition that the execution of the previous operation instruction of the first storage array body is not completed and the next operation instruction of the second storage array body is received, a chip selection signal is switched in advance, and then after the chip selection signal is switched, the next operation instruction is executed by the second storage array body, and the next operation instruction is executed by the second storage array body at the same time. And the first storage array body can continuously execute the last operation instruction according to the latched execution row address, so that the multiple storage array bodies of the memory can be accessed in parallel, some inevitable internal delays of the memory are relatively saved, and the effects of reducing access bubbles and improving the bandwidth utilization rate of the memory are achieved.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the parent application with application number CN202510772555.6, application date June 10, 2025, and invention title "Storage Control Module, Memory Controller and Three-Dimensional Stacked Memory". Technical Field

[0003] This invention relates to the field of integrated circuit technology, and in particular to a storage control module, a memory controller, and a three-dimensional stacked memory. Background Technology

[0004] Dynamic Random Access Memory (DRAM) is a commonly used type of memory, and its bandwidth utilization is often used as a key parameter for evaluating memory performance, playing a decisive role in the overall system performance. With the advancement of process technology, new memory architectures such as Through-Silicon Vias (TSV) hybrid bonding technology have continuously improved the bandwidth utilization of three-dimensional (3D) stacked DRAM. However, traditional DRAM controllers use a single-level scheduling strategy, which cannot effectively coordinate parallel access of multi-layer stacks. At the same time, since delays such as tRCD (Row to CASDelay) and tRP (Row Precharge Time) within DRAM are unavoidable, they naturally impose constraints on bandwidth utilization.

[0005] Therefore, how to improve the bandwidth utilization of DRAM and other three-dimensional stacked memories has become one of the hot technical issues that urgently need to be addressed by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a storage control module, a memory controller, and a three-dimensional stacked memory, which can relatively save some unavoidable latency within the memory when managing the execution of multiple operation instructions for corresponding storage cells in the memory stack, thereby improving the bandwidth utilization of the memory.

[0007] To achieve the above objectives, the present invention provides a storage control module for controlling the execution of multiple operation instructions of corresponding storage cells in a memory stack, wherein the storage cell comprises multiple stacked storage arrays, each of which has a latching circuit, and the storage control module is configured to:

[0008] The chip select signal corresponding to the memory cell is activated according to the decoding information of each operation instruction, so as to select a corresponding memory array in the memory cell for access, and then the execution address of the operation instruction is latched by the latch circuit in the selected memory array, and the selected memory array executes the operation instruction.

[0009] In the case where the first memory array among the multiple memory arrays is selected to execute the previous operation instruction, and the next operation instruction is received before the previous operation instruction is completed, the chip select signal corresponding to the next operation instruction is switched in advance to select the second memory array among the multiple memory arrays. Then, after the chip select signal is switched, while the second memory array executes the next operation instruction, the first memory array continues to execute the previous operation instruction according to the latched execution address.

[0010] Optionally, the storage control module includes:

[0011] The user interface is used to receive the decoding information of each of the plurality of operation instructions, wherein the decoding information of each operation instruction includes the execution address of the operation instruction and the line activation start signal;

[0012] The storage control logic is coupled to the user interface and the storage interface of the storage unit, and is used to provide the storage unit with corresponding chip select signal, row address signal, column address signal, row activation signal and column enable signal according to the decoding information of each operation instruction, so that the selected first storage array or the second storage array executes the corresponding operation instruction, and at the same time realizes the switching of the chip select signal.

[0013] Optionally, the storage control logic is configured to execute the following timing sequence:

[0014] At the first moment, the storage control logic receives the execution address of the previous operation instruction based on the row activation start signal of the previous operation instruction, and after a first delay, activates the previous chip select signal corresponding to the first storage array to select the first storage array for access.

[0015] At the second moment, the storage control logic receives the execution address of the next operation instruction based on the line activation start signal of the next operation instruction. After a first delay, it activates the next chip select signal corresponding to the second storage array to select the second storage array for access. During this period, the first storage array continues to execute the previous operation instruction according to its latched execution address.

[0016] At the third moment, after the first memory array completes the previous operation instruction, the memory control logic ends its access to the first memory array. After a second delay, the memory control logic turns off the previous chip select signal.

[0017] At the fourth moment, the storage control logic receives the execution address of the next operation instruction based on the row activation start signal of the next operation instruction. After a first delay, it activates the next chip select signal corresponding to the storage unit to select the third storage array in the storage unit for access. During this period, the second storage array continues to execute the next operation instruction according to its latched execution address. The third storage array may be the same as or different from the first storage array.

[0018] At the fifth moment, after the second memory array completes the next operation instruction, the memory control logic ends its access to the second memory array. After a second delay, the memory control logic turns off the next chip select signal.

[0019] Optionally, the storage control logic parses the information of the previous chip select signal and / or the next chip select signal from the high-order address of the execution address of the previous operation instruction and / or the next operation instruction.

[0020] Optionally, both the first delay and the second delay are measured in clock cycles, and the first delay is equal to 1 clock cycle.

[0021] Optionally, the previous operation instruction is a read instruction, the second delay is a read precharge delay, after the user interface sends the execution column address of the previous operation instruction, the user column enable signal received by the user interface is pulled low, and after the second delay, the row activation end signal received by the user interface is pulled high to indicate that the previous operation instruction has been executed; and / or, the next operation instruction is a read instruction, the second delay is a read precharge delay, after the user interface sends the execution column address of the next operation instruction, the user column enable signal received by the user interface is pulled low, and after the second delay, the row activation end signal received by the user interface is pulled high to indicate that the next operation instruction has been executed.

[0022] Optionally, the latch circuit in the first memory array responds to the activation of the previous chip select signal by latching the execution address of the previous operation instruction and causing the first memory array to begin executing the previous operation instruction; and / or, the latch circuit in the second memory array responds to the activation of the next chip select signal by latching the execution address of the next operation instruction and causing the second memory array to begin executing the next operation instruction.

[0023] Optionally, the storage control module simultaneously manages multiple storage cells in the memory stack, each storage cell comprising multiple stacked storage arrays, each storage array comprising multiple word lines corresponding to multiple rows and multiple bit lines corresponding to multiple columns.

[0024] Based on the same inventive concept, this invention also provides a memory controller for controlling the execution of multiple operation instructions of a corresponding memory stack. Each memory cell in the memory stack includes multiple stacked memory arrays, each of which has a latching circuit. The memory controller includes multiple host device interfaces, a memory control management module, and several memory control modules as described in this invention.

[0025] Each of the master device interfaces is communicatively connected to the corresponding master device and is used to receive operation instructions to be executed, wherein each of the master device interfaces is a multi-IO parallel interface;

[0026] The memory control management module is coupled to the main device interface and each of the memory control modules, and is used to parse each operation instruction received by the main device interface to generate corresponding decoding information, and determine the memory control module and memory unit hit by each operation instruction according to the decoding information, and then provide the decoding information of the operation instruction to the hit memory control module.

[0027] Each of the storage control modules is coupled to at least one storage cell in the memory stack and is used to receive corresponding decoding information, thereby accessing the coupled storage cell based on the decoding information and controlling the storage cell to execute corresponding operation instructions.

[0028] Optionally, the memory control management module includes a control manager and an address decoder;

[0029] The control manager is coupled to each of the main device interfaces, the address decoder, and each of the storage control modules. The control manager is used to send the address of the operation instruction to be executed received by the main device interface to the address decoder for address parsing, so as to determine the storage control module, the storage unit, and the row in the storage unit that is hit by each operation instruction to be executed, and then transmit the row address of the hit row parsed by the address decoder to the hit storage control module.

[0030] Optionally, the memory controller is disposed on the buffer die, the memory stack comprises stacked multilayer memory dies, each memory array in each memory cell is a part of the corresponding memory die, and the multilayer memory dies are hybrid-bonded to each other and to the buffer die via through-silicon vias.

[0031] Optionally, the master device is located in a logic die, the logic die, the buffer die and the memory stack are stacked in sequence, and the logic die and the buffer die are hybrid bonded through through-silicon vias.

[0032] Based on the same inventive concept, the present invention also provides a three-dimensional stacked memory, which includes a memory stack and a memory controller as described in the present invention, the memory controller being disposed on a buffer die, the memory stack including three-dimensionally stacked multi-layer memory dies, wherein the multi-layer memory dies are hybrid-bonded to each other and to the buffer die via through-silicon vias.

[0033] Compared with the prior art, the storage control module, memory controller, and three-dimensional stacked memory provided by the present invention can handle the timing of the execution of multiple operation instructions of the corresponding storage cells (which include multiple stacked storage arrays, each of which has a latching circuit) in the memory stack. In the case where the previous operation instruction of the first storage array has not been completed and the next operation instruction of the second storage array is received, the chip select signal corresponding to the next operation instruction can be switched in advance. Then, after the chip select signal is switched, while the second storage array is executing the next operation instruction, the first storage array will continue to execute the previous operation instruction according to its latched execution address. This allows for parallel access to the multiple storage arrays of the memory, relatively saving some unavoidable internal latency of the memory (such as saving tRP and tRCD), thereby reducing access bubbles and improving the bandwidth utilization of the memory. Attached Figure Description

[0034] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0035] Figure 1 This is a schematic diagram of an existing DRAM controller's operation instruction processing method.

[0036] Figure 2 This is a schematic diagram of the architecture of a storage control module according to an embodiment of the present invention.

[0037] Figures 3 to 5 This is a timing diagram illustrating the execution of a storage control module according to an embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of the architecture of a storage control module according to another embodiment of the present invention.

[0039] Figure 7 This is a schematic diagram of the architecture of a memory controller according to an embodiment of the present invention.

[0040] Figure 8 This is a schematic diagram of the packaging structure of a three-dimensional stacked memory according to an embodiment of the present invention.

[0041] Figure 9 This is a schematic diagram of the structure of a storage array in a three-dimensional stacked memory according to an embodiment of the present invention. Detailed Implementation

[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0043] Please refer to Figure 1 The current DRAM controller receives three read operation commands, A, B, and C, and sends these three read commands to the DRAM interface (the memory interface used for communication between the memory array and the DRAM controller) in the order of A, B, and C. During this process, due to unavoidable delays within the DRAM, such as tRDD (Row to Row Delay), tRCD (Row to CAS Delay), tRAS(min) (min RAS Active Time), tRP (Row Precharge Time), tRC(min) (min Row Cycle Time), and tRTP (Read to Precharge delay), the DRAM controller requires 54 clock cycles (1 clock cycle can be denoted as "1CLK") to send all three read commands (A, B, and C) to the DRAM interface. Clearly, the unavoidable delays such as tRP and tRCD within the DRAM naturally constrain the bandwidth utilization of the DRAM interface, resulting in low efficiency.

[0044] Here, tRCD represents the minimum latency between the row "activation command" and the sending of the column address command (i.e., the execution column address for sending read / write instructions), measured in clock cycles (CLK). When the memory controller activates a row (opens the row), it needs to wait for tRCD time before performing a read or write operation on that row. This is to ensure the capacitor charge of the cells in the row is stable, thus ensuring reliable data access.

[0045] tRP represents the waiting time, measured in clock cycles (CLK), required after executing a "Precharge" command to close the current row and then reactivating a new row in the same bank. Precharge closes the currently open row and prepares it for the next row activation. tRP ensures that the cell's capacitance has sufficient time to recover to its initial state, avoiding data collisions. After closing the current row (via the Precharge command), you must wait for tRP before sending a new ACTIVE command.

[0046] tRTP represents the minimum delay time between sending a "read" command and being allowed to send a "precharge" command, measured in clock cycles (CLK). tRTP ensures that data has been transferred from the memory cell (DU) to the sense amplifier before the current row is closed, after the read operation (i.e., the read command) is complete. Note: tRTP only applies to read operations (i.e., only to read commands); write operations can be precharged directly (without tRTP waiting).

[0047] Based on this, please refer to Figures 2 to 9 An embodiment of the present invention provides a storage control module IP, which is used to control the execution of multiple operation instructions (i.e., multiple operation instructions to be executed, such as multiple read instructions) of a corresponding storage unit DU (also referred to as a "data unit") in a memory stack 3. The storage unit DU includes multiple stacked storage arrays, each storage array having a latch circuit 30b. The storage control module IP is configured to:

[0048] Based on the decoding information of each operation instruction (e.g., row address signal MC_RADD and row activation start signal MC_WLACT), the chip select signal DU_CS corresponding to the memory cell DU is activated to select a corresponding memory array cell for access. Then, the execution address of the operation instruction (e.g., row address signal MC_RADD and column address signal MC_CADD) is latched by the latch circuit 30b in the selected memory array cell, and the selected memory array cell executes the operation instruction.

[0049] In the case where the first memory array in the multi-chip memory array of the memory cell DU is selected to execute the previous operation instruction, and the next operation instruction is received before the previous operation instruction is completed, the chip select signal corresponding to the next operation instruction is switched in advance to select the second memory array in the multi-chip memory array of the memory cell DU. Then, after the chip select signal is switched (for example, from DU_CS0 to DU_CS1), while the second memory array executes the next operation instruction, the first memory array will continue to execute the previous operation instruction according to its latched execution address.

[0050] Therefore, the storage control module IP can access multiple storage arrays of the storage unit DU in parallel, thereby relatively saving some unavoidable latency inside the memory (such as saving tRP and tRCD), achieving the effect of reducing access bubbles and improving the bandwidth utilization of the memory, thus improving bandwidth utilization, while being relatively simple in algorithm implementation.

[0051] These multiple operation instructions can all be read instructions, all be write instructions, a mixture of read and write instructions, or refresh instructions or other operation instructions.

[0052] Please combine Figure 2 and Figures 7-8 In one example, the memory stack 3 includes j+1 memory dies 300 to 30j, where j ≥ 1 and is an integer. These j+1 memory dies 300 to 30j are stacked together in three dimensions using through-silicon via (TSV) hybrid bonding. Therefore, each memory cell DU in the memory stack 3 includes j+1 stacked memory arrays, each memory array being a portion of a corresponding memory die among the dies 300 to 30j. Thus, each memory cell DU corresponds to j+1 chip select signals DU_CS0 to DU_CSj. Figure 2 and Figure 6(Not all chip select signals are shown). The j+1 memory array cells in each memory cell (DU) are also bonded together via through-silicon vias (TSVs) to form corresponding TSVs.

[0053] Furthermore, each memory die 300-30j can be any suitable type of memory die structure, such as DRAM. The DRAM can be any type, such as Synchronous DRAM (SDRAM) or Wide I / O DRAM. The memory stack 3 can be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc.

[0054] This through-silicon via (TSV) hybrid bonding technology, on the one hand, expands the capacity of the memory cells (DUs) managed by the memory control module IP, thereby expanding the capacity of the memory stack 3 managed by the corresponding memory controller and reducing the chip area. On the other hand, the memory control module IP can load corresponding information or data into its interior or into each memory cell (DU) it manages through through-silicon vias (TSVs), thus solving the problem of a large number of traces being occupied when loading this information through dedicated traces (such as EFUSE bus lines) in the prior art.

[0055] Please combine Figure 2 and Figure 9 Each memory array of each memory cell DU, in addition to having latch circuit 30b, also has a corresponding memory array. This memory array consists of multiple word lines WL (each word line can be considered a row), multiple bit lines BL (each bit line can be considered a column), and multiple cells determined by the intersections of these word lines WL and bit lines BL. Each cell is located at the intersection of a corresponding word line WL and a corresponding bit line BL, i.e., corresponding to a memory address. Each word line WL is addressed by the row address (RADD) of the corresponding memory address, and each bit line BL is addressed by the column address (CADD) of the corresponding memory address. A memory cell DU can be a memory block, a sector, or a page, etc., of any suitable management unit above the cell level in the memory stack 3. A page contains multiple bytes (its address range can be determined by multiple word lines and multiple bit lines), a sector contains multiple pages, a storage block contains multiple sectors, and multiple storage units (DUs) can form a storage array (Bank).

[0056] In one example, please refer to Figure 2 The storage control module IP includes a user interface IPa and storage control logic IPB.

[0057] Please combine further Figure 7 The user interface IPa can be coupled to the memory control management module 21 in the memory controller 2 to receive the decoding information of various operation instructions and other relevant information such as the row activation end signal MC_WLACT_END provided by the memory control management module 21. The decoding information of each operation instruction includes the execution address of the operation instruction (including the row address MC_RADD and column address MC_CADD accessed by the operation instruction), the row activation start signal MC_WLACT_START, etc. Among them, the row activation start signal MC_WLACT_START is used to indicate the start of execution of an operation instruction to the memory cell DU, and the row activation end signal MC_WLACT_END is a notification signal used to indicate the end of execution of an operation instruction to the memory cell DU. It is usually pulled high after a tRTP delay when the user column enable signal MC_COLEN is pulled low. The time when MC_COLEN is pulled low is the time when all CADs of the operation instruction have been received, and the time when MC_COLEN is pulled high is the time when MC_WLACT_START is pulled high again after a tRCD delay.

[0058] Furthermore, when the operation instruction is a read instruction, the decoded information received by the user interface IPa also includes the user column enable signal MC_COLEN. MC_COLEN indicates the execution column address MC_CADD after the user interface IPa has sent the read instruction. The user interface IPa outputs the data signal read from the memory cell DU by the memory control logic IPb (i.e., MC_DOUT = DOUT<*>). Moreover, please refer to... Figure 3 When the user interface IPa receives the decoding information of the corresponding read instruction, it will first receive the row address MC_RADD of the read instruction, and after a tRA2WLp delay, it will receive the row activation start signal MC_WLACT_START of the read instruction.

[0059] When the operation instruction is a write instruction, the decoded information received by the user interface IPa also includes the user write enable signal MC_WE, the user column enable signal MC_COLEN, and the data signal MC_DIN for the memory cell DU to be written. The user write enable signal MC_WE indicates that data is allowed to be written to the memory cell DU, and the user column enable signal MC_COLEN indicates the execution column address MC_CADD after the user interface has sent the corresponding operation instruction.

[0060] The storage control logic IPb is coupled to the user interface IPa and the storage interface 30a of the storage unit DU. Based on the decoded information received by the user interface IPa, it provides and switches the corresponding chip select signal DU_CS, row address signal DU_RADD, column address signal DU_CADD, row activation signal DU_WLACT, column enable signal DU_COLEN, etc. to the storage unit DU. Then, it selects the corresponding storage array in the storage unit for access and latches the execution address of the corresponding operation instruction (e.g., row address signal DU_RADD) through the latch circuit 30b in the selected storage array, so that the selected storage array executes the corresponding operation instruction according to the latched execution address.

[0061] Specifically, when the first memory array of the memory cell DU (e.g., its corresponding chip select signal DU_CS0) is selected to execute the previous operation instruction, but before the execution of the previous operation instruction is completed, the memory control logic IPb will switch the chip select signal corresponding to the next operation instruction in advance (e.g., its corresponding chip select signal DU_CS1) to select the second memory array in the memory cell DU for access. Then, after the chip select signal is switched (e.g., from DU_CS0 to DU_CS1), while the second memory array executes the next operation instruction, the first memory array will still continue to execute the previous operation instruction according to its latched execution address.

[0062] Optionally, the high-order bits of the execution address (e.g., the execution line address RADD) of each operation instruction received by the user interface IPa contain chip select information. The storage control logic IPb can parse the chip select signal DU_CS corresponding to the operation instruction from the high-order bits of the execution address of the corresponding operation instruction it receives. In other embodiments of the present invention, the storage control logic IPb can also generate the chip select signal DU_CS corresponding to the operation instruction based on the decoding information of the corresponding operation instruction received by the user interface IPa, etc., in any other suitable manner.

[0063] Please refer to Figures 3 to 5 (in Figures 3 to 5 The times are sequential, and combined with Figure 2 and Figure 7 The storage control logic IPb is also configured to execute the following timing sequence to achieve the above functions:

[0064] At the first moment (i.e., moment 1), the execution line address MC_RADD = RADD1 in the decoded information of the current operation instruction (i.e., the "previous operation instruction", denoted as CMD1, for example, a read instruction) received by the user interface IPa, the line activation start signal MC_WLACT_START is pulled high, and RADD1 maps to a memory array block (i.e., the "first memory array block", denoted as "die0") in the corresponding memory cell DU (e.g., DU0). Figure 7 In the storage cell DU0 shown (300), at this time, the storage control logic IPb receives the execution row address MC_RADD of the previous operation instruction CMD1 according to the MC_WLACT_START, and outputs the row address signal DU_RADD = RADD1. After a first delay (e.g., equal to 1CLK), it activates (or "generates") the chip select signal (i.e. the previous chip select signal, denoted as "DU_CS0") and the row activation signal DU_WLACT of the first storage array die0, so as to select the corresponding row of the first storage array die0 in the storage cell DU for access.

[0065] Optionally, the storage control logic IPb parses the information of DU_CS0 from the high-order address of the execution line address RADD1 of the previous operation instruction CMD1, and then generates DU_CS0.

[0066] Optionally, after DU_CS0 is generated, MC_WLACT_START can go from high to low in anticipation of the arrival of the next corresponding operation instruction (such as the next operation instruction below).

[0067] Please refer to Figure 3 The rising edges of the chip select signal DU_CS0 and the rising edges of the line activation signal DU_WLACT both correspond to the falling edges of the line activation start signal MC_WLACT_START (i.e., Figures 3 to 5 The rising edge of MC_WLACT_START is aligned with the rising edge of DU_WLACT. After the row activation signal DU_WLACT is transmitted to the first memory array die0, the resulting row activation signal is denoted as "WLACT_die0_core". The rising edge of WLACT_die0_core is aligned with the rising edge of DU_WLACT, and the falling edge of WLACT_die0_core is aligned with the rising edge of the row activation end signal MC_WLACT_END received by the subsequent user interface IPa (i.e., the first falling edge of MC_WLACT_START). Figure 4 The timing shown is aligned with the rising edge of MC_WLACT_END.

[0068] Furthermore, the latch circuit 30b inside the first memory array die0 is activated in response to the chip select signal DU_CS0 of the previous operation instruction CMD1, and latches the execution line address RADD1 of the previous operation instruction CMD1.

[0069] For example, the latch circuit 30b inside the first memory array die0 latches the execution line address RADD1 of the previous operation instruction CMD1 at time 1' after time 1 (i.e., the falling edge of the internal row latch signal RADD_die0_LAT), thereby the internal latch line address signal RADD_die0_core of the first memory array die0 is RADD1.

[0070] Please refer to the following: Figure 3 The rising edge of the internal row latch signal RADD_die0_LAT of the first memory array die0 is delayed relative to the rising edge of WLACT_die0_core by the internal delay of the first memory array die0, which is called "core delay". The delay of 1' relative to the rising edge of WLACT_die0_core at this moment is the sum of the internal delay "core delay" and the high level duration of RADD_die0_LAT (i.e., latching time). For example, it can be equal to the first delay (e.g., equal to 1CLK) or not equal to the first delay.

[0071] Furthermore, when the operation instruction is a read instruction, after time 1', the user interface IPa will successively receive the execution column addresses MC_CADD of the previous operation instruction CMD1, and the received user column enable signal MC_COLEN will then be pulled high. The rising edge of MC_COLEN is delayed by tRCD relative to the rising edge of MC_WLACT. The storage control logic IPb further sends the read enable signal DU_RE, the column address signals DU_CADD (corresponding to the execution column address MC_CADD), the column enable signal DU_COLEN, and the read clock signal DU_RDQS to the first storage array die0 through the storage interface 30a of the storage unit DU, thereby starting to read the data in the corresponding row and column of the first storage array die0, i.e., DU_DIO = DOUT, and then feeds back the read data through the user interface IPa, i.e., MC_DOUT = DOUT.

[0072] exist Figure 3In this context, the delay of the first rising edge of DU_COLEN relative to the rising edge of DU_WLACT is tRCD, the delay of the first falling edge of the read clock signal DU_RDQS relative to the first rising edge of DU_COLEN is denoted as "tCOL2RDQS", and the delay of the moment when DU_DIO starts outputting the data signal DOUT relative to the first falling edge of the read clock signal DU_RDQS is denoted as "tRDQS2DOUT".

[0073] It is worth noting that when the CMD1 executed by the first storage array die0 is a read instruction, and the previous operation instruction CMD0 executed before CMD1 is a write instruction, there is a delay tWERE between the rising edge of the read enable signal DU_RE corresponding to CMD1 and the falling edge of the write enable signal DU_WE corresponding to the previous operation instruction CMD0.

[0074] Afterwards, CMD1 will execute for a certain period of time (e.g., until...). Figure 4 At time 2-tRAWLp (when CMD1 has not yet finished executing), the user interface IPa begins to receive the execution line address MC_RADD = RADD2 from the decoding information of the next operation instruction (denoted as CMD2, for example, a read instruction).

[0075] At the second time (i.e., time 2, which is the time after time 1'), the row activation start signal MC_WLACT_START in the decoded information of the next operation instruction CMD2 received by the user interface IPa is pulled high, and the second memory array cell (denoted as "die1", for example) in the corresponding memory cell DU (e.g., DU0) mapped by RADD2 is... Figure 7 In the storage cell DU0 shown in 301), the storage control logic IPb receives the execution row address MC_RADD of the next operation instruction CMD2 according to MC_WLACT_START, and outputs it as a row address signal DU_RADD = RADD2. After a first delay (e.g., equal to 1CLK), it activates (or "generates") the chip select signal of the second storage array die1 (i.e., the next chip select signal, denoted as "DU_CS1") to select the corresponding row of the second storage array die1 in the storage cell DU for access.

[0076] Optionally, the storage control logic IPb parses the information of DU_CS1 from the high-order address of the execution line address RADD2 of the next operation instruction CMD2, and then generates DU_CS1.

[0077] Optionally, after DU_CS1 is generated, MC_WLACT_START can go low again to indicate the arrival of the next operation instruction.

[0078] Please refer to the following: Figure 4 The row address signal DU_RADD = RADD2 starts from the rising edge of the row activation start signal MC_WLACT_START, and the rising edge of the chip select signal DU_CS1 is aligned with the falling edge of the row activation start signal MC_WLACT_START. After the row activation signal DU_WLACT is transmitted to the second memory array die1, the generated row activation signal is denoted as "WLACT_die1_core". The rising edge of WLACT_die1_core is aligned with the rising edge of DU_WLACT, and the falling edge of WLACT_die1_core is aligned with the rising edge of the row activation end signal MC_WLACT_END received by the subsequent user interface IPa (i.e., ...). Figure 5 The timing shown is aligned with the rising edge of MC_WLACT_END.

[0079] Furthermore, please continue to refer to... Figure 4 and combined Figure 2 and Figure 7 The latch circuit 30b inside the second memory array die1 latches the execution line address RADD2 of the next operation instruction CMD2 in response to the activation of the chip select signal DU_CS1 of the next operation instruction CMD2.

[0080] For example, the latch circuit 30b inside the second memory array die1 latches the execution line address RADD2 of the next operation instruction CMD2 at time 2' (i.e., the falling edge of the signal RADD_die1_LAT) after time 2, thereby the internal latch line address signal RADD_die1_core = RADD2 of the second memory array die1.

[0081] Please continue to refer to the following: Figure 4 The rising edge of the internal row latch signal RADD_die1_LAT of the second memory array die1 is delayed relative to the rising edge of WLACT_die1_core by the internal delay of the second memory array die1, which is called "core delay". The delay of 2' relative to the rising edge of WLACT_die1_core is the sum of the internal delay of the second memory array die1, "core delay", and the high level duration of RADD_die1_LAT (i.e., latching time), which can also be equal to the first delay mentioned above (e.g., equal to 1CLK).

[0082] Please continue to refer to this. Figure 4 and combined Figure 2 and Figure 7When the next operation instruction CMD2 is a read instruction, after time 2', the user interface IPa will successively receive the execution column addresses MC_CADD of the next operation instruction CMD2, and the received user column enable signal MC_COLEN will then be pulled high. The rising edge of MC_COLEN is delayed by tRCD relative to the rising edge of MC_WLACT. The storage control logic IPb generates the read enable signal DU_RE, the column address signals DU_CADD, the column enable signal DU_COLEN, and the read clock signal DU_RDQS based on the user column enable signal MC_COLEN and the execution column addresses MC_CADD of the next operation instruction CMD2. Thus, it begins to read the data in the corresponding row and column of the second storage array die1, i.e., DU_DIO = DOUT, and then feeds back the read data MC_DOUT = DOUT through the user interface IPa.

[0083] Please continue to refer to this. Figure 4 and combined Figure 2 and Figure 7 While the second storage array die1 is executing the CMD2 read instruction, the first storage array die0 is simultaneously continuing to execute the previous operation instruction CMD1 according to the row address RADD1 latched by its internal latch circuit 30b.

[0084] Specifically, after the execution column address MC_CADD of the previous operation instruction CMD1 is fully sent to the user interface IPa, the user column enable signal MC_COLEN received by the user interface IPa is pulled low. After a second delay (e.g., for reading the precharge delay tRTP), at the third moment (i.e., moment 3), the row activation end signal MC_WLACT_END received by the user interface IPa is pulled high to indicate that the previous operation instruction CMD1 has been executed. At this point, please continue to refer to... Figure 4 and combined Figure 2 and Figure 7 Once the storage control logic IPb finishes accessing the first storage array die0, the storage control logic IPb can turn off DU_CS0 (i.e., DU_CS0 changes from high to low) based on the high MC_WLACT_END.

[0085] During the period when MC_COLEN is low, the column address signal DU_CADD received by the first memory array die0 remains empty, and the column enable signal DU_COLEN remains low.

[0086] Afterwards, CMD2 will execute for a certain period of time (e.g., until...). Figure 4At time 4-tRAWLp (when CMD1 has already finished executing but CMD2 has not yet finished executing), the user interface IPa begins to receive the execution line address MC_RADD = RADD3 from the decoding information of the next operation instruction (denoted as CMD3, for example, a read instruction).

[0087] For the fourth time point (i.e., time 4, which is the time after time 3), please refer to... Figure 5 and combined Figure 2 and Figure 7 The user interface IPa receives the execution line address MC_RADD = RADD3 in the decoded information of the next operation instruction CMD3. The row activation start signal MC_WLACT_START is pulled high again, and RADD3 maps to a memory array other than the second memory array die1 in the corresponding memory cell DU (e.g., DU0) (e.g., it is still the first memory array die0; in other examples, it can also be other memory arrays besides die0 to die1; die0 is used as an example below). At this time, the memory control logic IPb receives the execution line address MC_RADD of the next operation instruction CMD3 according to the row activation start signal MC_WLACT_START of the next operation instruction CMD3, and outputs the corresponding row address signal DU_RADD = RADD3. After a first delay (e.g., equal to 1CLK), the next chip select signal (e.g., DU_CS0) corresponding to CMD3 is activated to select the corresponding memory array in the memory cell DU (e.g., the first memory array die0) for access. Optionally, after the chip select signal is generated, MC_WLACT_START can go low again to indicate the arrival of the next operation instruction.

[0088] Please refer to the following: Figure 5 The row address signal DU_RADD = RADD3 starts from the rising edge corresponding to the row activation start signal MC_WLACT_START, and the rising edge of the chip select signal DU_CS0 is aligned with the falling edge of the row activation start signal MC_WLACT_START.

[0089] Optionally, the storage control logic IPb parses the information of DU_CS0 from the high-order address of the execution line address RADD3 of the next operation instruction CMD3, and then generates DU_CS0 again.

[0090] For further information, please continue to refer to [link / reference]. Figure 5 and combined Figure 2 and Figure 7When the first memory array die0 corresponding to CMD3 is selected again, a row activation signal WLACT_die0_core will be generated again inside the first memory array die0. The rising edge of WLACT_die0_core is aligned with the rising edge of the chip select signal DU_CS0.

[0091] Furthermore, please continue to refer to... Figure 5 and combined Figure 2 and Figure 7 The latch circuit 30b inside the first memory array die0 is activated in response to the chip select signal DU_CS0 of the next operation instruction CMD3, and latches the execution line address RADD3 of the next operation instruction CMD2. For example, at time 3' after time 4 (i.e., the falling edge of the internal row latch signal RADD_die0_LAT), the latch circuit 30b inside the first memory array die0 latches the execution line address RADD3 of the next operation instruction CMD3, thereby making the internal latch line address signal RADD_die0_core = RADD3 of the first memory array die0.

[0092] Please continue to refer to this. Figure 5 and combined Figure 4 , Figure 2 and Figure 7 When the next operation instruction CMD3 is a read instruction, after time 3', the user interface IPa will successively receive the execution column addresses MC_CADD of the next operation instruction CMD3, and the received user column enable signal MC_COLEN will then be pulled high. The rising edge of MC_COLEN is delayed by tRCD relative to the rising edge of MC_WLACT. The storage control logic IPb generates the read enable signal DU_RE, the column address signals DU_CADD, the column enable signal DU_COLEN, and the read clock signal DU_RDQS based on the user column enable signal MC_COLEN and the execution column addresses MC_CADD of the next operation instruction CMD3. Thus, it begins to read the data in the corresponding row and column of the first storage array die0, i.e., DU_DIO = DOUT, and then feeds back the read data MC_DOUT = DOUT through the user interface IPa.

[0093] Please continue to refer to this. Figure 5 and combined Figure 2 and Figure 7 While the first storage array die0 is executing the CMD3 read instruction, the second storage array die1 is simultaneously executing the next operation instruction CMD2 according to the row address RADD2 latched by its internal latch circuit 30b.

[0094] Specifically, after the execution column address MC_CADD of the next operation instruction CMD2 is fully sent to the user interface IPa, the user column enable signal MC_COLEN received by the user interface IPa is pulled low. After a second delay (e.g., for reading the precharge delay tRTP), at the fifth time (i.e., time 5), the row activation end signal MC_WLACT_END received by the user interface IPa is pulled high to indicate that the next operation instruction CMD2 has been executed. At this point, please continue to refer to... Figure 5 and combined Figure 2 and Figure 7 Once the storage control logic IPb finishes accessing the second storage array die1, the storage control logic IPb can turn off DU_CS1 (i.e., DU_CS1 changes from high to low) based on the high MC_WLACT_END.

[0095] Similarly, following the timing principle described above, the subsequent operation instructions of the storage unit DU are executed, and the layer-by-layer access of these storage arrays in the storage unit DU is realized based on these operation instructions and timing control.

[0096] Therefore, the timing of operation instructions for different memory arrays in the memory cell can be handled. If the previous operation instruction of the first memory array is not completed and the next operation instruction of the second memory array is received, the chip select signal corresponding to the next operation instruction can be switched in advance. Then, after the chip select signal is switched, while the second memory array is executing the next operation instruction, the first memory array will continue to execute the previous operation instruction according to its latched execution address. This allows for parallel access to multiple memory arrays, which can relatively save some unavoidable internal latency of the memory (such as saving tRP and tRCD). The data stream MC_DOUT returned by the user interface IPA will be as continuous as possible, thereby reducing access bubbles and improving the bandwidth utilization of the memory.

[0097] The examples above illustrate the concept of a storage control module (IP) controlling a storage unit (DU), but the technical solution of this invention is not limited to these examples. For other examples, please refer to [link / reference needed]. Figure 6 and Figure 7As shown, a storage control module IP can also control k+1 storage units DU0 to DUk, where k is an integer and k≥1. Each storage unit includes multiple word lines corresponding to multiple rows and multiple bit lines corresponding to multiple columns. The storage control module IP can find the hit storage unit based on the execution address of each operation instruction received by the user interface IPa, and then perform the aforementioned timing control on the execution of operation instructions of different memory arrays in the hit storage unit to parallelize access to the multiple memory arrays of the hit storage unit, thereby relatively saving some unavoidable internal latency.

[0098] Based on the same inventive concept, please refer to Figure 6 and Figure 7 As shown, an embodiment of the present invention also provides a memory controller 2 for controlling the execution of multiple operation instructions of a corresponding memory stack 3. Each memory cell DU in the memory stack 3 includes multiple stacked memory arrays, each of which has a latch circuit 30b. The memory controller 2 includes m main device interfaces 20_0 to 20_m-1, a memory control management module 21, and n+1 memory control modules IP0 to IPn as described in the present invention.

[0099] The master device interfaces 20_0 to 20_m-1 are used for communication with the master device (i.e., the device accessing the memory) 1, realizing the interface conversion between the master device 1 and the memory stack 3, receiving operation instructions and data to be written to the memory stack 3 from the master device 1, and transmitting read data back to the master device 1. The master device interfaces 20_0 to 20_m-1 can be any suitable parallel communication protocol interface that supports multiple I / O, such as the AXI (Advanced eXtensible Interface) interface. The AXI interface is an on-chip bus interface for high-performance, high-bandwidth, and low-latency master-slave architectures. Its address, instruction, and data phases are separated, supporting unaligned data transmission. In burst transmissions, only the starting address is needed. It also features separate read and write data channels, supports large pending instructions (e.g., a large number of incomplete transactions such as read and write instructions) and out-of-order access, and is easier to converge in timing, making it suitable for high-speed memory access. It is worth noting that although the accompanying drawings in the specification show the AXI protocol, the present invention is not limited to this. The main device interfaces 20_0 to 20_m-1 can also adopt any other suitable high-bandwidth interface protocol, such as the AHB (Advanced High-performance Bus) protocol or the CHI (Coherent Hub Interface) protocol.

[0100] The main device 1 may include any type of processing device with computing capabilities, such as a central processing unit (CPU), digital signal processor (DSP), network processor, application processor (AP), field-programmable gate array (FPGA), or dedicated processor. The processing device may be configured to execute instructions or software (including code, operating system, or application program, firmware, or a combination thereof) that can be executed by one or more computers.

[0101] The memory control management module 21 is coupled to each master device interface 20_0~20_m-1 and each memory control module IP0~IPn, and is used to parse each operation command received by the master device interface 20_0~20_m-1 to generate corresponding decoding information. Then, based on the decoding information, it determines the memory control module IP and memory unit DU that each operation command hits, and then provides the decoding information of the operation command and the data to be written MC_DIN to the hit memory control module IP, which includes MC_RADD, MC_WLACT_START, MC_WLACT_END, MC_WE, MC_COLEN, MC_CADD, etc.

[0102] Each storage control module IP is coupled to at least one storage cell DU in the corresponding memory stack 3 and is used to receive corresponding decoding information, thereby accessing the coupled storage cell DU according to the decoding information and controlling the storage cell DU to execute corresponding operation instructions.

[0103] Alternatively, please refer to Figure 7 The memory control management module 21 includes a control manager 211 and an address decoder 212. The control manager 211 is coupled to each master device interface 20_0 to 20_m-1, the address decoder 212, and each memory control module IP0 to IPn. The control manager 211 is used to send the address of the operation instruction to be executed received by the master device interface 20_0 to 20_m-1 to the address decoder 212 for address resolution, so as to determine the memory control module IP, the memory cell DU, and the row in the memory cell hit by each operation instruction to be executed, and then transmit the row address of the hit row resolved by the address decoder 212 to the hit memory control module IP.

[0104] Alternatively, please refer to Figure 8The memory controller 2 is located on the buffer die 200. The memory stack 3 includes j+1 layers of memory dies 300 to 30j. Each memory array in each memory cell DU is a part of the memory die of the corresponding chip. Therefore, each memory cell DU has j+1 layers of memory arrays, which correspond one-to-one with j+1 chip select signals DU_CS0 to DU_CSj. The multilayer memory dies 300 to 30j are bonded to each other and to the buffer die 200 through through-silicon vias.

[0105] Optionally, please combine Figure 7 and Figure 8 The main device 1 is located in the logic die 100, which, the buffer die 200, and the memory stack 3 are stacked in sequence, and the logic die 100 and the buffer die 200 are bonded together by through-silicon vias.

[0106] It should be understood that the memory controller 2 can realize the interface conversion between the master device 1 and the j+1 level memory bare dies 300-30j, and complete the address decoding and data format conversion (such as data bit width) between the master device 1 and the j+1 level memory bare dies 300-30j. It also converts the read, write, and refresh operation instructions issued by the master device 1 into signals that the j+1 level memory bare dies 300-30j can recognize, thus realizing the necessary control of the master device 1's refresh operations, read and write operations on the j+1 level memory bare dies 300-30j (including address signals, data signals, and various instruction signals). The main device 1 can access (or "use" or "operate") the storage resources (i.e., the corresponding storage units) on the j+1 layer memory bare die 300 to 30j according to the user's needs. Therefore, the internal circuit of the memory controller 2 may not be limited to the main device interface 20_0 to 20_m-1, the memory control management module 21 and n+1 storage control modules IP0 to IPn, but may also include any other required functional modules. Alternatively, the memory control management module 21 may not only have the control manager 211 and the address decoder 212, but may also include any other required functional modules. This invention does not specifically limit this.

[0107] Based on the same inventive concept, please refer to Figure 7 and Figure 8 An embodiment of the present invention also provides a three-dimensional stacked memory, which includes a memory stack 3 and a memory controller 2 as described in the present invention. The memory controller 2 is disposed on a buffer die 200. The memory stack 3 includes three-dimensionally stacked j+1 layers of memory dies 300 to 30j, wherein the memory dies 300 to 30j are hybrid bonded to each other and to the buffer die 200 through through-silicon vias.

[0108] Since the memory controller and three-dimensional stacked memory provided by this invention adopt the memory control module of this invention, the switching of the chip select signal in the three-dimensional stacked memory is controlled by the memory control module, and the latching of the latching circuit inside the three-dimensional stacked memory is coordinated to access multiple channels (i.e., multi-layer bare dies) of the three-dimensional stacked memory in parallel, thereby reducing the impact of some internal delays of the three-dimensional stacked memory, and achieving the purpose of reducing access bubbles, improving the interface data continuity of the memory controller, and improving bandwidth utilization.

[0109] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A memory control module for controlling execution of a plurality of operation instructions for corresponding memory cells in a memory stack, the memory control module comprising: The storage unit includes a plurality of stacked storage array bodies, each of which has a latch circuit, and the storage control module is configured to: activate a corresponding chip select signal of the storage unit according to decoding information of each operation instruction to select a corresponding one of the plurality of storage array bodies for access, latch an execution row address of the operation instruction through the latch circuit in the selected storage array body, and cause the selected storage array body to execute the operation instruction; wherein, in a case where a first one of the plurality of storage array bodies is selected to execute a previous operation instruction and a next operation instruction is received before the execution of the previous operation instruction is completed, a chip select signal corresponding to the next operation instruction is switched in advance to select a second one of the plurality of storage array bodies, and the first storage array body continues to execute the previous operation instruction according to the latched execution row address while the second storage array body executes the next operation instruction after the switching of the chip select signal.

2. The storage control module of claim 1, wherein, comprise: a user interface configured to receive decoding information of each of the plurality of operation instructions, the decoding information of each operation instruction comprising an execution address of the operation instruction and a row activation start signal; a storage control logic coupled to a storage interface of the storage unit and configured to provide a corresponding chip select signal, row address signal, column address signal, row activation signal, and column enable signal to the storage unit according to the decoding information of each operation instruction, so that the selected first or second storage array body executes the corresponding operation instruction while the switching of the chip select signal is implemented; and / or the execution address of the operation instruction comprises the execution row address and execution column address accessed by the operation instruction.

3. The storage control module of claim 2, wherein, The storage control logic is configured to implement the following timing: at a first time, the storage control logic receives the execution row address of the previous operation instruction according to the row activation start signal of the previous operation instruction, and activates a previous chip select signal corresponding to the first storage array body to select the first storage array body for access after a first delay; at a second time, the storage control logic receives the execution row address of the next operation instruction according to the row activation start signal of the next operation instruction, and activates a next chip select signal corresponding to the second storage array body to select the second storage array body for access after a first delay, during which the first storage array body continues to execute the previous operation instruction according to the latched execution row address; at a third time, the first storage array body finishes executing the previous operation instruction, the storage control logic ends the access to the first storage array body, and the storage control logic turns off the previous chip select signal after a second delay. In the fourth moment, the storage control logic receives an execution row address of the next operation instruction according to a row activation start signal of the next operation instruction, and activates a next chip select signal corresponding to the storage unit after a first delay to select a third storage array in the storage unit for access, during which the second storage array continues to execute the next operation instruction according to the latched execution row address. In the fifth moment, the second storage array finishes executing the next operation instruction, the storage control logic ends the access to the second storage array, and the storage control logic turns off the next chip select signal after a second delay.

4. The storage control module of claim 3, wherein, The storage control logic parses the information of the previous chip select signal and / or the next chip select signal from the high address of the execution row address of the previous operation instruction and / or the next operation instruction.

5. The storage control module of claim 3, wherein, The first delay and the second delay are both measured in clock cycles, and the first delay is equal to one clock cycle.

6. The storage control module of claim 3, wherein, The previous operation instruction is a read instruction, the second delay is a read-to-precharge delay, the user column enable signal received by the user interface is pulled low after the user interface sends the execution column address of the previous operation instruction, and the row activation end signal received by the user interface is pulled high after the second delay to indicate that the previous operation instruction is executed; and / or, the next operation instruction is a read instruction, the second delay is a read-to-precharge delay, the user column enable signal received by the user interface is pulled low after the user interface sends the execution column address of the next operation instruction, and the row activation end signal received by the user interface is pulled high after the second delay to indicate that the next operation instruction is executed.

7. The storage control module of claim 3, wherein, The latching circuit in the first storage array latches the execution row address of the previous operation instruction in response to the previous chip select signal being activated, and causes the first storage array to start executing the previous operation instruction. And / or, the latching circuit in the second storage array latches the execution row address of the next operation instruction in response to the next chip select signal being activated, and causes the second storage array to start executing the next operation instruction.

8. The storage control module of any one of claims 1-7, wherein, The storage control module simultaneously manages a plurality of storage units in the memory stack, each of the storage units includes a plurality of stacked storage arrays, and each of the storage arrays includes a plurality of word lines corresponding to a plurality of rows and a plurality of bit lines corresponding to a plurality of columns.

9. A memory controller for controlling execution of a plurality of operation instructions of a corresponding memory stack, characterized in that, Each of the storage units in the memory stack includes a plurality of stacked storage arrays, each of the storage arrays has a latching circuit, the memory controller includes a plurality of host interfaces, a memory control management module, and a plurality of storage control modules as claimed in any one of claims 1-8; wherein: Each of the host interfaces is in communication connection with a corresponding host device and is configured to receive an operation instruction to be executed, wherein each of the host interfaces is a multi-IO parallel interface; The memory control management module is coupled to the host interfaces and the memory control modules, and is configured to analyze each of the operation instructions received by the host interfaces to generate corresponding decoding information, and determine a memory control module and a memory cell hit by each of the operation instructions according to the decoding information, and then provide the decoding information of the operation instruction to the memory control module hit. Each of the memory control modules is coupled to at least one memory cell in the memory stack, and is configured to receive corresponding decoding information, and then access the memory cell coupled thereto according to the decoding information, and control the memory cell to execute a corresponding operation instruction.

10. The memory controller of claim 9, wherein, The memory control management module includes a control manager and an address decoder. The control manager is coupled to the host interfaces, the address decoder, and the memory control modules, and is configured to send an address of an operation instruction to be executed received by the host interfaces to the address decoder for address analysis, to determine a memory control module hit, a memory cell hit, and a row hit in the memory cell hit by each of the operation instructions to be executed, and then transmit a row address of the row hit analyzed by the address decoder to the memory control module hit.

11. The memory controller of claim 9 or 10, wherein, The memory controller is disposed in a buffer die, the memory stack includes a plurality of stacked memory dies, each memory array in each of the memory cells is a part of the corresponding memory die, and the plurality of memory dies and the buffer die are connected by through-silicon hybrid bonding.

12. The memory controller of claim 11, wherein, The host devices are disposed in a logic die, the logic die, the buffer die, and the memory stack are stacked in sequence, and the logic die and the buffer die are connected by through-silicon hybrid bonding.

13. A three-dimensional stacked memory, comprising: A memory stack and a memory controller as claimed in any one of claims 9-12, the memory controller is disposed in a buffer die, the memory stack includes a plurality of three-dimensionally stacked memory dies, and the plurality of memory dies and the buffer die are connected by through-silicon hybrid bonding.

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