Memory refresh control method, memory refresh control circuit and electronic equipment

Abstract

The invention provides a memory refreshing control method, a memory refreshing control circuit and electronic equipment, and the method comprises the steps: obtaining command information of a plurality of read-write commands of a current memory bank, the current memory bank being any one of a plurality of memory banks; and according to the command information of the plurality of read-write commands and the refreshing time interval of the current memory bank, determining a refreshing time sequence of the current memory bank during execution of the plurality of read-write commands. According to the scheme provided by the invention, a single memory bank is used for independently refreshing to realize a memory refreshing function, so that the whole equipment where the memory is located has a higher clock frequency, and efficient refreshing is helped to be realized; in addition, the command information of the read-write command and the refreshing time interval of the current memory bank are comprehensively considered, extra time loss caused by interruption of the read-write command can be effectively reduced, and therefore the effective bandwidth of memory read-write access is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip memory control, and in particular to a memory refresh control method, a memory refresh control circuit and an electronic device. BACKGROUND

[0002] Double Data Rate SDRAM (DDR) is widely used in System on Chips (SoC), and the effective access bandwidth of DDR is one of the important factors that restrict the performance of System on Chips.

[0003] In order to maintain the stability of internal data, the DDR controller needs to send a refresh command to the memory bank for a refresh operation at a certain interval. The refresh mechanism of DDR will greatly affect the effective access bandwidth of DDR. Specifically, there are two modes of the most commonly used DDR memory refresh method. The first mode is to refresh all banks at a time, and the second mode is to refresh one bank at a time and refresh all banks in multiple times.

[0004] In the latter case, if there are many banks in the DDR memory, the refresh command will increase exponentially. However, since the refresh cannot be performed at the same time as the read / write access, in the case of a large number of refresh commands and banks, the read / write operation and the refresh operation may occur at the same time, which makes the read / write operation need to wait until the refresh is completed. However, this method will reduce the effective bandwidth of read / write. SUMMARY

[0005] The present application provides a memory refresh control method, a memory refresh control circuit and an electronic device, which solve the technical problem of reducing the effective bandwidth of read / write access when refreshing the memory bank in the prior art.

[0006] The present application provides a memory refresh control method, wherein the memory includes a plurality of memory banks, and the method comprises: obtaining command information of a plurality of read / write commands of a current memory bank, the current memory bank being any one of the plurality of memory banks; determining a refresh timing of the current memory bank during execution of the plurality of read / write commands according to the command information of the plurality of read / write commands and a refresh time interval of the current memory bank.

[0007] In some embodiments, the determining of the refresh timing of the current memory bank during execution of the plurality of read / write commands according to the command information of the plurality of read / write commands and the refresh time interval of the current memory bank comprises: According to the command information of the read-write commands and the refresh time interval of the current memory bank, a priority of memory refresh of the current memory bank is evaluated to obtain evaluation information; According to the evaluation information, a refresh timing of the current memory bank during execution of the read-write commands is determined.

[0008] In some embodiments, the evaluating the priority of memory refresh of the current memory bank according to the command information of the read-write commands and the refresh time interval of the current memory bank to obtain evaluation information comprises: According to the command information of the read-write commands, a preliminary evaluation of the priority of memory refresh of the current memory bank is performed to obtain preliminary evaluation information; According to the refresh time interval of the current memory bank, the preliminary evaluation information is adjusted to obtain the evaluation information.

[0009] In some embodiments, the preliminary evaluation of the priority of memory refresh of the current memory bank according to the command information of the read-write commands to obtain preliminary evaluation information comprises at least one of: When the command information indicates that the read-write commands include a read-write command with row address switching and / or a read-write command with read-write switching, the preliminary evaluation information indicates that the memory refresh of the current memory bank has high priority; When the command information indicates that the read-write commands include a read-write command with unchanged row address, the preliminary evaluation information indicates that the memory refresh of the current memory bank has low priority; When the command information indicates that the current memory bank does not have the read-write commands, the preliminary evaluation information indicates that the memory refresh of the current memory bank has no timing restriction.

[0010] In some embodiments, the adjusting the preliminary evaluation information according to the refresh time interval of the current memory bank to obtain the evaluation information comprises: When the refresh time interval of the current memory bank is close to a time interval threshold, the evaluation information is adjusted to the highest priority from the preliminary evaluation information.

[0011] In some embodiments, the determining the refresh timing of the current memory bank during execution of the read-write commands according to the evaluation information comprises: In response to the evaluation information, a refresh command is inserted into a read-write command stream of the current memory bank to form the refresh timing of the current memory bank, and the read-write command stream is composed of the read-write commands according to timing.

[0012] In some embodiments, the determining the refresh timing of the current memory bank during execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank further comprises: command arbitration on the refresh timing of the current memory bank during execution of the read-write commands.

[0013] The present application provides a memory refresh control circuit, comprising a read-write command buffer and a command evaluation module; wherein, The read-write command buffer is configured to buffer a plurality of read-write commands in a current memory bank and command information of the read-write commands, and the current memory bank is any one of a plurality of memory banks. The command evaluation module is configured to time a refresh time interval of the current memory bank and trigger the refresh inserter to insert the refresh timing of the current memory bank during execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank.

[0014] In some embodiments, the command evaluation module comprises a refresh timer and a read-write command evaluator. The read-write command evaluator is configured to preliminarily evaluate the priority of the memory refresh of the current memory bank according to the command information of the read-write commands to obtain preliminary evaluation information. The refresh timer is further configured to adjust the preliminary evaluation information according to the refresh time interval of the current memory bank to obtain the evaluation information, so as to trigger the refresh inserter to insert the refresh timing of the current memory bank during execution of the read-write commands according to the evaluation information.

[0015] The present application provides an electronic device which executes the memory refresh control method as described above, or the electronic device comprises the memory refresh control circuit as described above.

[0016] The memory refresh control method, the memory refresh control circuit and the electronic device provided by the present application obtain the command information of a plurality of read-write commands of a current memory bank, the current memory bank being any one of a plurality of memory banks, and then determine the refresh timing of the current memory bank during execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank.

[0017] The current memory bank refresh timing of each single memory bank is determined according to the read / write command information of the memory bank and the refresh time interval of the current memory bank, that is, each single memory bank has a set of current memory bank refresh timing determination scheme. The independent refresh mode of each single memory bank, that is, the read / write commands of each bank are processed separately, is beneficial to realize efficient refresh. In addition, the current memory bank refresh timing of each bank is independently evaluated and determined, which makes the hardware logic circuit of memory refresh control simple and further beneficial to realize high-speed clock frequency and form high-speed logic circuit. Furthermore, the command information of the read / write command and the refresh time interval of the current memory bank are comprehensively considered, so that the current memory bank refresh timing inserted during the execution of the read / write command does not interrupt the execution of the read / write command, which can effectively reduce the additional time loss caused by the interruption of the read / write command, thereby improving the effective bandwidth of memory read / write access. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] In order to more clearly illustrate the technical solutions in the present application or prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other accompanying drawings according to these accompanying drawings without creative labor.

[0020] Figure 1 is a flowchart of the memory refresh control method provided by the present application.

[0021] Figure 2 is a structural schematic diagram of the memory refresh control circuit provided by the present application.

[0022] Figure 3 is a structural schematic diagram of the memory controller provided by the present application.

[0023] Figure 4 is a structural schematic diagram of the electronic device provided by the present application. DETAILED DESCRIPTION

[0024] In the following well-known manner, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings so as to make the persons skilled in the art have a better understanding of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the persons skilled in the art without any creative work should fall within the protection scope of the present application.

[0025] It should be noted that the terms "first", "second" and the like in the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units or modules does not have to be limited to those steps or units or modules clearly listed, but can include other steps or units or modules that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] Figure 1 is a flowchart of the memory refresh control method provided by the present application, as shown in Figure 1 the method comprises steps 110 and 120.

[0027] Step 110, obtaining command information of a plurality of read-write commands of a current memory bank, the current memory bank being any one of a plurality of memory banks; Step 120, determining a refresh timing of the current memory bank during execution of the plurality of read-write commands according to the command information of the plurality of read-write commands and a refresh interval of the current memory bank.

[0028] In the embodiment, the current memory bank refresh timing of a single memory bank is determined according to the read / write command information cached in the memory bank and the refresh time interval of the current memory bank, that is, it can be understood that each memory bank has a set of current memory bank refresh timing determination scheme. The independent refresh mode of each memory bank, that is, the read / write commands of each bank are processed separately, is beneficial to efficient refresh. In addition, the current memory bank refresh timing of each bank is independently evaluated and determined, which makes the hardware logic circuit of memory refresh control simple and further beneficial to high-speed clock frequency, forming a high-speed logic circuit. Furthermore, considering the command information of read / write commands and the refresh time interval of the current memory bank, the current memory bank refresh timing inserted during the execution of a plurality of read / write commands will not interrupt the execution of read / write commands, which can effectively reduce the additional time loss caused by the interruption of read / write commands, thereby improving the effective bandwidth of memory read / write access.

[0029] Specifically, the memory needs to be periodically refreshed to recharge to maintain the correctness of the data, for example, the memory can be a dynamic random access memory. The memory bank refers to a storage bank in the memory. One memory can be divided into multiple memory banks for data storage. The application scenario of the memory refresh control method provided by the embodiment of the application is to refresh each memory bank in the memory.

[0030] The embodiment of the application processes each memory bank in the memory separately, for example, a corresponding memory refresh control circuit can be independently set for each memory bank, so that the memory bank and the memory refresh control circuit correspond one by one. In some examples, a single memory bank can also correspond to multiple independent memory refresh control circuits.

[0031] The memory refresh control circuit corresponding to each memory bank can set the timing of inserting a refresh command into the read / write command sequence according to the circuit logic, in combination with the command information in the corresponding memory bank and the refresh time interval of the memory, that is, determine the current memory bank refresh timing of the memory bank during the execution of a plurality of read / write commands. Based on the mode of refreshing one bank at a time, the read / write commands of each bank are processed in channels, and the time of read / write and refresh is reasonably evaluated by the corresponding memory refresh control circuit, the reasonable insertion of the refresh command is realized, the problem that the same bank read / write access operation needs to wait for the completion of the refresh is effectively avoided, and the effective access bandwidth of DDR is improved.

[0032] The following will be described in combination with Figure 2 and Figure 3 The method provided by the embodiment of the application will be described taking the current memory bank (the current memory bank is any one of the plurality of memory banks) as an example.

[0033] The read / write command buffer in the memory refresh control circuit can buffer several read / write commands in the current memory database, generating a read / write command sequence for the current memory database. The read / write command sequence is arranged according to the execution time order. These read / write commands are used to read data from or write data to the current memory database.

[0034] In addition, the read / write command buffer also records command information for read / write commands, such as the column and row addresses. In some examples, this command information includes the command type (read or write), execution order (whether consecutive), row address (whether there is a row address switch), and time information.

[0035] The read / write command evaluator / command evaluation module in the memory refresh control circuit can obtain command information of several read / write commands in the current memory bank from the read / write command buffer, thereby estimating whether the corresponding bank is free and whether there are gaps between the read / write command sequences.

[0036] The refresh interval, also known as the refresh cycle, refers to the time interval at which data stored in memory needs to be refreshed periodically to avoid data loss. In this embodiment, each memory bank has an independent refresh interval. Each memory bank can be configured with a corresponding refresh timer, which can time the current refresh interval of the memory bank, and can also receive guidance from the read / write command evaluator or reference to gaps (time). Combined with the refresh interval of the memory bank, the urgency of refreshing the current memory bank is assessed to form the final determined gap information. Refresh commands can be sent to the refresh inserter based on the gap information, thus achieving staggered refreshes for each bank and avoiding read / write and refresh operations for each bank, solving the problem of reduced effective access bandwidth. It should be noted that for read / write commands, the command information can include time information. Time information refers to information related to the execution time of each read / write command in memory, such as the sending time, completion time, interval duration, and delay duration of the read / write command.

[0037] The read / write command evaluator and / or command evaluation module, considering information such as the command type (read or write), execution order (whether consecutive), and row address (whether row address switching exists) of each read / write command, can determine the gap time between read / write commands based on the time information of each read / write command. It can also combine this with the refresh time interval to determine the insertion timing of refresh commands, i.e., the current memory database refresh timing.

[0038] The aforementioned current memory bank refresh timing refers to the sending / execution sequence of memory refresh commands. Specifically, it refers to the timing formed by inserting the current memory bank refresh command into the gaps between the execution of several read and write commands. A single memory refresh control circuit, or its read / write command evaluator and / or refresh timer, can determine the current memory bank refresh timing during the execution of several read and write commands based on the command information of several read and write commands and the current memory bank refresh time interval. In other words, when sending a refresh command to the current memory bank, the refresh command can be inserted into the gaps between several read and write commands that need to be executed.

[0039] Because the gap time and refresh interval are taken into account, refresh commands can be accurately inserted into the gaps between read and write commands, allowing refresh commands to be executed during the intervals between read and write commands. This effectively avoids refresh commands interrupting the sequence of consecutive read and write commands. When intensive read and write commands need to be executed, fewer refresh commands can be inserted at appropriate times, thereby reducing the impact of memory refresh on data read and write and improving the effective bandwidth of DDR read and write access.

[0040] On the other hand, the read and write commands for each Bank are processed separately by channel and circuit, which simplifies the implementation of the entire logic circuit and facilitates the design of efficient refresh and high-clock logic circuits.

[0041] It should be noted that each implementation method of this application can be freely combined, rearranged, or executed individually, and does not need to rely on or depend on a fixed execution order.

[0042] In some embodiments, determining the current memory database refresh sequence during the execution of several read / write commands based on command information of several read / write commands and the current memory database refresh time interval in step 120 includes: Based on the command information of several read and write commands and the current memory library refresh interval, the priority of the current memory library refresh is evaluated to obtain evaluation information; based on the evaluation information, the current memory library refresh timing during the execution of several read and write commands is determined.

[0043] Specifically, memory refresh priority refers to the priority of performing a memory refresh relative to performing read / write commands.

[0044] In some examples, different command sequence types or different command types can be determined based on command information. Then, based on different types, the cost and impact of inserting refresh commands under the current type can be determined, thereby assessing the priority of memory refresh relative to executing read and write commands.

[0045] The priority of memory refresh in the current memory bank can be evaluated based on the command information of several read and write commands and the current memory bank refresh interval, thus obtaining evaluation information. Based on the evaluation information, the refresh sequence of the current memory bank during the execution of several read and write commands can be determined; for example, the evaluation information can be used to indicate whether the current memory bank refresh has a high priority or a low priority.

[0046] In the memory refresh control method provided in this embodiment, the priority of memory refresh of the current memory library is evaluated based on the command information of several read and write commands and the refresh time interval of the current memory library, and the refresh sequence of the current memory library is determined. This method can take into account the mutual influence between memory refresh and execution of read and write commands, help determine a suitable refresh sequence of the current memory library, and thus improve the memory refresh efficiency.

[0047] In some embodiments, the evaluation can be performed in two layers. The first evaluation assesses the mutual impact between basic memory refresh and the execution of read / write commands. The second evaluation takes into account that refresh commands cannot be postponed indefinitely. When the maximum postponement time is about to be reached, it is necessary to execute refresh commands urgently to ensure that DDR functions normally.

[0048] That is, based on the command information of several read and write commands and the current memory database refresh interval, the priority of the current memory database refresh is evaluated to obtain evaluation information, which may include: Based on the command information of several read and write commands, a preliminary assessment of the priority of the current memory library refresh is performed to obtain preliminary assessment information; based on the current memory library refresh interval, the preliminary assessment information is adjusted to obtain the final assessment information.

[0049] Specifically, based on the command information of several read and write commands, information such as whether column address switching or row address switching occurs between several read and write commands can be obtained. Based on this information, the priority of the current memory library refresh can be initially evaluated, and preliminary evaluation information can be obtained.

[0050] In addition, the refresh interval of the current memory library needs to be considered. For example, for DDR4 memory, it is typically required that all memory rows be refreshed every 64 milliseconds. The DDR memory protocol specification requires that refresh commands be sent at certain intervals. The sending time can be delayed or advanced, but the total number cannot be changed. This delay cannot be indefinite; once the maximum delay time has elapsed, the refresh command must be sent to ensure normal DDR functionality.

[0051] Therefore, the preliminary evaluation information needs to be adjusted according to the current memory library refresh interval to obtain the final evaluation information.

[0052] The memory refresh control method provided in this application embodiment sets up a two-level evaluation method. Combining command information and refresh time interval, it realizes multi-dimensional adaptive adjustment of the current memory library. In particular, it readjusts the preliminary evaluation information according to the refresh time interval of the current memory library, ensuring the normal operation of the memory and improving the refresh efficiency of the memory.

[0053] In some embodiments, the process of performing a preliminary evaluation of the priority of the current memory bank refresh based on command information of several read and write commands to obtain preliminary evaluation information includes at least one of the following: When the command information indicates that among several read / write commands are read / write commands that involve row address switching and / or read / write commands that involve read / write switching, the preliminary assessment information indicates that the memory refresh of the current memory bank has a high priority. When the command information indicates that among several read and write commands there is a read and write command with the same row address, the preliminary assessment information indicates that the memory refresh of the current memory bank has a low priority. When the command information indicates that there are no read / write commands in the current memory library, the preliminary assessment information indicates that there are no timing restrictions on memory refresh in the current memory library.

[0054] Specifically, the row address refers to the row address of the memory address accessed by the read / write command, while the column address refers to the column address of the memory address accessed by the read / write command. The row address is an identifier used to select a specific row in the memory array. The row address determines which memory cell in that row will be activated and accessed. The column address is an identifier used to select a specific column position within a specific row. The column address determines which specific data bit or storage cell in the activated row will be read or written.

[0055] Whether a row address or column address is hit or switched determines whether memory is precharged or reactivated, thus affecting memory refresh.

[0056] Preliminary assessment information can be determined based on the following three scenarios.

[0057] Scenario 1: If the command information of several read and write commands indicates that the read and write commands include row address switching read and write commands and / or read and write switching read and write commands, then the priority of memory refresh of the current memory bank is initially evaluated. The initial evaluation information indicates that memory refresh of the current memory bank has a high priority, indicating that there is a gap time between the several read and write commands, and memory refresh can be performed.

[0058] This is because refresh operations are usually performed row by row. The time gap between read and write commands for row address switching is relatively long, as is the time gap between read and write commands for read and write switching. A suitable time gap can be selected to insert refresh operations, thereby avoiding data loss and minimizing performance impact.

[0059] Scenario 2: If the command information indicates that several read / write commands include read / write commands with unchanged row addresses, then a preliminary assessment of the priority of memory refresh in the current memory bank is performed. The preliminary assessment information indicates that the memory refresh of the current memory bank has a low priority, meaning that there is no gap time between several read / write commands and memory refresh cannot be performed.

[0060] This is because refresh operations are usually performed row by row. The time interval between read and write commands that involve column address switching (while the row address remains unchanged) is very short. Inserting a refresh command will interrupt the current access, resulting in performance loss.

[0061] Scenario 3: If the command information indicates that there are no read / write commands for the current memory library, a preliminary assessment of the priority of the current memory library's memory refresh will be performed. The preliminary assessment information indicates that there are no timing restrictions on the current memory library's memory refresh.

[0062] This is because the memory library is currently idle, so refreshing will not interfere with current memory operations or affect memory performance, and memory can be refreshed at any time.

[0063] The memory refresh control method provided in this application embodiment performs a preliminary evaluation of the priority of current memory library refresh based on the command information of several read and write commands, fully considers the mutual influence between read and write commands and memory refresh, and improves memory refresh efficiency.

[0064] In some embodiments, the preliminary evaluation information is adjusted according to the current memory bank refresh interval to obtain evaluation information, including: When the current memory library refresh interval is close to the interval threshold, the evaluation information is adjusted from preliminary evaluation information to the highest priority.

[0065] Specifically, memory refresh needs to be performed at certain intervals. The refresh interval can be represented by a time interval counter. Based on the current refresh interval of the memory library, a refresh command can be generated. The command can be sent with a delay or with an advance.

[0066] The time interval threshold is the allowed delay time for refresh commands. If the current memory database refresh interval is close to the time interval threshold, the refresh command must be sent. In this case, the evaluation information can be adjusted from preliminary evaluation information to the highest priority to ensure that the basic refresh interval function is met. Then, based on the gap time, several read and write commands are inserted into the refresh command and sent.

[0067] It should be noted that the above-mentioned approaching time interval threshold means that the current memory library refresh time is about to reach the time interval threshold. The judgment criteria can be, for example, that the difference between the time interval threshold and the refresh time interval is less than a preset value, or that the refresh time interval is a certain critical value before reaching the time interval threshold.

[0068] Correspondingly, if the current refresh interval of the memory library is not close to the interval threshold, the priority does not need to be adjusted and can be directly used as the final evaluation information for inserting refresh commands.

[0069] The memory refresh control method provided in this application adjusts the evaluation information from preliminary evaluation information to the highest priority when the current memory library refresh time interval is close to the time interval threshold, thereby increasing the priority of the refresh command and helping to ensure data security.

[0070] In some embodiments, determining the current memory bank refresh timing during the execution of several read / write commands includes: In response to the evaluation information, refresh commands are inserted into the current memory bank read / write command stream to form the current memory bank refresh sequence. The read / write command stream consists of several read / write commands based on the sequence.

[0071] Specifically, in response to different evaluation information, the priority of refresh commands relative to read and write commands can be determined, thereby inserting refresh commands into the gaps during the execution of the current memory bank's read and write command stream to form the current memory bank refresh timing. Here, the read and write command stream consists of several read and write commands arranged in a timing sequence.

[0072] In some embodiments, after determining the current memory bank refresh sequence during the execution of several read / write commands based on command information of several read / write commands and the current memory bank refresh time interval, the method further includes: Command arbitration is performed on the current memory bank refresh timing during the execution of several read and write commands.

[0073] Specifically, refresh commands are scheduled based on memory access patterns (such as read / write conflicts, system load, etc.). These commands need to be inserted at appropriate times to ensure that memory data is refreshed at the correct time, preventing data loss. Therefore, command arbitration is required to manage the current memory library refresh sequence during the execution of several read / write commands.

[0074] Specifically, the collaboration between the memory library command arbitrator and the refresh inserter is crucial for optimizing memory access and ensuring data integrity. The arbitrator schedules refresh commands based on memory access conditions (such as read / write conflicts, system load, etc.), while the refresh inserter inserts refresh commands at appropriate times to ensure that memory data is refreshed at the correct time, preventing data loss. Their cooperation ensures that the memory system meets refresh cycle requirements while minimizing the impact on memory access performance.

[0075] In some embodiments, the method further includes: Determine the refresh interval of the current memory library based on the refresh time counter of the current memory library; The refresh time counters for each memory library have different start times.

[0076] Specifically, the refresh interval between the current memory library and other memory libraries can be adjusted to stagger the refresh operations of each memory library, thereby improving the effective bandwidth of the entire memory read and write access.

[0077] The refresh time interval of the current memory library can be determined by using a refresh time counter. The start time of the refresh time counter for each memory library can be differentiated, resulting in different refresh time intervals for each library within the same refresh cycle.

[0078] The apparatus provided in the embodiments of this application is described below. The apparatus described below can be referred to in correspondence with the method described above.

[0079] Figure 2 This is a schematic diagram of the memory refresh control circuit provided in this application, as shown below. Figure 2 As shown, the memory refresh control circuit 200 includes a read / write command buffer 210, a command evaluation module 201, and a refresh inserter 230.

[0080] The read / write command buffer 210 is used to buffer several read / write commands in the current memory bank, as well as the command information of the read / write commands. The current memory bank can be any one of multiple memory banks. The command evaluation module 201 is used to time the refresh interval of the current memory library and to trigger the refresh inserter 230 to determine the refresh timing of the current memory library during the execution of the read and write commands based on the command information of several read and write commands and the refresh interval of the current memory library.

[0081] The memory refresh control circuit provided in this application embodiment implements the memory refresh function by refreshing a single memory bank independently. This facilitates a higher clock frequency in memory and improves memory refresh efficiency. By comprehensively considering the command information of read and write commands and the current refresh time interval of the memory bank, memory refresh is performed during the execution of several read and write commands without interrupting the execution of read and write commands. This effectively reduces the additional time loss caused by the interruption of read and write commands, thereby improving the effective bandwidth of memory read and write access.

[0082] In some embodiments, the command evaluation module 201 includes a refresh timer 220 and a read / write command evaluator 240; The read / write command evaluator 240 is used to perform a preliminary evaluation of the priority of the current memory bank memory refresh based on the command information of several read / write commands, and obtain preliminary evaluation information. The refresh timer 220 is also used to adjust the preliminary evaluation information according to the current memory bank refresh interval to obtain evaluation information, so as to trigger the refresh inserter 230 to determine the current memory bank refresh timing during the execution of several read and write commands based on the evaluation information.

[0083] Figure 3 This is a schematic diagram of the memory controller provided in this application, as shown below. Figure 3 As shown, the memory controller 300 includes a memory refresh control circuit 200 and a memory bank command arbitrator 320, which can manage the memory bank 310.

[0084] The memory refresh control circuit 200 corresponds one-to-one with the memory bank 310.

[0085] The memory refresh control circuit 200 in the memory controller 300 provided in this application embodiment corresponds one-to-one with the memory bank. It adopts a single memory bank refresh method to realize the memory refresh function. The read and write commands of each memory bank are processed separately. In the memory chip implementation, it is beneficial to achieve a higher clock frequency. At the same time, it also simplifies the logic circuit of the memory refresh control circuit.

[0086] In some embodiments, the memory library command arbitrator is connected to the refresh inserter in each memory refresh control circuit and is used to arbitrate the read / write commands and refresh commands sent by the refresh inserter.

[0087] Specifically, the collaboration between the memory library command arbitrator and the refresh inserter is crucial for optimizing memory access and ensuring data integrity. The arbitrator schedules refresh commands based on memory access conditions (such as read / write conflicts, system load, etc.), while the refresh inserter inserts refresh commands at appropriate times to form the current memory library refresh sequence. This ensures that memory data is refreshed at the correct time, preventing data loss. Their cooperation ensures that the memory system meets refresh cycle requirements while minimizing the impact on memory access performance.

[0088] In some embodiments, the memory is a double-rate synchronous dynamic random access memory.

[0089] Specifically, Double Data Rate (DFR) Synchronous Dynamic Random Access Memory (SDRAM) is a type of memory widely used in computers, servers, and other electronic devices. It is an improved version of Synchronous Dynamic Random Access Memory (SDRAM) that increases the data transfer rate by performing two data transfers per clock cycle.

[0090] Figure 4 This is a schematic diagram of the structure of the electronic device provided in this application, such as... Figure 4 As shown, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communications bus 440, wherein the processor 410, the communications interface 420, and the memory 430 communicate with each other via the communications bus 440. The processor 410 can call logical commands stored in the memory 430 to execute the methods described in the above embodiments, for example: Obtain command information for several read / write commands in the current memory library, where the current memory library is any one of multiple memory libraries; determine the refresh sequence of the current memory library during the execution of the several read / write commands based on the command information of the several read / write commands and the refresh time interval of the current memory library.

[0091] Furthermore, the logical commands in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several commands to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0092] The processor in the electronic device provided in this application embodiment can call logical instructions in the memory to implement the above method. Its specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effect, which will not be repeated here.

[0093] It should be noted that the above-mentioned electronic device can be implemented by hardware methods to enable the above-mentioned electronic device to execute the memory refresh control method, or the above-mentioned electronic device may include the memory refresh control circuit involved.

[0094] The specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effects, so it will not be repeated here.

[0095] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A memory refresh control method, characterized by, The memory includes a plurality of memory banks, and the method comprises: obtaining command information of a plurality of read-write commands of a current memory bank, the current memory bank being any one of the plurality of memory banks; determining a refresh timing of the current memory bank during execution of the plurality of read-write commands according to the command information of the plurality of read-write commands and a refresh time interval of the current memory bank.

2. The memory refresh control method of claim 1, wherein, The determination of the refresh timing of the current memory bank during execution of the plurality of read-write commands according to the command information of the plurality of read-write commands and the refresh time interval of the current memory bank comprises: evaluating a priority of memory refresh of the current memory bank according to the command information of the plurality of read-write commands and the refresh time interval of the current memory bank to obtain evaluation information; determining the refresh timing of the current memory bank during execution of the plurality of read-write commands according to the evaluation information.

3. The memory refresh control method of claim 2, wherein, The evaluation of the priority of memory refresh of the current memory bank according to the command information of the plurality of read-write commands and the refresh time interval of the current memory bank to obtain evaluation information comprises: preliminarily evaluating the priority of memory refresh of the current memory bank according to the command information of the plurality of read-write commands to obtain preliminary evaluation information; adjusting the preliminary evaluation information according to the refresh time interval of the current memory bank to obtain the evaluation information.

4. The memory refresh control method of claim 3, wherein, The preliminary evaluation of the priority of memory refresh of the current memory bank according to the command information of the plurality of read-write commands to obtain preliminary evaluation information comprises at least one of the following: when the command information indicates that the plurality of read-write commands include a read-write command with row address switching and / or a read-write command with read-write switching, the preliminary evaluation information indicates that the memory refresh of the current memory bank has high priority; when the command information indicates that the plurality of read-write commands include a read-write command with unchanged row address, the preliminary evaluation information indicates that the memory refresh of the current memory bank has low priority; when the command information indicates that the current memory bank does not have the read-write command, the preliminary evaluation information indicates that the memory refresh of the current memory bank has no timing restriction.

5. The memory refresh control method of claim 3, wherein, The adjustment of the preliminary evaluation information according to the refresh time interval of the current memory bank to obtain the evaluation information comprises: when the refresh time interval of the current memory bank is close to a time interval threshold, the evaluation information is adjusted from the preliminary evaluation information to the highest priority.

6. The memory refresh control method of claim 2, wherein, The determination of the refresh timing of the current memory bank during execution of the plurality of read-write commands according to the evaluation information comprises: in response to the evaluation information, inserting a refresh command into a read-write command stream of the current memory bank to form the refresh timing of the current memory bank, the read-write command stream being composed of the plurality of read-write commands according to a timing.

7. The refresh control method of any of claims 1 to 6, wherein, After the determination of the refresh timing of the current memory bank during execution of the plurality of read-write commands according to the command information of the plurality of read-write commands and the refresh time interval of the current memory bank, the method further comprises: command arbitration on the refresh timing of the current memory bank during execution of the plurality of read-write commands.

8. A memory refresh control circuit, comprising: The read-write command buffer and the command evaluation module are included; wherein The read-write command buffer is used for buffering a plurality of read-write commands and command information of the read-write commands in a current memory bank, and the current memory bank is any one of a plurality of memory banks; The command evaluation module is used for timing a refresh time interval of the current memory bank, and triggering the refresh inserter to insert the refresh timing of the current memory bank during execution of the plurality of read-write commands according to the command information of the plurality of read-write commands and the refresh time interval of the current memory bank.

9. The refresh control circuit of claim 8, wherein, The command evaluation module includes a refresh timer and a read-write command evaluator; The read-write command evaluator is used for preliminarily evaluating a priority of memory refresh in the current memory bank according to the command information of the plurality of read-write commands, and obtaining preliminary evaluation information; The refresh timer is further used for adjusting the preliminary evaluation information according to the refresh time interval of the current memory bank, and obtaining the evaluation information, so as to trigger the refresh inserter to insert the refresh timing of the current memory bank according to the evaluation information during execution of the plurality of read-write commands.

10. An electronic device, comprising: The electronic device executes the memory refresh control method according to any one of claims 1 to 7, or the electronic device includes the memory refresh control circuit according to claim 8 or 9.

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