Non-volatile RAM including spin-transfer torque magnetic tunnel junction structure

Abstract

A non-volatile static random access memory (NVSRAM) includes at least one array of NVSRAM cells. And each NVSRAM unit comprises an SRAM unit and an MRAM unit. The SRAM cell includes at least six transistors, and the MRAM cell includes at least two transistors and two magnetic tunnel junction (MTJ) structures. The SRAM cell is accessed during a normal read-write operation, which enables the NVSRAM cell to achieve fast access, has infinite durability, and does not have a read-write error rate problem. In the NVSRAM unit which is not accessed by the normal read-write operation, the hidden MRAM write operation can be manually or automatically activated to back up the data stored in the corresponding SRAM unit. When the NVSRAM device is powered off, data stored in the SRAM unit may be lost, while data backed up in the corresponding MRAM unit may be retained. When power is resumed, an automatic data recovery write cycle will be initiated during which the SRAM cell recovers its data from its corresponding MRAM cell.

Description

[0001] Cross-referencing related documents This application claims priority to U.S. Provisional Application US 63 / 666,166, filed June 29, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to computer storage technology, and more specifically to a non-volatile RAM comprising a spin-transfer torque magnetic tunnel junction (STT-MTJ) structure. Background Technology

[0003] Static random-access memory (SRAM) loses its stored contents when power is off, and is therefore classified as volatile memory. Memory that retains data without the need for power is classified as non-volatile memory. Examples of non-volatile memory include non-volatile static random-access memory (NVSRAM), ferroelectric random-access memory (F-RAM™), electrically erasable programmable read-only memory (EEPROM), flash memory, and magnetoresistive random-access memory (MRAM). Non-volatile memory is used in applications where critical data needs to be retained after power is removed or during power interruptions.

[0004] NVSRAM is a type of non-volatile memory that combines the characteristics of SRAM with non-volatile properties. Compared to other alternatives that retain device data during power interruptions, it offers the advantages of high speed and relatively low cost in implementing non-volatile memory. Summary of the Invention

[0005] A non-volatile static random access memory (NVSRAM) device includes an array of NVSRAM cells. Each NVSRAM cell includes one SRAM cell and one spin-transfer torque magneto-resistive random-access memory (STT-MRAM or MRAM) cell. The SRAM cell includes at least six transistors (referred to as 6-T SRAM), while the STT-MRAM cell includes at least two transistors and two magnetic tunnel junction (MTJ) structures (referred to as 2T2M STT-MRAM). Therefore, an NVSRAM cell is sometimes referred to as 8T2M-NVSRAM. This type of NVSRAM device can be accessed for read / write operations. During normal read / write operations, reads and writes to the 8T2M-NVSRAM cells in the NVSRAM device are performed within the 6-T SRAM cells. This enables the NVSRAM cells to achieve fast access, have unlimited endurance, and eliminate read / write error rate issues. During standby or when other parts of the NVSRAM device are active, hidden MRAM write operations can be manually or automatically activated in NVSRAM cells that are not accessed by normal read / write operations. In this operation, differentiated bits are written from the corresponding SRAM cell to the MRAM cell using internally generated signals (i.e., signals generated on the device). When the device is powered off, the SRAM cell loses its data, while the data in the corresponding STT-MRAM cell is retained. When power is restored, an automatic recovery write cycle begins, during which the SRAM cell recovers its data from its corresponding MRAM cell.

[0006] According to some embodiments, the memory includes one or more memory arrays, each memory array including memory cells arranged in n rows and m columns. The memory array also includes n variable power supply voltage lines, each coupled to a memory cell in a corresponding row of the n rows. The memory array also includes n SRAM word lines, each coupled to a memory cell in a corresponding row of the n rows. The memory array also includes n MRAM word lines, each coupled to a memory cell in a corresponding row of the n rows. The memory array also includes m bit line pairs, each bit line pair coupled to a memory cell in a corresponding column of the m columns.

[0007] In some embodiments, each memory cell includes an SRAM cell and an MRAM cell. The SRAM cell includes a first memory node and a second memory node programmable via corresponding SRAM word lines and corresponding bit line pairs to be at two complementary voltage levels, respectively. The MRAM cell includes a first magnetic tunnel junction (MTJ) circuit and a second MTJ circuit. The first MTJ circuit includes a first transistor and a first MTJ structure. The first MTJ structure has a first pinned layer and a first free layer on opposite sides of the first tunnel barrier layer. The second MTJ circuit includes a second transistor and a second MTJ structure. The second MTJ structure has a second pinned layer and a second free layer on opposite sides of the second tunnel barrier layer.

[0008] In some embodiments, the first transistor has a first gate coupled to a corresponding MRAM word line and is configured to, in response to a voltage on the corresponding MRAM word line exceeding an MTJ programming threshold, connect the first free layer to the first bit line of the corresponding bit line pair, or connect the first pinned layer to the first memory node. The second transistor has a second gate coupled to a corresponding MRAM word line and is configured to, in response to a voltage on the corresponding MRAM word line exceeding the MTJ programming threshold, connect the second free layer to the second bit line of the corresponding bit line pair, or connect the second pinned layer to the second memory node.

[0009] In some embodiments, the first MTJ structure is configured to flip from an anti-parallel (AP) state to a parallel (P) state in response to a first current from the first bit line to the first memory node exceeding a first threshold. The second MTJ structure is configured to flip from a parallel (P) state to an anti-parallel (AP) state in response to a second current from the second memory node to the second bit line exceeding a second threshold.

[0010] In some embodiments, the first MTJ structure is configured to flip from a parallel (P) state to an anti-parallel (AP) state in response to a third current from the first memory node to the first bit line exceeding the second threshold, and the second MTJ structure is configured to flip from an anti-parallel (APs) state to a parallel (P) state in response to a fourth current from the second bit line to the second memory node exceeding the first threshold. In some embodiments, the first threshold is different from the second threshold.

[0011] In some embodiments, the memory further includes a variable power supply voltage control circuit configured to control the variable power supply voltage line. The variable power supply voltage control circuit is configured to output a first voltage to the corresponding variable power supply voltage line when the first memory node and the second memory node are programmed to be at two complementary voltage levels via corresponding word lines and corresponding bit line pairs, respectively. In some embodiments, the variable power supply voltage control circuit is configured to output a second voltage to the corresponding variable power supply voltage line such that the first current exceeds the first threshold and the second current exceeds the second threshold, wherein the second voltage is higher than the first voltage.

[0012] In some embodiments, the first transistor has a first source terminal and a first drain terminal, one of which is coupled to the first free layer and the other is coupled to the first bit line. In some embodiments, the second transistor has a second source terminal and a second drain terminal, one of which is coupled to the second free layer and the other is coupled to the second bit line.

[0013] In some embodiments, the first transistor has a first source terminal and a first drain terminal, one of which is coupled to the first pinning layer and the other is coupled to the first memory node.

[0014] In some embodiments, the second transistor has a second source terminal and a second drain terminal, one of which is coupled to the second pinning layer and the other is coupled to the second memory node.

[0015] In some embodiments, the memory further includes data recovery control logic, which can be configured to, after the memory experiences a power outage, in response to the restoration of power to the memory, cause the memory to perform a data recovery operation to recover data values ​​stored in the memory cells immediately prior to the power outage. The data recovery operation includes a first data recovery operation to recover data in the i-th row of the plurality of rows and a second data recovery operation to recover data in the j-th row of the plurality of rows.

[0016] In some embodiments, the first data recovery operation includes: during an i-th data recovery period, applying the second voltage to the i-th MRAM word line of the n MRAM word lines, the i-th MRAM word line corresponding to the i-th row; and during the i-th data recovery period, increasing the voltage on the i-th variable power voltage line of the n variable power voltage lines to the first voltage, wherein the i-th variable power voltage line corresponds to the i-th row.

[0017] In some embodiments, the first data recovery operation includes: during a j-th data recovery period following the i-th data recovery period, applying the second voltage to the j-th MRAM word line among the n MRAM word lines, wherein the j-th MRAM word line corresponds to the j-th row; and during the j-th data recovery period, increasing the voltage on the j-th variable power voltage line among the n variable power voltage lines to the first voltage, wherein the j-th variable power voltage line corresponds to the j-th row.

[0018] In some embodiments, the m bit line pairs are kept grounded during the data recovery operation.

[0019] According to some embodiments, a method of operating a memory includes: applying a first voltage to a corresponding variable power supply voltage line during a first time period; applying a second voltage to a corresponding MRAM word line during a second time period, wherein the second time period overlaps with at least a portion of the first time period; connecting a first bit line of a corresponding bit line pair to a third voltage during a third time period, wherein the third time period overlaps with at least a portion of the first time period; and connecting a second bit line of the corresponding bit line pair to a fourth voltage during a fourth time period, wherein the fourth time period overlaps with at least a portion of the third time period, wherein one of the third voltage and the fourth voltage is a power supply voltage and the other is a reference voltage.

[0020] In some embodiments, the method further includes applying a fifth voltage to a corresponding variable power supply voltage line when the first memory node and the second memory node are programmed to be at two complementary voltage levels via corresponding word lines and corresponding bit line pairs, respectively.

[0021] In some embodiments, the method further includes performing a data recovery operation after the memory experiences a power outage, in response to the restoration of power to the memory, to recover data values ​​stored in the memory cells immediately prior to the power outage, the data recovery operation including a first data recovery operation to recover data in the i-th row of the plurality of rows and a second data recovery operation to recover data in the j-th row of the plurality of rows.

[0022] In some embodiments, the first data recovery operation includes: during an i-th data recovery period, applying the second voltage to the i-th MRAM word line of the n MRAM word lines, the i-th MRAM word line corresponding to the i-th row; and during the i-th data recovery period, increasing the voltage on the i-th variable power voltage line of the n variable power voltage lines to the first voltage, wherein the i-th variable power voltage line corresponds to the i-th row.

[0023] In some embodiments, the second data recovery operation includes: during a j-th data recovery period following the i-th data recovery period, applying the second voltage to the j-th MRAM word line among the n MRAM word lines, wherein the j-th MRAM word line corresponds to the j-th row; and during the j-th data recovery period, increasing the voltage on the j-th variable power supply voltage line among the n variable power supply voltage lines to the first voltage, wherein the j-th variable power supply voltage line corresponds to the j-th row.

[0024] In some embodiments, the m bit line pairs are kept grounded during the data recovery operation.

[0025] According to some embodiments, a method of operating an NVSRAM memory includes writing to a plurality of memory cells during one or more write operations, the plurality of memory cells including a first memory cell and a second memory cell, wherein the one or more write operations cause an SRAM cell in each of the first memory cells to store a first data value and an SRAM cell in each of the second memory cells to store a second data value.

[0026] In some embodiments, the method of operating the NVSRAM memory further includes simultaneously backing up the first memory cell during a first time period, comprising: for each of the plurality of memory cells, applying a first voltage to the variable power supply voltage line coupled to each respective memory cell, applying a second voltage to the MRAM word line coupled to each respective memory cell, connecting the first bit line of the bit line pair coupled to each respective memory cell to a third voltage, and connecting the second bit line of the bit line pair coupled to each respective memory cell to a fourth voltage.

[0027] In some embodiments, the method of operating the NVSRAM memory further includes simultaneously backing up a second memory cell during a second time period following the first time period, comprising: for each specific memory cell, applying the first voltage to the variable power supply voltage line coupled to each specific memory cell, applying the second voltage to the MRAM word line coupled to each specific memory cell, connecting the first bit line of the bit line pair coupled to each specific memory cell to the fourth voltage, and connecting the second bit line of the bit line pair coupled to each specific memory cell to the third voltage.

[0028] In some embodiments, backing up the first memory cell causes a first current to flow from the SRAM cell of each corresponding memory cell through a first MTJ structure in the MRAM cell of each corresponding memory cell to the first bit line, and causes a second current to flow from the second bit line through a second MTJ structure in the MRAM cell of each corresponding memory cell to the SRAM cell of each corresponding memory cell. The first current sets the first MTJ structure to a high resistance (anti-parallel or AP) state, and the second current sets the second MTJ structure to a low resistance (parallel or P) state, thereby causing the first data value stored in the SRAM cell of each corresponding first memory cell in the plurality of first memory cells to be written into the MRAM cell of each corresponding first memory cell.

[0029] In some embodiments, backing up the second memory cell causes a third current to flow from the first bit line through the first MTJ structure of the MRAM cell of each particular second memory cell to the SRAM cell of each particular memory cell, and causes a fourth current to flow from the SRAM cell of each particular memory cell through the second MTJ structure in the MRAM cell of each particular memory cell to the second bit line. The third current sets the first MTJ structure to a low resistance (parallel or P) state, and the fourth current sets the second MTJ structure to a high resistance (anti-parallel or AP) state, thereby causing the second data value stored in the SRAM cell of each particular second memory cell to be written into the MRAM cell of each particular second memory cell.

[0030] In some embodiments, the method of operating the NVSRAM memory further includes, after the memory experiences a power outage, performing a data recovery operation in response to the restoration of power to the memory to recover data values ​​stored in the memory cells immediately preceding the power outage. The data recovery operation includes a first data recovery operation to recover data in a first row and a second data recovery operation to recover data in a second row. Multiple memory cells are located in the first row, and during the first time period and / or the second time period, one or more memory cells in the second row are accessed for read / write operations.

[0031] In some embodiments, the first data recovery operation includes: during a first data recovery period, applying the second voltage to a first MRAM word line of the n MRAM word lines, the first MRAM word line corresponding to the first row; and during the first data recovery period, increasing the voltage on a first variable power supply line of the n variable power supply lines to the first voltage, wherein the first variable power supply line corresponds to the first row.

[0032] In some embodiments, the second data recovery operation includes: during a second data recovery period following the first data recovery period, applying the second voltage to a second MRAM word line among the n MRAM word lines, wherein the second MRAM word line corresponds to the second row; and during the second data recovery period, increasing the voltage on a second variable power supply voltage line among the n variable power supply voltage lines to the first voltage, wherein the second variable power supply voltage line corresponds to the second row.

[0033] In some embodiments, the m bit line pairs are kept grounded during the data recovery operation. Attached Figure Description

[0034] Embodiments of this disclosure will now be described by way of example only and not in any limiting sense, with reference to the accompanying drawings, in which: Figure 1A This is a block diagram of an NVSRAM device according to certain embodiments of this application; Figure 1B This is a block diagram of an NVSRAM core circuit system according to certain embodiments of this application; Figure 2 This is a block diagram of a read / write circuit in a read / write circuit system according to certain embodiments of this application; Figure 3A and Figure 3B This is a circuit diagram of an NVSRAM cell in an NVSRAM core circuit system according to certain embodiments of this application; Figure 3C and Figure 3D This is a circuit diagram of a magnetic tunnel junction (MTJ) circuit according to certain embodiments of this application, which can be programmed to switch between a low-resistance state (parallel or P-state) and a high-resistance state (anti-parallel or AP-state). Figure 4 These are waveform diagrams according to certain embodiments of this application, which show simulated waveforms of various signals related to a series of operations involving two NVSRAM cells; Figure 5A This is a schematic diagram according to certain embodiments of the present application, which illustrates the current, voltage, and transistor state in an NVSRAM cell during an operation of writing a "1" to an SRAM cell of an NVSRAM cell; Figure 5B This is a schematic diagram according to certain embodiments of the present application, which illustrates the current, voltage, and transistor state in an NVSRAM cell during an operation of writing "0" to an SRAM cell of an NVSRAM cell; Figure 6AThis is a schematic diagram according to certain embodiments of the present application, which illustrates the current, voltage, and transistor state in an NVSRAM cell during an operation of writing "0" to an MRAM cell of an NVSRAM cell; Figure 6B This is a schematic diagram according to certain embodiments of the present application, which illustrates the current, voltage, and transistor state in an NVSRAM cell during an operation of writing a "1" to an MRAM cell of an NVSRAM cell; Figure 7 This is a schematic diagram according to certain embodiments of the present application, illustrating the operation of restoring data from an MRAM cell to an SRAM cell in an NVSRAM cell. Detailed Implementation

[0035] Figure 1A This is a block diagram of an NVSRAM device 100 according to certain embodiments of this application. As shown, the NVSRAM device 100 includes an NVSRAM core circuit system 110. The core circuit includes one or more NVSRAM arrays and peripheral circuit systems. The peripheral circuit systems include a power-on / voltage regulator, an SRAM data recovery control device, a clock generator, command decoding read / write (R / W) control logic, an address register counter, a data input / output (I / O) register, and an input / output driver.

[0036] Figure 1BThis is a block diagram of an n×m MRAM array 101 and associated control circuitry in an NVSRAM core circuitry system 110 according to certain embodiments of this application. As shown, the control circuitry includes a variable supply voltage control circuitry, a row control circuitry, a column select circuitry, and read / write control circuitry. The NVSRAM array 101 includes n rows and m columns of NVSRAM cells (bits 00, ..., nm). Each row of NVSRAM cells (e.g., the 0th row including bits 00, 01, ..., 0m) is coupled to the VCEL control circuitry via a corresponding voltage cell (VCEL) line (e.g., VCEL0) and to the row control circuitry via a corresponding set of word lines (e.g., WL0 and WLM0). Each column of NVSRAM cells (e.g., column 0 including bits 00, 10, ..., n0) is coupled to a corresponding bit line pair (e.g., BLT0 and BLC0), which is coupled to a corresponding column select driver in the column select circuitry system, which in turn is coupled to the read / write circuitry. Each word line (e.g., WL0) is used to select a corresponding row of memory cells (e.g., row 0), and each bit line pair (e.g., BLT0 and BLC0) is used to control a data read or write operation in the memory cell of the corresponding column (e.g., column 0) within the selected row. Each column select circuitry is configured to control the corresponding bit line pair. The read / write circuitry is configured to receive a read / write (R / W) control signal and, in response to the R / W control signal, control the column select circuitry system.

[0037] Figure 2 This is a block diagram of a read / write circuit in a read / write circuit system according to certain embodiments of this application. As shown, the read / write circuit includes a tri-state write driver and a sense amplifier similar to those in a conventional SRAM circuit. In some embodiments, BLT<0:m> and BLC<0:m> can be multiplexed to IBLT<0:j> and IBTC<0:j>, where j can be a part of m. Furthermore, each CS can select multiple BLT / BLC pairs. For example, one CS can select four BLT / BLC pairs. Each BLT / BLC pair is connected to the IBLT / IBLC corresponding to each read / write circuit. The read / write circuit also receives data write (DW) and write enable (WEN) signals and outputs a data read (DR) signal (driven by DZ / DZB signals).

[0038] Figure 3A and Figure 3BA schematic diagram of an NVSRAM cell 300 (which may be a bit cell, such as bit (i,j), where i = 0, 1, ..., n, j = 0, 1, ..., m) in an NVSRAM array 101 according to certain embodiments of this application is shown. As shown, according to certain embodiments of this application, the NVSRAM cell 300 is coupled to a voltage cell line VCEL, two complementary bit lines BLT and BLC, an SRAM word line WL, and an MRAM word line MWL. As shown, the NVSRAM cell 300 includes an SRAM cell 310 and an MRAM cell 320. In some embodiments of this application, the SRAM cell 310 is a six-transistor SRAM cell (6-T SRAM), but an SRAM cell with additional transistors may also be used. As shown, four of the six transistors in the SRAM cell form two cross-coupled inverters. As shown, one inverter includes complementary transistors PT and NT connected in series, and the other inverter includes complementary transistors PC and NC connected in series. The output of one inverter drives the input of another inverter, and vice versa. Two cross-coupled inverters form two complementary memory nodes, QT and QC, one for storing high (e.g., "1") or low (e.g., "0") data values, and the other for storing complementary low (e.g., "0") or high (e.g., "1") data values. Transistor PT acts as a load transistor, providing the voltage (e.g., Vdd) corresponding to a high data value to the first memory node QT; transistor PC acts as a load transistor, providing the voltage (e.g., Vdd) corresponding to a high data value to the second memory node QC; transistor NT acts as a drive transistor, providing the voltage (e.g., reference voltage Vss or ground) corresponding to a low data value to the first memory node QT; and transistor NC acts as a drive transistor, providing the voltage (e.g., reference voltage Vss or ground) corresponding to a low data value to the second memory node QC.

[0039] SRAM cell 310 also includes access transistors 311 and 312. Access transistor 311 is coupled between the BLT line and the QT node, and access transistor 312 is coupled between the BLC line and the QC node, and both can be activated via the word line WL. The SRAM cell may include additional transistors to allow the SRAM cell to be controlled by additional control signals when needed.

[0040] In some embodiments of this application, the voltages used to operate the NVSRAM cell 300 include Vdd, Vpp, Vbb, and Vrd. For example, Vdd is approximately 0.8V (nominal CMOS voltage), Vpp is approximately 1.0V to 1.5V, Vbb is approximately -0.3V to -0.2V, and Vrd is approximately 0.2V to 0.4V.

[0041] Continue to refer to Figure 3Aand Figure 3B MRAM cell 320 includes a first MTJ circuit 320T coupled between the BLT line and the QC node, and a second MTJ circuit 320C coupled between the BLC line and the QT node. The first MTJ circuit 320T includes a first driving transistor 321 and an MTJ structure MTJ-T connected in series. The pinning layer PL of the MTJ-T is directly coupled (…). Figure 3A (as shown) or coupled via transistor 321 ( Figure 3B (as shown) to the QC node, while the free layer FL of MTJ-T is coupled via transistor 321 ( Figure 3A (shown) or direct coupling ( Figure 3B (Shown) to the BLT line. The second MTJ circuit 320C includes a transistor 322 connected in series and an MTJ structure MTJ-C. The pinned layer PL of the MTJ-C is directly coupled ( Figure 3A (as shown) or coupled via transistor 322 ( Figure 3B (as shown) to the QT node, while the free layer FL of MTJ-C is coupled via transistor 322 ( Figure 3A (shown) or direct coupling ( Figure 3B (As shown) to the BLC line.

[0042] Each of the first and second MTJ circuits can be programmed to switch between a low-resistance state (parallel or P state) and a high-resistance state (anti-parallel or AP state), such as Figure 3C and Figure 3D As shown. Figure 3C This illustrates how the MTJ is programmed to switch to a parallel state (i.e., a low-resistance state or a logic "0" state) to store a "0" data value. To store "0", a current greater than a critical current flows through the MTJ circuit in the direction of arrow 331 (i.e., from the free layer FL of the MTJ to the pinned layer PL of the MTJ). To obtain this current, a positive voltage (e.g., Vdd or Vpp) is applied to the corresponding bit line BL (BLT or BLC) when the corresponding Q node (QC or QT) is at a low voltage level (e.g., Vss), and a positive voltage Vpp is applied to the gate node of the transistor MD through the word line MWL, in order to... Figure 3A In the case of turning on transistor MD and connecting the free layer FL of MTJ to the corresponding bit line BL (or in the case of turning on transistor MD and connecting the free layer FL of MTJ to the corresponding bit line BL), Figure 3B In this case, the pinned layer of the MTJ is connected to the corresponding Q node.

[0043] Figure 3DThis illustrates how the MTJ is programmed to switch to an anti-parallel state (i.e., a high-resistance state or a logic "1" state) to store a "1" data value. To store the "1", a current greater than the critical current flows through the MTJ circuit in the direction of arrow 332 (i.e., from the pinned layer PL of the MTJ to the free layer FL of the MTJ). To obtain this current, with the corresponding Q-node (QC or QT) at a high voltage level (e.g., Vdd), the corresponding bit line BL (BLT or BLC) is grounded (or connected to Vss), and a positive voltage Vpp is applied to the gate node of the transistor MD through the word line MWL to... Figure 3A In the case of turning on transistor MD and connecting the free layer FL of MTJ to the corresponding bit line BL (or in the case of turning on transistor MD and connecting the free layer FL of MTJ to the corresponding bit line BL), Figure 3B In this case, the pinned layer of the MTJ is connected to the corresponding Q node.

[0044] Figure 4 This includes analog waveforms of various signals related to a series of operations involving two NVSRAM cells in the NVSRAM array 101, namely NVSRAM cell bit 0 (e.g., bit 00) and NVSRAM cell bit 1 (e.g., bit 11), according to certain embodiments of this application. Each of NVSRAM cell bit 0 and NVSRAM cell bit 1 can be configured as follows: Figure 3A Or NVSRAM cell 300 as shown in 3B. NVSRAM cell bit 0 is coupled to word lines WL0 and MW0, column select line CS0, VCEL line VCEL0, and bit line pair BLT0 / BLC0. NVSRAM cell bit 1 is coupled to word lines WL1 and MW1, column select line CS1, VCEL line VCEL1, and bit line pair BLT1 / BLC1.

[0045] like Figure 4 As shown, at time t0, the data value "1" is written to the SRAM cell at bit 0. For this operation, CS0 is raised to Vdd, allowing bit lines BLT0 / BLC0 to be set to Vdd / Vss respectively. Around the same time, word line WL0 is set to Vdd. VCEL0 is already at Vdd and can remain there or be placed at a higher voltage. Figure 5AAs shown, when word line WL is at Vdd, access transistor 311 turns on, connecting the QT node to bit line BLT (at Vdd), thereby pulling the QT node up to Vdd. When word line WL0 is at Vdd, access transistor 312 also turns on, connecting the QC node to bit line BLC (at Vss), thereby pulling the QC node down to Vss. A high voltage at the Qt node turns on the driving transistor NC, thereby connecting the QC node to ground (or Vss). A high voltage at the Qt node turns off the load transistor PC, thereby isolating the QC node from VCEL (at Vdd). On the other hand, a low voltage at the QC node turns off the driving transistor NT, thereby isolating the QT node from ground (or Vss). A lower voltage at the QC node also turns on the load transistor PT, thereby connecting the QT node to the VCEL line. Therefore, at the end of the write cycle that writes a "1" to the NVSRAM cell, the QT node is held at Vdd by the load transistor PT, while the QC node is held at Vss by the drive transistor NC, even after WL and BLT / BLC return to their respective default voltage levels. Figure 5A The dotted and dashed lines in the diagram indicate the direction of the current during the write cycle.

[0046] refer to Figure 4 At time t1, the data value "0" is being written to the SRAM cell containing bit 1. For this operation, CS1 is raised to Vdd, allowing bit lines BLT1 / BLC1 to be set to Vss / Vdd respectively. Around the same time, word line WL1 is set to Vdd. VCEL1 is already at Vdd and can remain there or be placed at a higher voltage. Figure 5B As shown, when word line WL is at Vdd, access transistor 311 is turned on, connecting the QT node to bit line BLT (at Vss), thereby pulling the QT node down to Vss. Similarly, when word line WL0 is at Vdd, access transistor 312 is turned on, connecting the QC node to bit line BLC (at Vdd), thereby pulling the QC node up to Vdd. The low voltage at the Qt node turns on the load transistor PC, thereby connecting the QC node to VCEL (at Vdd). The low voltage at the Qt node also turns off the drive transistor NC, thereby isolating the QC node from ground (at Vss). On the other hand, the high voltage at the QC node turns off the drive transistor PT, thereby isolating the QT node from VCEL (or Vdd). The high voltage at the Qt node also turns on the drive transistor NT, thereby connecting the QT node to ground (or Vss). Therefore, at the end of the write cycle that writes a "0" to an NVSRAM cell, the QT node is held at Vss or ground by the drive transistor NT, while the QC node is held at Vdd by the load transistor PC, even after WL and BLT / BLC return to their respective default voltage levels. Figure 5A The dotted and dashed lines in the diagram indicate the direction of the current during the write cycle.

[0047] Continue to refer to Figure 4 From time t2 to time t4, bit 0 and subsequently bit 1 are read. As shown in the figure, the read operation of an NVSRAM cell is similar to the read operation of a standard SRAM cell.

[0048] From time t4 to t6, the NVSRAM device performs an operation to back up values ​​stored in some or all of the SRAM cells 310 of array 101 by writing them to the corresponding MRAM cells 320. This operation can be performed on the SRAM cells 310 of some or all of the cells of array 101 when these NVSRAM cells 300 are in standby mode (i.e., not accessed by the external memory controller) under the control of the SRAM data recovery control device or the external memory controller. Figure 4 As shown, at time t4, CS0 is raised to a high voltage value (e.g., Vdd) and held there during the backup process, allowing BLT0 to be connected to Vdd and BLC1 to ground (or Vss). Around the same time, VCEL0 is raised to Vpp, and MWL0 is raised to Vpp to activate transistors 321 and 322, allowing current to flow through the MTJ structure between VCEL0 and the corresponding bit lines BLT0 and BLC0, as shown. Figure 6A As shown. The direction of the current flowing through the MTJ depends on the voltage at the Q node to which the MTJ is coupled. With the SRAM cell storing "1" (i.e., QC node at Vss, QT node at Vdd), NT and PC are off, while NC and PT are on, causing current to flow from the pinned layer PL of the MTJ-C (which is coupled to the QT node, which is now connected to the VCEL line via transistor PT) to the free layer FL of the MTJ-C (which is now coupled to the BLC via transistor 322, as shown). Figure 3A As shown), this sets or flips the MTJ-C to the AP state. Therefore, the current charges the BLC line, pulling it up from ground (or Vss), as... Figure 4 As shown. Simultaneously, another current flows from the free layer FL of the MTJ-T (which is now coupled to the BLT via transistor 321) to the pinned layer PL of the MTJ-T (which is now coupled to the grounded QT node via transistor NT, as shown). Figure 3A As shown in the diagram, this sets or flips the MTJ-T to the P state. Therefore, the "1" value stored in the SRAM cell is written to the corresponding MRAM cell.

[0049] Note that the above process can be performed simultaneously on all NVSRAM cells not accessed by the memory controller (e.g., the process between t4 and t5 can be applied to an entire row or multiple rows of SRAM cells simultaneously). When multiple cells are involved, only the NVSRAM cells storing a value of "1" will be backed up between t4 and t5. For the corresponding SRAM cells storing "0" in the NVSRAM cells (i.e., QC nodes are at Vdd, QT nodes are at Vss), NC and PT are off, while NT and PC are on. Thus, QC nodes remain at Vdd, and QT nodes remain at Vss. Since FL and PL of each MTJ are at the same voltage, no current flows through MTJ-T or MTJ-C. Therefore, the NVSRAM cells storing "0" are unaffected by write operations to the backed-up SRAM cells storing "1".

[0050] Continue to refer to Figure 4 At time t5, CS1 is boosted to a high voltage value (e.g., Vdd), allowing BLC1 to connect to Vdd and BLT1 to ground. Around the same time, VCEL is pumped up to Vpp, and MWL is boosted to Vpp to activate transistors 321 and 322, allowing current to flow through the MTJ structure between VCEL and the corresponding bit lines BLT and BLC, as shown below. Figure 6B As shown. The direction of the current flowing through the MTJ depends on the voltage at the Q node to which the MTJ is coupled. With the SRAM cell storing "0" (i.e., QC node at Vdd, QT node at Vss), NC and PT are off, while NT and PC are on, causing current to flow from the pinned layer PL of the MTJ-T (which is coupled to the QC node, which is now connected to the VCEL line via transistor PC) to the free layer FL of the MTJ-T (which is now coupled to the BLT via transistor 321, as shown). Figure 3A As shown), this sets or flips the MTJ-T to the AP state. Simultaneously, another current flows from the free layer FL of the MTJ-C (which is now coupled to the BLC via transistor 322, as shown) Figure 3A (As shown) The current flows to the pinning layer PL of the MTJ-C, thereby setting or flipping the MTJ-C to the P state. Therefore, the "0" value stored in the SRAM cell is written to the corresponding MRAM cell.

[0051] Similarly, the above process can be executed simultaneously on all NVSRAM cells not accessed by the memory controller (e.g., the process between t5 and t6 can be applied to an entire row or multiple rows of SRAM cells simultaneously). When multiple cells are involved, only the NVSRAM cells storing "0" values ​​will be backed up between t5 and t6. When the SRAM cells of the NVSRAM cells store "1" (i.e., QC node is at Vss, QT node is at Vdd), NT and PC are off, while NC and PT are on. Thus, QC node remains at Vss, and QT node remains at Vdd. Since FL and PL of each MTJ are at the same voltage, no current flows through MTJ-T or MTJ-C. Therefore, the NVSRAM cells storing "1" are unaffected by write operations to the backed-up SRAM cells storing "0".

[0052] Refer again Figure 4 From time t6 to t7, the NVSRAM device 100 experiences a power failure. When power is restored between time t7 and t8, the NVSRAM device 100, under the control of a data recovery control device, performs a set of operations to recover the lost data stored in the SRAM cells before the power failure from its corresponding MRAM cells. For example... Figure 4 and Figure 7 As shown, to recover the data "1" previously stored in an SRAM cell coupled to a word line (e.g., WL0), the data recovery control device is configured to boost the voltage of the corresponding MWL line to Vrd, Vdd, or Vpp, while keeping the bit lines BLT / BLC grounded (this will allow low current to flow through transistors 321 and 322). The VCEL line is boosted to Vdd or pumped to Vpp, and the word line WL is grounded (turning off transistors 321 and 322). Thus, the Q node (QC or QT) will be set to Vdd or Vss depending on the state of the corresponding MTJ (MTJ-T or MTJ-C).

[0053] For example, when the MRAM cell stores a "1" (i.e., MTJ-T is in the P state and MTJ-C is in the AP state), QC is connected to BLT (at Vss), while QT is isolated from BLC (also at Vss). QC's ground-enabled transistor PT turns on and transistor NT turns off. Therefore, QT is connected to VCEL through PT and isolated from ground through NT. When QT is at Vdd (or higher), transistor PC is off and transistor NC is on. Therefore, QC is isolated from VCEL through PC and remains grounded through NC. Thus, the value of "1" is restored in the corresponding SRAM cell.

[0054] When the MRAM cell stores "0" (i.e., MTJ-T is in AP state and MTJ-C is in P state), QT is connected to BLC (at Vss), while QC is isolated from BLT (also at Vss). QT's grounding transistor PC turns on and transistor NC turns off. Therefore, QC is connected to VCEL through PC and isolated from ground through NC. When QC is at Vdd (or higher), transistor PT is off and transistor NT is on. Therefore, QT is isolated from VCEL through PT and remains grounded through NT. Thus, the value of "0" is restored in the corresponding SRAM cell.

[0055] After restoring the value stored in the SRAM cell before the power failure to the SRAM cell in the row containing bit 0, the data recovery control device continues to restore the value held in the SRAM cell in the row containing bit 1 during the time period t9 to t10, such as... Figure 4 As shown. In some embodiments, the data recovery control device is configured to recover SRAM data values ​​line by line until most or all of the data values ​​have been recovered.

[0056] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the singular forms “a,” “an,” and “a group” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. It should also be further understood that when the terms “comprising,” “including,” and / or “having” are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0057] The term “if” as used herein may optionally be interpreted as “when” or “in response to determination” or “in response to detection” or “according to determination”, depending on the context.

[0058] For illustrative purposes, the foregoing description has been set forth with reference to specific embodiments. However, the illustrative discussion above is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. In view of the foregoing teachings, many modifications and variations are possible. These embodiments were chosen and described in order to best explain their principles and their practical application, thereby enabling those skilled in the art to best utilize these embodiments, as well as various modified embodiments suitable for the particular intended use.

Claims

1. A memory, comprising: comprise: memory cells arranged in n rows and m columns; n variable supply voltage lines, each of which is coupled to the memory cells of a respective row of the n rows; n SRAM word lines, each of which is coupled to the memory cells of a respective row of the n rows; n MRAM word lines, each of which is coupled to the memory cells of a respective row of the n rows; and m bit line pairs, each of which is coupled to the memory cells of a respective column of the m columns; wherein: each memory cell comprises an SRAM cell and an MRAM cell; the SRAM cell comprises first and second storage nodes that are programmable via a respective SRAM word line and a respective bit line pair to be at two complementary voltage levels, respectively; the MRAM cell comprises first and second magnetic tunnel junction (MTJ) circuits, the first MTJ circuit comprising a first transistor and a first MTJ structure having a first pinned layer and a first free layer on opposite sides of a first tunnel barrier layer, the second MTJ circuit comprising a second transistor and a second MTJ structure having a second pinned layer and a second free layer on opposite sides of a second tunnel barrier layer; the first transistor has a first gate coupled to a respective MRAM word line and is configured to connect the first free layer to a first bit line of a respective bit line pair or to connect the first pinned layer to the first storage node in response to a voltage on the respective MRAM word line exceeding an MTJ programming threshold; and the second transistor has a second gate coupled to the respective MRAM word line and is configured to connect the second free layer to a second bit line of the respective bit line pair or to connect the second pinned layer to the second storage node in response to the voltage on the respective MRAM word line exceeding the MTJ programming threshold. the first MTJ structure is configured to flip from an anti-parallel (AP) state to a parallel (P) state in response to a first current from the first bit line to the first storage node exceeding a first threshold, and the second MTJ structure is configured to flip from a parallel (P) state to an anti-parallel (AP) state in response to a second current from the second storage node to the second bit line exceeding a second threshold.

2. The memory of claim 1, wherein, the first MTJ structure is configured to flip from a parallel (P) state to an anti-parallel (AP) state in response to a third current from the first storage node to the first bit line exceeding the second threshold, and the second MTJ structure is configured to flip from an anti-parallel (AP) state to a parallel (P) state in response to a fourth current from the second bit line to the second storage node exceeding the first threshold.

3. The memory of claim 2, wherein, the first threshold is different from the second threshold.

4. The memory of claim 2, wherein, further comprising variable supply voltage control circuitry configured to control the variable supply voltage lines, wherein:

5. The memory of claim 2, wherein, the variable supply voltage control circuitry is configured to control the variable supply voltage lines to be at a first voltage level when the memory cells are to be programmed as the SRAM cells, and to be at a second voltage level when the memory cells are to be programmed as the MRAM cells. The variable supply voltage control circuit is configured to output a first voltage to the respective variable supply voltage line when the first and second storage nodes are programmed to be at two complementary voltage levels via respective word lines and respective bit lines, respectively; and The variable supply voltage control circuit is configured to output a second voltage to the respective variable supply voltage line to cause the first current to exceed the first threshold and the second current to exceed the second threshold, wherein the second voltage is higher than the first voltage.

6. The memory of claim 1, wherein, The first transistor has a first source terminal and a first drain terminal, one of which is coupled to the first free layer and the other of which is coupled to the first bit line.

7. The memory of claim 1, wherein, The second transistor has a second source terminal and a second drain terminal, one of which is coupled to the second free layer and the other of which is coupled to the second bit line.

8. The memory of claim 1, wherein, The first transistor has a first source terminal and a first drain terminal, one of which is coupled to the first pinned layer and the other of which is coupled to the first storage node.

9. The memory of claim 1, wherein, The second transistor has a second source terminal and a second drain terminal, one of which is coupled to the second pinned layer and the other of which is coupled to the second storage node.

10. The memory of claim 1, wherein, Further comprising data recovery control logic that can be configured to cause the memory to perform a data recovery operation to recover data values stored in the memory cells immediately prior to a power down of the memory in response to a power supply of the memory having been restored after the power down, the data recovery operation including a first data recovery operation to recover data in an i-th row of the plurality of rows and a second data recovery operation to recover data in a j-th row of the plurality of rows; wherein the first data recovery operation includes: applying the second voltage to an i-th MRAM word line of the n MRAM word lines during an i-th data recovery period, the i-th MRAM word line corresponding to the i-th row; and increasing a voltage on an i-th variable supply voltage line of the n variable supply voltage lines to the first voltage during the i-th data recovery period, wherein the i-th variable supply voltage line corresponds to the i-th row; wherein the first data recovery operation includes: applying the second voltage to a j-th MRAM word line of the n MRAM word lines during a j-th data recovery period after the i-th data recovery period, wherein the j-th MRAM word line corresponds to the j-th row; and increasing a voltage on a j-th variable supply voltage line of the n variable supply voltage lines to the first voltage during the j-th data recovery period, wherein the j-th variable supply voltage line corresponds to the j-th row; wherein the m bit lines remain grounded during the data recovery operation.

11. A method of operating a memory, the method comprising: The memory comprises: memory cells arranged in n rows and m columns; n variable supply voltage lines, each of which is coupled to the memory cells of a respective row of the n rows; n SRAM word lines, each of which is coupled to the storage cells of a respective row of the n rows; n MRAM word lines, each of which is coupled to the storage cells of a respective row of the n rows; and m bit line pairs, each of which is coupled to the storage cells of a respective column of the m columns; the method comprises: applying a first voltage to a respective variable power supply voltage line during a first time period; applying a second voltage to a respective MRAM word line during a second time period, wherein the second time period overlaps at least a portion of the first time period; connecting a first bit line of a respective bit line pair to a third voltage during a third time period, wherein the third time period at least partially overlaps the first time period; connecting a second bit line of the respective bit line pair to a fourth voltage during a fourth time period, wherein the fourth time period at least partially overlaps the third time period, one of the third voltage and the fourth voltage being a power supply voltage and the other being a reference voltage; wherein: each storage cell comprises an SRAM cell and an MRAM cell; the SRAM cell comprises a first storage node and a second storage node configurable to be at two complementary voltage levels, respectively; the MRAM cell comprises a first magnetic tunnel junction (MTJ) circuit and a second MTJ circuit, the first MTJ circuit comprising a first transistor and a first MTJ structure having a first pinned layer and a first free layer on opposite sides of a first tunnel barrier layer, the second MTJ circuit comprising a second transistor and a second MTJ structure having a second pinned layer and a second free layer on opposite sides of a second tunnel barrier layer; the first transistor has a first gate coupled to the respective MRAM word line and is configured to connect the first free layer to the first bit line of the respective bit line pair or to connect the first pinned layer to the first storage node in response to the second voltage applied to the corresponding MRAM word line during the second time period exceeding an MTJ programming threshold; and the second transistor has a second gate coupled to the respective MRAM word line and is configured to connect the second free layer to the second bit line of the respective bit line pair or to connect the second pinned layer to the second storage node in response to the second voltage applied to the corresponding MRAM word line during the second time period.

12. The method of claim 11, wherein, the first MTJ structure is configured to flip from an anti-parallel (AP) state to a parallel (P) state in response to a first current from the first bit line to the first storage node exceeding a first threshold, and the second MTJ structure is configured to flip from a parallel (P) state to an anti-parallel (AP) state in response to a second current from the second storage node to the second bit line exceeding a second threshold.

13. The method of claim 12, wherein, the first MTJ structure is configured to flip from a parallel (P) state to an anti-parallel (AP) state in response to a third current from the first storage node to the first bit line exceeding the second threshold, and the second MTJ structure is configured to flip from an anti-parallel (AP) state to a parallel (P) state in response to a fourth current from the second bit line to the second storage node exceeding the first threshold.

14. The method of claim 12, wherein, the first threshold is different than the second threshold.

15. The method of claim 12, wherein, further comprising applying a fifth voltage to the respective variable supply voltage line when the first storage node and the second storage node are programmed to be at two complementary voltage levels via a respective word line and a respective bit line pair, respectively; the variable supply voltage control circuit is configured to output a second voltage to the respective variable supply voltage line to cause the first current to exceed the first threshold and the second current to exceed the second threshold, wherein the second voltage is higher than the first voltage.

16. The method of claim 11, wherein, further comprising, after the memory experiences a power down, in response to a power supply of the memory having been restored, performing a data recovery operation to recover data values stored in the storage cells immediately prior to the power down, the data recovery operation including a first data recovery operation to recover data in an i-th row of the plurality of rows and a second data recovery operation to recover data in a j-th row of the plurality of rows; wherein the first data recovery operation includes: applying the second voltage to an i-th MRAM word line of the n MRAM word lines during an i-th data recovery period, the i-th MRAM word line corresponding to the i-th row; and increasing a voltage on an i-th variable supply voltage line of the n variable supply voltage lines to the first voltage during the i-th data recovery period, the i-th variable supply voltage line corresponding to the i-th row; wherein the second data recovery operation includes: applying the second voltage to a j-th MRAM word line of the n MRAM word lines during a j-th data recovery period after the i-th data recovery period, the j-th MRAM word line corresponding to the j-th row; and increasing a voltage on a j-th variable supply voltage line of the n variable supply voltage lines to the first voltage during the j-th data recovery period, the j-th variable supply voltage line corresponding to the j-th row; wherein the m bit line pairs remain grounded during the data recovery operation.

17. A method of operating a memory, the method comprising: the memory includes: storage cells arranged in n rows and m columns, each of the storage cells including an SRAM cell and an MRAM cell; n variable supply voltage lines, each of which is coupled to the storage cells of a respective row of the n rows; n SRAM word lines, each of which is coupled to the storage cells of a respective row of the n rows; n MRAM word lines, each of which is coupled to the storage cells of a respective row of the n rows; and m bit line pairs, each of which is coupled to the storage cells of a respective column of the m columns; the method includes: writing into a plurality of memory cells during one or more write operations, the plurality of memory cells including first memory cells and second memory cells, wherein the one or more write operations cause an SRAM cell in each of the first memory cells to store a first data value and cause an SRAM cell in each of the second memory cells to store a second data value; simultaneously backing up the first memory cells during a first time period, including, for each of the plurality of memory cells, applying a first voltage to the variable power supply voltage line coupled to each respective memory cell, applying a second voltage to the MRAM word line coupled to each respective memory cell, connecting a first bit line of the bit line pair coupled to each respective memory cell to a third voltage, and connecting a second bit line of the bit line pair coupled to each respective memory cell to a fourth voltage; simultaneously backing up the second memory cells during a second time period after the first time period, including, for each of the particular memory cells, applying the first voltage to the variable power supply voltage line coupled to each of the particular memory cells, applying the second voltage to the MRAM word line coupled to each of the particular memory cells, connecting a first bit line of the bit line pair coupled to each of the particular memory cells to the fourth voltage, and connecting a second bit line of the bit line pair coupled to each of the particular memory cells to the third voltage; wherein backing up the first memory cells causes a first current to flow from the SRAM cell of each respective memory cell through a first MTJ structure in the MRAM cell of each respective memory cell to the first bit line, and a second current to flow from the second bit line through a second MTJ structure in the MRAM cell of each respective memory cell to the SRAM cell of each respective memory cell, the first current setting the first MTJ structure to a high resistance (anti-parallel or AP) state, the second current setting the second MTJ structure to a low resistance (parallel or P) state, such that the first data value stored in the SRAM cell of each respective first memory cell of the plurality of first memory cells is written into the MRAM cell of each respective first memory cell; wherein, backing up the second storage unit causes a third current to flow from the first bit line, through the first MTJ structure of the MRAM cell of each particular second storage unit, to the SRAM cell of each particular storage unit, and a fourth current to flow from the SRAM cell of each particular storage unit, through the second MTJ structure in the MRAM cell of each particular storage unit, to the second bit line, the third current setting the first MTJ structure to a low resistance (parallel or P) state, and the fourth current setting the second MTJ structure to a high resistance (anti-parallel or AP) state, such that the second data value stored in the SRAM cell of each particular second storage unit is written into the MRAM cell of each particular second storage unit.

18. The method of claim 17, wherein, Further comprising, after the memory experiences a power down, in response to a power supply of the memory having been restored, performing a data recovery operation to recover data values stored in the storage units immediately prior to the power down, the data recovery operation including a first data recovery operation to recover data in the first row and a second data recovery operation to recover data in the second row; wherein the first data recovery operation includes: applying the second voltage to a first MRAM word line of the n MRAM word lines during a first data recovery period, the first MRAM word line corresponding to the first row; and increasing a voltage on a first variable supply voltage line of the n variable supply voltage lines to the first voltage during the first data recovery period, wherein the first variable supply voltage line corresponds to the first row; wherein the second data recovery operation includes: applying the second voltage to a second MRAM word line of the n MRAM word lines during a second data recovery period after the first data recovery period, wherein the second MRAM word line corresponds to the second row; and increasing a voltage on a second variable supply voltage line of the n variable supply voltage lines to the first voltage during the second data recovery period, wherein the second variable supply voltage line corresponds to the second row; wherein the m bit line pairs remain grounded during the data recovery operation.

19. The method of claim 17, wherein, the plurality of storage units are located in the first row.

20. The method of claim 19, wherein, one or more storage units in the second row are accessed for read / write operations during the first period and / or the second period.

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