Data recovery in non-volatile memory with defective word lines

Abstract

An apparatus includes a control circuit configured to be connected to a word line coupled to a NAND string. The control circuit is configured to detect a defective word line, apply a single word line erase voltage to the word line to erase memory cells of the defective word line, and read data from adjacent memory cells of the NAND string with the memory cells of the defective word line in an erased state.

Description

Background Technology

[0001] This technology relates to non-volatile memory and operations for recovering data from non-volatile memory.

[0002] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Semiconductor memories can include non-volatile or volatile memories. Non-volatile memories allow information to be stored and retained even when not connected to a power source (e.g., a battery). Examples of non-volatile memories include flash memory (e.g., NAND and NOR flash memory), electrically erasable programmable read-only memory (EEPROM), etc. In NAND memories, memory cells are connected in series to form NAND strings. Some memories use two data states (single-level cell or SLC) to store one bit per cell, while others use more than two data states (multi-level cell or MLC, which can store two bits per cell) to store more than one bit per cell. Storing four bits per cell can use sixteen data states (quadruple-level cell or QLC).

[0003] When a data storage system including non-volatile memory is deployed in or connected to an electronic device (host), the memory system can be used to store and retrieve data. For example, data can be stored in response to a program (write) command. Data can be retrieved in response to a read command specifying the data to be retrieved. In some cases, defects in the non-volatile memory can cause programming and / or data retrieval failures. In some cases, such failures can affect large areas of a memory array containing a large amount of data. Recovering data from such affected areas can be challenging. Attached Figure Description

[0004] Elements with similar numbers refer to common components in different attached drawings.

[0005] Figure 1 It is a block diagram depicting one implementation of a storage system.

[0006] Figure 2A This is a block diagram of one implementation scheme for a memory die.

[0007] Figure 2B This is a block diagram of an example of an integrated memory component.

[0008] Figure 3 An example of a portion of a memory structure is shown.

[0009] Figures 4A to 4G An example of a memory structure is shown.

[0010] Figures 5A to 5C The threshold voltage distribution is shown.

[0011] Figure 6 An example of a defective word line is shown.

[0012] Figures 7A to 7C Examples of the effects of defective word lines on programming and reading operations are shown.

[0013] Figures 8A to 8B Examples of NAND strings with and without defective word lines are shown.

[0014] Figure 9 An example of using RC delay to identify defective word lines is shown.

[0015] Figure 10 An example of a single-word line erasure operation is shown.

[0016] Figures 11A to 11C Methods including defect WL detection and recovery are illustrated.

[0017] Figure 12 A method is shown that includes identifying defective word lines and performing single-word line erasure operations. Detailed Implementation

[0018] This document discloses a technique for detecting defective word lines (e.g., defective word lines that can affect a large amount of data) in NAND memory. Programming failures when attempting to program data in a programming block or reading failures when attempting to read data from a block can indicate that the block contains defective word lines (e.g., defective word lines with short circuits that make their voltage uncontrollable). In response to such failures, control circuitry can determine whether a defective word line exists in the block and, if so, identify which word line is defective. A single-word-line erase operation can then be performed to erase all memory cells of the defective word line while simultaneously putting memory cells of other word lines into a programming state. With the memory cells of the defective word line in an erased state (e.g., with a negative threshold voltage), the memory cells are turned on (the channel beneath the defective word line is conductive), making it possible to read other memory cells coupled to the same channel (other memory cells in the same NAND string). The original data can be read and subjected to a de-XOR operation to obtain recovered data, which can then be stored in another block.

[0019] This technology addresses technical problems related to recovering data stored in blocks of NAND memory, including defective word lines. The technology includes a method for identifying defective word lines and performing single-word line erasure to enable the reading of previously programmed data.

[0020] Figure 1This is a block diagram illustrating one embodiment of a storage system 100 implementing the techniques described herein. In one embodiment, the storage system 100 is a solid-state drive (“SSD”). The storage system 100 may also be a memory card, a USB drive, or other type of storage system. The techniques of this invention are not limited to any one type of storage system. The storage system 100 is connected to a host 102, which may be a computer, server, electronic device (e.g., a smartphone, tablet, or other mobile device), appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100 but connected to it. In other embodiments, the storage system 100 is embedded within the host 102.

[0021] Figure 1 The components of the storage system 100 depicted are electronic circuits. The storage system 100 includes a memory controller 120 (or storage device controller) connected to a non-volatile storage device 130 and a local high-speed memory 140 (e.g., DRAM, SRAM, MRAM). The local memory 140 is a non-transient memory, which may include volatile or non-volatile memory. The memory controller 120 uses the local high-speed memory 140 to perform certain operations. For example, the local high-speed memory 140 may logically store information in a physical address translation table (“L2P table”).

[0022] The memory controller 120 includes a host interface 152 that connects to and communicates with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) via PCI Express (PCIe). Other interfaces, such as SCSI, SATA, etc., may also be used. The host interface 152 is also connected to a network on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and provides significant improvements compared to conventional bus and crossbar interconnects. Compared to other designs, the NOC improves the scalability of the system-on-chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems increases, the NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other implementations, NOC 154 can be replaced by a bus.

[0023] Connected to and communicating with NOC 154 are processor 156, ECC engine 158, memory interface 160, and local memory controller 164. Local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., DRAM, SRAM, MRAM).

[0024] ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding. In one embodiment, ECC engine 158 is a software-programmable electronic circuit. For example, ECC engine 158 may be a programmable processor. In other embodiments, ECC engine 158 is a custom-designed dedicated hardware circuit without any software. In yet another embodiment, the functionality of ECC engine 158 is implemented by processor 156.

[0025] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom-designed dedicated hardware circuit without any software. Processor 156 also implements a translation module, either as a software / firmware process or as dedicated hardware circuitry. In many systems, non-volatile memory is addressed inward to the memory system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses while the memory system is idle to store data between locations of one or more memory dies as desired. To implement such a system, memory controller 120 (e.g., a translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory dies. An example specific implementation maintains a table (i.e., the L2P table described above) that identifies the current translation between logical and physical addresses. Entries in the L2P table may include identification of logical addresses and corresponding physical addresses. Although logical address to physical address tables (or L2P tables) include the word "table," they do not have to be tables in the literal sense. Instead, logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all the L2P tables. In such cases, the entire set of L2P tables is stored in storage device 130, and a subset of the L2P tables (the L2P cache) is cached in local memory 140.

[0026] Memory interface 160 communicates with non-volatile memory device 130. In one embodiment, the memory interface provides a switching mode interface. Other interfaces may also be used. In some example implementations, memory interface 160 (or another part of memory controller 120) implements a scheduler and buffer for transferring data to and receiving data from one or more memory dies.

[0027] Temperature measurement circuit 162 includes a temperature transducer 163 located in memory controller 120 (e.g., formed in memory controller die). Temperature measurement circuit 162 can generate a temperature measurement value from the temperature sensed by temperature transducer 163 (e.g., from a measurement of current, voltage, resistance, or other measurement or some combination of measurements).

[0028] In one embodiment, the non-volatile memory device 130 includes one or more memory dies. Figure 2A This is a functional block diagram of one embodiment of a memory die 200 including a non-volatile memory device 130. Each of the one or more memory dies of the non-volatile memory device 130 can be implemented as Figure 2A The memory die 200. Figure 2AThe components depicted are circuits. Memory die 200 includes a memory structure 202 (e.g., a memory array) that may include non-volatile memory cells (also referred to as non-volatile memory device cells), as described in more detail below. The array terminal lines of memory structure 202 include one or more various word line layers organized in rows and one or more various bit line layers organized in columns. However, other orientations may also be implemented. Memory die 200 includes row control circuitry 220, the output of which is connected to a corresponding word line of memory structure 202. Row control circuitry 220 receives a set of M row address signals and one or more various control signals from system control logic unit 260, and typically includes circuitry such as row decoder 222, array driver 224, and block select circuitry 226 for both read and write (programming) operations. Row control circuitry 220 may also include read / write circuitry. Memory die 200 also includes column control circuitry 210, which includes read / write circuitry 225. The read / write circuitry 225 may include a sense amplifier and a data latch. One or more sense amplifier inputs / outputs are connected to corresponding bit lines of the memory structure 202. Although only a single block is shown for the memory structure 202, the memory die may include multiple arrays that can be accessed individually. The column control circuitry 210 receives a set of N column address signals and one or more various control signals from the system control logic unit 260, and typically includes circuitry such as a column decoder 212, array terminal receiver or driver circuitry 214, block select circuitry 216, and read / write circuitry and I / O multiplexer circuitry.

[0029] System control logic unit 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, system control logic unit 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control for memory operations. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 does not use software and is implemented entirely in hardware (e.g., electronic circuitry). In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor located on or outside the memory chip. System control logic unit 260 may also include a power control module 264 that controls the power and voltage supplied to rows and columns of memory structure 202 during memory operations. System control logic unit 260 includes a storage device 266 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating memory structure 202. Temperature measurement circuitry 263 can generate temperature measurements by temperature sensing from one or more temperature transducers located in memory die 200. System control logic unit 260, read / write circuit 225, and / or other components may use temperature measurements obtained from temperature measurement circuit 263 to apply temperature adjustments based on the temperature on the chip. Temperature measurement circuit 263 may be configured as an alternative to or supplement to temperature measurement circuit 162.

[0030] Commands and data are transmitted between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as the "communication interface"). Memory controller interface 268 is an electrical interface used for communicating with memory controller 120. Examples of memory controller interface 268 include a switching mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used.

[0031] In some embodiments, all components of memory die 200 (including system control logic unit 260) may be formed as part of a single die. In other embodiments, some or all of the system control logic unit 260 may be formed on a different die than the die containing memory structure 202.

[0032] In one embodiment, memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory stages are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory, which is integrally formed in one or more physical stages of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0033] In another embodiment, memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0034] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. Implementing the novel embodiments claimed herein does not require a specific non-volatile memory technology. Other examples of suitable technologies for memory cells of memory structure 202 include ReRAM (Resistive Random Access Memory), magnetoresistive memory (e.g., MRAM, spin-torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), and so on. Examples of suitable technologies for memory cell architectures of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, and so on.

[0035] One example of a ReRAM crosspoint memory includes reversible resistive switching elements arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds across the entire temperature range.

[0036] Another example is magnetoresistive random access memory (MRAM), which stores data using magnetic storage elements. These elements are formed from two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. One of these layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the memory by an external magnetic field. The memory device is constructed from a grid of such memory cells. In one implementation for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0037] Phase-change memories (PCMs) utilize the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by changing the coordination state of germanium atoms using only a laser pulse (or a light pulse from another source). Therefore, the programming dose is the laser pulse. Memory cells can be disabled by preventing them from receiving light. In other PCM embodiments, memory cells are programmed by current pulses. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage, light, or other waves. These memory elements within individual selectable memory cells or bits may include additional series elements as selectors, such as bidirectional threshold switches or metallic insulator substrates.

[0038] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, memory configuration, or material composition, but encompass many related memory structures within the technical essence and scope as described herein and as understood by those skilled in the art.

[0039] Figure 2A The components can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuitry, which includes Figure 2AAll other components depicted herein. A key characteristic of memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die allocated to the memory system 100 for memory structure 202; however, this reduces the area of ​​the memory die available for peripheral circuitry. This can impose significant limitations on these peripheral circuitry components. For example, the need to mount sense amplifier circuitry within the available area can be a major constraint on sense amplifier design architecture. Regarding system control logic component 260, the reduced available area may limit the available functionality that can be implemented on the chip. Therefore, a fundamental trade-off must be made in the design of the memory die for memory system 100 between the amount of dedicated area for memory structure 202 and the amount of dedicated area for peripheral circuitry.

[0040] Another area where memory structure 202 often conflicts with peripheral circuitry is in the processing involved in forming these areas, as these areas typically involve different processing techniques and trade-offs when implementing different techniques on a single die. For example, when memory structure 202 is NAND flash memory, it is an NMOS structure, while the peripheral circuitry is typically CMOS-based. For example, elements such as sense amplifier circuitry, charge pumps, logic elements in state machines, and other peripheral circuitry in system control logic unit 260 typically employ PMOS devices. The processing operations used to fabricate CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures (see, for example, Figure 4) particularly benefit from specialized processing operations.

[0041] To mitigate these limitations, the implementation scheme described below can... Figure 2AThe components are separated onto individually formed dies, and then these dies are bonded together. More specifically, the memory structure 202 can be formed on a single die (referred to as the memory die), and some or all of the peripheral circuitry elements (including one or more control circuits) can be formed on separate dies (referred to as the control die). For example, the memory die can be formed solely of memory elements, such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory cell arrays of other memory types. Some or all of the peripheral circuitry (even including elements such as decoders and sense amplifiers) can then be moved to separate control dies. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS elements now moved to a control die that can be optimized for CMOS processing. This provides more space for peripheral elements, and additional capabilities that might not be easily combined can now be incorporated if peripheral elements were confined to the edges of the same die housing the memory cell array. Two dies can then be bonded together in a bonded multi-die memory circuit, with an array on one die connected to peripheral components on the other die. For example, while the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0042] Figure 2B It shows Figure 2A An alternative arrangement of the arrangement can be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of the integrated memory assembly 207 is depicted. One or more integrated memory assemblies 207 may be used to implement a non-volatile memory device 130 of the memory system 100. The integrated memory assembly 207 includes two types of semiconductor dies (or more simply, "dies"). Memory structure die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuitry 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to be connected to memory structure 202 within memory structure die 201. In some embodiments, memory structure die 201 and control die 211 are coupled together.

[0043] Figure 2B An example of peripheral circuitry is shown, including control circuitry formed in the peripheral circuitry or control die 211, which is coupled to the memory structure 202 formed in the memory structure die 201. General components are similar to... Figure 2AThe system control logic unit 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or part of the column control circuitry 210 and all or part of the row control circuitry 220 are located on memory structure die 201. In some embodiments, a portion of the circuitry in system control logic 260 is located on memory structure die 201.

[0044] System control logic unit 260, row control circuitry 220, and column control circuitry 210 can be formed using conventional processes (e.g., CMOS processes), making it possible to add elements and functions more commonly found on memory controller 120, such as ECC, with few or no additional process steps (i.e., the same process steps used to manufacture memory controller 120 can also be used to manufacture system control logic unit 260, row control circuitry 220, and column control circuitry 210). Therefore, while removing such circuitry from a die (e.g., memory structure die 201) can reduce the number of steps required to manufacture such a die, adding such circuitry to a die (e.g., control die 211) may not require many additional process steps. Because some or all of the control circuitry 260, 210, and 220 are implemented using CMOS technology, control die 211 may also be referred to as a CMOS die.

[0045] Figure 2BA column control circuit 210, including read / write circuitry 225, is shown on a control die 211. This column control circuit is coupled to a memory structure 202 on a memory structure die 201 via an electrical path 206. For example, electrical path 206 may provide electrical connections between a column decoder 212, a driver circuit 214, a block select circuit 216, and bit lines of the memory structure 202. The electrical path may extend from the column control circuit 210 in the control die 211 through pads on the control die 211 that bond to corresponding pads on the memory structure die 201 that are connected to bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path in electrical path 206 connected to the column control circuit 210, including a pair of bonded pads. Similarly, row control circuitry 220 (including a row decoder 222, an array driver 224, and a block select circuit 226) is coupled to the memory structure 202 via an electrical path 208. Each electrical path in electrical path 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory structure die 201. For example, one or more temperature transducers may be disposed in the memory structure die 201 and connected to the system control logic 260 in the control die 211, such that the system control logic 260 can use temperature measurements obtained from such temperature transducers to appropriately adjust operating parameters according to temperature. Temperature transducers may also or alternatively be disposed in the control die 211 and / or the memory controller 120.

[0046] For the purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include all or part of the memory controller 120, state machine 262, power control module 264, system control logic unit 260, all or part of row control circuitry 220, all or part of column control circuitry 210, read / write circuitry 225, sense amplifier, microcontroller, microprocessor, and / or other similar functional circuitry or any combination thereof. Control circuitry may consist of hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FPGAs, ASICs, integrated circuits, or other types of circuitry.

[0047] For the purposes of this document, the term "device" may include, but is not limited to, one or more of the following: storage system 100, memory controller 120, storage device 130, memory die 200, integrated memory assembly 207, and / or control die 211.

[0048] Figure 3This is a perspective view as part of an example embodiment of a monolithic three-dimensional memory array / structure that may include memory structure 202, which includes multiple non-volatile memory cells arranged as vertical NAND strings. For example, Figure 3 A portion 400 of a memory block is shown. The depicted structure includes a set of bit lines BL situated above a stack 401 of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. In one embodiment, the alternating dielectric and conductive layers are divided into four (or different numbers of) regions (e.g., sub-blocks) by an isolation region IR. Figure 3 An isolation region IR separating two sub-blocks is shown. The source line layer SL lies beneath alternating dielectric and word line layers. Memory vias are formed within the stack of alternating dielectric and conductive layers. For example, a memory via is labeled MH. Note that in... Figure 3 In the diagram, the dielectric layers are depicted as a perspective view, allowing the reader to see the memory holes located within the stack of alternating dielectric and conductive layers. In one embodiment, NAND strings are formed by filling the memory holes with a material including a charge-trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits. Further details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0049] Figure 4A This is a block diagram illustrating an example organization of memory structure 202, which is divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is the unit of erasure. That is, all memory cells in a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize memory structure 202 to enable signaling and selection circuitry. In some embodiments, a block represents a group of connected memory cells because the memory cells in a block share a common set of word lines.

[0050] Figures 4B to 4F An example three-dimensional (“3D”) NAND structure is depicted, which corresponds to Figure 3 The structure and can be used to implement Figure 2A or Figure 2B The memory structure 202. Figure 4B It is a block diagram depicting a top view of a portion of a block from memory structure 202. Figure 4B The part of the block depicted in the middle corresponds to Figure 4APart 306 of block 2. In one embodiment, the memory array has multiple layers; however, Figure 4B Only the top layer is shown.

[0051] Figure 4B Multiple circles representing vertical columns are depicted. Each vertical column includes multiple selection transistors (also called select gates) and multiple memory cells. In one implementation, each vertical column implements a NAND string. For example, Figure 4B Vertical columns 422, 432, 442, and 452 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details about these vertical columns are provided below. Due to... Figure 4B The block depicted extends beyond the portion shown, therefore the block includes more than... Figure 4B More vertical columns are depicted in the text.

[0052] Figure 4B A set of bit lines 415 is also depicted, including bit lines 411, 412, 413, 414, ..., 419. Figure 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is envisioned that more than twenty-four bit lines connect to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it connects to a bit line. For example, bit line 414 connects to vertical columns 422, 432, 442, and 452.

[0053] Figure 4B The block depicted includes a set of local interconnects 402, 404, 406, 408, and 410 that connect the various layers to source lines below the vertical columns. The local interconnects 402, 404, 406, 408, and 410 also serve to divide each layer of the block into four regions; for example, Figure 4BThe top layer depicted is divided into regions 420, 430, 440, and 450, which are referred to as fingers. In the layer of the blocks implementing memory cells, these four regions are referred to as word line fingers, and these regions are separated by local interconnects. In one embodiment, word line fingers on the common level of the block are connected together to form a single word line. In another embodiment, word line fingers on the same level are not connected together. In one example embodiment, the bit line is connected to only one vertical column in each of regions 420, 430, 440, and 450. In this embodiment, each block has sixteen active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to the common bit line are connected to the same word line (via different word line fingers connected together on the same level); therefore, the system uses source-side select lines and drain-side select lines to select one (or a subset of another) of the four to be used for memory operations (programming, verification, reading, and / or erasing).

[0054] although Figure 4B The illustration shows four vertical columns per region within a block, resulting in sixteen vertical columns for four regions; however, these exact numbers are for example implementations. Other implementations may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block.

[0055] Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggering patterns may be used. In some embodiments, the vertical columns are not staggered.

[0056] Figure 4C An implementation of stack 435 is depicted, showing along... Figure 4B A cross-sectional view of line AA. In addition to data word line layers WLL0 to WLL95, two SGD layers (SGD0, SDG1), two SGS layers (SGS0, SGS1), and six dummy word line layers DWLD0, DWLD1, DWLM1, DWLM0, DWLS0, and DWLS1 are provided. Each NAND string has a drain-side selected transistor at the SGD0 layer and a drain-side selected transistor at the SGD1 layer. In operation, the same voltage can be applied to each layer (SGD0, SGD1) such that the control terminal of each transistor receives the same voltage. Each NAND string has a source-side selected transistor at the SGS0 layer and a drain-side selected transistor at the SGS1 layer. In operation, the same voltage can be applied to each layer (SGS0, SGS1) such that the control terminal of each transistor receives the same voltage. Dielectric layers DL0 to DL106 are also depicted.

[0057] Columns 432 and 434 of memory cells are depicted in a multilayer stack. The stack includes a substrate 303, an insulating film 250 on the substrate, and a portion of the source line SL. A portion of bit line 414 is also depicted. Note that NAND string 484 is connected to bit line 414. NAND string 484 has a source terminal 439 at the bottom of the stack and a drain terminal 438 at the top of the stack. Source terminal 439 is connected to source line SL. Conductive via 441 connects the drain terminal 438 of NAND string 484 to bit line 414. Also depicted is... Figure 4B Local interconnects 404 and 406.

[0058] Stack 435 is divided into three vertical sub-blocks (VSB0, VSB1, VSB2). Vertical sub-block VSB0 includes WLL0 to WLL31. The following layers can also be considered as part of vertical sub-block VSB0 (SGS0, SGS1, DWLS0, DWLS1). Vertical sub-block VSB1 includes WLL32 to WLL63. Vertical sub-block VSB2 includes WLL64 to WLL95. The following layers can also be considered as part of vertical sub-block VSB2 (SGD0, SGD1, DWLD0, DWLD1). Each NAND string has a set of data memory cells in each vertical sub-block. The dummy word line layer DMLM0 is located between vertical sub-block VSB0 and vertical sub-block VSB1. The dummy word line layer DMLM1 is located between vertical sub-block VSB1 and vertical sub-block VSB2. The dummy word line layer has dummy memory cells that can be used to electrically isolate the first set of memory cell transistors (e.g., corresponding to word lines WLL0 to WLL31 of vertical subblock VSB0) within the memory string from the second set of memory cell transistors (e.g., corresponding to word lines WLL32 to WLL63 of vertical subblock VSB1) within the memory string during memory operations (e.g., erase operations or programming operations).

[0059] Figure 4D Depicting Figure 4C An alternative view of the SG layer and word line layer of the stack 435. SGD layers SGD0 and SGD0 (drain-side SG layer) each include rows of parallel SG lines associated with the drain side of a set of NAND strings. For example, SGD0 includes rows of parallel SG lines associated with the drain side of a set of NAND strings. Figure 4B Consistent drain-side SG regions 420, 430, 440, and 450.

[0060] Below the SGD layer is a drain-side dummy word line layer. In one approach, each dummy word line layer represents a word line and connects to a set of dummy memory cells at a given height in the stack. For example, DWLD0 includes word line layer regions 451, 453, 455, and 457. Dummy memory cells (also called non-data memory cells) do not store data and are unable to store data, while data memory cells are eligible to store data. Furthermore, the Vth of dummy memory cells is typically fixed at manufacturing time or can be periodically adjusted, while the Vth of data memory cells changes more frequently, for example, during erase and program operations of the data memory cells.

[0061] Below the dummy word line layer is the data word line layer. For example, WLL95 includes word line layer regions 471, 472, 473, and 474.

[0062] Below the data word line layer is the source-side dummy word line layer.

[0063] Below the source-side dummy word line layer is the SGS layer. SGS layers SGS0 and SGS1 (source-side SG layers) each include parallel rows of SG lines associated with the source side of a set of NAND strings. For example, SGS0 includes source-side SG lines 475, 476, 477, and 478. In one approach, each SG line can be controlled independently. Alternatively, these SG lines can be connected and controlled collectively.

[0064] Figure 4E Depicting Figure 4C A view of region 445. Data memory cell transistors 520 and 521 are located above dummy memory cell transistor 522. Data memory cell transistors 523 and 524 are located below dummy memory cell transistor 522. Multiple layers may be deposited, for example, along the sidewalls (SW) of memory via 444 and / or within each word line layer using atomic layer deposition. For example, each column (e.g., a pillar formed by material within the memory via) may include a blocking oxide / bulk high-k material 470, a charge trapping layer or film 463 (such as SiN or other nitrides), a tunnel layer 464, a polysilicon body or channel 465, and a dielectric core 466. The word line layer may include a conductive metal 462 (such as tungsten) as a control gate. For example, control gates 490, 491, 492, 493, and 494 are provided. In this example, all layers except the metal are provided within the memory via. In other methods, some of the layers may be within the control gate layer. Additional pillars are similarly formed in different memory vias. The pillars can form the pillar-shaped active regions (AA) of the NAND string.

[0065] When a data memory cell transistor is programmed, electrons are stored in a portion of the charge-trapping layer associated with the transistor. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunnel layer. The voltage (Vth) of the data memory cell transistor increases proportionally to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0066] Non-data transistors (e.g., select transistors, dummy memory cell transistors) may also include a charge trapping layer 463. Figure 4E In this configuration, the dummy memory cell transistor 522 includes a charge trapping layer 463. Therefore, the threshold voltage of at least some non-data transistors can be adjusted by storing or removing electrons from the charge trapping layer 463. Not all non-data transistors need to have an adjustable Vth. For example, the charge trapping layer 463 does not need to be present in every select transistor.

[0067] Each memory via in the memory via may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each memory via in the memory via is filled with the host material, and the multiple annular layers are located between the core region and the WLL in each memory via.

[0068] In some cases, tunnel layer 464 may include multiple layers, such as in an oxide-nitride-oxide configuration.

[0069] Figure 4F yes Figures 3 to 4E A schematic diagram depicting a portion of the memory. Figure 4F The physical word lines WLL0 to WLL95, which extend across the entire block, are shown. Figure 4F The structure corresponds to Figures 4A to 4E Section 306 of block 2 includes bit lines 411, 412, 413, 414, ..., 419. Within this block, each bit line is connected to four NAND strings. Drain-side select lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings is connected to the associated bit line. Source-side select lines SGS0, SGS1, SGS2, and SGS3 are used to determine which of the four NAND strings is connected to the common source line. It is also possible to divide this block into four horizontal sub-blocks: HSB0, HSB1, HSB2, and HSB3. Horizontal sub-block HSB0 corresponds to the vertical NAND strings controlled by SGD0 and SGS0, horizontal sub-block HSB1 corresponds to the vertical NAND strings controlled by SGD1 and SGS1, horizontal sub-block HSB2 corresponds to the vertical NAND strings controlled by SGD2 and SGS2, and horizontal sub-block HSB3 corresponds to the vertical NAND strings controlled by SGD3 and SGS3.

[0070] Figure 4G This is a schematic diagram of the horizontal sub-block HSB0. Horizontal sub-blocks HSB1, HSB2, and HSB3 have similar structures. Figure 4G The physical word lines WL0 to WL95, extending across the entire sub-block S0, are shown. All NAND strings in sub-block S0 are connected to SGD0 and SGS0. Figure 4G Only six NAND strings, 501, 502, 503, 504, 505, and 506, are depicted; however, the horizontal sub-block HSB0 will have thousands of NAND strings (e.g., 15,000 or more).

[0071] Figure 4G This concept is used to explain the selection of memory cells. Memory operations are operations designed for the purpose of using memory and include one or more of the following: reading data, writing / programming data, erasing memory cells, and refreshing data in memory cells. During any given memory operation, a subset of memory cells will be identified as undergoing one or more memory operations. These memory cells identified as undergoing memory operations are called selected memory cells. These memory cells not identified as undergoing memory operations are called unselected memory cells. Depending on the memory architecture, memory type, and memory operation, unselected memory cells may be actively or passively excluded from undergoing memory operations.

[0072] As an example of selected and unselected memory cells, during programming, the set of memory cells intended to adopt new electrical characteristics (or other characteristics) to reflect the changed programming state are called selected memory cells, while memory cells not intended to adopt new electrical characteristics (or other characteristics) to reflect the changed programming state are called unselected memory cells. In some cases, unselected memory cells may be connected to the same word line as selected memory cells. Unselected memory cells may also be connected to different word lines than selected memory cells. Similarly, during reading, the set of memory cells to be read is called selected memory cells, while memory cells not intended to be read are called unselected memory cells.

[0073] To better understand the concepts of selected and unselected memory cells, assume that a programming operation is to be performed, and for illustrative purposes only, word line WL94 and horizontal subblock HSB0 are selected for programming (see [link to documentation]). Figure 4GThis means that all memory cells connected to WL94 in horizontal subblocks HSB1, HSB2, and HSB3 (other horizontal subblocks) are unselected memory cells. Some memory cells connected to WL94 in horizontal subblock HS0 are selected memory cells, and some memory cells connected to WL94 in horizontal subblock HS0 are unselected memory cells, depending on how the programming operation is performed and how the data pattern is programmed. For example, those memory cells used to remain in the erase state S0 will be unselected memory cells because their programming state will not change in order to store the desired data pattern, while those memory cells designed to adopt new electrical characteristics (or other characteristics) to reflect the changed programming state (e.g., programmed to states S1 through S7) are selected memory cells. See also Figure 4G Assuming that, for illustrative purposes, memory cells 511 and 514 (which are connected to word line WL94) remain in an erased state; therefore, memory cells 511 and 514 are unselected memory cells. Figure 4G (marked as "unsel" in the text). Additionally, for illustrative purposes, it is assumed that memory cells 510, 512, 513, and 515 (these memory cells are connected to word line WL94) will be programmed to any of the data states S1 through S7; therefore, memory cells 510, 512, 513, and 515 are selected memory cells ( Figure 4G (marked as "sel" in the text). Although some memory cells along WL94 can be considered unselected memory cells because these memory cells are used to remain in an erased state, in this case, WL94 can be considered a "selected word line" because selected memory cells 510, 512, 513 and 515 are connected to WL94 and accessed via WL94.

[0074] Although Figures 3 to 4G The example memory system described herein is a three-dimensional memory structure comprising vertical NAND strings with charge-trapping material, but other (2D and 3D) memory structures can also be used with the techniques described herein. The various operations (e.g., read, program, program verification) described below for accessing data in non-volatile memory cells can be applied to the above-described... Figures 3 to 4G One or more of the example memory systems described.

[0075] Typically, during programming operations (via a selected word line), the programming voltage applied to the control gate is a series of programming pulses. Between the programming pulses is a set of verification pulses to perform verification. In many implementations, the magnitude of the programming pulses increases by a predetermined step size with each successive pulse.

[0076] In one implementation, a set of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and all connected to the same word line (selected word line). Other memory cells not selected for programming (unselected memory cells) may also be connected to the selected word line. That is, the selected word line will also be connected to memory cells that should be disabled for programming. For example, when data is written to a set of memory cells, some memory cells will need to store data associated with an erase state, making these memory cells unprogrammable. Furthermore, when memory cells reach their intended target data state, they will be disabled for further programming. These NAND strings (e.g., unselected NAND strings) boost their channels to disable programming; these strings include the memory cells to be disabled for programming connected to the selected word line. When the channel has a boosted voltage, the voltage difference between the channel and the word line is insufficient to induce programming.

[0077] Memory cells in a memory system can be erased, programmed, and read. At the end of a successful programming process, the threshold voltage of the memory cell should, where appropriate, be within one or more distributions of the threshold voltages of the memory cells used for programming or within the distribution of the threshold voltages of the erased memory cells. Figure 5A This is a graph showing the threshold voltage versus the number of memory cells, illustrating an example threshold voltage distribution of a memory array when each memory cell stores one bit of data per memory cell. A memory cell that stores one bit of data per memory cell is called a single-level cell (“SLC”). The data stored in an SLC memory cell is called SLC data; therefore, SLC data comprises one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to the erased data state. Threshold voltage distribution P corresponds to the programmed data state. Therefore, memory cells with a threshold voltage in threshold voltage distribution E are in the erased data state (e.g., they have been erased). Therefore, memory cells with a threshold voltage in threshold voltage distribution P are in the programmed data state (e.g., they have been programmed). In one embodiment, erased memory cells store data "1", and programmed memory cells store data "0". Figure 5A The reference voltage Vr is described. By testing (e.g., performing one or more sensing operations) whether the threshold voltage of a given memory cell is higher or lower than Vr, the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5AA verification reference voltage Vv is also described. In some implementations, when memory cells are programmed into data state P, the system tests these memory cells for a threshold voltage greater than or equal to Vv during a programming verification (or "verification") operation. In some implementations, verification is not performed during SLC programming.

[0078] A memory cell configured to store multiple bits of data per memory cell is called a multilevel cell (“MLC”). Data stored in an MLC memory cell is called MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple bits per memory cell is MLC data. Figure 5B In the example implementation, each memory cell stores three bits of data. Other implementations may use different data capacities per memory cell (e.g., two, four, or five bits of data per memory cell). Memory cells may be configured for SLC or MLC storage of data. In some cases, a block of non-volatile memory cells may be configured for SLC data storage at one time and for MLC data storage at another time.

[0079] Figure 5B Eight threshold voltage distributions are shown, corresponding to eight data states where each cell stores three bits. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) AG represent programmed memory cells and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of that cell depends on the data encoding scheme adopted by that cell. In one embodiment, Gray code allocation is used to assign data values ​​to the threshold voltage range such that if the memory's threshold voltage is erroneously shifted to its adjacent physical state, only one bit will be affected. In one embodiment, the number of memory cells in each state is approximately the same.

[0080] Figure 5B Seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG, are shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages, the system can determine the data state of the memory cell (i.e., A, B, C, D, ...). Figure 5BSeveral verification reference voltages are also shown. The verification voltages are VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some implementations, when memory cells are programmed to data state A, the system tests whether these memory cells have a threshold voltage greater than or equal to VvA. If a memory cell has a threshold voltage greater than or equal to VvA, further programming of the memory cell is prevented (locked). Similar reasoning applies to other data states.

[0081] Figure 5C This illustrates a distribution involving eight threshold voltages (corresponding to, for example, ...). Figure 5B Example of an erase operation for a memory (where each cell stores eight data states with three bits). In an erase operation, the threshold voltage of the memory cell in data state AG is reduced sufficiently so that the memory cell is in the Er state (e.g., a threshold voltage verified to be less than VvEr). While programming (writing) memory cells can be performed for relatively small cells (e.g., pages or word lines), erasing can be performed for larger cells (e.g., blocks).

[0082] In some cases, defects can occur in non-volatile memory structures (e.g., as relative to...). Figures 3 to 4G In the implemented memory structure 202), such defects may form during the manufacturing process. Defects may be detected during initial testing or may later become apparent during use. Defects may affect single cells, multiple cells, or larger cells, such as word lines, bit lines, or blocks. Defects affecting blocks may be particularly significant in memory structures with large blocks. In memory structures where memory cells are connected in series (e.g., in a NAND string), one memory cell can affect the connected memory cells.

[0083] One example of a defect that can affect most memory structures is a defective word line. For instance, in some cases, a word line may be short-circuited, making it difficult or impossible to apply the desired voltage to the short-circuited word line (e.g., the word line may be electrically connected to or short-circuited to another component with a fixed voltage that prevents voltage control of the short-circuited word line). This defect can affect all cells coupled to the short-circuited word line. Furthermore, memory cells connected in series with directly affected memory cells (memory cells coupled to the short-circuited word line) may also be affected.

[0084] Figure 6An example of word lines WL0-WL127 coupled to a NAND string (e.g., in memory structure 202) is shown. In this example, WL5 is defective because defect 610 (e.g., a fragment, metal or other foreign material, patterning defect, or other defect) electrically connects WL5 to line 612. This defect can affect the voltage that can be applied to WL5, which can affect read and / or write operations. For example, the electrical connection formed by defect 610 can cause WL5 to remain at approximately the same voltage as line 612 during read and / or write operations involving any of the memory cells in WL0-WL127 (not just defective WL5), which can cause such operations to fail, as illustrated in the example below. Because the memory cells in WL0-WL127 are affected, a significant amount of data may be lost if this defect manifests during use. For example, an entire block may be affected, and any data previously programmed into the block may be lost.

[0085] Figure 7A The diagram depicts voltage signals comprising multiple pulses applied to the control gate of a non-volatile memory cell (e.g., to word lines such as WL0-WL127) during an example programming operation. The horizontal axis represents the pulse number, ranging from 1 to 22, and the vertical axis represents the programming voltage. During the programming operation, a programming cycle is performed on selected word lines in selected blocks within each plane. The programming cycle includes a programming portion and a subsequent verification portion, in which a programming pulse at the corresponding programming voltage is applied to the selected word line, and in which a verification signal is applied to the selected word line while one or more verification tests are performed on the associated memory cell. Each assigned state, except for the erase state, has a verification voltage used for verification testing of that state during the programming operation.

[0086] Voltage signal 700 includes a series of programming pulses applied to the selected word line for programming at different programming voltages, including an initial programming pulse 701. In this example, the voltage signal includes programming pulses with corresponding programming voltages that gradually increase in amplitude using fixed or varying step sizes in programming cycles of programming iterations. This is called incremental step pulse programming, where the programming voltage starts at an initial level Vpgm_int with the initial programming pulse 701 and increases in steps of a certain size in each subsequent programming cycle, for example, until the programming operation is complete. Successful completion occurs when the threshold voltage of the selected memory cell reaches the verification voltage for allocating data state.

[0087] Based on the allocated data states being verified against the programming cycle, the verification signal in each programming cycle (including example verification signal 702) may include one or more verification voltages. As the programming operation progresses, the verification test may include a lower allocated data state, followed by a medium allocated data state, and then a higher allocated data state. The example verification signal depicts three verification voltages for simplicity.

[0088] For example, at the start of a programming operation, all memory cells may initially be in an erased state (Er). After the programming operation is complete, data can be read from the memory cells using a read voltage across the Vth distribution. Simultaneously, a read pass voltage Vpass (e.g., 8V-10V, also known as the pass voltage) is applied to the remaining word lines. By testing whether the Vth of a given memory cell is higher or lower than one or more read reference voltages, the system can determine the data state represented by the memory cell (e.g., ...). Figure 5B (VrA to VrG).

[0089] Figure 7B This illustrates programming operations (e.g., Figure 7A During part of the exemplified programming operation, the NAND structure (e.g., as shown) Figures 3 to 4G Examples of voltages on various components of the memory structure 202 illustrated in the example. Figure 7B A single programming pulse 710 is shown (e.g., Figure 7A Examples of voltage signals 700 and voltages associated with the application of programming pulse 710 are shown. The horizontal axis represents time, with each trace marked according to the component on which a corresponding voltage is applied (the voltage increases in the vertical direction). At time t0, the voltage ramps up from 0 volts to various target voltages. For example, the bit line (“BL”) voltage ramps up from 0 volts to VDDSA (e.g., 2V). The gate-drain (“SGD”) voltage ramps up from 0 volts to VSGD (e.g., 2.5V) to turn on the SGD transistor (conduct). The unprogrammed and programmed word line (“WL”) voltages ramp up from 0 volts to the pass voltage Vpass (e.g., 9V) to make the corresponding channel conductive. The WL voltage ramps up from 0 volts to the programming voltage VPGM (e.g., Vpgm_int, or ...) of programming pulse 710. Figure 6 Another programming voltage (as shown) is used to induce programming. The select gate-source (“SGS”) voltage is maintained at 0 volts to keep the SGS transistor off (non-conductive). The source voltage (“CELSRC”) is ramped up from 0 volts to VDDSA (e.g., 2.5 volts).

[0090] Subsequently, at time t1, the voltage ramps down (in other examples, different components may ramp down at different times). Figure 7BExamples of voltages that can be obtained from defects (such as defect 610) that cause a short circuit between a word line and another component are illustrated. When the defective word line is an unprogrammed word line, the resulting voltage on the unprogrammed word line may be as shown by dashed line 714. For example, if a short circuit connects an unselected word line to a line at or near zero volts, the voltage on the defective word line may remain at or near zero volts and may not rise to Vpass. When the defective word line is a selected word line, the resulting voltage on the selected word line may be as shown by dashed line 716. For example, if a short circuit connects a selected word line to a line at or near zero volts, the voltage on the defective word line may remain at or near zero volts and may not rise to VPGM, which can lead to programming failure (e.g., failure to program user data at a specified location). When the defective word line is a programmed word line, the resulting voltage on the unprogrammed word line may be as shown by dashed line 718. For example, if a short circuit connects a selected word line to a line at or near zero volts, the voltage on the defective word line may remain at or near zero volts and may not rise to Vpass. Although the examples shown by dashed lines 714, 716 and 718 indicate a voltage of zero volts, in some cases, memory operation may be affected even when a certain voltage is applied (e.g., when an unselected word line reaches a voltage between zero and Vpass or when a selected word line reaches a voltage between zero and VPGM).

[0091] When the selected word line is defective or the programming word line is defective (e.g., ... Figure 7B As illustrated, this can lead to programming failure. For example, if the voltage on the selected word line cannot rise to VPGM, then programming does not occur and the programming operation fails. If the voltage on the programming word line cannot rise to Vpass, then at least some programming memory cells (e.g., programmed to correspond to a higher threshold voltage range for a higher data state) may remain off (channels are not conductive), which can affect programming and programming verification.

[0092] Figure 7C An example of a read operation that can be affected by a defective word line (e.g., WL5 shorted due to defect 610) is shown. Figure 7C The voltages (curves 1400-1404) on various components of a memory structure (e.g., memory structure 202) are shown. Voltage 1400 depicts Vcgr, which is the voltage applied via a selected word line (“selected WL”) to the control gate of a selected memory cell to perform a read (e.g., to obtain a data logic page) at three different read voltages. The selected WL voltage used for reading is set to VrF, VrD, and VrB. Sensing is performed during each value of the selected WL voltage to determine the data of the logic page. If the selected word line is defective (e.g., as...), Figure 6If the selected WL voltage does not rise to VrF, VrD, or VrB (for example, the voltage may remain at or near zero, as indicated by dashed line 720), the memory cell may not be read accurately and a read failure may occur (for example, the data may not be corrected by ECC).

[0093] Voltage 1401 represents the read pass voltage (Vpass) applied to unselected word lines (e.g., WL0 to WLn-1 and WLn+1 to WL127). Applying Vpass turns on unselected memory cells (makes the channel conductive), where Vpass is selected to be a sufficiently high voltage to turn on all memory cells, including those with higher threshold voltages (e.g., in data states F and G). If an unselected word line is defective, the unselected word line voltage may not rise to Vpass (e.g., the voltage may remain at or near zero, as indicated by dashed line 722). This can cause at least some unselected memory cells to remain off (the channel is not conductive). For example, memory cells programmed to remain off for at least some higher data states.

[0094] The drain-side gate voltage SGD, as shown by voltage curve 1402, is set to a high level supplied to the selected SGD transistor (e.g., SGD0). BL 1403 represents the bit line voltage applied to the bit lines (such as bit lines 411 to 419) and is set to a level such as 0.5V as part of the sensing process. CELSRC 1404 represents the source line voltage applied to SL and can be set to a small positive voltage in one method.

[0095] When at least a portion of the channel of a NAND string (e.g., the portion coupled to a defective word line) becomes non-conductive due to the defective word line, all memory cells of the NAND string may be affected. A defective word line can cause some or all of the NAND strings connected to the defective word line to become unreadable and / or unprogrammable.

[0096] Figures 8A to 8B The potential impact of defects (e.g., short circuits) on word lines is further illustrated. Figure 8A The diagram illustrates a NAND string 800 formed by word lines WL0 to WLm coupled to channel 802, select gate SGS, and SGD. Figure 8A In this context, memory cells along WLn are being programmed or read (e.g., WLn is a selected WL for a programming operation with VPGM or a read operation with Vpass). Figure 8AThe voltages applied to different components when a programming pulse or read voltage is applied are shown. While channel 802 can be turned off at SGS (e.g., VSGS = 0 volts), channel 802 is otherwise turned on or conducted (e.g., unselected memory cells are turned on by Vpass, SGD by VSGD, and selected memory cells are turned on by VPGM for programming and may be turned on by Vread depending on the applied data state and read voltage). Programming can occur at the times shown because the electric field between the selected word line WLn and channel 802 causes electrons to move from channel 802 to the charge trapping layer 804 and be trapped there, which increases the threshold voltage. Reading can occur when different read voltages are applied to determine the threshold voltage of the memory cell and the corresponding data state.

[0097] Figure 8B The illustration shows a scenario where the previously programmed word line WLn+1 is defective (e.g., short-circuited, preventing its voltage from rising to Vpass). The memory cell 806 coupled to WLn+1 is shown with a data state G (a relatively high state associated with a high threshold voltage), making it potentially requiring a relatively high control gate voltage to turn on. Other memory cells along the NAND string 800 are turn-on. For example, unprogrammed memory cells on word lines WL0 to WLn-1 and programmed memory cells WLn+2 to WLm receive Vpass sufficient to turn them on. The memory cell in NAND string 800 WLm is shown with a data state G and is turned on by Vpass. Other memory cells (not shown) between WLn+1 and WLm that are programmed to a lower level (e.g., Er to E) are also turn-on with Vpass. Because the programming in this example proceeds from the drain side to the source side (from WLm to WL0), the memory cells along WL0 to WLn-1 remain in the erased state "Er" and remain on. Although Figures 8A to 8B The illustration shows Vpass being applied to all unselected word lines, but in other examples, different pass voltages are used for different word lines (e.g., different for programmed and unprogrammed word lines, different for word lines adjacent to selected word lines and more distant word lines, different for read and write operations, and / or other differences). This technique is not limited to any particular pass voltage scheme.

[0098] In some cases, memory cells in the erase (Er) state can be turned on by a voltage less than Vpass, so that a defective word line connected to an unprogrammed memory cell may not affect reading or writing and may go undetected. In some cases, the defective condition of WLn+1 may only become apparent after it has been programmed and after memory cells on other word lines have been programmed (e.g., WLm to WLn+2). In some cases, a word line may become defective after a period of use (e.g., the defect may lie dormant for a period of time). Large amounts of data can be stored in blocks before a defective word line is encountered. In some cases, a defective word line can prevent the recovery of such data. For example, attempting to retrieve data from... Figure 8B Reading data from memory cells WLn+1 to WLm can be prevented by not being able to raise WLn+1 to Vpass, causing some or all of the memory cells WLn+1 to remain off. When channel 802 is pinched off by memory cell 806 as shown, reads (e.g., by discharging via a NAND string such as NAND string 800) may not provide accurate data, potentially resulting in the loss of stored data.

[0099] According to various aspects of this technology, when a read or write failure is encountered that may correspond to a defective word line (e.g., a short-circuited word line), a defective word line detection is initiated. If a defective word line is detected, a single-word line erase operation is performed, which does not require a high voltage on the defective word line and can therefore be performed even if the defective word line is at a low voltage (e.g., zero volts or near zero volts). Erasing the memory cell of the defective word line to put it in an erased state (Er) allows the memory cell to be turned on without applying a pass voltage (e.g., the threshold voltage of the memory cell of the defective word line may be less than zero, causing it to be turned on at zero volts or near zero volts on the defective word line). With the memory cell of the defective word line turned on in this manner, the channel can be made conductive to enable reading of previously programmed memory cells along the NAND string.

[0100] In some cases, defective word lines can be detected in response to one or more triggering events (e.g., read failure, write failure, or other events). Detection may include multiple steps (e.g., determining whether defective word lines are possible and subsequently identifying which word line is defective). For example, in a first step, multiple programming word lines may be checked to see if more than a predetermined number of word lines (e.g., two) are affected, which may indicate a defective word line (e.g., in...). Figure 8B In this context, WLn+1 has a defect that affects the data in WLn+1 through WLm.

[0101] If more than a predetermined number of word lines are defective, then in the second step, the word lines can be tested to identify the defective word lines. For example, the time it takes to charge (or discharge) a word line to a target level can be checked to see if there are any word lines that charge or discharge beyond acceptable limits over time (the time depends on the resistor-capacitor or RC delay). Figure 9 An example of the RC delay time of a block's word lines (e.g., the time required to charge a word line connected to multiple NAND strings) is shown. An RC delay test can be performed in response to determining that more than a predetermined number of word lines in the block are unreadable (e.g., returned data that cannot be corrected by ECC or UECC). Defective word lines are identified by an RC delay time 920 that is significantly different from the average discharge time, which indicates a short circuit in the corresponding word line. Word lines identified as defective in this manner can subsequently undergo single-word line erasure.

[0102] Figure 10 An example of single-word line erasure according to an example word line WLn is shown. In this example, the selected word line (defective word line) WLn is kept at a low voltage (e.g., zero volts) because it is short-circuited. A relatively high positive voltage (e.g., 5 to 15 volts) is applied to the channel 802 via the bit line (BL), where the drain select gate SGD is turned on to generate a first electric field between the channel 802 and WLn. A second high positive voltage (e.g., 5 to 15 volts) is applied to the unselected (defect-free) word lines WL0 to WLn-1 and WLn+1 to WLm, which are coupled to the channel 802 to increase the channel voltage of the channel 802 (e.g., the select gate can be turned off to make the channel electrically isolated (floating)) and increase the first electric field. With a high positive voltage on the channel 802 and a low voltage on WLn, a strong electric field (first electric field) is formed below WLn, which is sufficient to cause electrons to escape from the charge trapping layer 80. 4. Move to channel 802 (e.g., sufficient to cause an erase). In contrast, other word lines are at a relatively high second positive voltage, making the electric field (second electric field) below the unselected word line weak and insufficient to cause an erase, resulting in little or no erase in memory cells with defective word lines. Therefore, in single-word-line erase, memory cells with the selected word line WLn (a defective word line in this example) are erased, while memory cells with unselected word lines (defective word lines in this example) are not erased.

[0103] exist Figure 10At the end of the illustrated single-word line erase operation, all memory cells of the defective word line WLn can be in an erased (Er) state, such that their threshold voltage is low (e.g., a negative threshold voltage) and the lower portion of channel 802 is conductive. Under this condition, data can be read from previously programmed memory cells of the NAND string 800 (e.g., memory cells from WLn+1 to WLm). In some cases, the raw data read from these memory cells may have a high error rate, making it possible to recover the data from the raw data using one or more appropriate recovery techniques. For example, in some data storage systems, data undergoes an XOR operation before storage, which allows for the recovery of large amounts of data. For example, in the case of XORing two or more data pages to produce XOR data pages, up to a maximum of corrupted data pages can be recovered by deXORing one or more uncorrupted pages and the XOR data pages to generate recovered data. The raw data read from WLn+1 to WLm can be deXORed to generate deXORed data. For example, the de-XOR operation can be applied to recover data pages whose original data cannot be corrected by ECC (e.g., data stored along WLn that was erased by a single-word line erase operation).

[0104] Figures 11A to 11C Methods for implementing various aspects of this technology are illustrated. Figure 11A An example of a method including triggering defective word line detection and recovery due to a write failure is shown. The method includes receiving a host data write request 1120 and programming a selected block's WLn (selected word line) 1122. A status determination 1124 is made regarding whether the WLn has been successfully programmed (status = Pass: Yes). If the selected word line is successfully programmed, a determination 1126 is made regarding whether the selected word line is the last word line in the block. If it is not the last word line in the block, the method includes returning to wait for subsequent host writes, and if it is the last word line, closing the block 1128. If a write failure is detected (status = Pass: No), the method includes triggering defective word line detection and recovery 1130.

[0105] Figure 11B An example of a method including triggering defective word line detection and recovery due to a read failure is shown. The method includes receiving a host data read request 1132, reading data from the NAND and decoding it 1134 (e.g., performing ECC decoding), and determining 1136 whether the decoded data is acceptable (e.g., whether it is correctable or has a bit error rate or BER below a specified value). If the decoded data is acceptable (e.g., correctable or BER below a specified value), the read is considered successful and the memory system can return the data to the host 1137.

[0106] If the decoded data fails, a read retry is performed (1138), and another determination is made (1140) regarding whether the decoded data from the read passed. If the data passes, the read is considered successful, and the decoded data is returned to the host (1137).

[0107] If the decoded data fails, the method includes changing the read voltage 1142 (e.g., changing all or some of the voltages VrA to VrG to attempt to obtain correctable data). The method includes a read retry 1144 using hard and / or soft bit reads with the changed read voltage, and making a determination 1146 regarding whether the decoded data from the read retry passes. Various different read schemes (e.g., different read voltages and / or other different voltages and / or times) can be used to attempt to obtain correctable data. If the decoding operation passes, the read is considered successful, and the decoded data is returned to the host 1137. If the decoding operation fails, the method includes triggering defective read level (WL) detection and recovery 1130.

[0108] Figure 11C Examples illustrating methods for defective word line detection and recovery (e.g., in...) Figures 11A to 11B Step 1130 is triggered, which includes reading pages from WLn, WLn-1, and WLn-2 1150 (e.g., reading data from a predetermined number of word lines previously programmed). A determination 1152 is made regarding whether more than two word lines are corrupted (e.g., pages from more than two word lines cannot be corrected by ECC). If more than two word lines are not corrupted (e.g., only one WL is corrupted), then... Figure 6 The defective word line is unlikely to be found and alternative recovery methods are attempted (1154). If more than two word lines are damaged, the method includes triggering a word line RC test to identify short-circuited word lines (1156, e.g., as shown). Figure 9 (As illustrated). If no single word line defect is detected, the method includes attempting to read data from WL0 to WLn-3, programming the recovered data into another block 1161, and reporting a problem 1162 (e.g., reporting data as UECC and / or a defect rate per million (DPPM) or BER above the limit).

[0109] If a single word line defect is detected and the defective word line is identified by RC testing, the method includes performing a single word line erasure operation 1164 on the defective word line (e.g., as...). Figure 10 As illustrated), read previously programmed data 1166 from all defect-free word lines (e.g., from...). Figure 10The original data is read from memory cells WLn+1 to WLm, the original data is de-XORed 1168 from the defect-free word line, and the recovered data is written to another block 1170 (e.g., a new block). This ends the defective word line detection and recovery, and the memory system can continue with subsequent operations. In the case where defective word line detection and recovery is triggered by a programming failure (e.g., ...), Figure 11A User data that failed to be programmed can be stored in a new block along with the recovered data, and programming can continue in the new block. In the case of defective word line detection and recovery triggered by a read failure ( Figure 11B This allows the data specified in a read command to be returned to the host. Blocks with defective word lines can be marked as defective (e.g., added to a bad block list) and subsequent memory access commands can be directed to a new block (e.g., the logical-to-physical address mapping can be updated to indicate that the data is in a new block).

[0110] Figure 12 An example of a method is shown, which includes: reading two or more data pages 1280 (e.g., reading WLn-1 and WLn-2) from memory cells connected by a plurality of NAND strings; and, in response to determining that the two or more data pages are uncorrectable, performing an RC delay test 1282 on a plurality of word lines coupled to the plurality of NAND strings (e.g., as shown in the diagram). Figure 9 (as shown); In response to identifying a defective word line through an RC delay test, a single-word line erase operation is performed to erase the memory cell 1284 coupled to the defective word line (e.g., as shown). Figure 10 (as shown); and then recover data 1286 from previously written memory cells of multiple NAND strings, which may include reading to obtain the original data and deXORing the original data to obtain the recovered data.

[0111] While the examples above illustrate single-word line erasure in response to defective word lines, in cases where two or more word lines are defective (e.g., short-circuited), the described erasure techniques can be applied to two or more word lines (e.g., sequentially as two or more single-word line erasure operations involving different word lines or in parallel as multi-word line erasure operations that do not affect the data of other word lines).

[0112] include Figures 11A to 12The techniques described above in the illustrated method can be implemented by any suitable control circuitry. For example, any or any combination of the memory controller 120, state machine 262, system control logic unit 260, row control circuitry 220, column control circuitry 210, read / write circuitry 225, sense amplifier, microcontroller, microprocessor, and / or other similar functional circuitry can implement the techniques described above and can be considered as examples of components used for: detecting short-circuited word lines; performing single-word line erasure of memory cells along the short-circuited word lines; and recovering previously written data from memory cells connected to the short-circuited word lines in the NAND string when the memory cells along the short-circuited word lines are in an erased state.

[0113] Examples of devices include one or more control circuits configured to be connected to multiple word lines coupled to multiple NAND strings. The one or more control circuits are configured to detect defective word lines among the multiple word lines, apply a single-word-line erase voltage to the multiple word lines to erase the memory cells of the defective word lines, and, while the memory cells of the defective word lines are in the erased state, read data from adjacent memory cells of the multiple NAND strings.

[0114] In one or more embodiments, the one or more control circuits are configured to detect defective word lines by determining that data in memory cells of two or more word lines stored in a plurality of word lines is uncorrectable.

[0115] In one or more embodiments, the one or more control circuits are configured to determine that the data is uncorrectable by reading data stored in a memory cell from a memory cell of two or more word lines of a plurality of word lines using two or more different read schemes.

[0116] In one or more embodiments, the one or more control circuits are further configured to detect defective word lines by testing the RC delay of multiple word lines.

[0117] In one or more embodiments, the one or more control circuits are configured to read data from all previously programmed memory cells of a plurality of NAND strings.

[0118] In one or more embodiments, the one or more control circuits are further configured to perform a de-XOR operation on data from a previously programmed memory cell to obtain recovered data.

[0119] In one or more implementations, multiple NAND strings are located in a first block, and one or more control circuits are further configured to store the recovered data in a second block.

[0120] In one or more embodiments, the one or more control circuits are configured to erase memory cells by applying a single-word-line erase voltage, including applying a first positive voltage to the channel of a plurality of NAND strings to generate a first electric field between the defective word line and the channel sufficient to erase the memory cell of the defective word line, and applying a second positive voltage to a defect-free word line such that the second electric field between the defect-free word line and the channel is insufficient to erase the memory cell of the defect-free word line.

[0121] In one or more embodiments, a plurality of NAND strings are located in the memory die of the integrated memory component, and one or more control circuits are located on the control die of the integrated memory component.

[0122] An example of one approach includes reading two or more data pages from memory cells connected by multiple NAND strings; in response to determining that the two or more data pages are uncorrectable, performing RC delay tests on multiple word lines coupled to the multiple NAND strings. The method also includes performing a single-word-line erase operation to erase the memory cells coupled to the defective word lines in response to identifying defective word lines through the RC delay tests, and subsequently recovering data from previously written memory cells in the multiple NAND strings.

[0123] In one or more embodiments, the method further includes retrying the reading of data pages connected by multiple NAND strings and obtaining uncorrectable data before reading two or more data pages.

[0124] In one or more embodiments, retrying the reading of a data page includes using a first read voltage in a first retry and a second read voltage in a second retry.

[0125] In one or more embodiments, recovering data from previously written memory cells of a plurality of NAND strings includes reading the original data from the previously written memory cells and performing a de-XOR operation to obtain de-XORed data.

[0126] In one or more embodiments, the method further includes storing the de-XORed data in a block that does not include the plurality of NAND strings.

[0127] In one or more embodiments, performing an RC delay test on multiple word lines includes measuring the time required to charge the word lines to a target level and identifying defective word lines based on the time required to charge a defective word line being outside an acceptable range.

[0128] In one or more embodiments, applying a single-word line erase includes: applying a first positive voltage to a bit line connected to a plurality of NAND strings while a drain-side select transistor is turned on, causing the channels of the plurality of NAND strings to reach a positive voltage and generating a first electric field between the channels and the defective word line; subsequently, turning off a drain-side select transistor to electrically isolate the channels; and subsequently, applying a second positive voltage to a defect-free word line to increase the channel voltage and amplify the first electric field, such that the first electric field is sufficient to cause the erasure of a memory cell, and the second electric field between the defect-free word line and the channel is insufficient to cause the erasure of a memory cell.

[0129] In one or more embodiments, in response to a programming failure, two or more data pages are read from memory cells connected by a plurality of NAND strings while attempting to program user data into memory cells of the plurality of NAND strings. The method further includes programming the user data and data from previously written memory cells of the plurality of NAND strings into a block that does not include the plurality of NAND strings.

[0130] An example of a data storage system includes: a plurality of non-volatile memory cells arranged in a NAND string; and components for detecting short word lines, performing single-word line erasure of memory cells along the short word lines, and recovering previously written data from memory cells connected to the short word lines in the NAND string when memory cells along the short word lines are in an erasure state.

[0131] In one or more embodiments, the NAND string is a vertical NAND string in a 3D non-volatile memory structure.

[0132] In one or more embodiments, a 3D non-volatile memory structure is formed on a memory die, and a detection component is formed on a control die coupled to the memory die in the integrated memory assembly.

[0133] For the purposes of this document, the terms “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” used in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0134] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is mentioned as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is mentioned as being directly connected to another element, there is no intermediary element between the two elements. If two devices are directly or indirectly connected, the two devices are “communicating”, enabling them to communicate electronic signals between them.

[0135] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0136] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an ordering of objects, but may be used for identification purposes to distinguish different objects.

[0137] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0138] The detailed description above has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise forms disclosed in the invention. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and various modifications suitable for the specific intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An apparatus comprising: one or more control circuits configured to connect to a plurality of word lines coupled to a plurality of NAND strings, the one or more control circuits configured to: detect a defective word line among the plurality of word lines, apply a single word line erase voltage to the plurality of word lines to erase memory cells of the defective word line, and read data from adjacent memory cells of the plurality of NAND strings in a case where the memory cells of the defective word line are in an erased state.

2. The apparatus of claim 1, wherein the one or more control circuits are configured to detect the defective word line by determining that data stored in memory cells of two or more word lines among the plurality of word lines is uncorrectable.

3. The apparatus of claim 2, wherein the one or more control circuits are configured to determine that the data is uncorrectable by reading the data stored in memory cells of two or more word lines among the plurality of word lines using two or more different read schemes.

4. The apparatus of claim 2, wherein the one or more control circuits are further configured to detect the defective word line by testing RC delays of the plurality of word lines.

5. The apparatus of claim 1, wherein the one or more control circuits are configured to read data from all previously programmed memory cells of the plurality of NAND strings.

6. The apparatus of claim 5, wherein the one or more control circuits are further configured to perform an XOR de- operation on the data from the previously programmed memory cells to obtain recovered data.

7. The apparatus of claim 6, wherein the plurality of NAND strings are in a first block, and the one or more control circuits are further configured to store the recovered data in a second block.

8. The apparatus of claim 1, wherein the one or more control circuits are configured to erase the memory cells by applying the single word line erase voltage includes applying a first positive voltage to a channel of the plurality of NAND strings to create a first electric field between the defective word line and the channel sufficient to erase memory cells of the defective word line, and applying a second positive voltage to a non-defective word line to make a second electric field between the non-defective word line and the channel insufficient to erase memory cells of the non-defective word line.

9. The apparatus of claim 1, wherein the plurality of NAND strings are in a memory die of an integrated memory component, and the one or more control circuits are on a control die of the integrated memory component.

10. A method comprising: reading two or more pages of data from memory cells connected by a plurality of NAND strings; in response to determining that the two or more pages of data are uncorrectable, performing an RC delay test of a plurality of word lines coupled to the plurality of NAND strings; in response to identifying a defective word line by the RC delay test, performing a single word line erase operation to erase memory cells coupled to the defective word line; and ​ Subsequently, data is recovered from previously written memory cells of the plurality of NAND strings.

11. The method of claim 10, further comprising: prior to reading the two or more pages of data, retrying a read of a page of data connected by the plurality of NAND strings and obtaining uncorrectable data.

12. The method of claim 11, wherein retrying the read of the page of data includes using a first read voltage in a first retry and a second read voltage in a second retry.

13. The method of claim 10, wherein recovering data from previously written memory cells of the plurality of NAND strings includes reading original data from the previously written memory cells and performing an XOR de- operation to obtain XOR de-d data.

14. The method of claim 13, further comprising storing the XOR de-d data in a block that does not include the plurality of NAND strings.

15. The method of claim 10, wherein performing an RC delay test of the plurality of word lines includes measuring a time required to charge a word line to a target level, and identifying a defective word line based on the time required to charge the defective word line being outside of an acceptable range.

16. The method of claim 10, wherein applying the single word line erase includes: applying a first positive voltage on a bit line connected to the plurality of NAND strings while a drain select switch is on to cause a channel of the plurality of NAND strings to reach a positive voltage and create a first electric field between the channel and the defective word line; subsequently, turning off a drain side select transistor to electrically isolate the channel; and subsequently, applying a second positive voltage on a non-defective word line to boost a channel voltage and increase the first electric field such that the first electric field is sufficient to cause an erase of a memory cell and a second electric field between the non-defective word line and the channel is insufficient to cause an erase of a memory cell.

17. The method of claim 10, wherein reading the two or more pages of data from memory cells connected by the plurality of NAND strings is performed in response to a program failure while attempting to program user data into memory cells of the plurality of NAND strings, the method further comprising programming the user data and the data from previously written memory cells of the plurality of NAND strings into a block that does not include the plurality of NAND strings.

18. A data storage system, the data storage system comprising: a plurality of non-volatile memory cells arranged in NAND strings; and means for detecting a shorted word line, performing a single word line erase of a memory cell along the shorted word line, and recovering previously written data from memory cells connected to the shorted word line in the NAND string in the case that the memory cell along the shorted word line is in an erased state.

19. The data storage system of claim 18, wherein the NAND strings are vertical NAND strings in a 3D non-volatile memory structure. ​ 20. The data storage system of claim 19, wherein the 3D non-volatile memory structure is formed on a memory die, and the means for detecting is formed on a control die coupled to the memory die in an integrated memory component.

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