Highly reliable memory cell fault-tolerant control system

Abstract

The application discloses a high-reliability storage unit fault-tolerant control system and relates to the technical field of storage unit fault-tolerant control.The system comprises a dynamic charge mapping model module, a potential inversion driving link module, a multi-channel phase conjugate regulation module, a nonlinear charge return channel module and a self-adaptive capacitance equalization control module.The dynamic charge mapping model module constructs a dynamic charge mapping model, takes the real-time response parameters of the parasitic capacitance of the parallel bit lines in the storage unit as input variables, extracts a potential transition curve in the high-frequency read-write switching stage, and generates a dynamic coupling atlas for identifying a pseudo-synchronous charge accumulation area based on the potential transition curve.The application realizes real-time suppression and energy equalization of the parasitic capacitance through dynamic charge mapping and potential inversion, maintains the stability of the bit line potential, realizes energy closed-loop control through nonlinear charge return and self-adaptive capacitance regulation, prevents charge regeneration, and thus improves the stability, reliability and service life of the storage unit.

Description

Technical Field

[0001] This invention relates to the field of fault-tolerant control technology for memory cells, and more specifically to a high-reliability fault-tolerant control system for memory cells. Background Technology

[0002] A high-reliability storage cell fault-tolerant control system is an intelligent data security assurance system for chip-level, module-level, or board-level storage architectures. Its core objective is to continuously maintain data integrity, stability, and recoverability under complex environments, long-term operation, or sudden anomalies. The system constructs a multi-level fault-tolerant management framework to implement real-time monitoring and dynamic error correction throughout the entire process of writing, transmitting, and reading data. It employs collaborative mechanisms such as parity checking, erasure coding, redundant mirroring, and self-healing write-back to achieve rapid detection, accurate location, and automatic repair of storage errors. Simultaneously, the system incorporates an aging prediction model based on parameters such as voltage drift, temperature stress, and write wear, which can identify potential failure units in advance and perform data migration and dynamic reconstruction, thus forming a self-diagnostic, self-repairing, and adaptive closed-loop management capability. This system is widely used in aerospace equipment, industrial control platforms, server arrays, and high-security embedded devices, providing highly reliable operational support for mission-critical storage.

[0003] The existing technology has the following shortcomings:

[0004] During fault-tolerant management, memory cells typically employ bit-line isolation and capacitance balancing designs to suppress charge crosstalk. However, during high-frequency read / write switching, complex dynamic phenomena can still occur, such as abrupt changes in parasitic capacitance coupling between multiple parallel bit lines. When parasitic capacitance undergoes a transient nonlinear change, a pseudo-synchronous charge accumulation region forms between bit lines, causing a temporary imbalance in potential distribution and triggering a cross-bit flip effect between adjacent cells. This type of flip is not caused by a single error event but rather by a chain-like instability triggered by electrical coupling. Since error detection logic usually relies on bit-by-bit comparison or parity checks, when pseudo-synchronous charges cause multiple cells to simultaneously generate reverse potential shifts, the detection algorithm may misjudge the data as being in a normal state, leading to error detection failure. This phenomenon is particularly insidious in high-density, multi-channel, high-speed switching memory structures. Once it occurs, it will disrupt data consistency, render fault-tolerant mechanisms ineffective, and severely weaken overall reliability.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a highly reliable fault-tolerant control system for memory cells to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a high-reliability memory cell fault-tolerant control system, comprising a dynamic charge mapping model module, a potential inversion drive link module, a multi-channel phase conjugate control module, a nonlinear charge foldback channel module, and an adaptive capacitor equalization control module;

[0008] The dynamic charge mapping model module constructs a dynamic charge mapping model, using the real-time response parameters of the parasitic capacitance of the parallel bit lines in the storage unit as input variables, extracting the potential transition curves during the high-frequency read / write switching phase, and generating a dynamic coupling spectrum based on the potential transition curves to identify the pseudo-synchronous charge accumulation region, so as to realize the time-sequential and quantitative control of the bit line energy distribution.

[0009] The potential inversion drive link module establishes a potential inversion drive link based on the pseudo-synchronous charge accumulation region identified in the dynamic coupling spectrum. It corrects the potential transition curve by injecting compensation current in reverse to suppress transient electric field imbalance caused by parasitic capacitance abrupt change in the source layer.

[0010] The multi-channel phase conjugate control module initiates the multi-channel phase conjugate control process based on the corrected potential transition curve. It uses the compensation current signal as the phase reference and dynamically adjusts the coupling vector of each bit line to achieve phase locking and potential synchronization between bit lines, thereby further stabilizing the electric field distribution.

[0011] The nonlinear charge return channel module establishes a nonlinear charge return channel in a phase-locked state. An energy absorption threshold is set within the charge return channel to actively capture unreleased residual charge and guide the energy corresponding to the residual charge into a closed-loop decay path, thereby blocking the regeneration of the pseudo-synchronous charge accumulation region.

[0012] The adaptive capacitor equalization control module generates adaptive capacitor equalization commands based on the energy attenuation results of the closed-loop attenuation path. It continuously adjusts the amplitude of the drive current and compensation current according to the adaptive capacitor equalization commands to achieve steady-state maintenance of parasitic capacitance during multi-frequency read / write switching, thereby eliminating the risk of cross-bit flipping and improving the fault tolerance reliability of the memory cell.

[0013] Preferably, the steps for constructing a dynamic charge mapping model include:

[0014] The parallel bit lines of the target memory cell are initialized. Pulse voltage signals with the same amplitude and opposite polarity are applied to both ends of each bit line to make the bit lines form periodic potential transitions under high-frequency read-write switching conditions. The complete potential transition curve is obtained through the potential sampling units at the input and output ends of the bit lines.

[0015] The potential transition curves are normalized and time-aligned to adjust the potential changes of each potential line to a unified reference standard. A two-dimensional energy distribution table corresponding to time and potential difference is constructed to reflect the direction and intensity of energy transfer between different potential lines.

[0016] Based on the energy distribution table, the potential change relationship between adjacent potential lines is continuously compared to identify potential synchronization behavior and extract the transmission trajectory of parasitic capacitance energy in the time dimension.

[0017] By integrating potential transition curves, time response data, and energy transfer trajectories, a dynamic coupling spectrum across potential lines is generated to achieve time-sequential and quantitative control of potential line energy distribution.

[0018] Preferably, the step of correcting the potential transition curve by reverse injection of compensation current includes:

[0019] After identifying the pseudo-synchronous charge accumulation region in the dynamic coupling spectrum, the set of potential lines corresponding to the pseudo-synchronous charge accumulation region is calibrated to determine the central potential line of charge accumulation and the affected adjacent potential lines. The polarity direction of the charge release path is determined based on the potential transition curve characteristics of the central potential line and the adjacent potential lines.

[0020] Based on the charge release path, a controllable current injection point is set at the source layer end of each bit line that needs to be corrected, and an adjustable reverse compensation current is injected into the target bit line with nanosecond-level time accuracy to form a charge flow trend opposite to the original potential change direction.

[0021] After the reverse injection is completed, the corrected potential transition curve is dynamically verified and closed-loop calibrated. By monitoring the change in potential difference between potential lines and fine-tuning the amplitude of the compensation current, the corrected potential transition curve is restored to the stable range of the non-accumulation region in the dynamic coupling spectrum, so as to achieve synchronous suppression of transient electric field imbalance caused by parasitic capacitance abrupt change.

[0022] Preferably, the injection amplitude and duration of the reverse compensation current are dynamically adjusted according to the real-time changes of the corrected potential transition curve, so that the reverse injection current is synchronized with the discharge process of the parasitic capacitance, so as to ensure that the overshoot or sag of the potential transition curve is smoothly canceled, thereby making the corrected potential distribution symmetrical and maintaining a stable electric field balance state.

[0023] Preferably, the steps of dynamically adjusting the coupling vectors of each bit line to achieve phase locking and potential synchronization between bit lines include:

[0024] After completing the potential inversion drive and obtaining the corrected potential transition curves, all bit lines involved in the coupling are synchronously initialized, the compensation current signal is used as the unified phase reference signal, and the potential transition curves of each bit line are time-aligned with the phase reference.

[0025] After completing the reference alignment, the phase difference between the potential transitions of each bit line is measured to obtain the phase offset and potential synchronization data between each pair of bit lines, and the target channel with the larger phase offset is determined.

[0026] Based on the phase difference measurement results, multi-channel phase conjugate modulation is performed. By controlling the current flow direction and intensity at the source layer of each bit line, the potential change direction of all bit lines is kept consistent with the phase reference, thereby achieving time coincidence of the potential waveform.

[0027] After initial locking is achieved through multi-channel phase conjugate control, phase stability and long-term synchronization are verified for each line. Through micro-compensation adjustment and phase reference update, each line maintains stable phase locking and potential synchronization during continuous operation.

[0028] Preferably, during the phase stability verification and long-term synchronization maintenance process, when a phase drift is detected in any bit line, the current amplitude adjustment is automatically triggered according to the instantaneous change direction of the compensation current signal to correct the potential change sequence of the bit line with phase drift in real time, and the phase reference signal is updated after each switching cycle to ensure continuous phase locking and long-term potential stability among multi-channel bit lines.

[0029] Preferably, the step of directing the energy corresponding to the residual charge into the closed-loop decay path to block the regeneration of the pseudo-synchronous charge accumulation region includes:

[0030] After achieving stable phase locking through multi-channel phase conjugate modulation, the potential changes of each bit line in the locked state are continuously detected to identify energy residue regions and mark them as high-risk areas for charge accumulation.

[0031] A nonlinear charge return channel is established based on the identified high-risk areas, which is activated only when the potential line exceeds the energy absorption threshold, so as to guide the residual charge to the closed-loop decay path.

[0032] The energy absorption threshold is set and dynamically calibrated based on the parasitic capacitance response characteristics, so that the charge return channel can be adaptively triggered and release residual charge when the energy accumulation reaches the set condition;

[0033] After the charge return channel is turned on, a closed-loop energy decay process is initiated. Energy is dissipated step by step through a gradual energy release path and intermediate buffer nodes to prevent potential fluctuations.

[0034] After the energy decay is complete, the potential change curve is verified and dynamically corrected to optimize the charge return channel triggering characteristics and achieve long-term blocking of the pseudo-synchronous charge accumulation region.

[0035] Preferably, the energy absorption threshold is set based on the maximum potential shift of the bit line during high-frequency switching and the charge storage capacity of the parasitic capacitor. During the closed-loop energy decay process, it is dynamically adjusted according to the matching result of the energy release rate and the discharge rate of the parasitic capacitor to ensure that the charge return channel is adaptively triggered only when the energy accumulation reaches the energy absorption threshold, thereby achieving stable energy release and electric field balance maintenance.

[0036] Preferably, the step of continuously adjusting the amplitude of the drive current and the compensation current according to the adaptive capacitor equalization command includes:

[0037] After the closed-loop decay process is completed, the potential changes during the energy decay stage are sampled and recorded to form a comprehensive potential distribution map after energy decay, so as to evaluate the electrical balance status of each line.

[0038] Based on the energy decay results, an adaptive capacitor equalization command is generated. Based on the potential recovery rate and residual fluctuation amplitude, the parasitic capacitance change trend is analyzed to determine the driving current and compensation current amplitude that need to be adjusted.

[0039] The driving current and compensation current amplitude of each line are continuously adjusted according to the equalization command to synchronize the potential recovery process and achieve the balance of parasitic capacitance energy storage and dissipation.

[0040] After adjustment, the parasitic capacitance equalization process is verified in steady state and monitored over a long period of time. The equalization command parameters are dynamically updated according to environmental changes to maintain electrical stability under multi-frequency read / write switching.

[0041] Preferably, during the generation of the adaptive capacitor equalization command, the potential recovery rate of each bit line is further graded and determined based on the comprehensive potential distribution map formed during the energy decay stage. During the adjustment of the amplitude of the driving current and the compensation current, the potential difference between adjacent bit lines is monitored in real time. When the potential difference is less than the zero-reaching threshold and remains stable for more than a preset period, the equalization command parameters are automatically locked to maintain the steady-state response of the parasitic capacitance. The zero-reaching threshold is a fixed value that tends to 0, and no specific limitation is made here.

[0042] The technical effects and advantages provided by the present invention in the above technical solution are as follows:

[0043] This invention constructs a dynamic charge mapping model and a potential inversion driving link, enabling memory cells to achieve real-time identification and active suppression of parasitic capacitance abrupt changes during high-frequency read / write switching. By establishing a dynamic coupling spectrum, pseudo-synchronous charge accumulation regions can be accurately captured, allowing transient changes in parasitic capacitance to be synchronously corrected at the source layer, thus forming an adaptive energy distribution control mechanism at the electrical level. This approach achieves dynamic balance of the potential transition curve, keeping the potential difference between bit lines within a safe range, significantly reducing cross-bit coupling interference, and making potential fluctuations smoother and more continuous. Through this process, the electrical consistency of data is continuously guaranteed during the write, transmission, and read phases, fundamentally avoiding collective instability during multi-channel synchronous switching, and significantly improving the operational stability of the memory array under high load environments.

[0044] This invention introduces a nonlinear charge foldback channel and adaptive capacitor equalization control in a phase-locked state, creating a closed-loop feedback between energy release and potential regulation. Dynamic triggering of the energy absorption threshold ensures that residual charge is captured and guided into the closed-loop decay path in the early stages of accumulation, avoiding secondary superposition of local energy and regeneration of pseudo-synchronous charge. Continuous adjustment of the adaptive capacitor equalization command maintains a long-term match between the bit line drive current and the compensation current, ensuring that parasitic capacitance maintains a steady-state response under multi-frequency switching, and the overall electric field distribution of the system tends to be balanced. Through this continuous energy management and self-regulation mechanism, the memory cell can maintain high electrical reliability and data integrity under complex electrical disturbances, thereby significantly enhancing fault tolerance and lifespan. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0046] Figure 1 This is a schematic diagram of the module of the high-reliability memory cell fault-tolerant control system proposed in this invention.

[0047] Figure 2 This is a flowchart of the high-reliability memory cell fault-tolerant control system proposed in this invention.

[0048] Figure 3 This is a schematic diagram of the principle of constructing the cross-line dynamic charge mapping model proposed in this invention.

[0049] Figure 4 This is a schematic diagram illustrating the principle of dynamically adjusting the coupling vector of each bit line to achieve phase locking and potential synchronization between bit lines, as proposed in this invention. Detailed Implementation

[0050] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0051] This invention provides, for example Figures 1 to 4 The high-reliability memory cell fault-tolerant control system shown includes a dynamic charge mapping model module, a potential inversion drive link module, a multi-channel phase conjugate control module, a nonlinear charge foldback channel module, and an adaptive capacitor equalization control module.

[0052] The dynamic charge mapping model module constructs a cross-bit line dynamic charge mapping model. It uses the real-time response parameters of the parasitic capacitance of the parallel bit lines in the memory cell as input variables, extracts the potential transition curves during the high-frequency read / write switching stage, and generates a dynamic coupling spectrum based on the potential transition curves to identify the pseudo-synchronous charge accumulation region, so as to realize the time-sequential and quantitative control of the bit line energy distribution.

[0053] The dynamic coupling spectrum for identifying pseudo-synchronous charge accumulation regions is generated based on potential transition curves. The specific steps are as follows:

[0054] Before constructing the cross-bit line dynamic charge mapping model, the parallel bit lines of the target memory cell are initialized. Specifically, pulse voltage signals with the same amplitude and opposite polarity are applied to both ends of each bit line, causing periodic potential transitions to occur under high-frequency switching conditions. The rising and falling edges of each pulse signal are precisely controlled within picosecond time ranges to ensure that the electric field changes rapidly enough to fully excite the transient response characteristics of parasitic capacitance. During signal application, the potential change over time is continuously monitored by potential sampling units embedded at the input and output ends of the bit lines, thereby obtaining the potential transition curve of each bit line within a complete switching cycle. These potential transition curves reflect the conduction and accumulation state of charge within the bit lines and between adjacent bit lines. To eliminate external interference, each measurement is repeated multiple times under the same temperature, driving voltage, and load conditions, and the average value of multiple measurements is taken as the standard curve. In this way, it can be ensured that the potential transition curves accurately reflect the real-time response characteristics of parasitic capacitance, rather than fluctuations caused by random signal noise.

[0055] After obtaining the potential transition curves of each bit line, the potential changes between different bit lines are normalized and time-aligned. First, the initial potentials of each bit line are uniformly adjusted to the same reference level, so that the starting point of all curves is at the same reference point. Then, based on the maximum amplitude of the potential change of each bit line, the amplitude of the curves is proportionally normalized so that they can be compared within a unified amplitude range. On the time axis, by detecting the position of the first obvious rising or falling edge of each curve, the key transition points of all curves are aligned, so that the potential changes of different bit lines are within the same time reference frame. After alignment, the potential difference changes of adjacent bit lines in the same time period are recorded, and parameters such as the potential rise rate, fall rate, settling time, and transient overshoot are extracted. Based on this, a two-dimensional energy distribution table corresponding to time and potential difference is constructed to describe the direction and intensity of energy transfer between different bit lines at each time point. When the potential difference of multiple bit lines fluctuates significantly and has a synchronous changing trend in the same time period, it indicates that the transient coupling strength of the parasitic capacitance is high. This information provides a preliminary basis for identifying potential pseudo-synchronous charge accumulation regions.

[0056] After identifying time periods where parasitic capacitance coupling may be enhanced, the potential change relationships between adjacent bit lines are continuously compared. Specifically, two bit lines are grouped together, and their potential change directions and rates within adjacent time intervals are compared. When the potentials of two bit lines exhibit the same change direction over multiple consecutive time intervals, and the change amplitude exceeds a preset threshold, stable potential synchronization behavior is determined to exist in that time period. Based on this, three or more bit lines are combined into multiple comparison groups, and the synchronization degree of all combinations is superimposed for judgment. When multiple bit line groups are detected to simultaneously exhibit continuous synchronous fluctuations with similar amplitudes, a pseudo-synchronous charge accumulation phenomenon is confirmed in that region. At this point, the potential transition curves in that region are analyzed in detail, extracting the average potential, maximum offset, and recovery time of each curve within that time period, thus obtaining the trajectory of parasitic capacitance energy transfer in the time dimension. Through this comparison and extraction process, the originally discrete potential sampling results can be converted into a continuous time response sequence, allowing the potential transition behavior to be expressed as a traceable temporal path, thereby revealing the dynamic response process of parasitic capacitance and the spatial distribution law of charge transfer.

[0057] After acquiring the potential transition curves, time response data, and energy transfer trajectories of multiple bit lines, the above information is integrated to form a dynamic coupling map across bit lines. Specifically, in this map, time is used as the vertical axis to represent the progress of the high-frequency read / write switching process; potential difference is used as the horizontal axis to indicate the instantaneous potential shift between bit lines; and the response intensity of parasitic capacitance is used as the depth dimension, with color depth or numerical value indicating the trend of coupling strength changes. During the plotting process, the potential difference and coupling strength of each pair of bit lines at each time point are mapped to this three-dimensional map, and the potential changes in continuous time periods are connected in the form of curves, thereby generating a complete time-series coupling distribution map. Through this map, it is possible to clearly observe which bit lines have synchronous charge accumulation at specific times during the entire high-frequency read / write cycle, which bit lines have the most significant coupling relationship, and the duration and dissipation trend of the pseudo-synchronous charge region. After completing the map, the potential balance between bit lines and the coupling stability of parasitic capacitance at different time points are further determined based on the energy distribution characteristics it displays. If a region in the spectrum exhibits concentrated coupling strength over a prolonged period, it indicates that the parasitic capacitance in that region is in a non-equilibrium state, requiring priority for potential inversion compensation in subsequent steps. This spectrum-based approach enables time-sequential and quantitative control of the bit line energy distribution, coordinating potential changes across each bit line over time and thus mitigating or eliminating instantaneous electric field imbalances caused by abrupt changes in parasitic capacitance. This entire process not only achieves detailed quantification of the dynamic behavior of parasitic capacitance but also provides precise timing data for subsequent potential inversion driving and energy balance control, ensuring that the memory cell maintains electrical stability and data reliability even under complex high-frequency read / write conditions.

[0058] The potential inversion drive link module establishes a potential inversion drive link based on the pseudo-synchronous charge accumulation region identified in the dynamic coupling spectrum. It corrects the potential transition curve by injecting compensation current in reverse to suppress transient electric field imbalance caused by parasitic capacitance abrupt change in the source layer.

[0059] The potential transition curve is corrected by injecting a compensation current in reverse. The specific steps are as follows:

[0060] After identifying the pseudo-synchronous charge accumulation region in the dynamic coupling spectrum, the corresponding set of potential lines is calibrated. During calibration, the high-density region of energy distribution in the dynamic coupling spectrum is used as the location basis to determine the central potential line of charge accumulation and the affected adjacent potential lines, and their potential transition curve characteristics during the high-frequency switching phase are recorded. For the potential changes of these potential lines, the peak potential, reverse offset time, and recovery delay time of each potential line during the pseudo-synchronous charge accumulation period are extracted to establish a time-correlated potential response sequence. Subsequently, based on these response sequences, the polarity direction of the charge release path is determined on the source layer side. Specifically, if the central potential line exhibits potential overshoot in the potential transition curve, it indicates that there is excessive charge accumulation inside the potential line, and a reverse current should be injected into the source layer to offset the charge potential energy; if adjacent potential lines exhibit potential lag or potential dip, a weak compensation current should be injected simultaneously in the opposite direction to achieve electric field balance. Through this bidirectional response method based on the potential difference direction, the polarity and target path of the reverse injection compensation current can be accurately determined, providing a foundation for subsequent potential inversion driving.

[0061] After determining the direction of reverse injection and the target bit line, the potential inversion drive link is established. Specifically, a controllable current injection point is first set at the source layer end of each bit line requiring correction. This controllable current injection point can input an adjustable-amplitude reverse compensation current to the target bit line with nanosecond-level time accuracy. To ensure that the reverse injection process does not cause new interference to adjacent bit lines, the injection point is electrically strictly isolated from adjacent bit lines, only momentarily conducting when the target bit line potential deviates. After the reverse compensation current is injected, a charge flow trend opposite to the original potential transition curve is formed inside the bit line, partially offsetting the potential rise or fall caused by sudden parasitic capacitance changes. At this time, the overshoot or sag of the original potential transition curve is weakened, and its change curve gradually becomes smoother. To achieve dynamic and continuous potential correction, the duration, amplitude, and rise rate of the current injection are adjusted in real time during the reverse compensation process, keeping the reverse injection current synchronized with the discharge process of the parasitic capacitance. This forms a stable reverse electric field throughout the entire potential transition process to counteract sudden potential imbalances. After multiple injections and feedback corrections, the potential distribution of the affected potential lines will return to symmetry, and the potential transition curve will change from a nonlinear fluctuation to a linear transition curve.

[0062] After completing the reverse injection driven by potential inversion, the corrected potential transition curves are dynamically verified and calibrated using a closed-loop system. Specifically, during a short period after the source layer injection compensation current ends, the potential difference between the corrected potential line and its adjacent potential lines is monitored in real time. When the potential difference recovers to the normal fluctuation range of the non-accumulation region in the dynamic coupling spectrum, it indicates that the compensation current has been effectively suppressed. At this point, the reverse injection path is closed to prevent excessive reverse charge inflow from causing secondary disturbances. If the monitoring results show that some potential lines still have slight potential hysteresis or residual offset, the amplitude of the compensation current is fine-tuned again to ensure that the potential changes of all potential lines maintain the same rate of change and endpoint potential within the same time window. Subsequently, the corrected potential transition curves are re-aligned and compared with the curves before correction. Indicators such as potential recovery time, residual offset, and correction stability are extracted from the difference curves. These indicators can be used to determine whether the correction effect of the potential inversion driving link has achieved the expected results. If the correction results show that the potential recovery time is significantly shortened and the stability is improved, it indicates that the reverse injection compensation process has effectively eliminated the transient electric field imbalance caused by the sudden change in parasitic capacitance. Furthermore, these verification data are fed back to the parameter control unit of the potential inversion drive to update the amplitude reference value and duration of subsequent reverse injections, thereby enabling the potential inversion drive process to have self-learning properties and automatically optimize the compensation strategy under different operating conditions to maintain long-term stable suppression effects.

[0063] Through the above implementation steps, the establishment of the potential inversion driving link not only achieves dynamic correction of the pseudo-synchronous charge accumulation region, but also synchronously cancels the electric field disturbance caused by parasitic capacitance abrupt changes at the source layer. The entire process achieves nanosecond-level response in time and precise inter-bit line compensation in space, ensuring that each bit line maintains an approximately constant potential balance during high-frequency switching. This method, through active reverse injection compensation, enables real-time control of the transient effects of parasitic capacitance, ensuring that the memory cell maintains a stable and reliable operating state under high-density, multi-channel, and fast switching conditions.

[0064] The multi-channel phase conjugate control module initiates the multi-channel phase conjugate control process based on the corrected potential transition curve. It uses the compensation current signal as the phase reference and dynamically adjusts the coupling vector of each bit line to achieve phase locking and potential synchronization between bit lines, thereby further stabilizing the electric field distribution.

[0065] Dynamically adjusting the coupling vectors of each bit line to achieve phase locking and potential synchronization between bit lines, the specific steps are as follows:

[0066] After completing the potential inversion drive and obtaining the corrected potential transition curves, all bit lines involved in the coupling are synchronously initialized to determine the reference base required for phase conjugate modulation. Specifically, the compensation current signal formed in the previous reverse injection process is selected as the unified phase reference signal. This signal, having the opposite polarity to the parasitic capacitance abrupt response, accurately reflects the reverse trend of the potential transition process in time. By monitoring the rising edge, falling edge, and zero-crossing point of this compensation current signal, its phase zero point position on the time axis is determined. Next, the potential transition curves of each bit line are aligned with this phase zero point to ensure that each bit line uses the same time base as a reference in subsequent adjustments. At this point, the potential change of each bit line is converted into a periodic waveform starting from the phase reference, facilitating precise control of its phase offset. Through this unified phase reference processing, all bit lines are placed under the same initial timing conditions before entering the phase conjugate modulation stage, providing an accurate starting point for subsequent phase locking.

[0067] After completing the baseline alignment, the phase difference of the potential transition relationship between each bit line was measured. To achieve high-precision measurement, the curve of potential change over time was continuously collected at both ends of each bit line, and the potential fluctuation range near the phase zero point was recorded. When the potential change directions of two bit lines at the same time point are the same but the amplitudes are different, it indicates that there is a potential coupling deviation with uneven amplitude; when the potential change directions of two bit lines at the same time point are opposite or there is a time lag, it indicates that there is a phase shift. By measuring the phase difference of all adjacent bit lines, a dataset representing the synchronicity of potential changes can be obtained. This dataset reflects the degree of potential coherence and energy transfer direction of each pair of bit lines within a specific time period. Bit line combinations with large phase shifts in the measurement are marked as target channels that need to be adjusted first. To ensure the accuracy of the data, each measurement was repeated multiple times under stable temperature and constant power supply conditions, and the average result was used as the final reference. Through this refined phase difference measurement, a quantitative description of the electrical synchronization state between multi-channel bit lines can be achieved, providing a precise basis for the next step of phase correction.

[0068] After determining the phase difference relationship between each bit line, a multi-channel phase conjugate modulation operation is performed. The core of this operation lies in adjusting the coupling vector on each bit line to ensure that the potential change direction of each bit line is consistent with the phase reference. Specifically, the trajectory of the compensation current signal is used as the conjugate reference signal. By controlling the current flow direction and intensity at the source layer end of each bit line, the potential change rate of that bit line within the same time period is gradually changed. When a potential change in a bit line is detected to lag behind the phase reference, the current flow rate is moderately increased to advance the potential rise or fall; when a potential change in a bit line is detected to advance the phase reference, the current change rate is moderately slowed down to delay the potential change. Through this positive and negative adjustment, the time lag between each bit line can be gradually eliminated, causing the potential transition waveforms of all bit lines to tend to coincide on the time axis. During the adjustment process, the potential waveform changes of each bit line are monitored in real time to ensure that its peaks and troughs remain consistent at the phase reference. When the potential transition waveforms of multiple bit lines exhibit the same change rhythm and phase position within several consecutive switching cycles, it indicates that a phase-locked state has been achieved. At this point, the coupling vectors between each line tend to be consistent, the charge transfer behavior is stable, the energy shift caused by the sudden change in parasitic capacitance is uniformly dispersed, and the electric field distribution reaches equilibrium.

[0069] After initial locking is achieved through multi-channel phase conjugate control, the phase stability verification and long-term synchronization maintenance phase begins. Specifically, during continuous operation, the phase maintenance of all bit lines is monitored across multiple consecutive switching cycles, with a focus on observing periodic deviations in potential changes and phase drift. When a slight phase shift is detected in a bit line during long-term operation, a micro-compensation adjustment process is immediately triggered. Based on the instantaneous change direction of the compensation current signal, the amplitude of the injected current is appropriately increased or decreased to recalibrate the potential change sequence of that bit line. Simultaneously, to prevent new phase instability caused by changes in ambient temperature or voltage fluctuations, the position of the phase reference signal is automatically updated after each cycle to keep it synchronized with the actual potential waveform. Through this continuous dynamic calibration, a stable phase-locked relationship is maintained for all bit lines during long-term operation. Ultimately, with the continuous operation of multi-channel phase conjugate control, the potential changes of all bit lines remain consistent over time, energy transfer between bit lines forms a balanced distribution, the abrupt response of parasitic capacitance is dynamically smoothed, and the overall stability of the electric field distribution is significantly improved, thus providing a stable electrical foundation for subsequent energy attenuation and adaptive equalization stages.

[0070] By implementing the above process, phase synchronization control between multiple channel bit lines can be achieved under high-frequency switching conditions, enabling the memory cell to maintain reliable potential balance and data consistency even under complex electrical disturbances.

[0071] The nonlinear charge return channel module establishes a nonlinear charge return channel in a phase-locked state. An energy absorption threshold is set within the charge return channel to actively capture unreleased residual charge and guide the energy corresponding to the residual charge into a closed-loop decay path, thereby blocking the regeneration of the pseudo-synchronous charge accumulation region.

[0072] The energy corresponding to the residual charge is directed into the closed-loop decay path to block the regeneration of the pseudo-synchronous charge accumulation region. The specific steps are as follows:

[0073] After achieving stable phase locking through multi-channel phase conjugate modulation, the potential changes of all bit lines in the locked state are continuously monitored to identify regions where energy remains after phase locking. Specifically, potential sampling points are deployed between the source layer and the termination layer of each bit line to collect the potential change curves at the end of the switching cycle in real time. When the potential fails to fully return to the equilibrium level within a preset recovery time, or when a slight potential drift occurs in the static phase, it indicates the presence of residual charge inside the bit line or between adjacent bit lines. These potential drift regions are then marked as high-risk areas for charge accumulation. To improve identification accuracy, data from multiple switching cycles are continuously sampled, and the deviation between the theoretical stable curve in the phase conjugate state and the actual measured curve is compared. When the deviation exceeds a set threshold, it is determined that there is charge that can be folded back in that region. In this way, the bit line combinations that may still form energy stagnation in the phase-locked state can be accurately identified, providing precise location for the subsequent establishment of charge foldback channels.

[0074] After identifying the region with residual charge, an initial path for a nonlinear charge return channel is established based on the identified set of potential lines. Specifically, an adjustable conduction path is constructed between the source layer end and intermediate nodes in the identified high-risk potential line region to guide residual charge to the energy return channel under specific energy conditions. The conduction condition of this channel is not fixed but dynamically changes according to the transient response characteristics of the parasitic capacitance; that is, the channel is only activated when the potential of the potential line exceeds a preset energy absorption threshold. This avoids misleading current during normal operation, ensuring that the return channel only functions when the parasitic capacitance response changes abruptly or energy accumulation reaches a dangerous level. The process of establishing this channel also considers the direction of charge flow, making it complementary to the phase conjugate modulation of the previous stage. That is, under the premise of potential synchronization achieved by conjugate modulation, the return channel is responsible for further reducing local energy, forming an interactive energy dissipation mechanism.

[0075] After the charge foldback channel is established, the energy absorption threshold is set and calibrated. The energy absorption threshold is determined based on the maximum potential offset that the bit line can withstand during high-frequency switching and the charge storage capacity of the parasitic capacitance. Specifically, the extreme values ​​of the bit line potential in the previous phase-conjugate locked state are recorded, and the safe potential range of the bit line under high-frequency switching conditions is calculated. When the potential exceeds the upper limit of the safe range, the foldback channel is automatically triggered, guiding the residual charge into the energy decay path. During energy absorption, the energy absorption threshold is dynamically adjusted by continuously monitoring the bit line potential decrease rate and the residual energy release rate to match the actual parasitic capacitance response. This process ensures that the foldback channel will not trigger frequently due to an excessively low threshold, nor will it delay energy release due to an excessively high threshold, thus achieving efficient energy dissipation while maintaining electrical stability. By setting the energy absorption threshold appropriately, adaptive triggering of the charge foldback channel can be achieved, enabling the system to automatically recover and release energy based on the dynamic characteristics of the parasitic capacitance.

[0076] After setting the energy absorption threshold, a closed-loop energy decay process is initiated, guiding the energy corresponding to the captured residual charge to the decay path for gradual release. Specifically, after the return channel is activated, the residual charge migrates along a preset path to the energy decay region. This path has a progressive resistance distribution, allowing the charge to gradually reduce its potential energy and dissipate as heat during flow. Multiple intermediate energy buffer nodes are set within the decay path to temporarily store some energy, preventing excessively rapid energy release from causing new potential fluctuations. As energy is sequentially transferred between these buffer nodes, its potential gradually decreases until it returns to the equilibrium level. Simultaneously, the energy release rate and temperature rise of the decay path are continuously monitored. When the energy release rate matches the parasitic capacitance discharge rate, the return channel is deactivated, ensuring controlled energy release. This progressive closed-loop decay method allows for the complete dissipation of excess energy without affecting the potential stability of adjacent potential lines, preventing the re-accumulation of pseudo-synchronous charges.

[0077] After energy decay is complete, the operational status and stability of the entire charge foldback channel are verified and evaluated. Specifically, by comparing the potential change curves of each bit line before and after energy decay, it is determined whether the potential has recovered to the stable range of the phase-locked state. If, after multiple foldback processes, the potential fluctuation remains within the preset allowable range and there is no new offset trend, it indicates that the energy release effect of the foldback channel is stable. If a slight rebound phenomenon is detected in the local bit line potential, the conduction time of the foldback channel is adjusted to make the energy release process smoother, thereby eliminating the potential bounce caused by secondary coupling. Subsequently, the potential change data of the entire foldback process is fed back to the energy threshold control loop to dynamically correct the trigger parameters of the next cycle, so that the foldback channel maintains high response sensitivity and stable energy dissipation capability during long-term operation. Through this closed-loop verification and dynamic correction method, the nonlinear charge foldback channel can not only capture and release residual charge in a timely manner, but also automatically optimize its trigger characteristics according to the operating status, fundamentally blocking the regeneration of the pseudo-synchronous charge accumulation region. After this process, the parasitic capacitance response of the memory cell under high-frequency switching conditions tends to be stable, the electric field distribution is more uniform, and the overall fault tolerance management capability is further improved.

[0078] The adaptive capacitor equalization control module generates adaptive capacitor equalization instructions based on the energy attenuation results of the closed-loop attenuation path. It continuously adjusts the bit line drive current and compensation current amplitude according to the adaptive capacitor equalization instructions to achieve steady-state maintenance of parasitic capacitance during multi-frequency read / write switching, thereby eliminating the risk of cross-bit flipping and improving the fault tolerance reliability of the memory cell.

[0079] The bit line drive current and compensation current amplitude are continuously adjusted according to the adaptive capacitor equalization command. The specific steps are as follows:

[0080] After the closed-loop decay process is completed, all potential changes during the energy decay phase are sampled and recorded to analyze the electrical stability state after energy release. Specifically, potential monitoring points are set at both ends of each bit line, and high-precision sampling is performed on a steady-state time window after decay is completed to obtain the potential recovery rate, stable level, and residual potential fluctuation range of the bit line. When the potential returns to the equilibrium range within a preset time and the fluctuation amplitude is lower than a set threshold, it indicates that the energy release is sufficient; if the potential still shows a slow fluctuation trend, it indicates that there is still a trace amount of energy remaining during the decay process. To make the energy decay results more dynamic and representative, the monitoring data of multiple bit lines are time-overlaid to form a comprehensive potential distribution map of the entire memory array after energy decay. This potential distribution map can intuitively reflect the differences in the electrical balance state and parasitic capacitance recovery rate of different bit lines after energy decay. Subsequently, this distribution information is used as the basic input condition for generating adaptive capacitance equalization commands to determine whether each bit line needs current adjustment compensation in subsequent stages. Through this accurate assessment based on the state after energy decay, it can be ensured that the target of subsequent equalization adjustment is clear and the response is timely.

[0081] After obtaining the potential recovery data during the energy decay phase, adaptive capacitance balancing commands are generated. In practice, the potential recovery rate and residual fluctuation amplitude from the energy decay results are used as primary reference parameters to analyze the parasitic capacitance trends between bit lines. When a bit line's potential recovery time is significantly longer than other bit lines, or its residual fluctuation amplitude remains persistently high, it indicates that the parasitic capacitance of that bit line is not yet fully balanced, requiring an increase in drive current or adjustment of the compensation current amplitude to accelerate its potential recovery. Conversely, if a bit line recovers its potential too quickly or experiences a slight overshoot, it indicates excessive energy release, requiring an appropriate reduction in drive current amplitude to avoid overcharging and discharging. Through dynamic identification of these situations, a set of balancing commands containing the drive current adjustment direction, amplitude change ratio, and duration can be formed. This balancing command set is generated in alignment with the time axis of the energy decay phase, ensuring precise connection between current adjustment and the end of the energy release process, thereby guaranteeing the continuity and smoothness of the potential balance transition. At this point, the adaptive capacitance balancing commands are equivalent to a set of dynamic adjustment commands based on both time and energy parameters, allowing for real-time adjustment of drive and compensation behavior according to the actual parasitic capacitance response.

[0082] After generating the adaptive capacitor balancing command, the amplitudes of the bitline drive current and compensation current are continuously adjusted according to the command to achieve dynamic electrical balance. Specifically, a precisely controllable current input channel is introduced at the source and terminal ends of each bitline, and current injection is adjusted according to the amplitude and duration defined in the balancing command. When a bitline's potential is detected to be in a recovery lag state, the drive current amplitude is increased according to the command to accelerate the potential transition process of that bitline and synchronize it with other bitlines. When a bitline's potential change is detected to be earlier than other bitlines, its drive current amplitude is decreased according to the command to slow down the rate of potential change and eliminate phase deviation. Simultaneously, for bitlines whose potential still has a slight residual at the end of decay, an appropriate amount of compensation current is injected to neutralize their potential deviation, ensuring a consistent final equilibrium level. Throughout the adjustment process, the trend of potential difference changes between each bitline is continuously monitored. When the potential difference approaches zero and remains stable, it indicates that the energy storage and release rates of the parasitic capacitance have been balanced. To prevent frequent adjustments from causing new potential disturbances, each adjustment interval is set to multiple switching cycles to ensure that the parasitic capacitance reaches a stable balance between natural response and external compensation. This continuous adjustment and gradual balancing method effectively suppresses potential drift caused by uneven energy accumulation or release during multi-frequency read / write switching, maintaining a stable electrical environment.

[0083] After completing the dynamic adjustment of the drive current and compensation current, the entire parasitic capacitance balancing process is verified and its steady-state maintenance is monitored. Specifically, under multi-frequency read / write switching conditions, the potential change characteristics of each bit line at different frequencies and switching rates are continuously detected, and the steady-state duration, potential difference between adjacent bit lines, and energy balance are recorded. When the monitoring results show that the maximum deviation of the potential of each bit line remains within the allowable range under low-frequency, medium-frequency, and high-frequency switching conditions, and there is no significant difference in the response delay of parasitic capacitance, it indicates that the adaptive capacitance balancing process has reached a steady state. To prevent new imbalances caused by environmental changes, fluctuations in temperature, power supply voltage, and switching load are recorded synchronously during the monitoring process, and the balancing command parameters are automatically updated when external environmental changes are detected to ensure that the electrical state always matches the current operating conditions. With repeated cycles of adaptive adjustment and verification, the dynamic response characteristics of parasitic capacitance will gradually stabilize, the energy distribution relationship between bit lines will remain constant, and the risk of cross-bit flipping will be completely eliminated. Ultimately, the entire storage cell achieves adaptive steady-state maintenance of parasitic capacitance during long-term operation, ensuring that the electric field distribution remains in equilibrium under multi-frequency switching conditions, thereby significantly improving the fault tolerance reliability and lifespan of the storage cell.

[0084] Through the above implementation steps, the process of generating adaptive capacitor balancing commands based on the energy attenuation results of the closed-loop attenuation path not only achieves dynamic compensation after electrical energy release but also enables parasitic capacitance to have self-balancing capabilities in multi-frequency environments. This implementation method closely integrates energy dissipation results with current regulation behavior, forming a complete feedback control closed loop. This ensures that the high-density storage structure maintains a stable electrical state under long-term high-load operation, thereby ensuring the integrity and reliability of stored data.

[0085] This invention constructs a cross-bit line dynamic charge mapping model and a potential inversion driving link, enabling memory cells to achieve real-time identification and active suppression of parasitic capacitance abrupt changes during high-frequency read / write switching. By establishing a dynamic coupling spectrum, pseudo-synchronous charge accumulation regions can be accurately captured, allowing transient changes in parasitic capacitance to be synchronously corrected at the source layer, thus forming an adaptive energy distribution control mechanism at the electrical level. This approach achieves dynamic balance of the potential transition curve, keeping the potential difference between bit lines within a safe range, significantly reducing cross-bit coupling interference, and making potential fluctuations smoother and more continuous. Through this process, the electrical consistency of data is continuously guaranteed during the write, transmission, and read phases, fundamentally avoiding collective instability during multi-channel synchronous switching, and significantly improving the operational stability of the memory array under high load environments.

[0086] This invention introduces a nonlinear charge foldback channel and adaptive capacitor equalization control in a phase-locked state, creating a closed-loop feedback between energy release and potential regulation. Dynamic triggering of the energy absorption threshold ensures that residual charge is captured and guided into the decay path in the early stages of accumulation, avoiding secondary superposition of local energy and regeneration of pseudo-synchronous charge. Continuous adjustment of the adaptive capacitor equalization command maintains a long-term match between the bit line drive current and the compensation current, allowing parasitic capacitance to maintain a steady-state response under multi-frequency switching, and resulting in a more balanced overall electric field distribution. Through this continuous energy management and self-regulation mechanism, the storage unit can maintain high electrical reliability and data integrity even under complex electrical disturbances, thus significantly enhancing fault tolerance and lifespan.

[0087] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A high-reliability memory cell fault-tolerant control system, characterized in that, It includes a dynamic charge mapping model module, a potential inversion driving link module, a multi-channel phase conjugate control module, a nonlinear charge return channel module, and an adaptive capacitor equalization control module; The dynamic charge mapping model module constructs a dynamic charge mapping model, using the real-time response parameters of the parasitic capacitance of the parallel bit lines in the storage unit as input variables, extracting the potential transition curves during the high-frequency read / write switching phase, and generating a dynamic coupling spectrum based on the potential transition curves to identify the pseudo-synchronous charge accumulation region. The potential inversion drive link module establishes a potential inversion drive link based on the pseudo-synchronous charge accumulation region identified in the dynamic coupling spectrum, and corrects the potential transition curve by injecting compensation current in reverse. The multi-channel phase conjugate control module initiates the multi-channel phase conjugate control process based on the corrected potential transition curve. It uses the compensation current signal as the phase reference and dynamically adjusts the coupling vector of each bit line to achieve phase locking and potential synchronization between bit lines. The nonlinear charge return channel module establishes a nonlinear charge return channel in a phase-locked state, sets an energy absorption threshold within the charge return channel, actively captures unreleased residual charge, and guides the energy corresponding to the residual charge into a closed-loop decay path to block the regeneration of the pseudo-synchronous charge accumulation region; The adaptive capacitor equalization control module generates an adaptive capacitor equalization command based on the energy attenuation result of the closed-loop attenuation path, and continuously adjusts the amplitude of the drive current and the compensation current according to the adaptive capacitor equalization command.

2. The high-reliability memory cell fault-tolerant control system according to claim 1, characterized in that, The steps to construct a dynamic charge mapping model include: The parallel bit lines of the target memory cell are initialized. Pulse voltage signals with the same amplitude and opposite polarity are applied to both ends of each bit line to make the bit lines form periodic potential transitions under high-frequency read-write switching conditions. The complete potential transition curve is obtained through the potential sampling units at the input and output ends of the bit lines. The potential transition curves are normalized and time-aligned to adjust the potential changes of each line to a unified reference standard, and a two-dimensional energy distribution table corresponding to time and potential difference is constructed. Based on the energy distribution table, the potential change relationship between adjacent potential lines is continuously compared to identify potential synchronization behavior and extract the transmission trajectory of parasitic capacitance energy in the time dimension. By integrating potential transition curves, time response data, and energy transfer trajectories, a dynamic coupling spectrum of the transpotential line is generated.

3. The high-reliability memory cell fault-tolerant control system according to claim 1, characterized in that, The steps for correcting the potential transition curve by reverse injection of compensation current include: After identifying the pseudo-synchronous charge accumulation region in the dynamic coupling spectrum, the set of potential lines corresponding to the pseudo-synchronous charge accumulation region is calibrated to determine the central potential line of charge accumulation and the affected adjacent potential lines. The polarity direction of the charge release path is determined based on the potential transition curve characteristics of the central potential line and the adjacent potential lines. Based on the charge release path, a controllable current injection point is set at the source layer end of each bit line that needs to be corrected, and an adjustable reverse compensation current is injected into the target bit line to form a charge flow trend opposite to the original potential change direction. After the reverse injection is completed, the corrected potential transition curve is dynamically verified and closed-loop calibrated. By monitoring the change in potential difference between potential lines and fine-tuning the compensation current amplitude, the corrected potential transition curve is restored to the stable range of the non-accumulation region in the dynamic coupling spectrum.

4. The high-reliability memory cell fault-tolerant control system according to claim 3, characterized in that, The injection amplitude and duration of the reverse compensation current are dynamically adjusted according to the real-time changes of the corrected potential transition curve, so that the reverse injection current is synchronized with the discharge process of the parasitic capacitance, and the overshoot or sag of the potential transition curve is smoothly canceled.

5. The high-reliability memory cell fault-tolerant control system according to claim 3, characterized in that, The steps to dynamically adjust the coupling vectors of each bit line to achieve phase locking and potential synchronization between bit lines include: After completing the potential inversion drive and obtaining the corrected potential transition curves, all bit lines involved in the coupling are synchronously initialized, the compensation current signal is used as the unified phase reference signal, and the potential transition curves of each bit line are time-aligned with the phase reference. After completing the reference alignment, the phase difference between the potential transitions of each bit line is measured to obtain the phase offset and potential synchronization data between each bit line. Based on the phase difference measurement results, multi-channel phase conjugate modulation is performed. By controlling the current flow direction and intensity at the source layer of each bit line, the potential change direction of all bit lines is kept consistent with the phase reference. After initial locking is achieved through multi-channel phase conjugate control, phase stability and long-term synchronization are verified for each line. Through micro-compensation adjustment and phase reference update, each line maintains stable phase locking and potential synchronization during continuous operation.

6. The high-reliability memory cell fault-tolerant control system according to claim 5, characterized in that, During phase stability verification and long-term synchronization maintenance, when phase drift is detected in any bit line, the current amplitude adjustment is automatically triggered according to the instantaneous change direction of the compensation current signal to correct the potential change timing of the bit line with phase drift in real time, and the phase reference signal is updated after each switching cycle.

7. The high-reliability memory cell fault-tolerant control system according to claim 1, characterized in that, The steps to channel the energy corresponding to the residual charge into the closed-loop decay path and block the regeneration of the pseudo-synchronous charge accumulation region include: After achieving stable phase locking through multi-channel phase conjugate modulation, the potential changes of each bit line in the locked state are continuously detected to identify energy residue regions and mark them as high-risk areas for charge accumulation. A nonlinear charge return channel is established based on the identified high-risk areas of charge accumulation. It is only activated when the potential line exceeds the energy absorption threshold, so as to guide the residual charge to the closed-loop decay path. The energy absorption threshold is set and dynamically calibrated based on the parasitic capacitance response characteristics, so that the charge return channel can be adaptively triggered and release residual charge when the energy accumulation reaches the set condition; After the charge return channel is turned on, a closed-loop energy decay process is initiated, and energy is dissipated step by step through a gradual energy release path and intermediate buffer nodes. After the energy decay is complete, the potential change curve is verified and dynamically corrected to optimize the charge return channel triggering characteristics.

8. The high-reliability memory cell fault-tolerant control system according to claim 7, characterized in that, The energy absorption threshold is set based on the maximum potential shift of the bit line during high-frequency switching and the charge storage capacity of the parasitic capacitor. During the closed-loop energy decay process, it is dynamically adjusted according to the matching result of the energy release rate and the discharge rate of the parasitic capacitor to ensure that the charge return channel is adaptively triggered only when the energy accumulation reaches the energy absorption threshold.

9. The high-reliability memory cell fault-tolerant control system according to claim 7, characterized in that, The steps for continuously adjusting the amplitude of the drive current and compensation current according to the adaptive capacitor equalization command include: After the closed-loop decay process is completed, the potential changes during the energy decay stage are sampled and recorded to form a comprehensive potential distribution map after energy decay, so as to evaluate the electrical balance status of each line. Based on the energy decay results, an adaptive capacitor equalization command is generated. Based on the potential recovery rate and residual fluctuation amplitude, the parasitic capacitance change trend is analyzed to determine the driving current and compensation current amplitude that need to be adjusted. The driving current and compensation current amplitude of each line are continuously adjusted according to the equalization command to synchronize the potential recovery process and achieve the balance of parasitic capacitance energy storage and dissipation. After adjustment, the parasitic capacitance equalization process is verified in steady state and monitored over a long period of time. The equalization command parameters are dynamically updated according to environmental changes to maintain electrical stability under multi-frequency read / write switching.

10. The high-reliability memory cell fault-tolerant control system according to claim 9, characterized in that, During the generation of adaptive capacitor equalization commands, the potential recovery rate of each bit line is graded and determined based on the comprehensive potential distribution map formed during the energy decay stage. During the adjustment of the amplitude of the driving current and the compensation current, the potential difference between adjacent bit lines is monitored in real time. When the potential difference is less than the zero threshold and remains stable for more than a preset period, the equalization command parameters are automatically locked to maintain the steady-state response of the parasitic capacitance.

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