Dual half-bridge circuit module packaging method and dual half-bridge circuit module

Abstract

The application relates to the field of electronic component packaging, in particular to a double half-bridge circuit module packaging method and a double half-bridge circuit module. The application needs to obtain a plurality of transistor chips and a circuit substrate first; wherein the drain of each transistor chip is located on the lower surface of the transistor chip, the gate and the source of each transistor chip are located on the upper surface of the transistor chip, and the circuit substrate is provided with a plurality of substrate chip seats; for each transistor chip, the lower surface of the transistor chip is mounted on the corresponding substrate chip seat; an isolation shielding layer is laid on the circuit substrate; for the positions of the gate and the source of each transistor chip, isolation material is removed, and copper is laid on the isolation shielding layer to arrange lines according to a preset double half-bridge circuit connection scheme, so that a double half-bridge circuit is formed; an insulating material is laid above the double half-bridge circuit to form a module packaging layer, and a double half-bridge circuit module is obtained, which helps electronic devices with better performance to realize miniaturization.

Description

Technical Field

[0001] This application relates to the field of electronic component packaging, and in particular to a packaging method for a dual half-bridge circuit module and a dual half-bridge circuit module. Background Technology

[0002] In the field of power electronics, the half-bridge circuit, as a fundamental and crucial topology, has long played a core role in applications such as PWM motor control, DC-AC inverters, and electronic ballasts. Its typical function is to realize the conversion and control of electrical energy, for example, by alternately turning on the high-side and low-side switches to generate the required AC or pulse waveform at the output.

[0003] The traditional approach involves mounting two separate metal-oxide-semiconductor field-effect transistors (MOSFETs, MOS) on a printed circuit board, and then connecting them to peripheral components such as a driver chip, capacitors, and inductors through PCB routing design to form a complete half-bridge functional module. This discrete construction method has been the industry standard practice for the past few decades, and its technology is mature with a stable supply chain.

[0004] However, the traditional method of constructing a half-bridge circuit using discrete MOS devices via PCB wiring results in a large system size and high cost. Furthermore, due to the physical limitations of interconnecting leads, traditional packaging technologies cannot reliably and efficiently integrate multiple MOS chips within a miniaturized package to form complex circuit functions. These limitations make it difficult to miniaturize electronic devices with good performance. Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a dual half-bridge circuit module packaging method and a dual half-bridge circuit module, which helps to miniaturize electronic devices with good performance.

[0006] The dual half-bridge circuit module packaging method according to the first aspect of this application includes:

[0007] A plurality of transistor chips and a circuit substrate are obtained; wherein the drain of each transistor chip is located on the lower surface of the transistor chip, and the gate and source of each transistor chip are located on the upper surface of the transistor chip, and the circuit substrate is provided with a plurality of substrate chip holders;

[0008] For each transistor chip, the lower surface of the transistor chip is mounted on the corresponding substrate chip holder so that the drain of each transistor chip is electrically connected to the circuit substrate to form a drain port;

[0009] After each transistor chip is installed, an insulating material is laid on the circuit board to form an isolation shielding layer;

[0010] The isolation material is removed at the positions of the gate and source on the upper surface of each transistor chip to form a gate outlet and a source outlet on the isolation shielding layer;

[0011] After forming the gate through-hole and the source through-hole, a copper pouring process is performed on the isolation shield layer to arrange lines for the gate, source and drain ports of each transistor chip according to the preset dual half-bridge circuit connection scheme, thereby forming a dual half-bridge circuit.

[0012] An insulating material is laid on top of the dual half-bridge circuit to form a module encapsulation layer, thus obtaining the dual half-bridge circuit module.

[0013] According to some embodiments of this application, the transistor chip includes an internal circuit chip, the drain port includes an internal drain port, and the substrate chip socket includes an internal chip socket. For each transistor chip, mounting the lower surface of the transistor chip onto the corresponding substrate chip socket, so that the drain of each transistor chip is electrically connected to the circuit substrate to form a drain port, includes:

[0014] For each of the aforementioned internal circuit chips, the lower surface of the internal circuit chip is fixed to the corresponding internal chip socket using conductive silver paste, and the conductive medium formed after the conductive silver paste is cured serves as the internal drain port.

[0015] According to some embodiments of this application, the transistor chip includes an external circuit chip, the drain port includes an external drain port, the substrate chip socket includes an external chip socket, and for each transistor chip, the lower surface of the transistor chip is mounted on the corresponding substrate chip socket so that the drain of each transistor chip is electrically connected to the circuit substrate to form a drain port, including:

[0016] For each of the aforementioned external circuit chips, the lower surface of the external circuit chip is fixed to the corresponding external chip socket using conductive silver paste; wherein, the circuit substrate has an external drain trace pre-embedded in the external chip socket, and the drain of the external circuit chip is connected to the external chip socket through conductive silver paste, and the external drain port is formed by leading out from the external drain trace.

[0017] According to some embodiments of this application, the step of laying insulating material on the circuit board to form an isolation shielding layer includes:

[0018] After mounting the lower surface of each transistor chip onto the corresponding substrate chip holder, the drop distance between each transistor chip and the circuit substrate is determined.

[0019] The drop distance is determined as the reference thickness of the isolation layer;

[0020] Based on the reference thickness of the isolation layer, insulating material is laid on the circuit board to form the isolation shielding layer.

[0021] According to some embodiments of this application, prior to forming the isolation shielding layer, the method further includes:

[0022] For each transistor chip disposed on the substrate chip holder, the position is calibrated based on the gate and source of each transistor chip to obtain multiple window opening orientations;

[0023] The step of removing the isolation material at the positions corresponding to the gate and source on the upper surface of each transistor chip to form a gate outlet and a source outlet on the isolation shielding layer includes:

[0024] Windows are opened on the isolation shielding layer based on the multiple window opening orientations to form corresponding gate through-holes and source through-holes.

[0025] According to some embodiments of this application, after forming the gate pass-through and the source pass-through, a copper plating process is performed above the isolation shielding layer to arrange lines for the gate, source, and drain ports of each transistor chip according to a preset dual half-bridge circuit connection scheme, thereby forming a dual half-bridge circuit, including:

[0026] A copper integral coating layer is laid on top of the aforementioned isolation and shielding layer;

[0027] According to the dual half-bridge circuit connection scheme, the copper overall coating layer is etched to arrange lines at the gate, source and drain ports of each transistor chip to form the dual half-bridge circuit.

[0028] According to some embodiments of this application, the etching operation of the copper monolithic coating layer according to the dual half-bridge circuit connection scheme to arrange lines at the gate, source, and drain ports of each transistor chip to form the dual half-bridge circuit includes:

[0029] According to the dual half-bridge circuit connection scheme, the copper overall coating layer is subjected to a trace etching operation to form a dual half-bridge circuit layout.

[0030] Pin etching is performed on the gate through-hole and the source through-hole to form a conductive copper pillar at the gate through-hole that connects the dual half-bridge circuit layout and each gate as a gate pin, and a conductive copper pillar at the source through-hole that connects the dual half-bridge circuit layout and each source as a source pin.

[0031] The dual half-bridge circuit is determined based on the dual half-bridge circuit layout, the gate pin, and the source pin.

[0032] According to some embodiments of this application, each transistor chip is covered with an aluminum-copper coating at the gate and source positions. The step of performing pin etching operations on the gate and source exit points to form conductive copper pillars at the gate exit point, connecting the dual half-bridge circuit layout and each gate as gate pins, and forming conductive copper pillars at the source exit point, connecting the dual half-bridge circuit layout and each source as source pins, includes:

[0033] A pin etching operation is performed on the gate through-hole and the source through-hole to form the gate pin at the gate through-hole and the source pin at the source through-hole;

[0034] A gap-filling operation is performed based on the gate through-hole and the source through-hole to transform the aluminum-copper coating into a conductive auxiliary medium; wherein the conductive auxiliary medium is used to fill the contact gap between the gate pin and each gate, and the contact gap between the source pin and each source.

[0035] According to some embodiments of this application, after forming the gate pass-through and the source pass-through, a copper plating process is performed above the isolation shielding layer to arrange lines for the gate, source, and drain ports of each transistor chip according to a preset dual half-bridge circuit connection scheme, thereby forming a dual half-bridge circuit, including:

[0036] Obtain various types of pin location requirements;

[0037] From the dual half-bridge circuit connection scheme, extract the hierarchical connection scheme that matches the requirements of each pin position;

[0038] A target layer connection scheme is determined from multiple layer connection schemes, and lines are arranged for the gate, source and drain ports of each transistor chip based on the target layer connection scheme to form the dual half-bridge circuit that meets one of the pin position requirements.

[0039] After forming the dual half-bridge circuit that meets one of the pin position requirements, the isolation shielding layer is laid on top of the dual half-bridge circuit.

[0040] After the isolation shielding layer is laid on top of the dual half-bridge circuit, the target layer connection scheme is re-determined in the layered connection scheme that was never selected before. Based on the re-determined target layer connection scheme, the lines are arranged for the gate, source, and drain ports of each transistor chip to form a dual half-bridge circuit that meets another pin position requirement, until the dual half-bridge circuit corresponding to each pin position requirement is formed; wherein, the isolation shielding layer fills the gaps between different dual half-bridge circuits.

[0041] The dual half-bridge circuit module according to the embodiments of this application is obtained by the packaging method described in any one of the embodiments of this application.

[0042] The dual half-bridge circuit module packaging method and the dual half-bridge circuit module according to the embodiments of this application have at least the following beneficial effects:

[0043] According to the dual half-bridge circuit module packaging method of this application embodiment, multiple transistor chips and a circuit substrate are first obtained. The drain of each transistor chip is located on its lower surface, and the gate and source of each transistor chip are located on its upper surface. The circuit substrate has multiple substrate chip mounts. For each transistor chip, its lower surface is mounted on the corresponding substrate chip mount, so that the drain of each transistor chip is electrically connected to the circuit substrate, forming a drain port. After mounting the transistor chips, an insulating material is laid on the circuit substrate to form an isolation shielding layer. The insulating material is removed from the positions corresponding to the gate and source on the upper surface of each transistor chip to form a gate through-hole and a source through-hole on the isolation shielding layer. After forming the gate through-hole and source through-hole, a copper plating process is performed above the isolation shielding layer to arrange lines for the gate, source, and drain ports of each transistor chip according to a preset dual half-bridge circuit connection scheme, forming a dual half-bridge circuit. An insulating material is laid on top of the dual half-bridge circuit to form a module packaging layer, resulting in a dual half-bridge circuit module. This method helps to miniaturize electronic devices with good performance.

[0044] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0045] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0046] Figure 1 A flowchart illustrating the dual half-bridge circuit module packaging method provided in this application embodiment;

[0047] Figure 2 This is another schematic flowchart of the dual half-bridge circuit module packaging method provided in the embodiments of this application;

[0048] Figure 3 This is another schematic flowchart of the dual half-bridge circuit module packaging method provided in the embodiments of this application;

[0049] Figure 4 This is another schematic flowchart of the dual half-bridge circuit module packaging method provided in the embodiments of this application;

[0050] Figure 5 This is another schematic flowchart of the dual half-bridge circuit module packaging method provided in the embodiments of this application;

[0051] Figure 6 This is another schematic flowchart of the dual half-bridge circuit module packaging method provided in the embodiments of this application;

[0052] Figure 7 This is another schematic flowchart of the dual half-bridge circuit module packaging method provided in the embodiments of this application;

[0053] Figure 8 A schematic diagram of the logic circuit of the dual half-bridge circuit provided in the embodiments of this application;

[0054] Figure 9 A side sectional view of the dual half-bridge circuit module provided in an embodiment of this application;

[0055] Figure 10 A top sectional view of the dual half-bridge circuit module provided in an embodiment of this application;

[0056] Figure 11 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0057] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0058] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0059] In the description of this application, it should be understood that the orientation descriptions, such as up, down, left, right, front, and back, are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0061] In the description of this application, it should be noted that, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly. Those skilled in the art can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution. Furthermore, the identification of specific steps in the following text does not imply a limitation on the order of steps or execution logic. The execution order and logic between each step should be understood and inferred from the content described in the embodiments.

[0062] In the field of power electronics, the half-bridge circuit, as a fundamental and crucial topology, has long played a core role in applications such as PWM motor control, DC-AC inverters, and electronic ballasts. Its typical function is to realize the conversion and control of electrical energy, for example, by alternately turning on the high-side and low-side switches to generate the required AC or pulse waveform at the output.

[0063] The traditional approach involves mounting two separate metal-oxide-semiconductor field-effect transistors (MOSFETs, MOS) on a printed circuit board, and then connecting them to peripheral components such as a driver chip, capacitors, and inductors through PCB routing design to form a complete half-bridge functional module. This discrete construction method has been the industry standard practice for the past few decades, and its technology is mature with a stable supply chain.

[0064] However, this traditional approach based on discrete components and PCB routing has revealed several inherent technical problems in today's era of miniaturization, high power density, and low cost in electronic devices. The primary issue is its significant use of valuable PCB space. Each individual MOS device requires a separate package and surrounding clearance, resulting in a considerable area occupied by the entire half-bridge circuit on the board. In space-constrained applications, such as ultra-thin televisions, smartphone power management units, or compact drone ESCs, this layout becomes a bottleneck for further miniaturization of electronic devices. Simultaneously, the complex PCB routing itself requires space on multiple layers, increasing the difficulty and number of layers involved in routing, thereby driving up PCB manufacturing costs.

[0065] Secondly, traditional wire bonding technology has significant limitations in complex multi-chip interconnections. When attempting to integrate multiple MOS chips (e.g., forming a dual half-bridge or full-bridge) into a single package to save space, traditional frame-type packaging relies on tiny copper pillars, gold wires, or aluminum strips for electrical connections between the chips and pins. The physical space and pin arrangement of the package are fixed and very limited. As the number of chips increases or the internal interconnections become more complex, these wires are highly susceptible to crossing, contact, or even short circuits. Furthermore, complex interconnection requirements may prevent all pins of some chips from being brought out outside the package, limiting the functionality of the device and the flexibility of its applications. This "connection bottleneck" makes it exceptionally difficult to implement complex circuit topologies within a single small package.

[0066] Furthermore, from the perspective of system performance and reliability, traditional structures also have shortcomings. Longer PCB traces and leads introduce unnecessary parasitic inductance and resistance, which can lead to severe voltage overshoot, ringing, and switching losses in high-frequency switching applications. This not only reduces energy efficiency but may also generate electromagnetic interference, affecting the stability of the entire system. The dispersed layout of discrete components on the PCB is also detrimental to thermal management; heat cannot be concentrated and dissipated efficiently, potentially affecting the long-term reliability of the devices.

[0067] It is evident that the traditional method of constructing a half-bridge circuit using discrete MOS devices via PCB wiring results in a large system size and high cost. Furthermore, traditional packaging technologies, due to the physical limitations of interconnecting leads, cannot reliably and efficiently integrate multiple MOS chips within a miniaturized package to form complex circuit functions. These limitations collectively restrict further optimization of power electronic systems in terms of performance, size, and cost.

[0068] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a dual half-bridge circuit module packaging method and a dual half-bridge circuit module, which helps to miniaturize electronic devices with good performance.

[0069] The following explanation is based on the accompanying drawings.

[0070] Reference Figure 1 The dual half-bridge circuit module packaging method according to the embodiments of this application may include:

[0071] Step S101: Obtain multiple transistor chips and circuit substrates; wherein, the drain of each transistor chip is located on the lower surface of the transistor chip, and the gate and source of each transistor chip are located on the upper surface of the transistor chip, and the circuit substrate is provided with multiple substrate chip holders.

[0072] Step S102: For each transistor chip, the lower surface of the transistor chip is mounted on the corresponding substrate chip holder so that the drain of each transistor chip is electrically connected to the circuit board to form a drain port.

[0073] Step S103: After installing each transistor chip, an insulating material is laid on the circuit board to form an isolation shielding layer;

[0074] Step S104: Remove the isolation material at the positions of the gate and source on the upper surface of each transistor chip to form a gate through-hole and a source through-hole on the isolation shielding layer.

[0075] Step S105: After forming the gate through-hole and the source through-hole, a copper pouring process is performed on the isolation shield layer to arrange lines for the gate, source and drain ports of each transistor chip according to the preset dual half-bridge circuit connection scheme to form a dual half-bridge circuit.

[0076] Step S106: Lay insulating material on top of the dual half-bridge circuit to form a module encapsulation layer, thereby obtaining the dual half-bridge circuit module.

[0077] The complete process flow from steps S101 to S106 systematically solves the core problems faced by traditional discrete half-bridge circuits. This application first establishes a foundation for high integration by integrating multiple transistor chips onto the same circuit substrate and using their lower surface drains for electrical connection, directly reducing the space occupied by multiple independent packages. Subsequently, by laying an insulating layer and selectively opening windows, followed by copper plating, a complete dual half-bridge circuit function is directly constructed inside the package. This replaces the complex external PCB routing and problematic wire bonding of traditional solutions, significantly reducing system size and routing difficulty, and avoiding lead crossing issues. Finally, the modular packaging forms a robust and reliable independent device, greatly simplifying the design and assembly of end applications. The entire process achieves a balance between miniaturization, low cost, and high reliability by completing the most complex interconnections at the package level.

[0078] In step S101 of some embodiments, a plurality of transistor chips and a circuit substrate are obtained; wherein, the drain of each transistor chip is located on the lower surface of the transistor chip, the gate and source of each transistor chip are located on the upper surface of the transistor chip, and the circuit substrate is provided with a plurality of substrate chip seats.

[0079] It should be noted that this involves acquiring multiple transistor chips and a circuit board with pre-set chip mounts. The key here lies in the electrode distribution design of the transistor chips: the drain is located on the lower surface, while the gate and source are located on the upper surface. This structure lays the foundation for subsequent electrical connections. The chip mounts on the circuit board not only provide mechanical fixing points but also constitute part of the electrical connections.

[0080] As the active components of a circuit, the physical layout of the electrodes in a transistor chip is one of its key technical features. In these embodiments, the drain electrode of each transistor chip is located on the lower surface of the chip. Correspondingly, the gate and source electrodes, the control and output electrodes, are located on the upper surface of the chip. This electrode distribution design, which vertically separates the main power path (drain) from the control signal paths (gate and source) in space, provides the structural possibility for achieving high-density electrical interconnections in three-dimensional space. It determines that the current flow will be primarily vertical, rather than flowing laterally only on the chip surface.

[0081] The circuit board serves as the mechanical support framework for the entire module and a preliminary electrical interconnection platform. This board is not a flat surface but rather prefabricated with multiple specific "board chip mounts." These chip mounts are precisely machined areas on the board surface, their positions, shapes, and sizes precisely corresponding to the transistor chips to be mounted. They are essentially exposed connection points of the board's internal wiring network, and one of their core functions is to establish electrical connections with the drain electrode on the chip's underside.

[0082] When the lower surface of the chip is mounted onto the corresponding substrate chip socket, a strong mechanical fixation and low-resistance electrical connection are achieved between the two through processes such as conductive adhesive (e.g., conductive silver paste) or eutectic bonding. This operation allows the drains of all transistors to be connected through wiring inside the circuit board, thus initially forming a common or topologically connected drain network. This can be regarded as the first layer and the most basic electrical connection layer in the entire dual half-bridge circuit construction process.

[0083] In step S102 of some embodiments, for each transistor chip, the lower surface of the transistor chip is mounted on the corresponding substrate chip holder so that the drain of each transistor chip is electrically connected to the circuit board to form a drain port.

[0084] It's important to note that each transistor chip is mounted onto the circuit board. Specifically, this involves attaching the lower surface of the transistor chip to a corresponding chip mount pre-installed on the circuit board. This mounting action has a clear electrical purpose. Since the drain of the transistor chip is located on its lower surface, and the chip mount is part of the conductive path of the circuit board, when the lower surface of the chip contacts the chip mount, the transistor's drain establishes an electrical connection with the circuit board through this contact surface. This connection method replaces the lead connections that might be used in traditional packaging, achieving electrical conduction with a larger contact area and lower resistance.

[0085] Multiple transistor chips are precisely positioned and fixed onto the circuit board in this way, forming an ordered array. At this point, the circuit board not only provides mechanical support for the chips but also begins to play the role of electrical interconnection. The drains of all chips are connected to the metal traces inside the circuit board through their respective chip sockets on the board.

[0086] From a circuit function perspective, this installation step directly facilitates the formation of the drain port. A drain port refers to a shared or grouped electrical node on the drain of a transistor. This node is interconnected through wiring within the circuit board and ultimately leads to a specific pin on the package, becoming one of the module's external electrical interfaces. This process enables the interconnection of one end (the drain) of the main current path of the power device within the package, marking a crucial first step in building a complete half-bridge circuit.

[0087] Therefore, step S102 completes the transition from physical installation to electrical connection. Utilizing the structural characteristics of the drain on the lower surface of the chip, it achieves efficient and reliable electrical interconnection through the substrate chip socket. This not only optimizes electrical performance but also frees up space for subsequent wiring of the gate and source on the upper surface of the chip, making it a key step in achieving a compact and highly integrated module.

[0088] According to some embodiments of this application, the transistor chip includes an internal circuit chip, the drain port includes an internal drain port, and the substrate chip socket includes an internal chip socket. Step S102, for each transistor chip, involves mounting the lower surface of the transistor chip onto the corresponding substrate chip socket to electrically connect the drain of each transistor chip to the circuit board, forming a drain port. This step may include:

[0089] For each internal chip in the circuit, the lower surface of the internal chip is fixed to the corresponding internal chip socket with conductive silver paste, and the conductive medium formed after the conductive silver paste is cured is used as the internal drain port.

[0090] It should be noted that for a type of transistor chip used as an internal circuit chip, its drain is used to connect to other components within the module. These chips are mounted onto corresponding internal chip mounts. During mounting, conductive silver paste is used to fix the lower surface of the chip to the surface of the internal chip mount, and then a curing process is used to harden the silver paste. The solid conductive medium formed after curing not only provides mechanical adhesion but also directly establishes a reliable electrical connection between the chip drain and the circuit board; this connection point itself constitutes the internal drain port. This process achieves integrated design between the chip and the internal circuitry of the substrate.

[0091] According to some embodiments of this application, the transistor chip includes an external circuit chip, the drain port includes an external drain port, and the substrate chip socket includes an external chip socket. Step S102, for each transistor chip, involves mounting the lower surface of the transistor chip onto the corresponding substrate chip socket to electrically connect the drain of each transistor chip to the circuit board, forming a drain port. This step may include:

[0092] For each external chip in the circuit, the lower surface of the external chip is fixed to the corresponding external chip socket using conductive silver paste. The circuit board is pre-embedded with external drain traces for the external chip socket. The drain of the external chip is connected to the external chip socket through conductive silver paste, and the external drain port is formed by leading out from the external drain traces.

[0093] It should be noted that for another type of transistor chip used as an external circuit chip, its drain needs to serve as an external connection port for the entire module. These chips are mounted on external chip sockets, and although they are also fixed using conductive silver paste, their substrate structure differs. The circuit board pre-embeds dedicated "external drain traces" for these external chip sockets. After the chip is fixed to the external chip socket with conductive silver paste, its drain's electrical signal is connected to the socket and immediately conducted to the pre-defined external drain trace. This trace is independent of other circuits within the module, extending directly to the pins of the module's outer casing, thus forming a dedicated external drain port.

[0094] It should be understood that the differentiated connection strategy reflects design considerations. The embodiments of this application can more flexibly and optimally construct complex internal circuit topologies by distinguishing transistor chips into internal and external circuit chips and planning different electrical paths for them during the substrate design and installation stages. This ensures the compactness of internal connections while providing dedicated, higher-performance output channels for signals that need to interact with external systems. This guarantees both the efficiency of the internal integration of the dual half-bridge circuit module and meets the requirement for reliable connection of the dual half-bridge circuit module as an independent device to external systems.

[0095] In step S103 of some embodiments, after each transistor chip is installed, an insulating material is laid on the circuit board to form an isolation shielding layer;

[0096] It's important to note that an insulating material is laid across the entire surface of the circuit board to form an isolation shield. The primary purpose of this step is to achieve electrical isolation. After the chips are mounted, the circuit board surface contains conductive areas such as connected transistor chips, exposed metal traces, and chip mounts. Directly routing metal traces over these areas would cause short circuits between conductors at different potentials. The insulating material effectively separates all existing conductive structures from the subsequent conductive layer, preventing accidental electrical connections.

[0097] Structurally, this insulating material forms a continuous and complete cover layer. It is not selectively applied, but rather evenly distributed over the entire area, including the chip and substrate. This ensures complete insulation, eliminating any uncovered gaps and providing a smooth and stable working surface for subsequent processes. The thickness and dielectric strength of this layer need to be carefully selected to ensure it can withstand potential differences that may occur during circuit operation.

[0098] In addition, this insulating shielding layer also serves a physical protection function. It can fix and encase the underlying transistor chips and precision circuit boards, protecting them from physical damage or contamination that may occur during subsequent processing steps (such as copper pouring and etching). At the same time, it also initially enhances the mechanical strength of the entire module.

[0099] Therefore, the isolation shielding layer constructed in step S103 plays a crucial role in the packaging structure, acting as a bridge between the upper and lower layers. It encapsulates and protects the drain connection network while simultaneously facilitating the safe construction of a new conductive layer above, namely the copper wiring connecting the gate and source.

[0100] Reference Figure 2 According to some embodiments of this application, step S103, which involves laying an insulating material on the circuit board to form an isolation shielding layer, may include:

[0101] Step S201: After mounting the lower surface of each transistor chip onto the corresponding substrate chip holder for each transistor chip, determine the drop distance between each transistor chip and the circuit substrate.

[0102] Step S202: Determine the drop distance as the reference thickness of the isolation layer;

[0103] Step S203: Based on the reference thickness of the isolation layer, an insulating material is laid on the circuit board to form an isolation shielding layer.

[0104] In step S201 of some embodiments, after mounting the lower surface of each transistor chip on the corresponding substrate chip holder, the drop distance between each transistor chip and the circuit board is determined.

[0105] It is important to note that after all transistor chips are installed, the maximum vertical height difference between the top surface of each transistor chip and the reference plane of the circuit board needs to be precisely measured, i.e., the drop distance. This measurement process needs to take into account the chip's own thickness tolerance, the difference in the thickness of the conductive silver paste, and the minute height changes that may occur during installation. By acquiring this data, the process system can fully understand the actual morphological characteristics of the package structure in three-dimensional space.

[0106] In step S202 of some embodiments, the drop distance is determined as the reference thickness of the isolation layer;

[0107] It should be noted that, in this embodiment, the measured drop distance is used as the reference thickness for the insulating layer. This step aims to ensure the absolute reliability of the electrical insulation; the insulating shield must be able to completely cover the highest point in the entire structure. Therefore, selecting the drop distance as the reference thickness ensures that the insulating material provides a sufficiently thick cover even at the most prominent location in the structure. This method of determination considers both the complexity of the actual structure and provides clear technical indicators for process implementation.

[0108] In some embodiments, step S203 involves laying an insulating material on the circuit board based on the reference thickness of the isolation layer to form an isolation shielding layer.

[0109] It should be noted that the laying of insulating material will follow the determined reference thickness of the isolation layer so that the insulating material can completely fill all gaps between the chip sidewall and the substrate, eliminating any possible uncovered areas; secondly, the uniform thickness distribution provides an ideal working plane for subsequent photolithography processes, avoiding photolithography defects caused by surface unevenness; finally, the appropriate thickness ensures that the isolation shielding layer has sufficient dielectric strength to withstand the potential difference generated during circuit operation.

[0110] As can be seen, the thickness control based on measured data in this embodiment reflects the shift in packaging technology from experience-based operation to precise control. Through real-time measurement and feedback, this embodiment can adapt to the natural fluctuations in materials and process parameters from different batches, ensuring that each packaged module receives high-quality insulation protection and improving product reliability.

[0111] In step S104 of some embodiments, the isolation material is removed for the positions of the gate and source on the upper surface of each transistor chip to form a gate through-hole and a source through-hole on the isolation shielding layer.

[0112] It should be noted that after the isolation shielding layer is laid, the packaging process proceeds to step S104. The goal of this step is to create precise electrical contact windows for the gate and source electrodes of each transistor chip on the newly formed, complete insulating layer.

[0113] The specific operation involves selectively removing the insulating material covering the gate and source electrodes on the surface of each transistor chip. This process requires extremely high positioning precision. It must be precisely aligned with the tiny metal pads on the chip surface to ensure that while removing the insulating material, the underlying gate and source electrodes are fully exposed without damaging the surrounding areas that need to be kept insulated.

[0114] The techniques used to achieve this selective removal are typically photolithography and etching processes. First, photoresist is coated onto the insulating layer, and then exposed using a pre-designed photomask with a pattern corresponding to all electrode positions. After development, the photoresist in the areas requiring windowing is removed, exposing the insulating material in these areas. Subsequently, dry or wet etching is used to completely remove this exposed insulating material, thus forming a series of regular holes on the continuous isolation shielding layer—the gate and source apertures.

[0115] The formation of these through-holes breaks the electrical isolation created by the insulating shield. They establish microscopic channels from the space above the insulating layer to the critical functional electrodes (gate and source) of the transistor below. This is absolutely necessary for subsequent electrical interconnection. Without these through-holes, even with copper pillars laid on top, it would be impossible to form an effective current path with the chip's electrodes.

[0116] Therefore, step S104 is a crucial patterning step. It transforms a uniform insulating layer into a functional dielectric layer with specific via patterns. This step directly determines whether the upper metal wiring can accurately achieve a reliable point-to-point connection with the lower transistor electrodes, laying a precise foundation for the next step of directly constructing a complete dual half-bridge circuit wiring inside the package.

[0117] Reference Figure 3 According to some embodiments of this application, before forming the isolation shielding layer, it may further include:

[0118] Step S301: For each transistor chip set on the substrate chip holder, position calibration is performed based on the gate and source of each transistor chip to obtain multiple window opening orientations;

[0119] In step S104, removing the isolation material at the positions corresponding to the gate and source on the upper surface of each transistor chip to form a gate through-hole and a source through-hole on the isolation shield layer may include:

[0120] Step S302: Based on the multiple window opening orientations, windows are opened on the isolation shielding layer to form corresponding gate through-holes and source through-holes.

[0121] In step S301 of some embodiments, for each transistor chip disposed on the substrate chip holder, position calibration is performed based on the gate and source of each transistor chip to obtain multiple window opening orientations;

[0122] It should be noted that precise spatial coordinate acquisition is performed on each transistor chip fixed to the substrate chip socket. This process can employ a high-precision optical vision system, using multi-angle imaging and pattern recognition technology to determine the precise positions of the gate and source pads on each transistor chip within the substrate coordinate system. In this embodiment, the planar coordinates (X, Y) and relative height (Z) of each pad are recorded, forming a complete set of spatial position data. This data includes not only the coordinates of the pad's center point but also information such as the pad's shape, size, and azimuth angle, collectively constituting the "window opening orientation" database required for subsequent processes.

[0123] This positioning calibration process needs to consider various practical factors. Due to the potential for minute displacement or rotation of the chip during installation, and the possible deformation of the substrate itself during high-temperature processing, the actual position may deviate from the designed position. Therefore, this calibration process is essentially a real-time position compensation mechanism that can correct these accumulated process errors, ensuring that the subsequent window opening position perfectly matches the actual chip position. The embodiments of this application can perform statistical analysis on the collected position data to establish a position error model, providing a basis for process optimization in subsequent batch processing.

[0124] In step S302 of some embodiments, windows are opened on the isolation shielding layer based on multiple window opening orientations to form corresponding gate through-holes and source through-holes.

[0125] It should be noted that step S302 describes the process of converting the previously obtained window opening orientation data into actual processing instructions. In this process, the photolithography system reads coordinate information from the position database and drives the photolithography mask to perform precise positioning, ensuring that the window pattern on the mask is perfectly aligned with the actual electrode positions on the chip. This alignment accuracy typically needs to be controlled at the micrometer level to ensure that subsequent metallization processes can form reliable electrical connections.

[0126] It should be noted that the implementation of the windowing process requires comprehensive consideration of multiple technical parameters. Firstly, the window size must be controlled to ensure complete exposure of the underlying electrode pads while minimizing the removal of surrounding insulating material to maintain the structural integrity of the isolation shielding layer. Secondly, the sidewall morphology of the window needs to be controlled, requiring adjustment of etching parameters to obtain steep and smooth sidewalls, which is beneficial for the uniformity of subsequent metal coverage. Furthermore, attention must be paid to the consistency of etching rates in different areas to ensure uniform depth of all windows across the entire substrate.

[0127] It should be understood that this "calibrate-then-process" approach, by separating position measurement and windowing processing into two independent stages, effectively avoids the contamination and damage that may result from direct measurement on the completed insulation layer. Simultaneously, this separated process design allows for offline analysis and optimization of position data, improving process stability and repeatability. More importantly, this processing method based on measured data can effectively compensate for accumulated dimensional errors from previous processes, improving product yield and reliability.

[0128] The entire process of position calibration and precise windowing reflects the trend of modern semiconductor packaging technology towards data-driven and intelligent manufacturing. By establishing a precise digital position model and corresponding process compensation mechanism, the embodiments of this application can adapt to the inevitable dimensional fluctuations in mass production, so that the packaged modules can all meet the accuracy standards required by the design.

[0129] In step S105 of some embodiments, after forming the gate through-hole and the source through-hole, a copper pouring process is performed on the isolation shield layer to arrange lines for the gate, source and drain ports of each transistor chip according to a preset dual half-bridge circuit connection scheme to form a dual half-bridge circuit.

[0130] It should be noted that after the gate and source transparent exits on the isolation shielding layer are fabricated, the process proceeds to step S105. The core of this step is to perform a copper pouring process on the patterned insulating layer to form a functional circuit.

[0131] The copper plating process begins by depositing a continuous layer of copper across the entire structure surface. This copper layer covers the upper surface of the isolation shielding layer and simultaneously fills each of the previously formed gate and source through-holes, establishing a strong electrical contact with the corresponding chip electrodes below. Subsequently, using patterning techniques such as photolithography and etching, this complete copper film is etched according to a pre-defined pattern to remove unwanted portions.

[0132] The remaining copper pillars form the intricate internal wiring. The connections between these wires are not arbitrary but must follow a pre-defined dual half-bridge circuit connection scheme. This scheme defines how to interconnect the gates, sources, and drains of four (or more) transistor chips, already connected via the substrate, into two fully functional half-bridge circuits. This means that the copper pillars formed after the copper plating needs to electrically connect the source of one transistor to the drain of another to form the output point of the half-bridge, and lead each gate to a control pin, while also establishing power and ground paths.

[0133] This step is crucial for achieving circuit functional integration. It connects multiple independent transistor chips through internal copper wiring into a complex circuit functional module with a specific topology—a dual half-bridge circuit. At this point, the main current and signal paths of the circuit have been constructed within the package, and its functionality is essentially achieved.

[0134] Therefore, step S105 essentially completes the wiring work that traditionally needs to be done on the printed circuit board at the packaging level. The advantage of this internal wiring is that the connection path can be shorter, the wiring density can be higher, and it avoids problems such as wire arc crossing and excessive parasitic parameters that may be encountered when using traditional wire bonding. It directly utilizes the planar copper layer to achieve high-efficiency and high-reliability electrical interconnection, which is the core link that enables the final module to achieve miniaturization and high performance.

[0135] Reference Figure 4 According to some embodiments of this application, after forming the gate and source exit points in step S105, a copper plating process is performed above the isolation shielding layer to arrange lines for the gate, source, and drain ports of each transistor chip according to a preset dual half-bridge circuit connection scheme, thereby forming a dual half-bridge circuit. This may include:

[0136] Step S401: Lay a copper integral coating layer on top of the isolation shielding layer;

[0137] In step S402, according to the dual half-bridge circuit connection scheme, the copper overall coating layer is etched to arrange lines on the gate, source and drain ports of each transistor chip to form a dual half-bridge circuit.

[0138] In some embodiments, step S401 involves laying a copper monolithic coating layer over the isolation shielding layer;

[0139] It should be noted that a continuous copper monolithic coating is laid on top of the entire isolation shielding layer. This process typically employs electroplating or chemical deposition to uniformly cover the surface of the insulating layer with metallic copper, simultaneously filling all previously formed gate and source through-holes. This copper film establishes direct metal-to-metal contact with the exposed chip electrodes beneath, forming an initial electrical connection. The thickness of the copper layer needs precise control to ensure sufficient current carrying capacity while also meeting the requirements of subsequent fine etching processes.

[0140] In step S402 of some embodiments, the copper overall coating layer is etched according to the dual half-bridge circuit connection scheme to arrange lines at the gate, source and drain ports of each transistor chip to form a dual half-bridge circuit.

[0141] It should be noted that after the overall copper plating is completed, patterning is performed according to the circuit design. This step requires selective etching of the complete copper coating layer according to the preset dual half-bridge circuit connection scheme. First, photoresist is coated on the copper layer surface, and then exposed through a pre-fabricated photomask containing the circuit pattern. After exposure, the photoresist is developed to expose the copper areas that need to be removed, and then the copper material in these areas is completely removed by chemical etching or dry etching.

[0142] Furthermore, the copper pillars retained after etching form a sophisticated internal circuit network. These copper pillars, according to design requirements, interconnect the gates, sources, and drain ports of each transistor chip connected via the substrate, forming a complete dual half-bridge circuit topology. The width, spacing, and orientation of each copper pillar must strictly comply with electrical performance requirements to ensure it can carry the corresponding current and provide stable signal transmission.

[0143] This process, which involves overall copper plating followed by selective etching, allows for complex, high-density wiring within a two-dimensional plane compared to traditional wire bonding techniques. It avoids the crosstalk and parasitic parameter issues that can arise with three-dimensional leads. Furthermore, planar copper pillars offer superior current carrying capacity and heat dissipation compared to traditional circular leads, contributing to improved circuit reliability and power density.

[0144] Reference Figure 5 According to some embodiments of this application, in accordance with a dual half-bridge circuit connection scheme, an etching operation is performed on the copper overall coating layer to arrange lines at the gate, source, and drain ports of each transistor chip to form a dual half-bridge circuit, which may include:

[0145] Step S501: According to the dual half-bridge circuit connection scheme, the copper overall coating layer is etched to form a dual half-bridge circuit layout.

[0146] Step S502: Perform pin etching operation on the gate through-hole and the source through-hole to form a conductive copper pillar connecting the dual half-bridge circuit layout and each gate as a gate pin in the gate through-hole, and form a conductive copper pillar connecting the dual half-bridge circuit layout and each source as a source pin in the source through-hole.

[0147] Step S503: Determine the dual half-bridge circuit based on the dual half-bridge circuit layout, gate pins, and source pins.

[0148] In step S501 of some embodiments, according to the dual half-bridge circuit connection scheme, the copper overall coating layer is subjected to a trace etching operation to form a dual half-bridge circuit layout.

[0149] It should be noted that, according to the pre-designed dual half-bridge circuit connection scheme, the overall copper coating layer is patterned. This process employs photolithography, transferring the circuit design to the copper surface using a photomask with a specific pattern: first, photoresist is coated onto the copper layer; after exposure and development, the areas where the circuitry needs to be retained are protected by the photoresist, while the areas where the copper material needs to be removed are exposed. Subsequently, techniques such as chemical etching or plasma etching are used to completely remove the unprotected copper layer, ultimately forming a precise circuit trace pattern on the insulating layer surface. These traces constitute the current path and signal transmission backbone network of the dual half-bridge circuit.

[0150] In step S502 of some embodiments, pin etching operations are performed on the gate through-hole and the source through-hole to form a conductive copper pillar connecting the dual half-bridge circuit layout and each gate as a gate pin in the gate through-hole, and a conductive copper pillar connecting the dual half-bridge circuit layout and each source as a source pin in the source through-hole.

[0151] It should be noted that the formation of the vertical interconnect structure and the planar wiring in step S501 form a three-dimensional connection. After the main circuit wiring is completed, a secondary etching operation is required specifically for the gate and source through-hole areas. This process requires precise control of the etching depth to ensure that the copper material filling the through-hole is retained while removing the surface copper layer. These retained copper pillars connect upwards to the planar lines formed in step S501 and directly contact the chip electrode surface downwards, thus forming a vertical electrical channel. These conductive copper pillars serve as gate and source pins, respectively; they are both structural supports and current conduction paths, achieving a reliable connection between the two-dimensional planar wiring and the three-dimensional electrode structure.

[0152] Reference Figure 6According to some embodiments of this application, each transistor chip is covered with an aluminum-copper coating at the gate and source positions. Step S502 performs pin etching operations on the gate and source exits to form conductive copper pillars connecting the dual half-bridge circuit layout and each gate as gate pins at the gate exit, and conductive copper pillars connecting the dual half-bridge circuit layout and each source as source pins at the source exit. This may include:

[0153] Step S601: Perform pin etching operation on the gate through-hole and the source through-hole to form a gate pin at the gate through-hole and a source pin at the source through-hole.

[0154] Step S602: A gap filling operation is performed based on the gate through-hole and the source through-hole to convert the aluminum-copper coating into a conductive auxiliary medium; wherein the conductive auxiliary medium is used to fill the contact gap between the gate pin and each gate, and the contact gap between the source pin and each source.

[0155] In some embodiments, step S601 involves performing pin etching operations on the gate through-hole and the source through-hole to form a gate pin at the gate through-hole and a source pin at the source through-hole.

[0156] It should be noted that on the substrate where overall copper plating and main circuit etching have been completed, a fine etching operation is specifically performed on the gate and source through-hole areas. This operation requires precise control of etching parameters to ensure that while removing excess copper layer on the surface, the copper material filling the through-hole is retained, forming a vertical conductive structure that directly contacts the underlying aluminum-copper coating. These retained copper pillars constitute the gate and source pins, respectively, connecting upwards to the planar traces of the dual half-bridge circuit layout and extending downwards to the chip electrode surface.

[0157] In some embodiments, step S602 involves a gap-filling operation based on the gate pass-through and source pass-through to convert the aluminum-copper coating into a conductive auxiliary medium; wherein the conductive auxiliary medium is used to fill the contact gap between the gate pins and each gate, and the contact gap between the source pins and each source.

[0158] It should be noted that due to microscopic surface irregularities and lattice mismatches between the aluminum-copper coating on the chip electrode surface and the copper lead material, contact gaps may form between them. This step involves gap filling, utilizing the material properties of the aluminum-copper coating to induce controlled interfacial diffusion and metallurgical reactions under specific process conditions. This transformation process converts the aluminum-copper coating from a simple electrode plating layer into a conductive auxiliary medium with bridging capabilities.

[0159] This material conversion process typically requires controlled heat treatment conditions. When the temperature reaches the aluminum-copper eutectic point, the aluminum-copper alloy at the interface undergoes localized liquefaction and fills the contact gap, subsequently forming a dense intermetallic compound layer with the copper leads during cooling. This metallurgical bonding significantly increases the effective contact area, reduces interfacial contact resistance, and simultaneously improves mechanical connection strength. The resulting conductive auxiliary medium not only fills the microscopic voids but also establishes a reliable metallic bonding interface.

[0160] This application's embodiments effectively solve common contact reliability problems in power devices through material-level interface engineering. The formation of a conductive auxiliary dielectric ensures a smooth current transition from the chip electrodes to the package pins, reducing the risk of localized hot spots. Simultaneously, this metallurgical bonding method can adapt to thermal stress changes caused by power cycling, improving the reliability of the package structure under long-term operating conditions.

[0161] In some embodiments, step S503 determines the dual half-bridge circuit based on the dual half-bridge circuit layout, gate pins, and source pins.

[0162] It should be noted that circuit integrity verification is performed based on the established dual half-bridge circuit layout, gate pins, and source pins. This process includes checking circuit connectivity, verifying that the gate and source of each transistor are correctly connected to the circuitry through the corresponding pins, and confirming that each drain port forms the predetermined topology through the in-substrate wiring and planar routing. Furthermore, it is necessary to check whether the line spacing meets electrical safety standards, assess whether the current carrying capacity meets design requirements, and ensure that the final circuit structure fully complies with the functional specifications of the dual half-bridge circuit.

[0163] It should be understood that this step-by-step etching process design embodies a modular manufacturing mindset. By breaking down the complex circuit forming process into two relatively independent process stages—planar routing and vertical interconnects—it reduces the complexity of one-time pattern transfer while improving manufacturing flexibility and reliability. Planar routing etching focuses on optimizing the layout efficiency of current paths, while vertical pin etching ensures the stability of electrode connections. The synergy between the two ensures comprehensive optimization of the final circuit in terms of electrical performance, thermal performance, and reliability. This refined process decomposition provides an effective technical path for the manufacturing of high-density power modules.

[0164] Reference Figure 7 According to some embodiments of this application, after forming the gate and source exit points in step S105, a copper plating process is performed above the isolation shielding layer to arrange lines for the gate, source, and drain ports of each transistor chip according to a preset dual half-bridge circuit connection scheme, thereby forming a dual half-bridge circuit. This may include:

[0165] Step S701: Obtain the pin position requirements for various types;

[0166] Step S702: Extract the hierarchical connection scheme that matches the requirements of each pin position from the dual half-bridge circuit connection scheme.

[0167] Step S703: Determine the target layer connection scheme from multiple layer connection schemes, and arrange the lines for the gate, source and drain ports of each transistor chip based on the target layer connection scheme to form a dual half-bridge circuit that meets one of the pin position requirements.

[0168] Step S704: After forming a dual half-bridge circuit that meets one of the pin position requirements, an isolation shielding layer is laid on top of the dual half-bridge circuit.

[0169] In step S705, after laying an isolation shielding layer on top of the dual half-bridge circuit, the process returns to the previously unselected layered connection scheme to redetermine the target layer connection scheme. Based on the redetermined target layer connection scheme, the circuits are arranged for the gate, source, and drain ports of each transistor chip to form a dual half-bridge circuit that meets another pin position requirement, until the dual half-bridge circuit corresponding to each pin position requirement is formed. The different dual half-bridge circuits are filled with an isolation shielding layer.

[0170] In some embodiments, step S701 involves obtaining various types of pin location requirements;

[0171] It's important to note that the primary task of the requirements gathering phase is to identify the specific requirements for the pin positions of the half-bridge circuit module. These requirements may include differences in pin spacing, arrangement order, and the location distribution of specific functional pins. This step establishes a comprehensive requirements database by investigating application scenarios and circuit board design specifications. This process requires full consideration of mechanical installation limitations, thermal design requirements, and electrical connection characteristics under different application scenarios, laying the foundation for the subsequent realization of diverse outputs from standardized modules.

[0172] In some embodiments, step S702 involves extracting a hierarchical connection scheme from the dual half-bridge circuit connection scheme that matches the requirements of each pin position.

[0173] It should be noted that a unified dual half-bridge circuit connection scheme is broken down into routing schemes adapted to different pin requirements. Although the electrical connection logic of all schemes remains consistent, at the physical implementation level, corresponding routing paths need to be designed for different pin positions. This process requires consideration of signal integrity, power integrity, and optimization of heat conduction paths to ensure that each layered connection scheme can meet specific pin arrangements while guaranteeing optimal circuit performance.

[0174] In some embodiments, step S703 involves determining a target layer connection scheme from multiple layer connection schemes, and arranging lines for the gate, source, and drain ports of each transistor chip based on the target layer connection scheme to form a dual half-bridge circuit that meets one of the pin position requirements.

[0175] It should be noted that one of several layered solutions was selected as the current implementation target. Based on the selected layered interconnection scheme, precise copper traces were laid out on the substrate surface to form the first dual half-bridge circuit that meets the specific pin requirements. This process requires strict control of parameters such as trace width, trace spacing, and copper thickness to ensure the circuit can handle the expected current load. Simultaneously, the routing path needs to be optimized to reduce parasitic parameters and guarantee high-frequency performance.

[0176] In step S704 of some embodiments, after forming a dual half-bridge circuit that meets one of the pin position requirements, an isolation shielding layer is laid on top of the dual half-bridge circuit.

[0177] It should be noted that after the first layer of circuitry is constructed, a new insulating shielding layer is laid on top of the entire circuit. This insulating material needs to possess good dielectric properties, thermal conductivity, and mechanical strength. During the laying process, it is essential to ensure that the material completely covers the underlying circuitry, forming a uniform insulation thickness, while maintaining surface flatness to provide an ideal base plane for the construction of subsequent circuit layers.

[0178] In some embodiments, step S705 involves laying an isolation shielding layer above the dual half-bridge circuit, then returning to the previously unselected layered connection scheme to redetermine the target layer connection scheme, and arranging lines for the gate, source, and drain ports of each transistor chip based on the redetermined target layer connection scheme to form a dual half-bridge circuit that meets another pin position requirement, until the dual half-bridge circuit corresponding to each pin position requirement is formed; wherein, the different dual half-bridge circuits are filled with an isolation shielding layer.

[0179] It should be noted that multi-layered circuits are stacked by iteratively executing the processes of scheme selection, circuit construction, and insulating layer placement. Each iteration selects a new target scheme from the remaining layered connection schemes, constructing a circuit on a new insulating layer that meets a different pin requirement. This iterative process continues until all different types of pin location requirements are satisfied, ultimately forming an integrated package module containing multiple independent circuit layers.

[0180] It should be understood that this multi-layered iterative construction method achieves a balance between standardization and customization. By integrating multiple circuit layers within a single package, diverse needs can be met while maintaining the consistency of the core chipset. This design significantly improves production flexibility, reduces development costs, and effectively lowers material costs because each circuit layer shares the same substrate and chip resources. The entire process embodies the advanced concept of modular design, providing a new technological path for power semiconductor packaging.

[0181] In some embodiments, step S106 involves laying an insulating material over the dual half-bridge circuit to form a module encapsulation layer, thereby obtaining a dual half-bridge circuit module.

[0182] It should be noted that after all the wiring of the internal circuitry is completed, the packaging process proceeds to step S106. This step involves laying insulating material on top of the constructed dual half-bridge circuit to form the final module encapsulation layer.

[0183] The primary function of this step is to provide comprehensive environmental protection. The laid insulating encapsulation material completely covers and encapsulates the delicate copper wiring and transistor chips beneath, isolating them from the external environment. This effectively prevents moisture, dust, pollutants, and other chemicals in the air from corroding or damaging the circuitry, thereby significantly improving the module's long-term reliability and lifespan.

[0184] Secondly, this encapsulation layer provides crucial mechanical protection. Once cured, it forms a robust shell capable of withstanding external physical shocks, vibrations, and stresses. This protects the delicate internal copper pillars from damage and prevents the connection between the chip and the substrate from failing due to mechanical forces. Simultaneously, it tightly integrates all internal structures into a single, robust whole, enhancing the module's structural integrity.

[0185] From an electrical safety perspective, this insulating material is also crucial. As a reliable insulating barrier, it ensures that in the final application, the high-voltage and high-current conductors inside the module will not accidentally short-circuit with external systems or components such as heat sinks.

[0186] Therefore, the completion of step S106 marks the end of the manufacturing process for the dual half-bridge circuit module. After this step, a standalone, plug-and-play standard power module integrating multiple transistor chips and complex internal wiring is obtained. It is no longer a collection of discrete components and circuits, but a fully functional, robustly protected end product that can be directly used by downstream system designers.

[0187] The dual half-bridge circuit module according to the second aspect of this application is obtained by encapsulation using any one of the methods in the first aspect of this application.

[0188] Reference Figure 8 This illustrates a logic circuit for a dual half-bridge circuit. Figure 2 The study reveals a dual half-bridge topology integrated into a single package to achieve increased power conversion density through functional reuse and compact layout.

[0189] Figure 8 The left half-bridge uses VIN as the high-voltage bus input terminal. The drain of the high-side MOSFET is directly connected to this node. The gate drive signal is independently controlled by the HG1 port, and the source (Src) is led out to the externally detectable switching node SW1. The drain of the corresponding low-side MOSFET is shorted to SW1 to form the midpoint of the half-bridge. The gate receives the drive signal from the LG1 port, and the source is finally connected to GND to form a complete loop.

[0190] Figure 8 The right half-bridge follows a similar architecture, but its high-voltage side power input is labeled VOUT. The output of this half-bridge can serve as the power source for the next stage circuit, or it can be connected in parallel with VIN via PCB traces to form a unified bus. The high-side and low-side MOSFETs are independently driven by the HG2 and LG2 ports, respectively, corresponding to the SW2 switching node. This dual half-bridge configuration is electrically isolated but highly integrated physically, providing flexibility for package design.

[0191] It is worth noting that HG1 represents the gate drive signal input terminal of the high-side MOSFET of the left half-bridge, used to control the turn-on and turn-off of the upper MOSFET. VIN is the DC power input terminal of the left half-bridge, connected to the drain of the high-side MOSFET, providing the bus voltage. HG2 corresponds to the gate drive signal of the high-side MOSFET of the right half-bridge, which can independently control the upper MOSFET on the right. VOUT is the high-side drain connection terminal of the right half-bridge, and in external applications it is usually connected in parallel with VIN or used as a cascaded output node. The Drain symbol appears four times, corresponding to the drain regions of the four MOSFET devices. In the physical structure, the drain of the high-side MOSFET is connected to the frame through conductive silver paste to achieve electrical and thermal conduction. The Gate symbol represents the gate control terminal of the four MOSFETs, which are connected to the corresponding drive pins (HG1, HG2, LG1, LG2) through copper pillar interconnects inside the package to achieve independent control. The Src symbol represents the source region, where the source of the high-side MOSFET and the drain of the low-side MOSFET are shorted inside the package to form the switching node of the half-bridge. SW1 and SW2 are the switching node leads of the left and right half-bridges, connected to an external inductor or load. The voltage at these nodes switches between high and low levels during switching, and they are the core operating points for power conversion. LG1 and LG2 are the gate drive signals for the low-side MOSFETs of the left and right half-bridges, respectively, controlling the switching action of the lower MOSFETs. They work in conjunction with the corresponding high-side drive signals to achieve complementary or synchronous rectification operation. GND represents the ground terminal; the sources of the low-side MOSFETs of the two half-bridges share a common ground within the package, providing a return path for the current.

[0192] Reference Figure 9 The image shows a side sectional view of a dual half-bridge circuit module in some embodiments. Figure 9 The vertical dimension presents the three-dimensional integrated structure of the dual half-bridge module, fully demonstrating the manufacturing process sequence from the bottom substrate to the top pins. The entire module adopts a sandwich architecture with panel-level packaging, integrating two transistor chips into a functional half-bridge unit through the synergistic effect of conductive silver paste bonding, dielectric shielding, and copper pillar interconnection.

[0193] At the bottom is the circuit board, which serves as the mechanical support and primary electrical interconnect platform for the entire package. A conductive silver paste layer is printed on the substrate surface. Transistor chip 1 and transistor chip 2 are bonded to the silver paste via a back metallization layer. After the silver paste cures, it both secures the chips and establishes the electrical connection and heat conduction path between the chip's back drain and the substrate. In the cross-sectional view, the "internal drain port" refers to the area where the chip's drain is connected to the copper foil inside the substrate via the silver paste. This design combines the heat dissipation path and the power loop into one.

[0194] A dielectric shielding layer, typically made of epoxy resin or polyimide film, covers the top of the chip. This layer completely covers the chip surface and sidewalls, with precise openings only at the gate and source pads on the top layer. The shielding layer serves to provide electrical isolation between chips, preventing high-voltage breakdown, and also to smooth the surface, providing a flat base for subsequent copper deposition. In the cross-sectional view, the layer clearly covers the chip at the "shielding layer" label, but a void is left directly below the copper pillars.

[0195] Copper pillar interconnects are the core technology. After opening windows in the shielding layer, a copper metal layer is deposited across the entire surface through electroplating or sputtering. Subsequently, photolithography is used to etch vertical vias at the locations where electrodes need to be brought out, and the vias are filled with copper to form pillar-like structures. The cross-sectional view shows four copper pillars: the two on the left connect to the "gate 1" and "source 1" of transistor chip 1, respectively, and the two on the right correspond to the "gate 2" and "source 2" of chip 2. These copper pillars penetrate the shielding layer directly to the chip pads, forming a low-impedance vertical interconnect that replaces the arc-shaped crossovers of traditional wire bonding.

[0196] The top structure consists of a metallized layer at the top of a copper pillar and external pins. The upper end of the copper pillar is integrated with the pad on the top of the package, forming pins such as "External Gate Port 1" and "External Gate Port 2". The "External Drain Port" on the right side of the cross-sectional view is not directly connected to the copper pillar, but is connected to the drain on the back of the chip through internal traces on the substrate. This three-dimensional wiring design achieves physical separation between the power and control terminals, reducing electromagnetic interference.

[0197] This structure reduces chip-level interconnect length to the micrometer level, and parasitic inductance is reduced by an order of magnitude compared to traditional bonding. The current-carrying capacity of the vertical copper pillars far exceeds that of gold wires, improving reliability. The synergistic design of conductive silver paste and copper pillars not only meets heat dissipation requirements but also enables precise signal extraction, allowing a half-bridge circuit that originally required multiple discrete components and complex PCB layouts to be integrated into a single package module.

[0198] Reference Figure 10 The image shows a top-view cross-sectional view of the dual half-bridge circuit module in some embodiments. Gray represents the bottom wiring layout, and light orange represents the front wiring layout. From a top-view perspective, the package interior exhibits a double-layer metal wiring structure. The bottom wiring (gray) is embedded in the package substrate and primarily handles power current transmission, such as distributing the high voltage of the VIN pin to the drains of the two high-side MOSFETs through internal substrate wiring. These wirings are positioned close to the package edge for easy connection to external pins. The light orange front wiring is located above the chip and shielding layer, interconnected via copper pillars. It primarily redistributes the gate drive signal and source connection, featuring narrower linewidths but flexible layout, avoiding intersections in a two-dimensional plane and enabling complex interconnections.

[0199] Based on the logic circuit diagram and side sectional view, it can be inferred that the two transistor chips should be arranged side-by-side in the top view, occupying the central area of ​​the package. Each chip's gate and source pillars will form two independent pads on their surface, corresponding to the gate drive signal (HG1 / LG1 or HG2 / LG2) and the switching node (SW1 / SW2), respectively. The left-hand chip forms the first half-bridge arm, with its pillars positioned closer to the left side of the package; the right-hand chip forms the second half-bridge arm, with its pillars closer to the right side. This mirror-symmetric arrangement facilitates balanced current distribution and heat dissipation, while also simplifying the wiring design.

[0200] The external pinout follows a functional zoning principle. VIN and VOUT, as high-voltage power inputs, are typically located on the upper edge of the package with wider pins to reduce contact resistance. SW1 and SW2, as the midpoint outputs of the two half-bridges, are positioned in the center of the package for easy connection to external inductors or loads. The GND pin is generally located on the lower edge and may employ a multi-pin parallel structure to provide a low-impedance return path. The gate drive pins HG1, LG1, HG2, and LG2 are concentrated on one side, such as the left or right edge, for convenient routing with the controller IC and to reduce the drive loop area.

[0201] In some embodiments, the shielding layer can be a continuous thin film covering the chip area, with openings only at the corresponding locations of the copper pillars to form an isolation barrier. The bottom and front traces are vertically interconnected at specific locations via copper pillars, forming a three-dimensional electrical network. This layered design physically separates the power circuitry from the control circuitry, significantly reducing electromagnetic interference and is key to improving module performance.

[0202] It should be understood that the embodiments of this application achieve high-density chip-level integration through double-layer metallization and vertical copper pillars, compressing the planar layout on the traditional PCB into the package, and completing the coordinated optimization of power transmission, signal control and thermal management within a limited area.

[0203] Reference Figure 11 , Figure 11 This illustration shows the hardware structure of an electronic device according to another embodiment. The electronic device may include:

[0204] The processor 1101 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0205] The memory 1102 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 1102 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1102 and is called and executed by the processor 1101 using the dual half-bridge circuit module packaging method of the embodiments of this application.

[0206] Input / output interface 1103 is used to implement information input and output;

[0207] The communication interface 1104 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0208] Bus 1105 transmits information between various components of the device (e.g., processor 1101, memory 1102, input / output interface 1103, and communication interface 1104);

[0209] The processor 1101, memory 1102, input / output interface 1103 and communication interface 1104 are connected to each other within the device via bus 1105.

[0210] This application also provides a computer program product, which includes a computer program. A processor of a computer device reads and executes the computer program, causing the computer device to perform the above-described dual half-bridge circuit module packaging method.

[0211] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “including,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0212] It should be understood that in this disclosure, "at least one item" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0213] It should be understood that in the description of the embodiments of this application, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0214] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0215] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0216] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0217] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this disclosure. The aforementioned storage medium may include: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code.

[0218] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0219] The above is a detailed description of the embodiments of this disclosure. However, this disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this disclosure. All such equivalent modifications or substitutions are included within the scope defined by the claims of this disclosure.

Claims

1. A method for packaging a dual half-bridge circuit module, characterized in that, The method comprises the following steps: obtaining a plurality of transistor chips and a circuit substrate; wherein the drain of each transistor chip is located on the lower surface of the transistor chip, the gate and the source of each transistor chip are located on the upper surface of the transistor chip, and the circuit substrate is provided with a plurality of substrate chip seats; for each transistor chip, mounting the lower surface of the transistor chip on the corresponding substrate chip seat to electrically connect the drain of each transistor chip with the circuit substrate and form a drain port; after mounting each transistor chip, laying insulating material on the circuit substrate to form an isolation shielding layer; for the position of the upper surface gate and source of each transistor chip, removing the insulating material to form a gate through port and a source through port on the isolation shielding layer; after forming the gate through port and the source through port, performing a copper laying process above the isolation shielding layer to arrange lines for the gate, the source of each transistor chip and each drain port according to a preset double half-bridge circuit connection scheme and form a double half-bridge circuit; wherein the copper laying process above the isolation shielding layer to arrange lines for the gate, the source of each transistor chip and each drain port according to a preset double half-bridge circuit connection scheme and form a double half-bridge circuit specifically comprises: obtaining a plurality of types of pin position requirements; extracting a layered connection scheme matching each pin position requirement from the double half-bridge circuit connection scheme; determining a target layer connection scheme from a plurality of layered connection schemes and arranging lines for the gate, the source of each transistor chip and each drain port based on the target layer connection scheme to form the double half-bridge circuit meeting one of the pin position requirements; after forming the double half-bridge circuit meeting one of the pin position requirements, laying another isolation shielding layer above the double half-bridge circuit; after laying another isolation shielding layer above the double half-bridge circuit, returning to determine the target layer connection scheme from the layered connection schemes that have not been selected, and arranging lines for the gate, the source of each transistor chip and each drain port based on the re-determined target layer connection scheme to form the double half-bridge circuit meeting another pin position requirement, until the double half-bridge circuit corresponding to each pin position requirement is formed; wherein the double half-bridge circuits are filled with the isolation shielding layer; laying insulating material above the double half-bridge circuit to form a module packaging layer to obtain a double half-bridge circuit module.

2. The method of claim 1, wherein, The transistor chip comprises an in-circuit chip, the drain port comprises an in-circuit drain port, the substrate chip seat comprises an in-circuit chip seat, and the mounting of the lower surface of each transistor chip on the corresponding substrate chip seat to electrically connect the drain of each transistor chip with the circuit substrate and form a drain port comprises: For each of the circuit inner chip, the lower surface of the circuit inner chip is fixed on the corresponding inner chip seat through conductive silver paste, and the conductive medium formed after the conductive silver paste is solidified is used as the inner drain port.

3. The method of claim 1, wherein, The transistor chip includes a circuit outer chip, the drain port includes an outer drain port, the substrate chip seat includes an outer chip seat, and the lower surface of the transistor chip is mounted on the corresponding substrate chip seat to electrically connect the drain of each transistor chip with the circuit substrate to form a drain port. For each of the circuit outer chip, the lower surface of the circuit outer chip is fixed on the corresponding outer chip seat through conductive silver paste; wherein the circuit substrate is pre-buried with an outer drain trace in the outer chip seat, and the drain of the circuit outer chip is connected to the outer chip seat through conductive silver paste and is led out from the outer drain trace to form the outer drain port.

4. The method of claim 1, wherein, The insulating material is laid on the circuit substrate to form an isolation shielding layer, including: After the lower surface of each transistor chip is mounted on the corresponding substrate chip seat, the distance between each transistor chip and the circuit substrate is determined; The distance is determined as the reference thickness of the isolation layer; Based on the reference thickness of the isolation layer, the insulating material is laid on the circuit substrate to form the isolation shielding layer.

5. The method of claim 1, wherein, Before the isolation shielding layer is formed, it further includes: For each transistor chip arranged on the substrate chip seat, the positions of the gate and the source of each transistor chip are calibrated to obtain a plurality of window opening orientations; The positions of the upper surface gate and the source of each transistor chip are removed from the insulating material to form gate and source through holes on the isolation shielding layer, including: Based on a plurality of window opening orientations, windows are opened on the isolation shielding layer to form corresponding gate and source through holes.

6. The method of claim 1, wherein, After the gate and source through holes are formed, a copper laying process is performed above the isolation shielding layer to arrange lines for the gate, the source of each transistor chip and each drain port according to a predetermined double half-bridge circuit connection scheme to form a double half-bridge circuit, including: A copper overall coating layer is laid above the isolation shielding layer; According to the double half-bridge circuit connection scheme, the copper overall coating layer is etched to arrange lines for the gate, the source of each transistor chip and each drain port to form the double half-bridge circuit.

7. The method of claim 6, wherein, According to the double half-bridge circuit connection scheme, the copper overall coating layer is etched to arrange lines for the gate, the source of each transistor chip and each drain port to form the double half-bridge circuit, including: According to the double half-bridge circuit connection scheme, the copper overall coating layer is etched to form a double half-bridge line layout; performing a pin etching operation on the gate and source through-holes to form conductive copper pillars as gate pins in the gate through-holes and as source pins in the source through-holes, the conductive copper pillars connecting the double half-bridge layout and the respective gates and sources; determining the double half-bridge circuit based on the double half-bridge layout, the gate pins and the source pins.

8. The method of claim 7, wherein, The transistor chip is covered with an aluminum-copper coating at the positions of the gate and source, and the performing of the pin etching operation on the gate and source through-holes to form conductive copper pillars as gate pins in the gate through-holes and as source pins in the source through-holes, the conductive copper pillars connecting the double half-bridge layout and the respective gates and sources, comprises: performing a pin etching operation on the gate and source through-holes to form the gate pins in the gate through-holes and the source pins in the source through-holes; performing a gap filling operation based on the gate and source through-holes to convert the aluminum-copper coating into a conductive auxiliary medium; wherein the conductive auxiliary medium is used to fill the contact gaps between the gate pins and the respective gates, and the contact gaps between the source pins and the respective sources.

9. A dual half bridge circuit module characterized by, The double half-bridge circuit is packaged by the method of any one of claims 1 to 8.

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