Surface-mounted metal ceramic packaging structure suitable for power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and power MOSFET device
By increasing the source bonding finger area and introducing Kelvin source bonding fingers, the bonding finger layout is optimized, solving the problem of large parasitic inductance in traditional metal-ceramic packaging and improving the high-frequency performance and reliability of power MOSFET devices.
Patent Information
- Application Number
- CN202511765171.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2025-12-30
AI Technical Summary
Traditional metal-ceramic packages have large parasitic inductance, which limits the high-frequency performance of power MOSFET devices, leading to switching overshoot and gate oscillation. Existing packaging structures fail to fully utilize the high-frequency advantages of SiC/GaN devices.
By increasing the area of the source bonding fingers, increasing the number of source bonding lines, and introducing Kelvin source bonding fingers to isolate the power circuit and the drive circuit, the layout of the bonding fingers is optimized to reduce parasitic inductance, thus constructing a pure drive circuit.
It significantly improves the current carrying capacity and high-frequency performance of power MOSFET devices, reduces switching overshoot and gate oscillation, and enhances the high-frequency switching stability and reliability of the devices.
Smart Images
Figure CN121237772A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor power device packaging technology, specifically relating to a surface mount metal-ceramic packaging structure and a power MOSFET device suitable for power MOSFETs. Background Technology
[0002] With the widespread application of third-generation wide-bandgap semiconductors (such as silicon carbide (SiC) and gallium nitride (GaN), the operating frequency and switching speed of power MOSFET devices have significantly improved. However, the parasitic inductance of traditional metal-ceramic packages (especially the source loop inductance) has become a key factor restricting the high-frequency performance of devices and causing switching overshoot and gate oscillation. Existing package structures have not been specifically optimized in terms of bonding finger layout, resulting in limited current carrying capacity and large parasitic inductance, which prevents the full utilization of the high-frequency advantages of SiC / GaN devices. Summary of the Invention
[0003] To address the aforementioned problems in the prior art, this invention provides a surface-mount metal-ceramic package structure and a power MOSFET device suitable for power MOSFETs.
[0004] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a surface-mount metal-ceramic package structure suitable for power MOSFETs, comprising a metal-ceramic housing, a chip, source bonding fingers, gate bonding fingers, and multiple bonding wires; wherein, the chip is disposed in a sintering region on the bottom surface of the inner cavity of the metal-ceramic housing; the source bonding fingers and the gate bonding fingers are both disposed on the bottom surface of the inner cavity of the metal-ceramic housing, and an insulating layer is disposed between the sintering region, the source bonding fingers, and the gate bonding fingers for isolation, and the area of the source bonding fingers is larger than the area of the gate bonding fingers; the multiple bonding wires are respectively connected between the chip and the source bonding fingers, and between the chip and the gate bonding fingers.
[0005] In a second aspect, the present invention provides a power MOSFET device, including a surface mount metal-ceramic package structure suitable for power MOSFETs as described in the first aspect.
[0006] This invention provides a surface-mount metal-ceramic package structure and a power MOSFET device suitable for power MOSFETs. The surface-mount metal-ceramic package structure includes a metal-ceramic shell, a chip, source bonding fingers, gate bonding fingers, and multiple bonding wires. The chip is disposed in a sintering region on the bottom surface of the inner cavity of the metal-ceramic shell. Both the source bonding fingers and the gate bonding fingers are disposed on the bottom surface of the inner cavity of the metal-ceramic shell. An insulating layer is provided between the sintering region, the source bonding fingers, and the gate bonding fingers for isolation, and the area of the source bonding fingers is larger than that of the gate bonding fingers. Multiple bonding wires connect the chip to the source bonding fingers and the chip to the gate bonding fingers, respectively. This invention increases the effective area of the source bonding fingers, making their total area larger than that of the gate bonding fingers, providing space for bonding more source bonding wires. Therefore, by increasing the number of source bonding wires, the current-carrying capacity of the power MOSFET device can be improved. When applied to silicon carbide and gallium nitride power MOSFET devices, the high-frequency advantages of the device can be fully utilized.
[0007] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description
[0008] Figure 1 This is a schematic diagram of a surface mount metal-ceramic package structure suitable for power MOSFETs provided in an embodiment of the present invention.
[0009] Figure label: 1-Metal-ceramic tube shell; 2-Chip; 3-Insulating layer; 4-Source bond finger; 41-Source bond line; 5 - Gate bond finger; 51 - Gate bond line; 6-Kelvin source pole bond finger; 61-Kelvin source pole bond line. Detailed Implementation
[0010] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0011] Firstly, see [the following] Figure 1 This invention provides a surface mount metal-ceramic package structure for power MOSFETs, including a metal-ceramic housing 1, a chip 2, source bonding fingers 4, gate bonding fingers 5, and multiple bonding lines.
[0012] In this configuration, chip 2 is disposed in the sintering region on the bottom surface of the inner cavity of metal-ceramic housing 1; source bonding fingers 4 and gate bonding fingers 5 are both disposed on the bottom surface of the inner cavity of metal-ceramic housing 1; an insulating layer 3 is disposed between the sintering region, source bonding fingers 4 and gate bonding fingers 5 for isolation, and the area of source bonding fingers 4 is larger than the area of gate bonding fingers 5; multiple bonding wires are respectively connected between chip 2 and source bonding fingers 4, and between chip 2 and gate bonding fingers 5.
[0013] For example, an inner cavity is formed in the metal-ceramic housing 1, and a chip 2 is welded to the sintering zone on the bottom surface of the inner cavity. The chip 2 can be bonded to the sintering zone using lead-tin-silver solder. Additionally, an insulating layer 3 is formed in the inner cavity. The insulating layer 3 can be an insulating ceramic layer, and it is formed outside the sintering zone to isolate the sintering zone, the source bonding fingers 4, and the gate bonding fingers 5. The chip 2 includes a source and a gate. The source bonding fingers 4 are connected to the source of the chip 2 via multiple source bonding lines 41, and the gate bonding fingers 5 are connected to the gate of the chip 2 via at least one gate bonding line 51.
[0014] The existing metal-ceramic package 1 has a small source bonding finger area, which cannot meet the requirements of high-current wire bonding and restricts the current carrying capacity of the chip 2. To address this, this embodiment increases the effective area of the source bonding fingers 4, making their total area larger than that of the gate bonding fingers 5. This provides space for bonding more source bonding wires 41, thereby increasing the current carrying capacity of the power MOSFET device by increasing the number of source bonding wires 41. When applied to silicon carbide and gallium nitride power MOSFET devices, this can fully utilize the high-frequency advantages of the device.
[0015] In one optional embodiment, the surface mount metal-ceramic package structure further includes: Kelvin source bonding fingers 6, disposed on the bottom surface of the inner cavity of the metal-ceramic housing 1, and isolated from the sintering region, source bonding fingers 4 and gate bonding fingers 5 by an insulating layer 3, wherein the area of the source bonding fingers 4 is larger than the area of the Kelvin source bonding fingers 6; the Kelvin source bonding fingers 6 are connected to the chip 2 by Kelvin source bonding lines 61.
[0016] Specifically, in the pin layout of the insulating layer 3 formed inside the cavity of the metal-ceramic casing 1, an independent source Kelvin pin, namely Kelvin source bonding finger 6, is added. This pin is physically isolated from the main source power pin (i.e., source bonding finger 4). Therefore, within the cavity of the metal-ceramic casing 1, the Kelvin source pad of chip 2 can be directly connected to the Kelvin pin via an independent short lead (Kelvin source bonding wire 61), thus constructing a pure driving circuit.
[0017] Existing metal-ceramic casings (1) suffer from parasitic inductance in the circuit when there are many wires, especially for high-frequency devices (silicon carbide and gallium nitride power MOSFETs). This leads to problems such as large parasitic inductance and poor high-frequency switching stability, severely affecting device performance. To address this, this embodiment introduces a Kelvin source bonding finger (6) to isolate the power circuit from the drive circuit, significantly reducing switching overshoot and gate oscillation, and improving switching speed and reliability.
[0018] In one alternative embodiment, the area of the Kelvin source bonding finger 6 is equal to the area of the gate bonding finger 5.
[0019] In one alternative embodiment, the area of the source bonding finger 4 is The areas of Kelvin source bonding finger 6 and gate bonding finger 5 are both .
[0020] In one alternative embodiment, the size of the source bonding finger 4 is... The dimensions of Kelvin source bonding finger 6 and gate bonding finger 5 are both .
[0021] Specifically, most existing SMD-1s have the same size for the source and gate bonding fingers, around 2.4*2.4mm. In this embodiment, while ensuring a reliable connection, the size of the gate bonding finger 5 is appropriately reduced to allow for an increase in the area of the source bonding finger 4 and an increase in the Kelvin source bonding finger 6.
[0022] In one alternative embodiment, the number of source bonding lines 41 connecting chip 2 and source bonding fingers 4 is greater than the number of gate bonding lines 51 connecting chip 2 and gate bonding fingers 5.
[0023] In one alternative embodiment, the number of source bonding lines 41 is greater than 3 and less than or equal to 6.
[0024] In one alternative embodiment, the diameter of the source bonding line 41 is greater than the diameter of the Kelvin source bonding line 61, and the diameter of the source bonding line 41 is greater than the diameter of the gate bonding line 51.
[0025] For example, source bonding wire 41 can be six 20mil (mil) aluminum wires, and gate bonding wire 51 and Kelvin source bonding wire 61 can be 5mil aluminum wires. The optimized source bonding finger 4 allows six 20mil (approximately 500μm) aluminum wires to interconnect the source of chip 2 with the source bonding finger 4. Compared to the design with a maximum of three wires in the prior art, the interconnection resistance of the source in this embodiment is significantly reduced, the current carrying capacity is increased by approximately double, and the heat dissipation performance is improved. The bonding wires can also be ultrasonically or soldered using metal strips or connecting pieces to further reduce parasitic inductance and resistance.
[0026] Secondly, embodiments of this application also provide a power MOSFET device, including a surface mount metal-ceramic package structure suitable for power MOSFETs as described in the first aspect.
[0027] This application provides a high-frequency, high-reliability surface-mount metal-ceramic package structure that can fully utilize the performance of SiC / GaN power MOSFET devices, thereby improving the performance of SiC / GaN power MOSFET devices.
[0028] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.
[0029] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0030] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.
[0031] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A surface mount cermet package structure suitable for power MOSFET, characterized in that, include: Metal-ceramic tube shell (1); Chip (2) is disposed in the sintering zone on the bottom surface of the inner cavity of the metal-ceramic tube shell (1); The source bonding finger (4) and the gate bonding finger (5) are both disposed on the bottom surface of the inner cavity of the metal ceramic tube shell (1). An insulating layer (3) is disposed between the sintering zone, the source bonding finger (4) and the gate bonding finger (5) for isolation, and the area of the source bonding finger (4) is larger than the area of the gate bonding finger (5). Multiple bonding lines are respectively connected between the chip (2) and the source bonding finger (4), and between the chip (2) and the gate bonding finger (5).
2. The surface mountable cermet package structure for power MOSFET according to claim 1, wherein, The surface-mount metal-ceramic packaging structure also includes: Kelvin source bonding finger (6) is disposed on the bottom surface of the inner cavity of the metal ceramic tube shell (1) and is isolated from the sintering region, the source bonding finger (4) and the gate bonding finger (5) by the insulating layer (3), and the area of the source bonding finger (4) is larger than the area of the Kelvin source bonding finger (6). The Kelvin source bonding finger (6) is connected to the chip (2) via the Kelvin source bonding line (61).
3. The surface mountable cermet package structure for power MOSFET according to claim 2, wherein, The area of the Kelvin source bonding finger (6) is equal to the area of the gate bonding finger (5).
4. The surface mountable cermet package structure for power MOSFET according to claim 2, wherein, The number of source bonding lines (41) connecting the chip (2) and the source bonding finger (4) is greater than the number of gate bonding lines (51) connecting the chip (2) and the gate bonding finger (5).
5. The surface mountable cermet package structure for power MOSFET according to claim 4, wherein The number of source bonding lines (41) is greater than 3 and less than or equal to 6.
6. The surface mountable cermet package structure for power MOSFET according to claim 3, wherein The area of the source bonding finger (4) is , and the area of the Kelvin source bonding finger (6) and the gate bonding finger (5) is .
7. The surface mount cermet package structure for power MOSFET according to claim 6, wherein The dimensions of the source bonding fingers (4) are The dimensions of the Kelvin source bonding fingers (6) and the gate bonding fingers (5) are .
8. The surface mountable cermet package structure for power MOSFET according to claim 4, wherein, The diameter of the source bonding line (41) is greater than the diameter of the Kelvin source bonding line (61), and the diameter of the source bonding line (41) is greater than the diameter of the gate bonding line (51).
9. A power MOSFET device characterized by, Includes a surface mount metal-ceramic package structure suitable for power MOSFETs as described in any one of claims 1-8.