Fabrication of trench transistors with in-trench ESD structures

Abstract

A trench transistor and method of manufacture includes a semiconductor substrate including ions of a first conductivity type, where the ions of the first conductivity type are opposite ions of a second conductivity type. An electrostatic discharge protection (ESD) trench is formed in the semiconductor substrate, and a lower insulating layer is formed on a surface of the ESD trench of the semiconductor substrate. A nitride layer is formed on the lower insulating layer in the ESD trench, and an upper insulating layer is formed on the nitride layer. An ESD semiconductor layer is formed on the upper insulating layer.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge protection technology in transistor devices, and in particular to the manufacture of trench transistors with in-trench ESD (electrostatic discharge protection) structures. Background Technology

[0002] Electrostatic discharge (ESD) is the sudden and instantaneous flow of current from one object to another. ESD generates extremely high currents and voltages, lasting only a very short time, sometimes referred to as a high-voltage transient. In most cases, the transient nature of ESD allows the current to dissipate quickly across the surface of an object without causing damage. However, this is not the case for electronic devices such as transistors, as they are highly sensitive to high-voltage transients. In transistors, high-voltage transients can cause the insulating layer of the device to break down, leading to malfunction.

[0003] Transistor devices employ various technologies to protect their active regions from high-voltage transients. Transistor devices can be packaged in a grounded enclosure to protect them from external transients. However, grounded enclosures may not be suitable for all applications and can take up more space than the transistor itself. Therefore, transistor manufacturers have developed electrostatic discharge (ESD) protection solutions integrated within the transistor device.

[0004] Previous ESD mitigation methods involved fabricating diode structures on the semiconductor substrate of transistor devices. These earlier structures included shallow trench junction diodes, where the insulating layer was formed during the gate oxide layer formation process.

[0005] It is against this backdrop that the various aspects of this disclosure have been put forward. Summary of the Invention

[0006] The purpose of this invention is to provide a method for manufacturing trench transistors with in-trench ESD structures, which can solve the problem that the active region of transistor devices is susceptible to high voltage transients.

[0007] To achieve the above objectives, the present invention provides the fabrication of a trench transistor with an in-trench ESD structure, comprising:

[0008] a) Forming an ESD trench in a semiconductor substrate, wherein the semiconductor substrate comprises ions of a first conductivity type, and the ions of the first conductivity type are opposite to the ions of a second conductivity type;

[0009] b) A lower insulating layer made of insulating material is formed in the ESD trench of the semiconductor substrate;

[0010] c) Deposit a nitride layer on the lower insulating layer in the ESD trench of the semiconductor substrate;

[0011] d) Deposit an ESD semiconductor layer on the nitride layer in the ESD trench.

[0012] Optionally, the method further includes forming an oxide layer on the nitride layer before depositing the ESD semiconductor layer.

[0013] Optionally, a) further includes forming an active trench in the semiconductor substrate simultaneously with the ESD trench.

[0014] Optionally, the method further includes forming an active trench before forming the ESD trench.

[0015] Optionally, the method further includes depositing an active trench insulating layer in the active trench of the semiconductor substrate before forming the ESD trench.

[0016] Optionally, the method further includes forming a gate conductive electrode in the active trench before forming the ESD trench.

[0017] Optionally, the method further includes e) doping the ESD semiconductor layer with ions of a second conductivity type.

[0018] Optionally, the method further includes f) doping one or more ESD contact regions in the ESD semiconductor layer with ions of a first conductivity type.

[0019] Optionally, the method further includes forming an active trench after forming the ESD trench.

[0020] Optionally, the method further includes polishing the top surface of the substrate to remove the ESD semiconductor layer from the top surface of the substrate, leaving the ESD semiconductor layer material in the ESD trench, and applying an ESD etching mask on the ESD semiconductor layer material after polishing the top surface of the substrate.

[0021] Optionally, the method further includes applying an ESD etching mask to the ESD semiconductor layer material after polishing the top surface of the substrate.

[0022] Optionally, the method further includes etching away the ESD semiconductor layer material from the active trench.

[0023] Optionally, the method further includes depositing a conductive material in the ESD semiconductor layer material while depositing the gate electrode material.

[0024] Optionally, the method further includes forming an ESD top insulating layer on the ESD semiconductor layer and forming a source metal layer, wherein the ESD top insulating layer includes one or more spaces such that the source metal layer contacts the ESD semiconductor layer.

[0025] Optionally, the method further includes forming an upper insulating layer made of an insulating material on the nitride layer, and the ESD semiconductor layer is formed on the upper insulating layer.

[0026] The present invention also provides a trench transistor, comprising:

[0027] A semiconductor substrate comprising ions of a first conductivity type, wherein the ions of the first conductivity type are opposite to ions of a second conductivity type;

[0028] An ESD trench formed in the semiconductor substrate;

[0029] A lower insulating layer formed on the surface of the ESD trench of the semiconductor substrate;

[0030] A nitride layer formed on the lower insulating layer in the ESD trench;

[0031] An upper insulating layer formed on the nitride layer in the ESD trench; and

[0032] An ESD semiconductor layer formed on the upper insulating layer.

[0033] Optionally, the trench transistor may have an active trench that extends deeper into the semiconductor substrate than the ESD trench.

[0034] Optionally, the trench transistor, wherein the ESD semiconductor includes a recess at the top surface interface.

[0035] Optionally, in the trench transistor, the nitride layer is located only in the ESD trench.

[0036] Optionally, in the trench transistor, the ESD semiconductor layer is doped with ions of a second conductivity type and includes one or more ESD contact regions doped with ions of a first conductivity type, wherein the ESD contact regions serve as the cathode of a junction diode and are formed between the ESD contact regions and the ESD semiconductor layer, and the ESD semiconductor layer serves as the anode.

[0037] In summary, compared with the prior art, the present invention has the following beneficial effects:

[0038] 1. The trench transistor with an in-trench ESD structure provided by the present invention improves the resistance of the ESD structure to high voltage transient leakage to the active region by adding a thick bottom insulating layer and a nitride layer to the transistor device, and reduces the substrate area required for the ESD trench.

[0039] 2. The trench transistor with in-groove ESD structure provided by the present invention does not occupy additional space compared with the traditional protection method of being packaged in a grounded housing. It is an integrated electrostatic discharge protection (ESD) solution for the inside of a transistor device. Attached Figure Description

[0040] Figure 1 A cross-sectional view of a transistor device according to one aspect of the present invention, the device having an improved ESD trench including a recess at the interface between the nitride layer and the ESD semiconductor layer.

[0041] Figure 2 This is a cross-sectional view of a transistor device according to one aspect of the present invention, which has an improved ESD trench including a nitride layer, and the active region gate trench is etched independently from the ESD trench.

[0042] Figure 3 This is a cross-sectional view of a transistor device according to one aspect of the present invention, the device having an improved ESD trench including a nitride layer, and an active region formed after the ESD trench is formed;

[0043] Figure 4A-4I A method for manufacturing a transistor device according to one aspect of the present invention, the device having an improved ESD trench including a depression at the interface between the nitride layer and the ESD semiconductor layer.

[0044] Figure 5A-5I An improved method for manufacturing a transistor device, one aspect of the present invention, is provided, wherein the device has a nitride layer and an active region gate trench extends deeper into the semiconductor substrate than the ESD trench layer.

[0045] Figure 6A-6G A method for manufacturing a transistor device according to one aspect of the present invention, the device having an improved ESD trench including a nitride layer, and an active region formed after the ESD trench is formed. Detailed Implementation

[0046] While the following detailed description contains numerous specific details for illustrative purposes, those skilled in the art will understand that many variations and modifications to these details are within the scope of the invention. Therefore, the exemplary embodiments of the invention described below are presented without losing the generality of the claimed invention and without imposing limitations upon it. In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, illustrating specific embodiments in which the invention can be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “leading,” “tailing,” etc., are used to refer to the orientation of the described figures. Because components of the embodiments of this disclosure can be positioned in multiple different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments can be utilized, and structural or logical changes can be made without departing from the scope of the invention. Therefore, the following detailed description should not be considered as intended to be limiting, and the scope of the invention is defined by the appended claims.

[0047] This disclosure relates to semiconductor materials, such as silicon, doped with ions of a first conductivity type or a second conductivity type. The ions of the first conductivity type can be the opposite of the second conductivity type. For example, but not limited to, in some embodiments, the ions of the first conductivity type can be n-type, which, when doped into silicon, contributes negative charge carriers, such as electrons. In such embodiments, the ions of the first conductivity type can include phosphorus, antimony, bismuth, lithium, and arsenic. In such embodiments, the ions of the second conductivity type can be p-type, which, when doped into silicon, creates holes for charge carriers and is therefore referred to as the opposite of n-type. P-type ions include boron, aluminum, gallium, and indium. Although the foregoing description refers to n-type as the first conductivity type and p-type as the second conductivity type, this disclosure is not limited thereto; p-type can be the first conductivity type and n-type can be the second conductivity type. Furthermore, according to aspects of this disclosure, semiconductor materials other than silicon can be used in MOSFET devices.

[0048] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, illustrating specific embodiments in which the invention can be practiced. For convenience, the use of + or - after specifying conductivity or net impurity carrier type (p or n) generally refers to the relative concentration of the specified type of net impurity carriers in the semiconductor material. Generally, n+ materials have a higher concentration of n-type net dopant (e.g., electrons) than n materials, and n materials have a higher carrier concentration than n- materials. Similarly, p+ materials have a higher concentration of p-type net dopant (e.g., holes) than p materials, and p materials also have a higher concentration than p- materials. It is important to note that what is relevant is the net carrier concentration, and not necessarily the dopant concentration. For example, a material can be heavily doped with n-type dopant, but if the material is also sufficiently dedoped with p-type dopant, its net carrier concentration will still be relatively low. As used herein, less than about 1e 16 cm -3 The dopant concentration can be considered "lightly doped", greater than about 1e 17 cm -3 The concentration of dopant can be considered "heavily doped".

[0049] In previous embodiments, an insulating layer was created for the ESD structure in the same fabrication step as the gate oxide formation. This saved fabrication steps, but it was found that the oxide layer formed in the ESD structure at this step was insufficient to isolate the ESD trench from transients with small ESD trench widths. Therefore, in previous embodiments, the substrate had to allocate a large area for the ESD trench to provide sufficient protection against high-voltage transients.

[0050] Recognizing this problem, a trench ESD structure with a thick bottom insulating layer and a nitride layer has been proposed based on various aspects of this disclosure. The thick ESD semiconductor layer with the bottom insulating layer and nitride layer improves the ESD structure's resistance to high-voltage transient leakage into the active region, thereby reducing the substrate area required for the ESD trench. Therefore, this paper provides various fabrication methods for producing transistor devices with ESD trenches having a nitride layer.

[0051] like Figure 1As shown, according to various aspects of this disclosure, the improved transistor device 100 may include an ESD trench 114 and an active region gate trench 115 formed in a semiconductor substrate 101. The ESD trench 114 is lined with a lower ESD insulating layer 105, a nitride layer 106, and an upper ESD insulating layer 107. The upper and lower ESD insulating materials 107 may be made of any suitable electrically insulating material, such as, but not limited to, silicon dioxide. In this embodiment, the semiconductor substrate 101 may be doped with ions of a first conductivity type, such as n-type ions. The ESD semiconductor layer 102 may be a conductive material, such as polysilicon doped with ions of a second conductivity type (e.g., p-type ions). The ESD semiconductor layer may also include an ESD contact region 104 doped with ions of the first conductivity type. The ESD contact region 104 may serve as the cathode of a junction diode formed between the contact region and the doped ESD semiconductor layer 102. In this configuration, the doped ESD semiconductor layer may serve as the anode. The source metal layer 108 can contact the first ESD contact region 104 through the via 116 at the top of the ESD trench insulating layer 112. The gate metal layer 108' can contact the second ESD contact region 104' through the via 116' at the top of the ESD trench insulating layer 112, thereby forming a back-to-back ESD diode between the gate and the source.

[0052] The improved transistor device 100 also includes conventional transistor components, such as a gate insulating layer 109 formed in the active gate trench 115, and a gate electrode 120 formed on the top insulating layer of the shielding electrode 110. The shielding electrode 110 is formed in the bottom portion of the active gate trench 115, above the gate insulating layer 109. The semiconductor substrate 101 may be doped with ions of a second conductivity type in its upper region to form a body region 103. The source region 113 may be formed in the body region 103 near the gate trench 115 and heavily doped with ions of a first conductivity type.

[0053] Figure 1 The illustrated embodiment is a shielded gate trench (SGT) implementation, wherein the gate insulating layer 109 includes a thin upper portion (separating the gate electrode 120 from the body region 103 and the source region 113), a thick lower portion (surrounding the shielding electrode 110 in the gate trench 115), and a middle portion (separating the gate electrode 120 from the shielding electrode 110). Alternatively, in a single-gate electrode implementation (not shown in the figure), the gate electrode 120 can be directly connected to the shielding electrode 110 without the need for... Figure 1 The intermediate insulating part is shown.

[0054] A via 118 in the top gate insulating layer 111 allows the source metal 108 to form a conductive contact with the source contact region 113. The body region 103 contacts the source metal through the via in the top insulating layer, forming an antiparallel body diode in the transistor device. This region is not shown in the current view but can be formed in separate masking, etching, and deposition steps, or in the same step that creates a conductive contact with the source region. As shown, the via 118 extends only through the top gate insulating layer 111 to form a conductive contact with the source region 113. Alternatively, the via 118 can extend into or even through the source region 113 to simultaneously contact the body region 103. The drain metal 119 can be formed on the back side of the device, and a gate contact (not shown) can be connected to the gate electrode to control the gate of the transistor device. While this disclosure discusses transistor devices with shielded electrodes, it should be understood that various aspects of this disclosure are not limited thereto and can be extended to transistor structures without shielded electrodes.

[0055] Figure 2 The overall layout of the transistor device shown in -4 is Figure 1 The layout shown is similar, therefore it will be connected via devices and Figure 1 The structural differences between the devices shown will be discussed. These differences may be due to variations in the manufacturing processes between the devices, which will be discussed in later sections.

[0056] Figure 2 An example of a transistor device 200 is illustrated, which has an improved ESD trench including a nitride layer, and the active region gate trench is etched independently of the ESD trench, according to one aspect of this disclosure. In this embodiment, the ESD trench 214 can be of arbitrary depth because it is created in a step independent of the creation step of the active gate trench 215. Here, the ESD trench 214 is depicted as shallower than the active gate trench 215 to compare this with... Figure 1 The implementation is distinguished as follows. Therefore, due to the shallower ESD trench, the corresponding lower ESD insulating layer 205, nitride layer 206, and upper ESD insulating layer 207 are shallower in the substrate composition. The top of the ESD semiconductor layer 202 can also be formed above the top of the body region 203 of the semiconductor substrate composition 201. This shallow trench is a result of forming the active gate trench 215 before the ESD trench 214 during the manufacturing process. This results in a more regular, rectangular shape for the ESD semiconductor layer 202, without... Figure 1 The recess shown in the middle semiconductor layer 102. This may cause the top ESD insulating layer 212 to bulge slightly on the surface of the substrate composition, and similarly, the conductive electrode metal 208 may follow this bulge above the ESD trench. Figure 1Similar to the device shown, the source metal layer 208 can contact the first ESD contact region 204 through a via in the top portion of the top ESD insulating layer 212. The gate metal layer 208' can contact the second ESD contact region 204' through a via in the top portion of the ESD trench insulating layer 212, thereby forming a back-to-back ESD diode between the gate and the source.

[0057] It should also be understood that ESD trenches can have arbitrary depths, even deeper than the active region gate trenches; because they are etched independently, unlike... Figure 1 The two trenches are etched simultaneously, so the ESD trench must be much deeper than the active region gate trench and cannot have an arbitrary depth.

[0058] Figure 3 A cross-sectional view of a transistor device 300 is shown, which has an improved ESD trench including a nitride layer, and an active region formed after the ESD trench is formed, according to one aspect of this disclosure. In the illustrated embodiment, the ESD trench 314 is formed before the active gate trench 315. It should be understood that since the ESD trench 314 is formed independently of the active gate trench 315, it can have any depth, and this implementation is not limited to the case where the ESD trench and the active trench have similar depths. Furthermore, the ESD semiconductor layer 302 is substantially rectangular, with no additional conductive side structures in the ESD trench. A lower ESD insulating layer 305, a nitride layer 306, and an upper ESD insulating layer 307 may be continuously lined in the ESD trench 314, and a continuous ESD semiconductor layer 302 may be formed on the upper ESD insulating layer 307. A recess may be formed on the upper portion of the top ESD insulating layer 312 during manufacturing. The source metal 308 may also include a recess that follows the contour of the ESD insulating layer 312. Figure 1 and Figure 2 Similar to the device shown, the source metal layer 308 can contact the first ESD contact region 304 through a via in the top portion of the top ESD insulating layer 312. The gate metal layer 308' can contact the second ESD contact region 304' through a via in the top portion of the ESD trench insulating layer 312, thereby forming a back-to-back ESD diode between the gate and the source.

[0059] Figure 4A –4I represents a method for fabricating a transistor device with improved ESD trenches, including recesses at the interface between the nitride layer and the ESD semiconductor layer, such as… Figure 1 As shown. In this manufacturing method, the ESD trench 402 and the active gate trench 403 are formed in the semiconductor substrate 401 in the same etching step, as... Figure 4AAs shown. Semiconductor substrate 401 may include a lightly doped epitaxial layer of a first conductivity type ions, formed on top of a heavily doped layer of the first conductivity type. Semiconductor substrate 401 is masked with an oxide hard mask, and then ESD trench 402 and active gate trench 403 are etched using a suitable trench forming method (e.g., but not limited to anisotropic processes, such as reactive ion etching (RIE)). Isotropic etching may also be applied to create a rounded bottom for the active gate trench. Isotropic etching may use any suitable isotropic etchant, such as nitrous acid (HNO2), hydrofluoric acid (HF), acetic acid (CH3COOH), or any combination thereof. After etching the trenches, an oxide layer 404 is formed on the top surface of the substrate composition (including the exposed surfaces in the trenches) by thermal oxidation or deposition.

[0060] Next, as Figure 4B As shown, an n-doped polysilicon layer is deposited on the top surface of the entire substrate composition, filling the active gate trench 403 with the polysilicon layer. The n-doped polysilicon layer is then etched away from the top surface, the ESD trench, and the upper part of the active gate trench 403, forming a shielding electrode 405 at the bottom portion of the active trench 403. The oxide layer 404 on the upper sidewall of the active gate trench 403 not covered by the shielding electrode 405 is then removed by wet etching. The substrate is then oxidized to form a polysilicon oxide layer on the shielding electrode 405 and a thin oxide layer 406 on the upper sidewall of the active gate trench 404. This thin oxide layer also covers the upper sidewall of the ESD trench 402 and increases the thickness of the oxide layer on the top surface of the substrate composition.

[0061] In the single-gate electrode embodiment, the lower active gate polysilicon forming the shielding electrode 405 can be etched away in the active gate trench immediately after the upper oxide layer 404 of the active gate trench is removed, leaving the lower oxide layer 404 of the active gate trench 403. The substrate can then be oxidized to form a thin oxide layer 406 on the upper sidewall of the active gate trench 404.

[0062] Next, as Figure 4C As shown, an n-doped polysilicon layer 407 is deposited on the top surface of the substrate composition (including the active gate trench 403 and the ESD trench 402). This will form the upper gate electrode, which can be formed by any suitable deposition method (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.). Figure 4D As shown, the polysilicon layer is completely etched back from the top surface of the substrate composition and the ESD trench 402, leaving the top gate electrode layer 409 in the gate trench 403.

[0063] An optional oxide layer can be deposited on the exposed surface of the substrate composition using any suitable deposition method (e.g., but not limited to chemical vapor deposition, thermal oxidation, etc.). The optional oxide layer and hard mask layer are then removed from the top surface of the substrate composition by chemical mechanical polishing (CMP). Figure 4E As shown, the result is the formation of a lower ESD trench oxide layer 410 and a top gate oxide layer 411 in the ESD trench 402.

[0064] Next, Figure 4F This describes the deposition of additional oxide material on the surface of the substrate composition to form a complete lower ESD trench oxide layer 412 in the ESD trench 402. A nitride layer 413 is then deposited, followed by an upper ESD oxide layer 414 deposited on the top surface of the ESD trench 402 and the substrate composition. Finally, an ESD semiconductor layer 415 is deposited on the upper ESD oxide layer 414 in the ESD trench 402 and on the top surface of the substrate composition. The ESD semiconductor layer 415, the upper ESD insulating layer 414, the nitride layer 413, and the lower ESD insulating layer 412 can be formed by any suitable deposition method (e.g., but not limited to CVD). The ESD semiconductor layer 415 can be undoped polysilicon, subsequently... Figure 4G As shown, ions of a second conductivity type are doped. Alternatively, this step can be performed simultaneously with the step of doping the bulk region. The doped ESD semiconductor layer 416 is heated to drive the diffusion of ions of the second conductivity type throughout the semiconductor layer. The ion driving described above can be performed by any suitable thermal driving method, such as, but not limited to, heating the substrate composition to 900-1500°C for up to one hour, for example, at 1050°C for 30 minutes. The thermal driving performed here typically requires a longer heating time than the rapid thermal annealing step, which can, for example, but not limited to, heating the substrate composition for less than one minute, for example, 30 seconds.

[0065] The top surface of the substrate composition is polished by CMP to remove the semiconductor material layer not in the ESD trench 402, forming the final shape of the ESD semiconductor material layer 418. After CMP, the nitride layer 413 and the upper ESD layer 414 are etched away from the areas of the substrate composition not covered by the ESD semiconductor material layer 418, as shown below. Figure 4HAs shown. The oxide material 419 on the top surface of the substrate composition is protected by a nitride layer, which serves as an etch stop layer. It can be seen that CMP reveals a depression on the surface of the ESD trench semiconductor material 418 because the polishing wheel cannot remove the material, as the semiconductor material is below the top surface of the semiconductor substrate. Furthermore, one or more ESD contact regions 417 are formed in the semiconductor material 418. If multiple ESD contact regions are formed, there should be sufficient space between these regions so that each region can function as a junction diode without interference from other ESD contact regions. Alternatively, this step can be performed simultaneously with the step of forming the source region.

[0066] Finally, as Figure 4I As shown, substrate 401 can be selectively doped with ions of a first conductivity type to form JFET region 430, followed by pre-body thermal drive, steps omitted in the formation of a single-gate transistor. Next, substrate 401 is doped with ions of a second conductivity type to form body region 422, followed by rapid thermal annealing to further drive the ions into the substrate. One or more source regions 423 are implanted into the body region near the active gate trench 403 with a heavy doping concentration. The semiconductor composition is then heated to drive the dopants in the source regions 423 to diffuse deeper into the body region 422 and further diffuse the ESD contact region 417 into the entire ESD semiconductor material 418. Low-temperature oxide (LTO) is then grown on the surface of the substrate composition, followed by deposition of borosilicate glass (BPSG) and heating of the BPSG to allow an insulating layer to flow on the substrate composition, forming the top portion of the ESD trench insulating layer 420 and the top gate insulating layer 424. The BPSG also insulates that portion of the substrate composition in the body region.

[0067] Vias can be created in the borosilicate glass layer via etching or mechanical drilling for source contacts and ESD contacts. Next, one or more ESD direct contact regions 431 are implanted into the ESD contact region 417 with heavily doped ions of a second conductivity type, followed by rapid thermal annealing to diffuse the ions into the ESD contact region, resulting in a decreasing concentration gradient from the top of the ESD contact outwards. Finally, a conductive material 421 (such as a metal layer) can be deposited on the insulating layer and in the vias, contacting the source region 423, the body region 422, and the ESD trench contact region 417. The conductive material 421 is then etched to form the final layout of the conductive material on the substrate composition. According to one aspect of this disclosure, the result is a transistor device with an improved ESD trench, including a recess at the interface between the nitride layer and the ESD semiconductor layer surface.

[0068] Figure 5A–5I illustrates an example of a method for fabricating an improved transistor device having a nitride layer and an active region gate trench extending deeper into the semiconductor substrate than the ESD trench layer, such as Figure 2 As shown. In this manufacturing method, the active gate trench 503 is formed before the ESD trench is formed, as... Figure 5A As shown. A semiconductor substrate 501 may be provided, comprising a lightly doped epitaxial layer of a first conductivity type ions formed on top of a heavily doped layer of the first conductivity type. The semiconductor substrate 501 is masked with an oxide hard mask, and then an active gate trench 503 is etched by a suitable trench forming method (e.g., but not limited to, reactive ion etching). After etching the active gate trench, an oxide layer 502 is deposited on the top surface of the substrate composition (including the exposed surface in the trench) by thermal oxidation and / or CVD.

[0069] Next, an n-doped polysilicon layer is deposited on the exposed top surface of the entire substrate composition to form the lower active gate polysilicon layer in the active trench 503. Then as... Figure 5B As shown, the n-doped polysilicon layer is dry-etched, and the oxide layer is wet-etched back inside the top of the active gate trench 503.

[0070] In a single-gate electrode implementation, the lower active gate polysilicon can be etched away in the active gate trench after wet etching of the pad oxide to remove the oxide on the upper sidewalls of the trench; however, this step can be omitted in SGT transistor fabrication. Polysilicon oxide is formed on the top surface of the polysilicon shield electrode 504 by thermal oxidation. Then, a gate oxide layer is grown on the sidewalls of the active gate trench 503 by thermal oxidation. Next, as... Figure 5C As shown, an n-doped polysilicon layer 506 is deposited on the top surface of the substrate composition (including within the active gate trench 503). This forms the upper active gate layer, which can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. Figure 5D As shown, the polysilicon layer is etched back from the top surface of the substrate composition by wet etching, including leaving a top gate electrode layer 507 in the gate trench 503.

[0071] An oxide hard mask is deposited on the exposed surface of the substrate composition using any suitable deposition method (e.g., but not limited to CVD). An ESD trench mask is then formed on the surface of the substrate composition. The ESD trench mask can be any suitable mask, such as, but not limited to, a patterned photomask or a patterned mask for mechanical applications. ESD trenches 510 are etched through gaps in the patterned mask. The ESD trenches can be formed by any suitable etching method, such as, but not limited to, reactive ion etching (RIE) or wet etching. The oxide 505 is then removed from the top surface of the substrate composition by chemical mechanical polishing (CMP). Figure 5E As shown, the result is the formation of an active gate having an upper active gate electrode 507 and a lower shielding electrode 504 in an active gate trench 503, insulated from the substrate by a gate electrode insulating layer 509, and an exposed ESD trench 510. Due to this process, the ESD trench 510 is shallower than the active gate trench 503. Furthermore, compared to... Figure 4A Compared to the ESD trench 402 implementation shown in –4I, the ESD trench 503 here is shallower. This is due to manufacturing details, but as mentioned above, in this embodiment, the ESD trench can have any depth because it is formed independently of the active gate trench. It should be noted that the active gate insulating layer 509 is thicker near the bottom of the active gate trench than near the top.

[0072] Next, Figure 5F This describes depositing additional oxide material on the surface of the substrate composition to form a complete lower ESD trench oxide layer 512 in the ESD trench, followed by the deposition of a nitride layer 513. Then, an upper ESD oxide layer 514 is deposited on the top surface of the ESD trench 510 and the substrate composition. Finally, an ESD semiconductor layer 511 is deposited on the upper ESD oxide layer 514 in the ESD trench 510 and on the top surface of the substrate composition. The ESD semiconductor layer 511, the upper ESD insulating layer 514, the nitride layer 513, and the lower ESD insulating layer 512 can be formed by any suitable deposition method (e.g., but not limited to CVD). The ESD semiconductor layer 511 can be undoped polysilicon, subsequently doped with ions of a second conductivity type, such as... Figure 5G As shown, the ESD-doped semiconductor layer 515 is heated to drive ions of a second conductivity type to diffuse throughout the semiconductor layer.

[0073] The top surface of the substrate composition is polished by CMP to remove the semiconductor material layer not in the ESD trench 510, forming the final shape of the ESD semiconductor layer 524. Figure 5HAs shown, after CMP, the nitride layer 513 and the upper ESD layer 514 are etched away from the area of ​​the substrate composition not covered by the ESD semiconductor layer 524. During the deposition of the lower ESD insulating layer 512, the silicon dioxide material 520 formed on the top surface of the substrate composition is protected by the nitride layer 513, which can serve as an etch stop layer.

[0074] Substrate 501 can be selectively doped with ions of a first conductivity type by ion implantation to form JFET region 530, followed by pre-body thermal drive; these steps are omitted in the formation of a single-gate transistor. Next, ions of a second conductivity type are implanted into substrate 501 by ion implantation to form body region 518, followed by rapid thermal annealing to further drive the ions into the substrate. One or more source regions 519 are implanted into the body region near the active gate trench 503 with a heavy doping concentration. Additionally, one or more ESD contact regions 517 are formed in the semiconductor material. If multiple ESD contact regions are formed, there should be sufficient space between these regions to allow each region to function as a junction diode without interference from other ESD contact regions. The semiconductor composition is then heated to drive the dopant in the source regions to diffuse deeper into the body region.

[0075] Finally, as Figure 5I As shown, a low-temperature oxide (LTO) is grown on the surface of the substrate composition, followed by the deposition of borosilicate glass (BPSG) and heating of the BPSG to allow an insulating layer to flow onto the substrate composition, forming the top portion of the ESD trench insulating layer 522 and the top gate insulating layer 521. The BPSG can also insulate portions of the substrate composition in the body region.

[0076] Vias can be created in the borosilicate glass layer via etching or mechanical drilling for source and ESD contacts. Next, one or more ESD direct contact regions 531 are implanted into the ESD contact region 516 with heavily doped ions of a first conductivity type, followed by rapid thermal annealing to diffuse the ions deeper into the ESD contact region. Finally, a conductive material 523 (such as a metal layer) can be deposited on the insulating layer and in the vias, contacting the source region 519, the body region 518, and the ESD trench contact region 516. The conductive material can be masked and etched to form the final layout of the conductive material layer 523. According to one aspect of this disclosure, the result of the above process is a transistor device with an improved ESD trench, including a nitride layer, and the active region gate trench extending deeper into the semiconductor substrate than the ESD trench.

[0077] Figure 6A –6G indicates an example of a method for manufacturing a transistor device, such as Figure 3As shown, the device features an improved ESD trench, including a nitride layer, and the active region is formed prior to the formation of the ESD trench. As... Figure 6A As shown, an ESD trench 602 is formed in a semiconductor substrate 601, after which an active gate trench is formed. The semiconductor substrate 601 may be provided, comprising a lightly doped epitaxial layer of a first conductivity type ions formed on top of a heavily doped layer of the first conductivity type. The semiconductor substrate 601 is masked with an oxide hard mask, and then the ESD trench 602 is etched using a suitable trench formation method (e.g., but not limited to, reactive ion etching).

[0078] After etching the ESD trench, a lower ESD trench insulating layer 605 is deposited on the top surface of the substrate composition (including the exposed surface in the trench). A nitride layer 606 is deposited on the lower ESD trench insulating layer 605. Then, an upper ESD trench insulating layer is deposited on the nitride layer 606. The nitride layer can be masked and patterned using any suitable type of masking and patterning method (e.g., but not limited to, photoresist masks or patterned masks for mechanical applications) for the active gate trench. After masking, the active gate trench 603 is etched into the semiconductor substrate 601 using any suitable etching method (e.g., but not limited to anisotropic etching processes such as RIE).

[0079] Then, a gate insulating layer 630 can be deposited on the top surface of the substrate composition and in the active gate trench 603. The deposited gate insulating material can increase the thickness of the top ESD trench insulating layer 607 in the ESD trench 602, as well as the thickness on the top surface of the substrate composition. The lower ESD trench insulating layer 605, the nitride layer 606, and the ESD trench insulating layer 607 can be made of, for example but not limited to, silicon dioxide, and formed by a suitable method (such as CVP). Next, an undoped polysilicon layer 604 is deposited on the exposed top surface of the entire substrate composition to form a precursor ESD semiconductor layer in the ESD trench 602. Finally, the upper portion U of the undoped polysilicon layer 604 can be doped with ions of a second conductivity type by ion implantation, and then the substrate composition is heated in a subsequent processing stage to drive the ions deeper into the precursor ESD semiconductor layer. The result is as follows: Figure 6B The trench transistor shown.

[0080] After doping and thermal drive, the top surface of the substrate composition can be selectively polished by CMP to remove polysilicon material not present in the ESD trench 602 or the active gate trench 603. Then, as... Figure 6C As shown, an ESD mask 609 is formed on the top surface of the ESD semiconductor layer 608. The ESD mask 609 can be any suitable type of patterned mask, applied by any suitable mask application and patterning method (e.g., but not limited to patterned photoresist masks).

[0081] The oxide layer 607 is then etched back from the exposed surfaces of the substrate composition (including around the polysilicon material 610 in the gate trench) using any suitable insulating etchant. The substrate composition is then polysilicon etched to remove the semiconductor material from the active gate trench 603, leaving undoped polysilicon material at the bottom of the active gate trench to form the shielding electrode 612. Alternatively, n-type ion implantation can be performed to dope the shielding electrode 612. In a single-gate electrode implementation, a different mask is used during the polysilicon etching process, and the material that will form the shielding electrode is etched away. After polysilicon etching, the ESD mask 609 is removed by any suitable method (e.g., chemical washing and / or CMP).

[0082] After removing the ESD mask 609, the pad oxide 607 is further wet-etched using any suitable etchant to create the desired thickness of the bottom insulating wall of the active gate trench 603. Next, as... Figure 6D As shown, an oxide layer 613 is grown on the sidewalls of the active gate trench, above the shielding electrode 612, on the top surface of the substrate, and on top of the ESD semiconductor layer 611 by thermal oxidation.

[0083] Next, as Figure 6E As shown, an n-doped polysilicon layer 614 is deposited on the top surface of the substrate composition (including the oxide layer 613 in the ESD trench and the active gate trench). This forms the etched active gate electrode 615. The n-doped polysilicon layer 614 can be deposited by any suitable method, such as, but not limited to, CVD.

[0084] A portion of the n-doped polysilicon layer 614 and the upper ESD insulating layer 607 are removed from the top surface of the substrate composition using CMP. The nitride layer 606 is then wet-etched using any suitable nitride etching process, removing it from the top surface of the substrate composition and exposing the lower ESD insulating layer on the top surface of the substrate composition. Furthermore, a polishing process removes a portion of the oxide layer 613 and the ESD semiconductor layer 611, leaving a relatively flat top surface of the ESD semiconductor layer 611. It is important to note that the ESD semiconductor layer and the ESD trench contour protect the upper ESD insulating layer 607 and the nitride layer 606 within the ESD trench from being removed.

[0085] The oxide layer is then etched back from the surface of the substrate composition using any suitable etch-back method. In embodiments with shielded electrodes, substrate 601 can be selectively doped with ions of a first conductivity type by ion implantation to form a JFET region, followed by pre-body thermal drive; these steps are omitted in the formation of a single-gate electrode transistor. Next, substrate 601 is doped with ions of a second conductivity type by ion implantation to form a body region 618. The substrate composition is then subjected to rapid thermal annealing to complete the body region. A source region 619 is formed by implanting a portion of the body region 618 near the active gate trench 603 with heavily doped first conductivity type ions (such as n-type ions). Furthermore, one or more ESD contact regions 617 are formed in the ESD semiconductor material 611. If multiple ESD contact regions are formed, there should be sufficient space between these regions so that each region can function as a junction diode without interference from other ESD contact regions. The substrate composition is then heated to drive the source region ions to diffuse into the body region and the ESD contact regions 617 into the ESD semiconductor material 611. Thus, as... Figure 6F The trench transistor shown.

[0086] like Figure 6G As shown, a low-temperature oxide (LTO) is grown on the surface of the substrate composition, followed by the deposition of borosilicate glass (BPSG) and heating of the BPSG to allow an insulating layer to flow onto the substrate composition, forming the top portion of the ESD trench insulating layer 621 and the top gate insulating layer 620. The borosilicate glass also insulates portions of the substrate composition in the bulk region.

[0087] Vias can be created in the borosilicate glass layer via etching or mechanical drilling for source and ESD contacts. Next, one or more ESD direct contact regions 631 are implanted into the ESD contact region 617 by heavily doping with ions of a second conductivity type, followed by rapid thermal annealing to diffuse the ions deeper into the ESD contact region 617. Finally, a conductive material 622 (such as a metal layer) can be deposited on the insulating layer and in the vias to contact the source region 619, the body region 618, and the ESD trench contact region 617. The conductive material can be masked and etched to form the final layout of the conductive material layers 622 and 622'. According to one aspect of this disclosure, the result of the above process is a transistor device with an improved ESD trench, including a nitride layer, and the active region is formed prior to the formation of the ESD trench.

[0088] Therefore, it is possible to fabricate a transistor device with a thick bottom insulating layer plus a nitride layer, which improves the resistance of the ESD structure to high voltage transient leakage into the active region and reduces the substrate area required for the ESD trench.

[0089] While the foregoing is a complete description of preferred embodiments of the invention, various alternatives, modifications, and equivalents may be used. Therefore, the scope of the invention should not be determined by reference to the foregoing description, but rather by reference to the full scope of the appended claims and their equivalents. Any feature described herein, whether preferred or not, may be combined with any other feature described herein, whether preferred or not. In the following claims, the indefinite article “A” or “An” refers to the number of one or more items following that clause, unless expressly stated otherwise. The appended claims should not be construed as including means plus functional limitations, unless such limitation is expressly stated in a given claim using the phrase “means”.

Claims

1. A method for fabricating a trench transistor with in-trench electrostatic discharge protection, comprising: including the steps of: a) forming an ESD trench in a semiconductor substrate, wherein the semiconductor substrate includes ions of a first conductivity type, and the ions of the first conductivity type are opposite to ions of a second conductivity type; b) forming a lower insulating layer of insulating material in the ESD trench of the semiconductor substrate; c) depositing a nitride layer on the lower insulating layer in the ESD trench of the semiconductor substrate; d) depositing an ESD semiconductor layer on the nitride layer in the ESD trench.

2. The method of claim 1, wherein, also including forming an oxide layer on the nitride layer prior to depositing the ESD semiconductor layer.

3. The method of claim 1, wherein, wherein a) further includes forming an active trench in the semiconductor substrate at the same time as the ESD trench.

4. The method of claim 1, wherein, also including forming an active trench prior to forming the ESD trench.

5. The method of claim 4, wherein, also including depositing an active trench insulating layer in the active trench of the semiconductor substrate prior to forming the ESD trench.

6. The method of claim 5, wherein, also including forming a gate conductive electrode in the active trench prior to forming the ESD trench.

7. The method of claim 1, wherein, also including e) doping the semiconductor ESD layer with ions of the second conductivity type.

8. The method of claim 7, wherein, also including f) doping one or more ESD contact regions in the ESD semiconductor layer with ions of the first conductivity type.

9. The method of claim 1, wherein, also including forming an active trench after forming the ESD trench.

10. The method of claim 9, wherein, also including polishing a top surface of the substrate to remove the ESD semiconductor layer from the top surface of the substrate, leaving ESD semiconductor layer material in the ESD trench, and applying an ESD etch mask on the ESD semiconductor layer material after polishing the top surface of the substrate.

11. The method of claim 9, wherein, also including applying an ESD etch mask on the ESD semiconductor layer material after polishing a top surface of the substrate.

12. The method of claim 9, wherein, also including etching away ESD semiconductor layer material from the active trench.

13. The method of claim 12, wherein, also including depositing a conductive material in the ESD semiconductor layer material at the same time as depositing a gate electrode material.

14. The method of claim 1, wherein, also including forming an ESD top insulating layer on the ESD semiconductor layer, and forming a source metal layer, wherein the ESD top insulating layer includes one or more spaces such that the source metal layer is in contact with the ESD semiconductor layer.

15. The method of claim 1, wherein, also including forming an upper insulating layer of insulating material on the nitride layer, and the ESD semiconductor layer is formed on the upper insulating layer.

16. A trench transistor, comprising: including: a semiconductor substrate including ions of a first conductivity type, wherein the ions of the first conductivity type are opposite to ions of a second conductivity type; an ESD trench formed in the semiconductor substrate; a lower insulating layer formed on a surface of the ESD trench of the semiconductor substrate; a nitride layer formed on the lower insulating layer in the ESD trench; an upper insulating layer formed on the nitride layer in the ESD trench; and an ESD semiconductor layer formed on the upper insulating layer. wherein an active trench extends deeper into the semiconductor substrate than the ESD trench.

17. The trench transistor of claim 16, wherein the gate oxide layer is formed of a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbide. wherein the ESD semiconductor includes a recess at a top surface interface.

18. The trench transistor of claim 16, wherein the gate oxide layer is formed of a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbide. wherein the nitride layer is only in the ESD trench.

19. The trench transistor of claim 16, wherein the gate oxide layer is formed of a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbide. ​ 20. The trench transistor of claim 16, wherein the gate oxide layer is formed of a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbide. wherein the ESD semiconductor layer is doped with ions of a second conductivity type and includes one or more ESD contact regions doped with ions of a first conductivity type, wherein the ESD contact regions function as cathodes of junction diodes formed between the ESD contact regions and the ESD semiconductor layer, and the ESD semiconductor layer functions as an anode.

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