SnS-WSe2 contact construction method based on thermal evaporation and application

Abstract

The application discloses a SnS-WSe2 contact construction method based on thermal evaporation and application, belongs to the field of two-dimensional semiconductor devices and contact engineering, and under the condition of high vacuum and low rate deposition, SnS is deposited on two-dimensional semiconductor WSe2 by using Co as a stabilizer through a thermal evaporation process to form a semiconductor-semiconductor van der Waals interface. The semiconductor property of SnS and the near-zero state density in the band gap are utilized to effectively inhibit metal-induced gap states; meanwhile, the low melting point property of SnS is beneficial to obtain a clean contact interface and reduce defect-induced gap states, thereby significantly weakening Fermi level pinning, realizing a near-zero hole injection barrier and ideal ohmic contact. Compared with commonly used high work function metal contact, the application can realize efficient hole injection and low contact resistance without additional doping treatment, the process flow is simple, compatible with the existing micro-nano processing technology, and suitable for high-performance two-dimensional p-FET and scalable two-dimensional CMOS integration.

Description

Technical Field

[0001] This invention belongs to the field of two-dimensional semiconductor devices and contact engineering, specifically relating to a method for constructing SnS-WSe2 semiconductor-to-semiconductor van der Waals contacts using a Co-doped stable evaporation source and its application in high-performance p-type WSe2 transistors. Background Technology

[0002] Two-dimensional semiconductors, due to their atomic-level thickness and lack of dangling bonds on the surface, are considered key candidate materials for realizing high-performance, low-power FETs. Although n-type devices based on MoS2 channels and semi-metallic contacts have approached the International Equipment and Systems Roadmap (IRDS) benchmark, the development of 2D CMOS (Complementary Metal Oxide Semiconductor) remains constrained by p-type contacts. The root cause lies in Fermi level pinning caused by interface states: on the one hand, the continuous band structure of conventional metals generates wavefunction penetration at the interface, forming metal-induced gap states (MIGS); on the other hand, high-energy deposition of high-melting-point metals (such as Pd and Pt) easily leads to two-dimensional lattice damage, generating defect-induced gap states (DIGS). While metal transfer can alleviate DIGS, it is incompatible with extreme scaling and large-scale manufacturing, and typically introduces an interface distance larger than the intrinsic van der Waals (vdW) gap, thereby increasing tunneling impedance. Simultaneously, suitable semi-metallic contact materials are lacking. Therefore, a scalable p-type contact path that can simultaneously suppress MIGS / DIGS is urgently needed.

[0003] To this end, this invention proposes a semiconductor-semiconductor van der Waals (SS vdW) contact: using a three-dimensional semiconductor SnS to form a contact with a two-dimensional semiconductor WSe2, which can effectively suppress Fermi level pinning. This contact strategy has three advantages: (1) SnS, as a semiconductor, has a near-zero density of states in its bandgap, which can fundamentally avoid MIGS when used as a contact layer; (2) SnS has low melting point and low boiling point, and can be thermally evaporated and deposited under "low energy" conditions. Compared with traditional metals (such as Pd or Pt), it is easier to obtain an atomically clean vdW interface with fewer defects, thereby significantly suppressing DIGS; (3) There is a favorable band alignment between p-type SnS and WSe2, which can achieve a near-zero hole injection barrier. As a result, the WSe2 field-effect transistor with SnS contact exhibits a stable p-type ohmic contact, providing a feasible process route for high-performance 2D p-FET and 2D CMOS integration. Summary of the Invention

[0004] This invention aims to solve the long-standing contact problem in two-dimensional semiconductor p-type field-effect transistors (FETs). The root cause of this problem lies in the Fermi level pinning caused by the combined effects of metal-induced gap states and defect-induced gap states, which makes p-type hole injection difficult and contact resistance hard to reduce, thus restricting the scalable integration and industrialization of 2D CMOS.

[0005] The technical solution of the present invention is as follows:

[0006] This invention first discloses a method for constructing SnS-WSe2 contact based on thermal evaporation, including the following steps:

[0007] 1) Fabrication of two-dimensional material substrates:

[0008] The mechanical exfoliation technique is used to obtain a target number of two-dimensional materials as a substrate from a bulk material. Specifically, the mechanical exfoliation method involves placing a WSe2 or h-BN bulk material on an adhesive tape, repeatedly peeling and sticking the tape, then attaching the tape to a flat, viscous dielectric (PDMS) film (corresponding to the material area on the tape). After removing the tape, the target substrate (silicon wafer) is attached to the PDMS film coated with the two-dimensional material. After a period of time, the substrate is removed, and the target number of two-dimensional materials on the silicon wafer can be identified under an optical microscope.

[0009] 2) Preparation of SnS thin films using a Co-doped SnS composite evaporation source:

[0010] The substrate was placed in a high-vacuum chamber for thermal evaporation. Several Co-doped SnS composite evaporation sources were placed on a tungsten boat, and the vacuum was evacuated to a base pressure ≤ 1 × 10⁻⁶. -4 Pa, slowly apply current up to 90 A, so that the SnS evaporation rate stabilizes at ~0.1 Å / s.

[0011] The present invention also discloses a SnS contact WSe2 transistor prepared based on the above method, comprising:

[0012] A few layers of h-BN are used as the substrate isolation layer;

[0013] Two layers of WSe2 serve as the active region;

[0014] SnS source and drain electrodes deposited by Co-doped SnS composite evaporation source;

[0015] The transistor has an on / off ratio ≥1×10⁻⁶ at room temperature. 9 The conduction current is ≥20 μA / μm, the hole barrier height is 20meV, and the contact resistance is as low as 292 Ω·μm.

[0016] This invention also discloses the application of a Co-doped SnS composite evaporation source in suppressing SnS evaporation instability. By fixing part of Sn with Co to form a solid phase residue, the SnS / S2 gas phase component is selectively released, thereby stabilizing the evaporation rate at 0.1 Å / s.

[0017] The present invention also discloses the application of the above-described transistor in two-dimensional CMOS integrated circuits.

[0018] Beneficial effects:

[0019] 1) Co doping stabilizes SnS evaporation flux and stoichiometry, solving the problem of evaporation stability.

[0020] This invention employs a Co-doped SnS composite evaporation source, which, during heating, causes Co to form a solid residue with a portion of Sn, while selectively releasing the SnS / S2 gaseous component. This locks the effective chemical potential of Sn and S, maintaining stable evaporation flux and film stoichiometry. This is achieved within a high vacuum, low-rate window (e.g., base pressure ≤ 1 × 10⁻⁶). -4 At Pa and a deposition rate of approximately 0.1 Å / s, the consistency between the rate and composition can be maintained for a long period of time.

[0021] 2) SnS-WSe2 contacts can form atomically clean SS van der Waals interfaces, significantly reducing Fermi pinning.

[0022] Under stable evaporation conditions, semiconductor SnS is directly deposited on the WSe2 surface, constructing semiconductor-semiconductor van der Waals contacts. Mechanistically, SnS, being a semiconductor, has a near-zero density of states within its bandgap, which fundamentally suppresses metal-induced interstitial states; simultaneously, low-energy deposition significantly reduces defect-induced interstitial states. The synergistic effect of these two factors effectively weakens Fermi level pinning, achieving a near-zero hole injection barrier and improving p-type carrier injection efficiency.

[0023] 3) High-performance p-type WSe2 transistor based on SnS contact.

[0024] The WSe2FET constructed based on the above stable process and ideal interface exhibits a high-performance p-type ohmic contact and a low hole Schottky barrier (Φ). B ≈ 43 meV), high on-state current (I ON = 20 μA·μm -1 V DS = 1 V, L CH = 1 μm), large on / off ratio (I ON / I OFF > 10 9 ), and the contact resistance is extremely low (R C(≈ 292 Ω·μm). Compared with commonly used high work function metals (such as Pd, Pt) contacts, the solution of this invention exhibits a lower injection barrier and better contact resistance under the same device geometry, demonstrating advantages in MIGS / DIGS synchronization suppression and interface engineering; moreover, the entire process is based on PVD (physical vapor deposition), CMOS compatible, and BEOL (back end of line) friendly, meeting the requirements of 2D p-FET and 2D CMOS integration for low power consumption and large-scale manufacturing. Attached Figure Description

[0025] Figure 1 Schematic diagram of the structure of the Co-doped SnS composite evaporation source and deposition process.

[0026] Figure 2 XRD (X-ray diffraction analysis) pattern of SnS thin film.

[0027] Figure 3 STEM (high-resolution transmission electron microscopy) analysis of SnS thin films.

[0028] Figure 4 Comparison of XPS (X-ray photoelectron spectroscopy) tests of WSe2 before and after SnS evaporation.

[0029] Figure 5 Transfer characteristic curves and output characteristic curves of SnS-WSe2 transistors.

[0030] Figure 6 Schottky barrier height of SnS contact device.

[0031] Figure 7 Extraction of contact resistance of SnS-WSe2 transistor. Detailed Implementation

[0032] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. However, the following embodiments are only for explaining the present invention, and the scope of protection of the present invention should include all the contents of the claims. Moreover, through the description of the following embodiments, those skilled in the art can fully implement all the contents of the claims of the present invention.

[0033] Example 1

[0034] This embodiment provides a SnS-WSe2 contact construction method based on thermal evaporation, and the specific steps are as follows:

[0035] Preparation of two-dimensional semiconductor substrates: WSe2 thin films with the target number of layers were prepared on Si / SiO2 substrates by mechanical exfoliation.

[0036] Sample loading and vacuuming: The WSe2 / Si / SiO2 substrate prepared in step 1 is placed in a high-vacuum thermal evaporation chamber. The base pressure of the chamber is controlled at ≤1×10⁻⁶. -4 The level of Pa.

[0037] Thermal evaporation deposition of SnS: A Co-doped SnS composite evaporation source was used for thermal evaporation to deposit a SnS thin film on the surface of the WSe2 sheet. This process aims to form the SS vdW interface.

[0038] Evaporation source mechanism: During the heating process of this evaporation source, Co reacts with some Sn to form a solid residue, while selectively releasing the SnS / S2 gaseous component. This mechanism effectively stabilizes the stoichiometry of Sn and S and ensures the stability of the evaporation flux (e.g., a stable evaporation rate of about 0.1 Å / s can be achieved).

[0039] Thin film characteristics: It is worth noting that Co does not co-evaporate with SnS during the deposition process and enter the final film. Therefore, the resulting SnS film is phase-pure SnS.

[0040] Interface characterization: X-ray photoelectron spectroscopy (XPS) and scanning transmission electron microscopy (STEM) confirmed that no chemical reaction occurred at the constructed SnS-WSe2 interface, confirming it as an atomically clean van der Waals (vdW) contact interface.

[0041] SnS contact WSe2 transistor prepared according to the above method based on the embodiments

[0042] This embodiment further provides a SnS contact WSe2 transistor prepared using the above method. The transistor structure includes:

[0043] Substrate isolation layer: A few layers of h-BN are used as the substrate isolation layer.

[0044] Active region: The active channel region of a transistor consisting of two WSe2 layers.

[0045] Source and drain electrodes: These are formed by patterning using electron beam lithography and depositing a SnS thin film using a Co-doped SnS composite evaporation source.

[0046] Transistor performance:

[0047] This transistor exhibits excellent electrical performance at room temperature:

[0048] On / off ratio (I) on / I off )≥1×10 9 ;

[0049] On-current (I) on≥20 μA / μm;

[0050] The hole barrier height is 20 meV;

[0051] The contact resistance is as low as 292 Ω·μm. Furthermore, the transistor's output characteristic curve exhibits linearity above a preset threshold, indicating the formation of a good ohmic contact. In the field of semiconductor devices (especially two-dimensional material devices), the standard unit for contact resistance is ohms multiplied by micrometers (Ω·μm), where Ω·μm represents the contact resistance value per unit width (per micrometer of channel width). For example, a contact resistance of 292 Ω·μm means that when the channel width is 1 μm, the contact resistance is 292 Ω.

[0052] This embodiment also provides the application of the SnS contact WSe2 transistor in a two-dimensional CMOS integrated circuit.

[0053] Example 2

[0054] This embodiment provides a evaporation process for preparing high-quality SnS semiconductors using Co doping. SnS contacts can be used to realize high-performance p-type WSe2 transistors. The specific fabrication steps are as follows:

[0055] 1. Co-doped SnS composite evaporation source deposition:

[0056] To determine the crystallinity of the prepared SnS thin film, X-ray diffraction was used in this embodiment for crystallinity analysis. In process-compatible physical vapor deposition (PVD), the evaporation rate of SnS can be significantly unstable because its vapor pressure varies exponentially, and the evaporation coefficient is affected by surface stoichiometry and morphology. Therefore, the relationship between evaporation flux and temperature (lnJ⁻¹ / T) exhibits piecewise linearity and drift. To stabilize the evaporation process, this embodiment developed a method using high-melting-point Co as a stabilizer, namely, using a Co-doped SnS composite evaporation source (e.g., Figure 1 As shown in the figure, upon heating, Co fixes part of Sn as a Co-Sn solid residue, while simultaneously releasing gaseous SnS / S2, thereby stabilizing the effective chemical potential of Sn and S, resulting in a SnS evaporation rate that is stable at ~0.1 Å / s. XRD confirmed that Co only acts as a stabilizer and is not co-evaporated; the resulting film is still pure SnS (as shown in the figure). Figure 2 (As shown).

[0057] 2. Characterization of the SnS-WSe interface:

[0058] To evaluate the interfacial properties of the SnS-WSe2 contact, scanning transmission electron microscopy was performed in this embodiment. Sn and S atoms grew in an ordered layered structure on the surfaces of the two WSe2 layers and were in close contact with WSe2, forming a sharp and clean semiconductor-semiconductor interface. This confirms that the SnS-WSe2 interface is an ideal van der Waals contact interface (e.g., ...). Figure 3 (As shown). To further verify the interfacial chemical state, XPS analysis was performed in this example, and the core energy levels of 2L WSe2 before and after deposition of ~1 nm SnS were compared. For pristine WSe2, 4f W +4 (32.4 and 34.58 eV) and 3d Se -2 The apparent doublet at (54.63 and 55.49 eV) coincides with the energy positions of 2H-WSe2. However, after SnS deposition, the binding energy of W4f and Se3d remains unchanged within the experimental resolution, with no significant chemical shift or new chemical state composition (e.g., ...). Figure 4 (As shown). These results indicate the absence of detectable interfacial reactions or strong couplings, consistent with STEM analysis.

[0059] 3. Fabrication and electrical performance characterization of ultra-low contact resistance field-effect transistors:

[0060] 1) Fabrication of SnS-WSe2 field-effect transistors:

[0061] In this embodiment, the fabrication process of the SnS-WSe2 field-effect transistor includes patterning of the two-dimensional semiconductor WSe2 and construction of high-quality single-crystal metal source and drain electrodes. First, a few-layer h-BN film is obtained on a SiO2 / Si substrate using a mechanical lift-off method as an isolation layer to reduce substrate-induced doping and interface scattering. Then, 2L WSe2 is transferred onto the h-BN with PDMS assistance. Subsequently, polymethyl methacrylate (PMMA) is uniformly spin-coated onto the substrate surface (spray coating parameters: 500 rpm, 5 s; 4000 rpm, 40 s), and then baked on a hot plate at 150 °C for 5 minutes to cure the photoresist layer. Electron beam lithography (EBL) is used to precisely define the source and drain electrode patterns at both ends of the 2L WSe2 active region. The contact electrodes are deposited using a Co-doped SnS composite evaporation source, sequentially depositing a 20 nm thick SnS layer and a 20 nm thick Au protective layer. Finally, the photoresist is removed by immersion in acetone solution combined with rinsing with isopropanol, achieving pattern lift-off and completing device fabrication. The semiconductor SnS and WSe2 can form an atomically clean and flat van der Waals contact interface, which makes it possible to realize high-performance, low-contact-resistance devices.

[0062] 2) Transfer characteristic curve and output characteristic curve test:

[0063] WSe2 transistors employing SnS contacts exhibit excellent p-type field-effect device characteristics (e.g. Figure 5 As shown). At the source-drain bias V DS At 1V, the conduction current is 20μA / μm, and the on / off ratio is as high as 1.3×10⁻⁶. 9 This significantly outperforms traditional high work function metal (Pt, Pd) contact devices. Due to the undoped solid-state channels and efficient hole injection, the transistor exhibits enhancement-mode p-type behavior. Furthermore, the output curves at different gate voltages are highly linear, confirming the formation of a good ohmic contact and providing crucial support for realizing high-performance, low-power p-type two-dimensional semiconductor devices.

[0064] 3) Schottky barrier height extraction:

[0065] Schottky barrier height (Φ) B Extracting (e.g., from the Arrhenius fitting curve under varying temperatures) Figure 6 As shown, SBH Hole V represents the Schottky Barrier Height for holes. GS (Gate-Source Voltage). The results show that the semiconductor SnS contact device exhibits a Schottky barrier characteristic close to zero, indicating that an ideal ohmic contact is formed between SnS and the two WSe2 layers. This is mainly attributed to two aspects: (1) SnS has semiconductor properties, with a zero density of states in the band gap, which can effectively suppress metal-induced gap states; (2) Co-doped SnS composite evaporation source deposition can realize an atomically neat, ordered and clean semiconductor-semiconductor van der Waals contact interface on the two-dimensional semiconductor surface, with an extremely low interface defect state density, effectively reducing defect-induced gap states. Both significantly alleviate Fermi level pinning, which is beneficial for realizing ohmic contacts. This verifies the unique advantages and industrial value of the semiconductor-semiconductor van der Waals contact strategy adopted in this invention in constructing a low-barrier, ideal contact interface.

[0066] 4) Transmission line method for extracting contact resistance (R) C ):

[0067] To accurately assess the contact quality of the device, this embodiment uses the transmission line method to extract and analyze the contact resistance (e.g., Figure 7 As shown), the R of the WSe2 FET with SnS contact. C The resistance is as low as 292 Ω·μm. This performance is leading among currently reported two-dimensional semiconductor p-type contact technologies, significantly outperforming traditional high work function metal Pd and Pt contact strategies. This demonstrates the unique advantages of the SnS semiconductor-to-semiconductor contact of this invention in achieving low-resistance and high-efficiency hole injection, suppressing MIGS and DIGS at the source, and eliminating Fermi level pinning.

[0068] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for constructing SnS-WSe2 contact structures based on thermal evaporation, characterized in that, Includes the following steps: (1) Fabrication of two-dimensional semiconductor substrate: The target number of WSe2 layers is obtained on a Si / SiO2 substrate by mechanical exfoliation; (2) Place the substrate in a high-vacuum thermal evaporation chamber; (3) SnS is thermally evaporated and deposited on the surface of the two-dimensional semiconductor substrate using a Co-doped SnS composite evaporation source to form an S-SvdW interface; During the heating process, the Co-doped SnS composite evaporation source forms a solid residue with some Sn and releases SnS / S2 gaseous components, thereby stabilizing the chemical formulas of Sn and S and obtaining a stable evaporation flux.

2. The method according to claim 1, characterized in that, The cavity base pressure is ≤1×10 -4 Pa.

3. The method according to claim 1, characterized in that, Co does not co-evaporate with SnS into the film during the deposition process, and the resulting film is phase-pure SnS.

4. The method according to claim 1, characterized in that, X-ray photoelectron spectroscopy and STEM verification showed that the SnS-WSe2 interface had no chemical reaction and was an atomically clean vdW contact interface.

5. A SnS-contact WSe2 transistor prepared according to the method of any one of claims 1-4, characterized in that, include: A few layers of h-BN are used as the substrate isolation layer; Two layers of WSe2 serve as the active region; SnS source and drain electrodes deposited by Co-doped SnS composite evaporation source; The transistor has an on / off ratio ≥1×10⁻⁶ at room temperature. 9 The conduction current is ≥20 μA / μm, the hole barrier height is 20 meV, and the contact resistance is as low as 292 Ω·μm.

6. The transistor according to claim 5, characterized in that, The source and drain electrodes are formed by electron beam exposure patterning and Co-doped SnS composite evaporation source deposition.

7. The transistor according to claim 5, characterized in that, The linearity of the transistor's output characteristic curve is higher than a preset linearity threshold, indicating the formation of an ohmic contact.

8. The application of the transistor according to any one of claims 5-7 in a two-dimensional CMOS integrated circuit, characterized in that, By fixing a portion of Sn with Co to form a solid-phase residue, the SnS / S2 gas phase components are selectively released, achieving an evaporation rate stable at 0.1 Å / s.

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