Extended processing circuit activation

Abstract

Apparatuses, methods, computer programs, and computer-readable media of data processing are disclosed. A data processing pipeline performs data processing operations defined by a received sequence of instructions. Extension processing circuitry associated with the data processing pipeline performs a delegation task in response to a delegation signal received from the data processing pipeline, the delegation task being performed asynchronously with the data processing pipeline. The data processing pipeline performs speculative instruction execution. In response to an extension start instruction, the data processing pipeline issues the delegation signal to the extension processing circuitry to delegate the delegation task, and the extension processing circuitry responds by starting the delegation task before generating a speculative acknowledgement for the extension start instruction. The extension processing circuitry ensures that results generated by the delegated task are invisible outside the extension processing circuitry until the speculative confirmation is generated for the extension start instruction.

Description

[0001] The present technology relates to an apparatus, a method of operating an apparatus, a computer program and a computer readable medium.

[0002] An apparatus can comprise a data processing pipeline configured to perform data processing operations in accordance with a received sequence of instructions.

[0003] At least some examples provide an apparatus for data processing, the apparatus comprising:

[0004] a data processing pipeline configured to perform data processing operations in accordance with a received sequence of instructions, wherein the data processing pipeline comprises a decode circuit configured to decode the received sequence of instructions and generate control signals to control the data processing pipeline to perform the data processing operations; and

[0005] an extension processing circuit associated with the data processing pipeline and configured to perform a delegated task in response to a delegation signal received from the data processing pipeline, wherein the extension processing circuit is configured to perform the delegated task asynchronously to the data processing operations performed by the data processing pipeline,

[0006] wherein the data processing pipeline is configured to perform speculative instruction execution, whereby modifications to a state of the apparatus resulting from execution of a speculatively executed instruction are not committed until a speculation acknowledgement is generated indicating that execution of the speculatively executed instruction was correct,

[0007] wherein the decode circuit generates the control signals to control the data processing pipeline to issue the delegation signal to the extension processing circuit to delegate the delegated task in response to an extension start instruction specifying the delegated task,

[0008] and wherein the extension processing circuit starts the delegated task in response to the delegation signal before the speculation acknowledgement is generated for the extension start instruction,

[0009] whereby the extension processing circuit is configured to ensure that results generated by the delegated task are not visible outside the extension processing circuit until the speculation acknowledgement is generated for the extension start instruction.

[0010] At least some examples provide a non-transitory computer readable medium for storing computer readable code for manufacturing the apparatus.

[0011] At least some examples provide a method of operating an apparatus, the method comprising:

[0012] performing data processing operations in a data processing pipeline in accordance with a received sequence of instructions;

[0013] decoding the received instruction sequence in a decode circuit of the data processing pipeline and generating control signals to control the data processing pipeline to perform the data processing operation;

[0014] performing a delegated task in extension processing circuitry associated with the data processing pipeline in response to a delegation signal received from the data processing pipeline, wherein the delegated task is performed asynchronously to the data processing operation performed by the data processing pipeline;

[0015] performing speculative instruction execution in the data processing pipeline whereby modifications to the state of the apparatus resulting from execution of the speculatively executed instructions are not committed until a speculation acknowledgement is generated indicating that execution of the speculatively executed instructions was correct;

[0016] in response to an extension start instruction specifying the delegated task, generating the control signals to control the data processing pipeline to issue the delegation signal to the extension processing circuitry to delegate the delegated task;

[0017] in response to the delegation signal, starting the delegated task in the extension processing circuitry before the speculation acknowledgement is generated for the extension start instruction; and

[0018] ensuring that results generated by the delegated task are not visible to the data processing pipeline until the speculation acknowledgement is generated for the extension start instruction.

[0019] At least some examples provide a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising:

[0020] data processing pipeline logic configured to perform a data processing operation in accordance with a received instruction sequence, wherein the data processing pipeline logic comprises decode logic configured to decode the received instruction sequence and generate control signals to control the data processing pipeline logic to perform the data processing operation; and

[0021] extension processing logic associated with the data processing pipeline logic and configured to perform a delegated task in response to a delegation signal received from the data processing pipeline logic, wherein the extension processing logic is configured to perform the delegated task asynchronously to the data processing operation performed by the data processing pipeline logic,

[0022] wherein the data processing pipeline logic is configured to perform speculative instruction execution whereby modifications to the state of the instruction execution environment caused by execution of speculatively executed instructions are not committed until a speculation confirmation is generated indicating that execution of the speculatively executed instructions was correct,

[0023] wherein the decode logic generates the control signal to control the data processing pipeline logic to issue the delegation signal to the extension processing logic to delegate the delegated task in response to an extension start instruction specifying the delegated task,

[0024] and wherein the extension processing logic, in response to the delegation signal, starts the delegated task before the speculation confirmation is generated for the extension start instruction,

[0025] whereby the extension processing logic is configured to ensure that results generated by the delegated task are not visible to the data processing pipeline logic until the speculation confirmation is generated for the extension start instruction.

[0026] The present technology will be further described, by way of example only, with reference to the accompanying drawings in which embodiments thereof are illustrated as follows:

[0027] Figure 1 schematically illustrates a data processing apparatus in which various examples of the present technology can be embodied;

[0028] Figure 2 schematically illustrates a data processing apparatus in which various examples of the present technology can be embodied;

[0029] Figure 3 schematically illustrates a data processing apparatus in which various examples of the present technology can be embodied;

[0030] Figure 4 is a state diagram illustrating a set of example states between which extension processing circuitry embodying the present technology can transition;

[0031] Figure 5 schematically illustrates an extension start instruction present on a predicted branch path during speculative instruction execution in accordance with some examples;

[0032] Figure 6 schematically illustrates a data processing apparatus comprising confidence calibration circuitry in which various examples of the present technology can be embodied;

[0033] Figure 7 schematically illustrates a confidence calibration circuit in accordance with some examples that modifies or replaces branch predictions generated in a data processing pipeline for use by extension processing circuitry;

[0034] Figure 8extension set instruction to cause extension processing circuitry to perform one or more preparation steps according to some examples;

[0035] Figure 9 extension set instruction to cause extension processing circuitry to perform one or more preparation steps according to some examples;

[0036] Figure 10 extension set instruction to cause extension processing circuitry to perform one or more preparation steps according to some examples;

[0037] Figure 11 is a flow diagram showing a sequence of steps taken in a method of some examples; and

[0038] Figure 12 illustrating a simulator implementation that can be used.

[0039] In one example herein, there is an apparatus for data processing, the apparatus comprising:

[0040] a data processing pipeline configured to perform data processing operations according to a received sequence of instructions, wherein the data processing pipeline comprises a decode circuit configured to decode the received sequence of instructions and generate control signals to control the data processing pipeline to perform the data processing operations; and

[0041] extension processing circuitry associated with the data processing pipeline and configured to perform a delegated task in response to a delegation signal received from the data processing pipeline, wherein the extension processing circuitry is configured to perform the delegated task asynchronously from the data processing operations performed by the data processing pipeline,

[0042] wherein the data processing pipeline is configured to perform speculative instruction execution whereby modifications to a state of the apparatus resulting from execution of a speculatively executed instruction are not committed until a speculation acknowledgement is generated indicating that execution of the speculatively executed instruction was correct,

[0043] wherein the decode circuit generates the control signals to control the data processing pipeline to issue the delegation signal to the extension processing circuitry to delegate the delegated task in response to an extension start instruction specifying the delegated task,

[0044] and wherein the extension processing circuitry starts the delegated task in response to the delegation signal before the speculation acknowledgement is generated for the extension start instruction,

[0045] Thereby the extension processing circuit is configured to ensure that results generated by the delegated task are not visible outside the extension processing circuit until the speculation confirmation is generated for the extension start instruction.

[0046] Devices comprising data processing pipelines can need to perform an infinite variety of data processing operations as defined by instruction sequences provided thereto. To efficiently perform those data processing operations, the data processing pipeline can be configured with a variety of functional units each having a given special type of data processing capability, such as an arithmetic logic unit (ALU), a floating point (FP) unit, a load / store unit, and so on. However, even though such special functional units are provided as part of the data processing pipeline, the inventors of the present technology have determined that in certain types of data processing, i.e., in certain programs (i.e., instruction sequences), there can be specific functions that are frequently performed and require a certain amount of processing such that it is worth providing custom hardware dedicated to support these functions as this can greatly improve the overall performance of the device. In identifying such functions, two key properties are considered as relevant: the ubiquity of the function (i.e., the function can also be found in many other use cases); and the impact of the function (i.e., the proportion of time spent executing such functions takes a large percentage of the overall run time such that improvements in the execution of this function have a large impact on the overall use case). Such impactful and ubiquitous functions have been found to include tasks or functions such as memcpy, memset, compression, encryption, and string processing, although the present technology is not limited to these particular examples. The present technology provides an extension processing circuit that is associated with the data processing pipeline and is configured to perform such functions (delegate tasks) in response to a delegation signal received from the data processing pipeline. Such extension processing circuit can also be referred to herein as a small thread extension (TE). The sequence of operations it goes through in order to perform the defined function can also be referred to herein as a small thread. Although the extension processing circuit is closely associated with (tightly coupled to) the data processing pipeline, the extension processing circuit is configured to perform the delegate tasks asynchronously from the data processing operations performed by the data processing pipeline. The data processing pipeline can also be referred to herein as a CPU. A small thread is a set of functions or operations that can be executed asynchronously with respect to other CPU activity once started. The asynchronous operation of the extension processing circuit with respect to the data processing pipeline is possible because, unlike some prior art, the extension processing circuit receives instructions or commands from the thread currently executing on the CPU and independently performs the required operations, i.e., without the need for direct control from the CPU or instruction stream influencing its internal operations. Thus, the CPU is free to continue executing other code and potentially reduce the overall run time by overlapping the execution of the instruction stream with the operations of the extension processing circuit after the instructions or commands have been sent to the extension processing circuit.While the ability of the extension processing circuitry to operate asynchronously with respect to the data processing pipeline is thus advantageous, the inventors of the present technology have observed that when the data processing pipeline is configured to perform speculative instruction execution, in the case where a task is delegated from the data processing pipeline to the extension processing circuitry, if the speculative execution requires restriction, then efficient use of the data processing pipeline can be disruptive. However, such restriction of the extent of speculative execution is indeed a standard approach in the prior art when tasks are offloaded to dedicated hardware coupled to the processor. For example, it is common to deploy a dispatch fence, or to enforce a requirement to drain the re-order buffer (ROB) in the vicinity of a special offload instruction, which can have an adverse impact on performance.

[0047] In the case where the granularity of the tasks performed by the small threads is low, such an approach of disabling speculation or starting the small thread only after a speculation fence can be detrimental to performance. The reason for this is that an out-of-order processor develops considerable "momentum" during its operation, i.e. the out-of-order processor builds up a lot of related state within its pipeline, which generally takes a lot of cycles to regenerate when an exceptional event such as a speculation fence or pipeline flush occurs. The impact of this effect will depend on a number of factors, such as the size of the re-order buffer (instruction window), the number of issue slots, the number of functional units, the extent of speculation enabled by the branch prediction circuitry, the rate of conflict between newer loads and older stores, etc.

[0048] Accordingly, the present technology adopts an alternative approach which enables the start of execution of a small thread to be speculative. That is, when an extension start instruction is encountered in an instruction sequence, it is not required that the extension start instruction be committed before the extension processing circuitry starts to delegate tasks, but rather the extension processing circuitry can speculatively start to delegate tasks. A countermeasure provided to ensure that this approach does indeed cause problems is that the extension processing circuitry is configured to ensure that results generated by the delegated tasks are not visible outside the extension processing circuitry until a speculation confirmation is generated for the extension start instruction. Any new state generated by the delegated tasks is confined within the extension processing circuitry.

[0049] If the extension start instruction is committed, the extension processing circuitry is signalled the fact, and then the extension processing circuitry can begin to clear parts of its L1 cache or other internal buffers. However, if the extension start instruction is cancelled, the extension processing circuitry is also signalled the fact, and so in such cases the data processing pipeline is configured to generate a speculation cancellation when it determines that execution of a speculatively executed instruction is incorrect, and wherein the extension processing circuitry invalidates any results generated by the delegated task in response to a speculation cancellation being generated for the extension start instruction. Thus, the extension processing circuitry performs a rollback by invalidating any modifications made, such as in its L1 cache, deleting any information gathered during the set-up operation, such as TLB entries, and reverting to an idle state.

[0050] The extension processing circuitry can keep such results internally in a variety of ways, but in some examples the extension processing circuitry comprises a private data store configured to hold results generated by the delegated task. Note that in general the term "results" is used herein to apply to the product of a data processing task performed by the extension processing circuitry, and it is limited in accordance with the present technology to being within the extension processing circuitry and not visible to the rest of the device until a speculation confirmation is generated for the extension start instruction. In contrast, in general the term "output" is used for the case that the product of a data processing task performed by the extension processing circuitry is released from the extension processing circuitry or becomes accessible outside of the extension processing circuitry.

[0051] The capacity of the extension processing circuitry to hold its newly generated state is necessarily limited, and so in some examples the extension processing circuitry suspends execution of the delegated task in response to the results generated by the delegated task reaching the results storage capacity of the private data store. The extension processing circuitry then remains suspended until the extension start instruction is committed or cancelled.

[0052] For a data processing pipeline that performs speculative instruction execution, the decision about which branch outcome to execute speculatively is generally based on branch confidence information generated by a branch prediction circuit based on previous execution history. Furthermore, the branch confidence information can also be tuned based on a cost-benefit analysis made from the perspective of the data processing pipeline. However, the present technology recognises that such branch confidence information and such cost-benefit analysis can not be so suitable for the extension processing circuitry. In short, the speculation cost of the extension processing circuitry can be different to the speculation cost of the rest of the device. In view of this, in some examples the data processing pipeline comprises a branch prediction circuit configured to generate branch confidence information indicating a predicted likelihood of a branch direction being taken, wherein the data processing pipeline is configured to perform the speculative instruction execution in accordance with the branch confidence information,

[0053] and wherein the apparatus further comprises a confidence calibration circuit configured to generate extension-oriented confidence information associated with the extension start instruction,

[0054] wherein the extension processing circuit is configured to determine whether to start the delegated task prior to generating the speculation confirmation for the extension start instruction in dependence on the extension-oriented confidence information.

[0055] This enables the decision about whether to speculatively start the extension processing circuit to take into account specific costs and benefits with respect to the extension processing circuit. The approach recognizes that there is potentially a higher loss in wasted system bandwidth and power, among other things, when the extension processing circuit is speculatively started when it should not be started, as compared to a general CPU instruction. On the other hand, when the extension processing circuit is not speculatively started at the appropriate time when it should be started, then there is a potentially lost opportunity for performance because it can take many cycles to complete the setup of the extension processing circuit. Thus, the generated extension-oriented confidence information can provide a more customized prediction of allowable speculation depth than what a branch predictor can generally provide. For example, the confidence computation can be used to throttle a pre-fetcher or determine how far into the execution of the extension processing circuit to progress before stalling in order to wait for further confirmation of the speculative result from the data processing pipeline.

[0056] The confidence calibration circuit can be arranged to generate the extension-oriented confidence information in dependence on a plurality of pre-defined parameters, observed run-time metrics, and / or other characteristics or factors related to the extension processing circuit. Accordingly, in some examples, the confidence calibration circuit is configured to generate the extension-oriented confidence information in dependence on the branch confidence information and in dependence on at least one extension processing circuit specific factor.

[0057] In some examples, the confidence calibration circuit is configured to generate the extension-oriented confidence information in dependence on a relative size of the delegated task.

[0058] In some examples, the confidence calibration circuit is configured to generate the extension-oriented confidence information in dependence on an execution history of a portion of an instruction sequence that includes the extension start instruction. Execution path statistics can be collected around a call site in which one or more extension start instructions occur, and the extension-oriented confidence information is generated based at least in part on the statistics.

[0059] In some examples, the confidence calibration circuitry is configured to generate the extension-directed confidence information in dependence on a history of suspensions of the extension processing circuitry. This can be a recent history of suspensions or a relevant history (e.g. a recent history of suspensions or a relevant history of executing the same part of the code). Thus, the confidence calibration circuitry can monitor the frequency of suspensions in the extension processing circuitry, where one cause of such suspensions can be a storage limit of the extension processing circuitry for holding speculatively generated state. If such limits are reached too frequently, resulting in corresponding suspensions, then the threshold for triggering speculative execution by the extension processing circuitry can be increased (by adjusting the extension-directed confidence information).

[0060] Starting the extension processing circuitry can require a number of initialisation actions to be performed. Such initialisation actions can be triggered by the confidence calibration circuitry at appropriate times. Thus, in some examples, the confidence calibration circuitry is configured to cause the extension processing circuitry to perform at least one preparation step to configure the extension processing circuitry for execution of the delegated task in dependence on the extension-directed confidence information.

[0061] When the apparatus comprises multiple instances of the extension processing circuitry, various preparation steps can be initiated by the confidence calibration circuitry and the confidence calibration circuitry can also cause selected instances of the extension processing circuitry to prepare for action. Thus, in some examples, there are multiple instances of the extension processing circuitry, where the confidence calibration circuitry is configured to designate a selected instance of the extension processing circuitry to perform the at least one preparation step.

[0062] One example of a preparation step is to warm up the internal caches of the extension processing circuitry, i.e. to bring particular content into such cache(s) in preparation for the expected workload. This can be performed in various mechanisms, but in some examples, the confidence calibration circuitry is configured to designate an address identifier, where the address identifier is indicative of cache content to be brought into a private cache of the extension processing circuitry as at least part of the at least one preparation step.

[0063] In addition to or alternatively to the ability of the confidence calibration circuitry to initiate various preparation steps for the extension processing circuitry, the present technology further proposes to provide instructions forming part of the instruction set of the data processing pipeline (CPU) that can also be used to initiate various preparation steps. Thus, in some examples, the decode circuitry is responsive to an extension setup instruction to generate the control signal to control the extension processing circuitry to perform at least one preparation step to configure the extension processing circuitry for execution of the delegated task.

[0064] As in the case of the preparation steps initiated by the confidence calibration circuit, the preparation steps initiated by the extension setting instruction can take a variety of forms. In some examples, the apparatus comprises a plurality of instances of extension processing circuitry, and wherein the extension setting instruction specifies that a selected instance of extension processing circuitry is to perform the at least one preparation step.

[0065] In some examples, the extension setting instruction specifies an address identifier, wherein the address identifier indicates cache content to be brought into a private cache of the extension processing circuitry as the at least one preparation step.

[0066] In some examples, the extension processing circuitry comprises a private address translation buffer, and the at least one preparation step comprises copying address translation information from a main address translation buffer of the data processing pipeline into the private address translation buffer.

[0067] When causing the extension processing circuitry to perform a context switch from a current execution context to a further execution context, the extension processing circuitry can be arranged in various ways to handle the saving of its state. In particular, when substantially all of the extension processing circuitry state is to be saved immediately in the case that a context switch is triggered, some methods of state saving for context switches are marked as "eager". When the saving of the extension processing circuitry state is delayed, other methods are marked as "lazy", which are only enforced when it is determined that the state would otherwise be overwritten (e.g. by an action of the incoming context). The present technology further proposes that when the extension processing circuitry is configured for such lazy context saving, and an extension context save instruction has been executed on the data processing pipeline (CPU), the context save can be performed early and proactively, as a preparation step for starting the extension processing circuitry. Thus, in some examples, the decode circuitry generates the control signal to trigger the extension processing circuitry to perform a context switch from a current execution context to a further execution context in response to an extension context save instruction comprising a storage location identifier, wherein the extension processing circuitry is configured to defer storing the extension state information to a location identified by the storage location identifier until a point in time at which it is determined that the further execution context requires the extension processing circuitry to modify the extension state information,

[0068] and wherein the at least one preparation step triggered in response to the extension setting instruction comprises storing extension state information to the location identified by the storage location identifier.

[0069] The extension processing circuitry can be arranged to be clock-gated and / or power-gated when in the idle state, and preparing the extension processing circuitry for active processing can comprise exiting the clock-gated and / or power-gated state. Thus, in some examples, the extension processing circuitry is configured to be in at least one of a clock-gated state and / or a power-gated state when in the idle state,

[0070] and wherein the at least one preparation step triggered in response to the extension set instruction comprises causing the extension processing circuitry to exit at least one of the clock-gated state and / or the power-gated state.

[0071] In case the extension processing circuitry can consume a significant amount of power (relative to the rest of the apparatus), it is proposed to perform the exiting of the clock-gated state and / or the power-gated state incrementally in some examples. For example, when powering up the extension processing circuitry as a preparation step for the start-up, the segments of the extension processing circuitry that are each in a clock-gated state and / or a power-gated state can be sequentially brought out of the clock-gated state and / or the power-gated state into an active state. One advantage of this is that the power supply stability of the apparatus can thereby be improved, as large rates of change of the current consumption by the extension processing circuitry, which can otherwise cause the power supply voltage to drop, are avoided, adversely affecting other components of the apparatus.

[0072] In one example herein, there is a (non-transitory) computer readable medium for storing computer readable code for manufacturing an apparatus of any of the above examples.

[0073] In one example herein, there is a method of operating an apparatus, the method comprising:

[0074] performing a data processing operation in a data processing pipeline in accordance with a received sequence of instructions;

[0075] decoding the received sequence of instructions in a decode circuit of the data processing pipeline, and generating control signals to control the data processing pipeline to perform the data processing operation;

[0076] performing a delegation task in extension processing circuitry associated with the data processing pipeline in response to a delegation signal received from the data processing pipeline, wherein the delegation task is performed asynchronously to the data processing operation performed by the data processing pipeline;

[0077] performing speculative instruction execution in the data processing pipeline, whereby modifications to a state of the apparatus resulting from execution of the speculatively executed instructions are not committed until a speculation acknowledgement is generated indicating that execution of the speculatively executed instructions was correct;

[0078] In response to an extension start instruction specifying the delegated task, the control signal is generated to control the data processing pipeline to issue the delegation signal to the extension processing circuit to delegate the delegated task.

[0079] In response to the delegation signal, the delegation task is initiated in the extended processing circuitry before the speculative confirmation is generated for the extended start instruction; and

[0080] Ensure that the results generated by the delegated task are not visible to the data processing pipeline until the speculative confirmation is generated for the extended start instruction.

[0081] In one example of this document, there is a computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising:

[0082] A data processing pipeline logic configured to perform data processing operations based on a received instruction sequence, wherein the data processing pipeline logic includes decoding logic configured to decode the received instruction sequence and generate control signals to control the data processing pipeline logic to perform the data processing operations; and

[0083] An extended processing logic, associated with the data processing pipeline logic and configured to execute a delegated task in response to a delegation signal received from the data processing pipeline logic, wherein the extended processing logic is configured to execute the delegated task asynchronously with the data processing operation performed by the data processing pipeline logic.

[0084] The data processing pipeline logic is configured to execute speculative instructions. Therefore, any modifications to the state of the instruction execution environment resulting from the execution of a speculative instruction will not be committed until a speculative confirmation indicating that the execution of the speculative instruction was correct is generated.

[0085] The decoding logic generates the control signal in response to the extended start instruction specifying the delegated task, thereby controlling the data processing pipeline logic to issue the delegation signal to the extended processing logic to delegate the task.

[0086] Furthermore, the extended processing logic, in response to the delegation signal, begins the delegation task before generating the speculative confirmation for the extended start instruction.

[0087] Therefore, the extended processing logic is configured to ensure that the results generated by the delegated task are not visible to the data processing pipeline logic until the speculative confirmation is generated for the extended start instruction.

[0088] Some specific implementation schemes are now described with reference to the accompanying drawings.

[0089] Figure 1 A data processing apparatus 10 according to some examples is schematically illustrated. The data processing apparatus 10 is schematically shown as having a pipelined configuration, which is shown conceptually here for the purpose of simplicity and clarity. The illustrated pipeline stages include an instruction cache 11, a fetch stage 12, a decode stage 13, a microoperations cache 14, a release stage 15, and a register access stage 16. Instruction sequences are retrieved from memory (not shown) and cached in the instruction cache 11. The fetch stage 12 controls which instructions are retrieved as instruction sequences, and these instructions are subsequently decoded in the decode stage 13. This decoding essentially identifies the type of each instruction, and any additional operands specified by that instruction, and generates control signals to control the rest of the apparatus to perform the data processing operation defined by that instruction. Decoding an instruction may include breaking it down into one or more microoperations, and these microoperations may be cached in the microoperations cache 14. The final stage of the pipeline before execution is the release stage 15, where instructions (or micro-operations) are queued, awaiting the availability of the register values ​​specified as operands and the corresponding functional unit of the data processing pipeline, which will perform the defined operation. Generally, the data processing operations defined by the instructions are performed by functional units forming part of the data processing pipeline (i.e., load / store unit 17, execution unit 18, and execution unit 19). These subsequent execution units may be, for example, an arithmetic logic unit (ALU), a floating-point unit (FPU), etc. The functional units forming part of the data processing pipeline perform their data processing operations on data values ​​provided from a set of registers (conceptually represented by register access stage 16 in the diagram) and return the results of those data processing operations to that set of registers. Load / store unit 17 is provided for storing the values ​​from this set of registers into the memory system; only the L1 cache 21 and L2 cache 22 of this memory system are shown in the diagram. The L1 cache 21 is private to the data processing unit 10, and the L2 cache 22 can be shared with another data processing unit when that unit is part of a broader data processing system. The data processing unit 10 is also shown to include a branching unit 20 that monitors the execution flow of an instruction sequence and attempts to predict whether a given branch will be taken based on previous execution history. The prediction from the branching unit 20 provides information for the instruction sequence that will be fetched by the fetching phase 12.

[0090] The data processing device 10 also includes extended processing circuitry 23, which is provided to support the efficient execution of one or more defined functions that have been established to be influential and generalizable to the data processing operations performed by the data processing device 10. Example functions of this type have been found to include tasks or functions such as memcpy, memset, compression, encryption, and string manipulation, but the present invention is not limited to these specific examples. The extended processing circuitry is closely associated with the data processing pipeline and is configured to execute the defined functions (also referred to herein as delegated tasks) in response to a delegation signal received from the data processing pipeline. Extended processing circuitry 23 is an example of thread-small extension (TE) according to the present invention. The sequence of operations it performs to execute the defined functions is referred to herein as a thread-small. Although extended processing circuitry 23 is closely associated with the data processing pipeline, it is configured to execute delegated tasks asynchronously with respect to the data processing operations performed by the data processing pipeline. The data processing pipeline may also be referred to herein as a CPU. A thread-small is a set of functions or operations that can be executed asynchronously relative to other CPU activities once started. In response to an extended start instruction defined for this purpose in the instruction set of the data processing pipeline, an instruction or command is generated and sent to the extended processing circuit 23 to initiate the delegated task. Thus, the extended start instruction proceeds along the data processing pipeline in the manner any other CPU instruction would take, but when the decoding circuit 13 identifies the extended start instruction, it can directly signal the extended processing circuit 23. The tight integration of the extended processing circuit 23 with the data processing pipeline is illustrated by the fact that the extended processing circuit 23 has direct access to the load / store unit 17, and therefore shares the path from the data processing pipeline to memory. The extended processing circuit 23 also has access to the set of registers 16, such that, for example, the extended start instruction can specify one or more registers as operands, and subsequently pass the values ​​from these registers directly to the extended processing circuit 23 associated with the command sent to initiate the delegated task. Upon completion of the task, the result of the delegated task can be provided as output and returned to the register value via an extended synchronization instruction.

[0091] Figure 2 A data processing apparatus 30 according to some examples is schematically illustrated. It should be noted that the arrangement of the components of the data processing apparatus 30 is different from... Figure 1 The components of the data processing device 10 shown are arranged similarly. One difference is that... Figure 1Data processing device 10 is intended to represent an ordered processor, while data processing device 30 is an unordered processor. As a result, the data processing pipeline of data processing device 30 includes a renaming stage 35, which allows data processing device 30 to change the order of instructions in its execution instruction sequence, such that those instructions can be executed in the order determined by when their operands become available and the availability of functional units, rather than in the order in which the instructions appear in the sequence. The illustrated pipeline stages include instruction cache 31, fetch stage 32, decode stage 33, microoperations cache 34, renaming stage 35, issue stage 35, and register access stage 37. The instruction sequence is retrieved from memory (not shown) and cached in instruction cache 31. Instructions are referenced above. Figure 1 The data processing apparatus 10 is passed through a data processing pipeline in the manner described, wherein additional register renaming is performed by a renaming stage 35. The functional units of the data processing pipeline in this example are a loading unit 38, a storage unit 39, an FPU 41, an integer ALU 42, and a vector unit 43. The throughput of the FPU 41, integer ALU 42, and vector unit 43 is sufficient to provide a result cache 44 as an intermediary before the results of their data processing are returned to register 37. A branch prediction unit 45 is also provided, and its predictions inform the operation of the fetch stage 32.

[0092] The data processing apparatus 30 also includes extended processing circuitry (“small thread extension”) 49, which is provided to support the efficient execution of one or more defined functions that are established to be influential and generalizable to the data processing operations performed by the data processing apparatus 30. The extended processing circuitry 49 is closely associated with the data processing pipeline and is configured to execute the defined functions in response to delegation signals received from the data processing pipeline. Figure 2 In the example, the delegation signal is shown as being issued from the publish queue stage 36. It is noteworthy that this occurs after the renaming stage 35, allowing the extended processing circuitry 49 to operate on the physical registers of that set of registers 37 according to the same mapping used for the architecture registers of the rest of the device. (As in...) Figure 1In this example, the data processing pipeline (instruction cache 31 to register fetch stage 37, load unit 38 and memory unit 39, and functional units 41 to 45) can also be referred to as the CPU. Once started, the small thread extension 49 operates asynchronously relative to other CPU activities. In response to an extension start instruction defined for this purpose in the instruction set of the data processing pipeline, an instruction or command is generated and sent to the extension processing circuit 49 to initiate the delegated task. The tight integration of the extension processing circuit 49 with the data processing pipeline is also evident in this example by the fact that the extension processing circuit 49 has direct access to the load unit 38 and the memory buffer 40, and therefore shares the path from the data processing pipeline to memory. The extension processing circuit 49 also has access to the set of registers 37, such that, for example, an extension start instruction can specify one or more registers as operands, and then the values ​​from these registers are directly passed to the extension processing circuit 49 associated with the command sent to initiate the delegated task. Note that the output of the branch prediction unit 45 is also provided to the extension processing circuit 49. After the task is completed, the result of the delegated task can be provided as output and returned to the register value via extended synchronization instructions.

[0093] Figure 3 A data processing apparatus 50 is schematically illustrated according to some examples. This example provides... Figure 1 and Figure 2 A comparison of examples shows that in those examples, the extended processing circuitry is so closely embedded with the data processing pipeline that those instances of the extended processing circuitry can be considered to be within the CPU. Figure 3 In the example device 50, the CPU 51 and the extended processing circuitry (small thread extension) 52 are not tightly integrated. This is illustrated, for example, by the fact that each has its own path to memory, where L1 cache 53 is CPU 51 private and L1 cache 54 is small thread extension 52 private. The CPU and the small thread extension share L2 cache 55. However, the small thread extension 52 remains tightly coupled to the CPU 51 and can be quickly initiated when an extension start instruction, specifying the function to be performed by the small thread extension 52, is encountered in the CPU pipeline. The small thread extension 52 can obtain data directly from the CPU registers at the start of its execution. Upon completion, it can return a value via an extension synchronization instruction. Figure 3 The small thread extension 52 is also shown as having its own dedicated TLB 56, in which it can cache the currently used address translation. As a preparatory step before or associated with a delegation signal, the contents of TLB 57 from CPU 51 can be copied to dedicated TLB 56 to warm up the cache before the small thread begins operation.

[0094] Figure 4 This is a state diagram illustrating a set of example states in which the extended processing circuit (TE) transitions between some examples. Initially, the TE is in idle state 60. When the data processing pipeline encounters an extended start (XSTART) instruction, a delegation signal can cause the TE to switch to setup state 61. This may also require an assertion signal, which indicates that the XSTART instruction has been committed. In setup state 61, certain actions necessary to prepare the TE can be performed, for example, in examples where the TE has a separate path to memory (such as in...). Figure 3 In the case of a setup state (60), a setup task is to transfer the relevant entry currently in the CPU's TLB to a dedicated TLB within the TE. This allows the TE to perform transitions independently at a faster rate than if it relied entirely on the existing transition mechanism within the CPU. If the TE is already clock-gated or power-gated while in idle state 60, setup state 61 may also include a task to exit the clock-gated or power-gated condition. Once setup state 61 is complete, the TE can switch to running state 62. If the TE encounters a memory fault during its processing, it asserts a signal that will trigger an interrupt within the CPU, causing it to stop executing the main thread and switch to the handler. The TE switches to interrupt state 63. The address that caused the fault is placed in a special synthesis information system register, and a bit in the program status register (PSR) is set, allowing the handler to quickly determine the source of the fault. Setting the bit in the PSR makes communicating the recovery of the small thread intuitive, as the handler can reset the relevant bit in the SPSR, and the TE can detect the reset of the bit and resume execution when the CPSR recovers from the SPSR during an exception return. If the main thread is switched out, for example during a context switch initiated by the operating system, the TE will also switch to interrupt state 63. In interrupt state 63, the TE can be clock-gated or power-gated unless another thread initiates a new command for it, or an associated thread returns to resume execution, or a disposeer returns. The TE returns from interrupt state 63 to running state 62 via reload state 64, in which any context or state previously saved to memory related to its execution can be restored. This can happen if another thread uses a previously interrupted TE. Finally, when the extension reaches the end of the unloaded compute granule (delegated task), it moves to idle state 60. The TE will announce task completion, allowing the extension synchronization instruction (XSYNC) to pick up the "complete" signal and provide a return value to the designated register if necessary. If the TE has any lingering data in its private cache, it may also need to clear those entries upon completion.

[0095] Now, let's describe an example of using small threads. Programmers or compilers identify functions whose execution within custom hardware (extended processing circuitry) meets a cost-effectiveness threshold in their use case. Instructions (such as XSTART) are used to initiate commands within a specified CPU extension. An example of pseudocode for such identified functions, "funcX", is as follows: funcA(){ … XSTART {x0 – x3}, #imm_op / / funcX(a, b, c, d); I1 I2 I3 I4 … XSYNC x0, #imm_op … }

[0096] Therefore, within the function `funcA`, the `XSTART` instruction initializes the CPU extension and transfers the parameters (a, b, c, d) of `funcX` to the extension processing circuitry, which reside in registers x0, x1, x2, and x3, respectively. The `XSTART` instruction in this example also specifies the immediate value `#imm_op`, which defines the specific function to be executed. For example, although only one instance of the extension processing circuitry may exist, it may be able to execute more than one function, or at least more than one function variant, and the immediate value `#imm_op` can select the desired variant and / or function. In other examples, there may be more than one instance of the extension processing circuitry, and the immediate value `#imm_op` can select among them. Depending on the setup, the extension may also automatically obtain a copy of the relevant entry in the TLB. The extension processing circuitry then performs the required task (`funcX`), and during its execution, the CPU is free to continue executing other instructions I1, I2, I3, I4, etc. At some point in the future, the CPU executes the extension synchronization instruction (`XSYNC`), which automatically checks whether the extension has been completed. If not completed, for some variants of the extended synchronization instruction, the CPU will wait for the delegated task to complete. Other variants of the extended synchronization instruction (such as the XSYNCS variant) allow the CPU to continue executing other code (if an alternative routine is available), or to stop execution and wait for the extension to complete (typically if there is nothing else to perform during this interval).

[0097] Figure 5The diagram schematically illustrates extended start instructions present on a speculative branch path during speculative instruction execution, according to some examples. The instruction flow is shown at the top of the diagram, where a first conditional branch instruction (BRANCH1) is found in instruction sequence 100. Accordingly, depending on the condition of this branch instruction, further instruction execution will follow either an adopted (T) path or an unadopted (NT) path. In this example, the adopted path leads to another instruction sequence 101, at the end of which an additional unadopted branch instruction (BRANCH2) causes the instruction flow to jump back to the instructions sequentially following the first conditional branch instruction (BRANCH1). Thus, it can be seen that the additional instruction sequence 101 is an additional function that is sometimes executed during the execution of the first instruction sequence 100. It should also be noted that the additional instruction sequence 101 includes the XSTART instruction, an extended start instruction used to start a small thread. Execution Figure 5 The data processing device for the instructions shown in the upper part is configured for speculative instruction execution, an example of which occurs in the execution of conditional branch instructions. That is, instead of waiting until the condition upon which the first conditional branch instruction (BRANCH1) is based is explicitly resolved, the data processing device speculatively continues instruction execution along either the unused (NT) path or the used (T) path. This is done based on the execution history of the instruction sequence, i.e., based on how frequently the result was used (T) or not used (NT) when BRANCH1 was encountered at that moment in the past. Speculative execution assumes that the same will happen on this iteration when the data processing device has previously primarily used one path rather than another. Data processing device 110 is shown in... Figure 5 The lower part includes a data processing pipeline 110, which is partially controlled by predictive control generated by the branch prediction unit 111, i.e., the data processing pipeline 110 is arranged to speculatively execute instructions based on the prediction. Figure 5The diagram illustrates that the first conditional branch instruction (BRANCH1) is predicted as adopted (T) by the branch prediction unit 111, and therefore the data processing pipeline 110 continues to execute the additional instruction sequence 101 based on this prediction until it is confirmed as correct. When the additional instruction sequence 101 includes an XSTART instruction, the data processing pipeline 110 speculatively executes the instruction, and according to the art, this causes a delegation signal to be sent to the extended processing circuit 112, which begins to delegate the task without waiting for an indication from the submission stage 113 that the prediction is correct and a signal indicating that the XSTART instruction has been submitted or will be submitted. The extended processing circuit 112 also receives the speculative prediction generated by the branch prediction unit 111, and therefore knows (at least initially) that XSTART has been speculatively executed, and thus ensures that the result 114 generated by the delegated task is not visible outside the extended processing circuit (as an "output") until a speculative confirmation is generated for the extended start instruction. Such sandboxing results can be retained in various storage structures in the extended processing circuit 112, but result 114 can represent, for example, one or more of a private data cache, data memory, and register.

[0098] Figure 6 A data processing apparatus 120, including confidence calibration circuitry, is schematically illustrated, embodying various examples of the present technology. Here, the data processing pipeline is shown as a CPU 121, with an associated extended processing circuitry (small thread extension) 122. These two processing components have their own memory paths, with the CPU 121 having a private L1 cache 123 and the extended processing circuitry 122 having a private L1 cache 124. They share access to the memory system via a shared L2 cache 125. Each also has its own TLB, namely TLB 126 in the CPU 121 and TLB 130 in the small thread extension 122. The CPU 121 is configured to perform speculative instruction execution based on branch predictions generated by its branch prediction unit 127. (Refer to the above...) Figure 5As explained, through extension, the small thread extension 122 also performs a speculative function execution. That is, when the CPU 121 encounters an extension start instruction, a delegation signal is sent to the small thread extension 122. However, whether and when the small thread extension 122 starts executing the delegated task further depends on the confidence calibration circuit (predictor confidence calibration unit) 128. The PCCU 128 can modify or even completely replace the branch prediction generated by its branch prediction unit 127. The PCCU 128 therefore signals the small thread extension 122 to notify of the modified or replaced branch prediction (extension-oriented confidence information). The PCCU 128 can base its signaling to the extension processing circuit (small thread extension) 122 on a series of factors. These factors may include any of the following: extension processing circuit-specific factors; the relative size of the delegated task; the execution history of the instruction sequence portion including the extension start instruction; and / or the recent pause history of the extension processing circuit. Additionally, PCCU 128 is also configured to signal extended processing circuitry 122 to perform at least one preparatory step to configure it for the execution of a delegated task. That is, PCCU 128 may not immediately start extended processing circuitry 122, but may prepare it for startup, for example, by exiting an idle state, powering the components, or pre-filling a cache with data. For the latter purpose, PCCU 128 is also communicatively coupled to prefetcher 129 and can thus trigger the retrieval of predefined data associated with the delegated task (e.g., using address identifiers). When more than one instance of extended processing circuitry exists in the device, PCCU 128 may designate a selected instance of extended processing circuitry to perform at least one preparatory step. When extended processing circuitry 122 begins speculative execution of a task, it does so to ensure that the results generated by the delegated task are not visible outside the extended processing circuitry until a speculative acknowledgment (spec_result_ok) signal is received from CPU 121. If the speculative execution of the XSTART instruction is incorrect and a speculative cancellation signal (spec_result_cancelled) is received from the CPU 121, the extended processing circuit 122 rolls back the results it holds internally, thus invalidating the modified cache contents, etc.

[0099] Figure 7 A confidence calibration circuit, according to some examples, is schematically illustrated that modifies or replaces branch predictions generated in a data processing pipeline for use by extended processing circuitry. Data processing pipeline 150 includes branch prediction 151. Predictions generated by branch prediction 151 are received by confidence calibration circuitry 152. Confidence calibration circuitry 152 modifies or replaces the branch predictions for use by extended processing circuitry 153. Figure 7Three types of information are schematically illustrated, upon which the calculations of the confidence calibration circuit 152 can be based. The first type is a set of task information 154 maintained by the confidence calibration circuit. This can be, for example, an indication of the granularity (size) of multiple tasks that the extended processing circuit 153 can perform; therefore, for any given task delegated to the extended processing circuit 153 and speculatively initiated, the confidence calibration circuit 152 can modify the probability of that speculative initiation by the extended processing circuit 153 according to the task size. The second type of information maintained by the confidence calibration circuit 152 is path statistics 155. These are based on information received from the data processing pipeline 150, indicating the frequency at which the execution path includes an extended start instruction. This can also form the basis for modifying the probability of speculative initiation of a delegated task triggered by a given extended start instruction. The third type of information maintained by the confidence calibration circuit 152 is the pause history 156. This represents the history of how frequently the extended processing circuit 153 pauses due to reaching its internal storage limits before receiving a speculative acknowledgment signal. When such pauses occur too frequently, the likelihood of speculative initiation of delegated tasks can be reduced.

[0100] Figure 8 An extended setup instruction, according to some examples, causes an extended processing circuit to perform one or more preparatory steps. Here, the XSETUP instruction takes the form: XSETUP x0, #imm. Thus, when decoded by the CPU's decoder 161, this form of XSETUP instruction 160 causes the extended processing circuit 162 to perform one or more preparatory steps, expecting the CPU to delegate the task as early as possible. The contents of register x0 and the immediate value #imm can be used to direct aspects of these preparatory steps. When there is more than one example of extended processing circuitry in the device, the contents of register x0 or the immediate value #imm can be used to indicate a specific instance of extended processing circuitry that should perform preparatory steps. Alternatively or additionally, the contents of register x0 or the immediate value #imm can be received by the extended processing circuit 162 to direct a specific preparatory step performed by that extended processing circuitry. As an example preparatory step, the extended processing circuit 162 may copy the contents of its TLB 164 from the CPU's TLB and / or may pre-fill specified data in its L1 cache 165.

[0101] Figure 9An extended setup instruction, according to some examples, causes an extended processing circuit to perform one or more preparatory steps. Here, the XSETUP instruction may additionally specify registers and / or immediate values ​​as operands, although this is not required. When decoded by the CPU's decoder 171, this form of XSETUP instruction 170 causes the extended processing circuit 172 to perform one or more preparatory steps in anticipation of early task delegation by the CPU. An example of an extended processing circuit 172 with a context state 173 is given here, which is a remnant from a previous context in which the extended processing circuit 172 was executed. Because the extended processing circuit 172 is configured in a relaxed save mode, this context state has not yet been saved, and thus context state 173 will (normally) only be saved when a newly incoming context will modify context state 173. However, as a preparatory step triggered by the XSETUP instruction, the extended processing circuit 172 saves context state 173 to a specified location 174 in memory 175. This preparatory save of context state 173 can also be triggered by PCCU 176.

[0102] Figure 10 An extended setup instruction, according to some examples, causes the extended processing circuitry to perform one or more preparatory steps. Here, the XSETUP instruction may additionally specify registers and / or immediate values ​​as operands, although this is not required. When decoded by the CPU's decoder 181, this form of XSETUP instruction 180 causes the extended processing circuitry 182 to perform one or more preparatory steps in anticipation of early task delegation by the CPU. An example of the extended processing circuitry 182 in an idle state is given here, in which the extended processing circuitry is either clock-gated or power-gated. This is controlled by clock control 183 and power control 184. The power supply to the extended processing circuitry can be incremental; for example, in this case, the four components 185, 186, 187, and 188 are not powered simultaneously but sequentially. As just one example, these components could be four memory banks that have already been de-energized in the idle state. This exit from clock-gated and / or power-gated state can also be triggered by the PCCU 189.

[0103] Figure 11This is a flowchart illustrating a sequence of steps taken in some example methods. The process can be considered to begin at step 200, where a sequence of instructions is executed in the data processing pipeline. Step 201 indicates that instruction execution includes speculative instruction execution, and at step 202 it is determined whether an extended start instruction has been encountered during speculative execution. When this is not the case, the process simply loops through steps 200 to 202. However, when an extended start instruction is speculatively executed, the process proceeds to step 203, where the extended processing circuitry begins delegating a task before the extended start instruction is submitted, the delegated task being executed asynchronously with the data processing pipeline. Then, at step 204 it is determined whether the extended start instruction (XSTART) has been submitted. When the extended start instruction has been submitted, the process proceeds to step 205, where it is determined whether the delegated task has completed. When the delegated task has completed, then at step 206, the result of the delegated task is made available externally as output (i.e., used by the rest of the data processing apparatus except for the extended processing circuitry). The XSYNC instruction can then collect these outputs for use in other data processing operations by the data processing pipeline. The flow returns to step 200. Otherwise, if it is determined at step 205 that the task has not yet been completed, the flow proceeds via step 206 and the task delegation continues, however, it is permissible for some of the results of the delegation to be externally visible as output (because the XSTART instruction has been committed, and therefore the delegation is no longer speculative). Returning to the consideration of step 204, if the XSTART instruction has not yet been committed, the flow proceeds to step 208, where it is determined whether the delegation has been completed. If the delegation has not yet been completed, the flow proceeds to step 209 and the delegation continues, but its results are not visible externally to the extended processing circuitry. The flow then loops back via step 204 to determine whether the XSTART instruction has now been committed. When it is determined at step 208 that the task has been completed, the flow proceeds to step 210 and determines whether the XSTART instruction has been cancelled. If the XSTART instruction has not been cancelled, the flow returns to step 204 to determine whether the XSTART instruction has now been committed. However, if it is determined at step 210 that the XSTART instruction has been cancelled, the process proceeds to step 211, where the result of the delegated task is invalidated (and therefore never visible outside the extended processing circuitry) and the process returns to step 200.

[0104] Figure 12A specific implementation of a simulator that can be used is illustrated schematically. While the embodiments described earlier implement the invention with means and methods for operating specific processing hardware supporting the technology of interest, an instruction execution environment can also be provided according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as simulators because they provide a software-based implementation of a hardware architecture. Types of simulator computer programs include emulators, virtual machines, models, and binary converters (including dynamic binary converters). Generally, a simulator implementation can run on a host processor 515 that optionally runs a host operating system 510 and supports a simulator program 505. In some arrangements, there may be multiple layers of emulation between the hardware and the provided instruction execution environment and / or multiple dissimilar instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that execute at reasonable speeds, but such approaches may be reasonable in certain situations, such as when it is necessary to run code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. For a review of simulation techniques, see “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0105] Where implementations have been described previously with reference to specific hardware architectures or features, equivalent functionality may be provided in simulated implementations by suitable software architectures or features. For example, specific circuitry may be implemented as computer program logic in simulated implementations. Similarly, memory hardware (such as registers or caches) may be implemented as software data structures in simulated implementations. Where one or more of the hardware elements mentioned in the previously described implementations are arranged on host hardware (e.g., host processor 515), some simulated implementations may utilize the host hardware where appropriate.

[0106] The simulator program 505 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 500 (which may include applications, operating systems, and management programs). This program interface is identical to the interface of the hardware architecture modeled by the simulator program 505. Therefore, the program instructions of the target code 500 can be executed from within the instruction execution environment using the simulator program 505, enabling the host computer 515, which does not actually possess the hardware characteristics of the devices discussed above, to simulate these characteristics.

[0107] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of a semiconductor design and manufacturing process, including an electronic design automation (EDA) stage, to manufacture integrated circuits that include devices for implementing these concepts. The aforementioned computer-readable code may additionally or alternatively implement the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0108] For example, computer-readable code used to manufacture a device embodying the concepts described herein may be embodied in code that defines a hardware description language (HDL) representation of those concepts. For instance, the code may define a register-transfer level (RTL) abstraction for one or more logic circuits used to define a device embodying these concepts. The code may define an HDL representing one or more logic circuits, using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL to embody the device. The computer-readable code may provide a definition embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of the concepts that can be interpreted by a computer to enable simulation, functional, and / or formal verification and testing of the concepts.

[0109] Additionally or alternatively, computer-readable code may define a detailed description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to an RTL representation to generate a definition for manufacturing a device embodying the invention. Alternatively or additionally, the one or more logic synthesis processes may generate a bitstream from the computer-readable code, which is loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for proof-of-concept and testing purposes prior to manufacturing of the integrated circuit, or the FPGA may be deployed directly in a product.

[0110] Computer-readable code may include a mixture of code representations used for manufacturing apparatus, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in semiconductor design and manufacturing processes to manufacture apparatus implementing the present invention. Alternatively or additionally, the concept may be defined using a combination of: a computer-readable definition used in semiconductor design and manufacturing processes to manufacture apparatus; and computer-readable code defining instructions that will be executed by the defined apparatus after it is manufactured.

[0111] Such computer-readable code may be disposed in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium (such as semiconductors, disks, or optical discs). Integrated circuits made using computer-readable code may include one or more components such as a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that individually or collectively implement the concept.

[0112] In summary, apparatus, methods, computer programs, and computer-readable media for data processing are disclosed. A data processing pipeline executes data processing operations defined by a received sequence of instructions. An extended processing circuit associated with the data processing pipeline executes a delegated task in response to a delegation signal received from the data processing pipeline, the delegated task being executed asynchronously with the data processing pipeline. The data processing pipeline performs speculative instruction execution. In response to an extended start instruction, the data processing pipeline issues the delegation signal to the extended processing circuit to delegate the delegated task, and the extended processing circuit responds by initiating the delegated task before generating a speculative acknowledgment for the extended start instruction. The extended processing circuit ensures that the results generated by the delegated task are not visible outside the extended processing circuit until the speculative acknowledgment is generated for the extended start instruction.

[0113] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operations. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform that function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0114] While exemplary embodiments have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and that various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims. For example, various combinations of the features of the independent claims with the features of the dependent claims can be made without departing from the scope of the invention.

Claims

1. Apparatus for data processing, the apparatus comprising: a data processing pipeline configured to perform data processing operations in dependence on a received sequence of instructions, wherein the data processing pipeline comprises a decode circuit configured to decode the received sequence of instructions and to generate control signals to control the data processing pipeline to perform the data processing operations; and an extension processing circuit associated with the data processing pipeline and configured to perform a delegated task in response to a delegation signal received from the data processing pipeline, wherein the extension processing circuit is configured to perform the delegated task asynchronously from the data processing operations performed by the data processing pipeline, wherein the data processing pipeline is configured to perform speculative instruction execution whereby modifications to a state of the apparatus resulting from execution of a speculatively executed instruction are not committed until a speculation acknowledgement is generated indicating that execution of the speculatively executed instruction was correct, wherein the decode circuit is responsive to an extension start instruction specifying the delegated task to generate the control signals to control the data processing pipeline to issue the delegation signal to the extension processing circuit to delegate the delegated task, and wherein the extension processing circuit is responsive to the delegation signal to start the delegated task before the speculation acknowledgement is generated for the extension start instruction, whereby the extension processing circuit is configured to ensure that results generated by the delegated task are not visible outside the extension processing circuit until the speculation acknowledgement is generated for the extension start instruction.

2. The apparatus of claim 1, wherein the data processing pipeline is configured to generate a speculation cancellation when it is determined that execution of the speculatively executed instruction was incorrect, and wherein the extension processing circuit is responsive to the speculation cancellation generated for the extension start instruction to invalidate any results generated by the delegated task.

3. The apparatus of claim 1 or claim 2, wherein the extension processing circuit comprises a private data store configured to hold results generated by the delegated task.

4. The apparatus of claim 3, wherein the extension processing circuit is responsive to results generated by the delegated task reaching a results storage capacity of the private data store to suspend execution of the delegated task.

5. The apparatus of any preceding claim, wherein the data processing pipeline comprises a branch prediction circuit configured to generate branch confidence information indicating a predicted likelihood of a branch direction being taken, wherein the data processing pipeline is configured to perform the speculative instruction execution in dependence on the branch confidence information, and wherein the apparatus further comprises a confidence calibration circuit configured to generate extension directed confidence information associated with the extension start instruction. wherein the extension processing circuit is configured to determine whether to start the delegated task before generating the speculation confirmation for the extension start instruction in dependence on the extension-directed confidence information.

6. The apparatus of claim 5, wherein the confidence calibration circuit is configured to generate the extension-directed confidence information in dependence on the branch confidence information and in dependence on at least one extension processing circuit-specific factor.

7. The apparatus of claim 5 or claim 6, wherein the confidence calibration circuit is configured to generate the extension-directed confidence information in dependence on a relative size of the delegated task.

8. The apparatus of any one of claims 5 to 7, wherein the confidence calibration circuit is configured to generate the extension-directed confidence information in dependence on an execution history of a portion of an instruction sequence that includes the extension start instruction.

9. The apparatus of any one of claims 5 to 8, wherein the confidence calibration circuit is configured to generate the extension-directed confidence information in dependence on a suspension history of the extension processing circuit.

10. The apparatus of any one of claims 5 to 9, wherein the confidence calibration circuit is configured to cause the extension processing circuit to perform at least one preparation step to configure the extension processing circuit for execution of the delegated task in dependence on the extension-directed confidence information.

11. The apparatus of claim 10, the apparatus comprising a plurality of instances of extension processing circuit, wherein the confidence calibration circuit is configured to designate a selected instance of extension processing circuit to perform the at least one preparation step.

12. The apparatus of claim 10 or claim 11, wherein the confidence calibration circuit is configured to designate an address identifier, wherein the address identifier indicates cache content to be brought into a private cache of the extension processing circuit as at least part of the at least one preparation step.

13. The apparatus of any one of claims 5 to 10, wherein the decode circuit is responsive to an extension setup instruction to generate the control signal to control the extension processing circuit to perform at least one preparation step to configure the extension processing circuit for execution of the delegated task.

14. The apparatus of claim 13, the apparatus comprising a plurality of instances of extension processing circuit, and wherein the extension setup instruction designates a selected instance of extension processing circuit to perform the at least one preparation step.

15. The apparatus of claim 13 or claim 14, wherein the extension setup instruction designates an address identifier, wherein the address identifier indicates cache content to be brought into a private cache of the extension processing circuit as the at least one preparation step.

16. The apparatus of any one of claims 10 to 15, wherein the extension processing circuit comprises a private address translation buffer, and the at least one preparation step comprises copying address translation information from a main address translation buffer of the data processing pipeline into the private address translation buffer.

17. The apparatus according to any one of claims 10 to 16, wherein the decode circuitry is responsive to an extension context save instruction comprising a storage location identifier to generate the control signals to trigger the extension processing circuitry to perform a context switch from a current execution context to a further execution context, wherein the extension processing circuitry is configured to defer storing the extension state information to a location identified by the storage location identifier until a time at which it is determined that the further execution context requires the extension processing circuitry to modify the extension state information, and wherein the at least one preparation step triggered in response to the extension set instruction comprises storing the extension state information to the location identified by the storage location identifier.

18. The apparatus according to any one of claims 10 to 17, wherein the extension processing circuitry is configured to be in at least one of a clock gating state and / or a power gating state in an idle state, and wherein the at least one preparation step triggered in response to the extension set instruction comprises causing the extension processing circuitry to exit at least one of the clock gating state and / or the power gating state.

19. The apparatus according to claim 18, wherein exiting the clock gating state and / or the power gating state is performed incrementally.

20. A non-transitory computer readable medium for storing computer readable code for manufacturing an apparatus according to any one of claims 1 to 19.

21. A method of operating an apparatus, the method comprising: performing data processing operations in a data processing pipeline in accordance with a received sequence of instructions; decoding the received sequence of instructions in a decode circuitry of the data processing pipeline and generating control signals to control the data processing pipeline to perform the data processing operations; performing a delegated task in extension processing circuitry associated with the data processing pipeline in response to a delegation signal received from the data processing pipeline, wherein the delegated task is performed asynchronously to the data processing operations performed by the data processing pipeline; performing speculative instruction execution in the data processing pipeline whereby modifications to a state of the apparatus resulting from execution of a speculatively executed instruction are not committed until a speculation acknowledgement is generated indicating that execution of the speculatively executed instruction was correct; generating the control signals in response to an extension start instruction specifying the delegated task to control the data processing pipeline to issue the delegation signal to the extension processing circuitry to delegate the delegated task; starting the delegated task in the extension processing circuitry in response to the delegation signal before the speculation acknowledgement is generated for the extension start instruction; and ensuring that results generated by the delegated task are not visible to the data processing pipeline until the speculation acknowledgement is generated for the extension start instruction. ​ 22. A computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising: data processing pipeline logic configured to perform data processing operations in dependence on a sequence of received instructions, wherein the data processing pipeline logic comprises decode logic configured to decode the sequence of received instructions and to generate control signals to control the data processing pipeline logic to perform the data processing operations; and extension processing logic associated with the data processing pipeline logic and configured to perform a delegated task in response to a delegation signal received from the data processing pipeline logic, wherein the extension processing logic is configured to perform the delegated task asynchronously from the data processing operations performed by data processing pipeline logic, wherein the data processing pipeline logic is configured to perform speculative instruction execution whereby modifications to a state of the instruction execution environment caused by execution of speculatively executed instructions are not committed until a speculation acknowledgement is generated indicating that execution of the speculatively executed instructions was correct, wherein the decode logic is responsive to an extension start instruction specifying the delegated task to generate the control signals to control the data processing pipeline logic to issue the delegation signal to the extension processing logic to delegate the delegated task, and wherein the extension processing logic is responsive to the delegation signal to start the delegated task before the speculation acknowledgement is generated for the extension start instruction, whereby the extension processing logic is configured to ensure that results generated by the delegated task are not visible to the data processing pipeline logic until the speculation acknowledgement is generated for the extension start instruction.

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