Chip composite with embedded interposer

Abstract

A chip composite is provided that includes at least a first IC die present in a first common layer, a passive interposer, and a plurality of IC dies present in a second common layer. The passive interposer includes interconnects formed in a back end of line (BEOL) region. A first IC die present in the first common layer is hybrid bonded to a top side of the passive interposer. A plurality of IC dies present in the second common layer are also hybrid bonded to the bottom side of the passive interposer.

Description

Background Technology Technical Field

[0002] The specific implementations described herein generally relate to chip packages having stacked integrated circuit (IC) dies, and more specifically to stacked IC dies consisting of at least two layers separated by a passive interposer, wherein dies from the two layers are mixed and bonded to the passive interposer.

[0003] Related technical descriptions Some chip packages with multiple layers of IC dies utilize bridging dies to provide interconnects between adjacent IC dies disposed on different layers. Since the bridging die only partially overlaps with each of the adjacent IC dies, the bridging area available for each adjacent IC connected to the bridging die is limited. Therefore, the density and number of interconnects obtainable through this bridging area are limited.

[0004] Therefore, an improved multilayer chip package is needed. Summary of the Invention

[0005] A chip composite is provided, comprising a plurality of IC dies in a first common layer, a passive interposer, and a plurality of IC dies in a second common layer. The plurality of IC dies in the first common layer are co-bonded to the bottom side of the passive interposer. The plurality of IC dies in the second common layer are co-bonded to the top side of the passive interposer.

[0006] In one example, a passive interposer layer covers the entirety of one of the multiple IC dies present in the first common layer.

[0007] In another example, the passive interposer layer also covers the entirety of the second IC die among the multiple IC dies present in the first common layer.

[0008] In one example, a passive interposer layer covers the entirety of one of the multiple IC dies present in the second common layer.

[0009] In another example, the passive interposer layer also covers the entirety of the second IC die among the multiple IC dies present in the second public layer.

[0010] In one example, the passive interposer includes interconnects formed by a BEOL process disposed on a thinned substrate. Alternatively, the passive interposer may consist of only BEOL regions including interconnects formed by a BEOL process, wherein the substrate has been removed. Optionally, the passive interposer includes only passive wiring and, for example, does not have any transistors.

[0011] In one example, an integrated circuit (IC) chip composite is provided. The chip composite includes a passive interposer, at least a first (IC) die, and at least two or more second (IC) dies. The passive interposer includes interconnects formed in a back-end process (BEOL) region. The first IC die is part of a first common layer co-bonded to a first side of the passive interposer. The two or more second IC dies are part of a second common layer co-bonded to a second side of the passive interposer.

[0012] In another example, an integrated circuit (IC) chip package is provided. The chip package includes a chip composite mounted to a substrate. The chip composite includes: a passive interposer; at least a first (IC) die of a first common layer, the at least first IC die of the first common layer being co-bonded to a first side of the passive interposer; and at least two or more second IC dies of a second common layer, the at least two or more second IC dies of the second common layer being co-bonded to a second side of the passive interposer. In some examples, the passive interposer includes interconnects disposed in a BEOL region, the BEOL region including a first side and a second side of the passive interposer.

[0013] In yet another example, an integrated circuit (IC) memory chip complex is provided, the IC memory chip complex including a passive interposer, a plurality of memory IC dies stacked together, one memory IC die being co-bonded to a first side of the passive interposer, and at least two or more IC dies of a first common layer being co-bonded to a second side of the passive interposer.

[0014] In another example, an integrated circuit (IC) chip package is provided. The chip package includes: a substrate; one or more logic IC dies mounted on the substrate; and a chip composite mounted to the substrate. The chip composite is communicatively coupled to the one or more logic IC dies via the substrate. The chip composite includes a passive interposer and a plurality of memory IC dies stacked together. One of the memory IC dies is co-bonded to a first side of the passive interposer. At least two or more (IC) dies of the first common layer are co-bonded to a second side of the passive interposer. Attached Figure Description

[0015] To gain a more detailed understanding of the above-described features of the invention, a more specific description of the invention, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the invention and should therefore not be considered as limiting the scope of the invention, as the invention allows for other equivalent embodiments.

[0016] Figure 1 This is a schematic diagram of an electronic device with a chip package, which has a chip complex.

[0017] Figure 2 This is a block diagram of a method for manufacturing chip composites, which can be extended to form chip packages.

[0018] Figures 3A to 3K This is a schematic cross-sectional view of a chip composite at different manufacturing stages.

[0019] Figures 3L to 3P This is a schematic cross-sectional view of different passive interposers that can be used in chip composites at different manufacturing stages.

[0020] Figure 4 This is a schematic diagram of an electronic device with a chip package, which has a chip complex.

[0021] Figures 5 to 7 It is possible Figure 4 The diagram shows a schematic of different chip composites used in the chip package.

[0022] Figure 8 This is a block diagram of a method for manufacturing chip composites, which can be extended to form chip packages.

[0023] Figures 9A to 9G This is a schematic cross-sectional view of a chip composite at different manufacturing stages.

[0024] Figure 10 This is a block diagram of a method for manufacturing chip composites, which can be extended to form chip packages.

[0025] Figures 11A to 11F This is a schematic cross-sectional view of a chip composite at different manufacturing stages.

[0026] Figure 12 This is a block diagram of a method for manufacturing chip composites, which can be extended to form chip packages.

[0027] Figures 13A to 13G This is a schematic cross-sectional view of a chip composite at different manufacturing stages.

[0028] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is conceivable that elements of one embodiment can be advantageously incorporated into other embodiments. Detailed Implementation

[0029] This document describes a chip composite comprising at least a first IC die in a first common layer, a passive interposer, and a plurality of IC dies in a second common layer. The chip composite can be used in chip packages and electronic devices. The passive interposer of the chip composite includes wiring formed in a back-to-office (BEOL) region. By using a BEOL process to combine the wiring of the passive interposer with a hybrid bonding between the first die disposed in the first common layer, the communication interface between the interposer and the IC dies is denser compared to conventional interposers having stacked layers or relying on conventional bridging dies as described above. To further increase the interconnect density between the passive interposer and the IC dies in the second common layer, the plurality of IC dies in the second common layer are also hybrid-bonded to opposite sides of the passive interposer.

[0030] Passive interposers are fabricated from a substrate such as a silicon wafer or other suitable substrate, which includes interconnects formed on the surface of the substrate. For example, interconnects are pre-fabricated on the substrate using a BEOL process that forms patterned metal wiring within multiple dielectric layers. The interconnects formed in the BEOL layer consist only of passive wiring, e.g., without any transistors. Therefore, a passive interposer is a passive wiring structure without active circuitry elements. In some examples, the substrate is thinned and vias are formed through the substrate to connect the patterned metal wiring of the interconnects to the wiring formed in a hybrid bonding layer. In other examples, the substrate is completely removed from the BEOL region, leaving the BEOL region to define both sides of the passive interposer. Hybrid bonding layers are formed on both sides of the BEOL region to allow the use of wafer-on-wafer bonding (WBC) technology to package the passive interposer. WBC provides improved registration between bonding pads while also enabling reduced spacing between bonding pads. Using passive interposers as intermediate layers between layers allows chip composites to extend beyond mask limitations, making large-scale packaging more reliable and cost-effective.

[0031] In some examples described herein, a chip package is provided that utilizes a chip complex integrating memory dies (such as DRAM) and logic dies using 3D hybrid bonding. The memory-based chip complex enables high-bandwidth and low-power interconnects between the logic and memory dies. By achieving high-bandwidth connections, the overall computational performance of the chip package is enhanced. Since many AI applications are memory-bound, the memory-based chip complex alleviates this bottleneck for large language model AI chips (training and inference). The memory-based chip complex also improves the performance of the chip package executing AI applications by reducing the energy consumed in transferring data between the computation engine of the computation die and the memory die. This energy-efficient implementation helps reduce the power requirements of large data centers and also improves performance / power by allocating more available power to improve computation rather than wasting power on data transfer between the computation die and the memory die. By leveraging parallel manufacturing processes, by creating partial stacks and combining them to create multi-layer die stacks as chip complexes, the processing time for manufacturing chip packages with memory-based chip complexes can be reduced.

[0032] Some advantages of memory-based chip complexes include: increased memory bandwidth between memory and logic dies; improved energy efficiency of chip packages by reducing interconnect power consumption; avoidance of the need for very large 2.5D chip modules required to achieve similar performance; reduced manufacturing process time; and avoidance of expensive process steps for chip-on-wafer assembly by utilizing wafer-on-wafer assembly technology.

[0033] Additionally, the passive interposer layer of the chip composite improves alignment between interconnects, thereby eliminating the need to design and fabricate TSVs at locations that match the precise interface geometry between logic and memory dies. Using wafer-on-wafer processes for die stacking reduces the number of expensive process steps involved in wafer-on-wafer processes, such as gap-filling oxide deposition. Furthermore, using reconstructed wafers with known good IC dies increases yield. The widespread use of hybrid bonding improves energy efficiency and provides higher bandwidth than traditional 2.5D interconnects.

[0034] Now go to Figure 1 A schematic cross-sectional view of an example chip package 100 is provided. The chip package 100 includes at least one integrated circuit (IC) chip composite 150 mounted on one or more substrates. The substrate may be a package substrate 104, or it may be an interposer 102 mounted to the package substrate 104. The interposer 102 (when present) may have a silicon core with through-silicon vias (TSVs), a hybrid silicon-organic interposer such as one with raised fan-out bridges (EFBs), or other suitable interposers. Figure 1 In the example depicted, the chip package 100 includes an interposer 102 mounted on a package substrate 104 at a chip composite 150 mounted on an interposer 102. The chip package 100 may optionally include one or more additional chip composites 170 also mounted on the package substrate 104 and / or the interposer 102. Figure 1 The diagram illustrates an add-on chip complex 170. The add-on chip complex 170 includes one or more IC dies 116.

[0035] Any or all of the IC dies 116 can be memory IC dies, computing IC dies, voice IC dies, or other desired IC dies. When configured as a computing die, IC die 116 includes a central processing unit (CPU) core and / or a graphics processing unit (GPU) core. The functional circuitry of the computing die may also include system management unit (SMU) circuitry. The SMU is circuitry configured to monitor thermal and power conditions and adjust power and cooling to keep IC die 116 operating within specifications. The functional circuitry of the computing die may also include dynamic function exchange (DFX) controller IP circuitry. DFX circuitry provides management of hardware or software-triggered events. For example, DFX circuitry can pull portions of a bitstream from memory and deliver them to the internal configuration access port (ICAP). DFX circuitry also assists with customizable logic decoupling and startup events for each reconfigurable partition. When included in the functional circuitry of IC die 116, GPU cores typically include math engine circuitry. Math engine circuitry is typically designed for task-specific computations, such as those used in data center computing, high-performance computing, and AI / ML computations. Along with the accelerated computing core, the functional circuitry of IC die 116 may also include SMU circuitry and DFX circuitry.

[0036] Chip composite 150 includes a first side 132 and an opposing second side 134. The first side 132 faces away from the interposer layer 102. The first side 132 may optionally be connected to a thermal management device ( Figure 1 (Not shown in the image) docking. Examples of thermal management devices are heat sinks or liquid heat exchangers. The second side 134 of the chip composite 150 is coupled to the top surface 136 of the interposer 102 via solder interconnects 106. The solder interconnects 106 may be solder microbumps or other suitable electrical connections for transmitting ground, signal, and power transfer between the routing circuitry of the interposer 102 and the functional circuitry of the IC die within the chip composite 150.

[0037] The bottom surface 138 of the interposer 102 can be coupled to the top surface 140 of the package substrate 104. The bottom surface 138 of the interposer 102 is coupled to the top surface 140 of the package substrate 104 via solder interconnects 108 or other suitable interconnects. The bottom surface 146 of the package substrate 104 can be coupled to the top surface 128 of the printed circuit board (PCB) 130, thereby forming an electronic device 160. The bottom surface 146 of the package substrate 104 is coupled to the top surface 128 of the PCB 130 via solder interconnects 148 (such as a ball grid array) or other suitable interconnects. The electronic device 160 can be a tablet computer, computer, server, data center, call center, automotive electronic system, copier, digital camera, smartphone, control system, ATM, computing system, gaming system, artificial intelligence system, or machine learning system, etc.

[0038] The chip composite 150 includes at least one IC die 112 disposed in a first common layer 152 and a plurality of IC dies 114 disposed in a second common layer 154. Layers 152 and 154 are disposed on opposite sides of a passive interposer layer 110. The chip composite 150 may optionally include additional layers of one or more IC dies disposed on one or both sides of the passive interposer layer 110. The chip composite 150 may also optionally include one or more additional passive interposers 110 disposed between the layers as needed. A dielectric material 118 may be disposed between the IC dies within the common layer to increase structural rigidity and reduce the likelihood of warping of the chip composite 150. The dielectric material 118 may be a molding compound, gap-filling oxide, or other suitable dielectric material. In one example, the dielectric material 118 is a silicon-based dielectric film, such as SiO or SiN.

[0039] The passive interposer 110 is typically at least as wide as or wider than the IC die 112, which advantageously increases the area (i.e., bridging region) available for signal, ground, and power interconnects between the passive interposer 110 and the IC die 112 of the first common layer 152. For example, as... Figure 1 As illustrated, the first surface 124 of the passive interposer 110 covers the entirety of the adjacent sides 142 of the first IC die 112. In some other examples where multiple IC dies 112 exist in the first common layer 152, the first surface 124 of the passive interposer 110 covers the entirety of the adjacent sides 142 of at least two of the more or even all IC dies 112 in the first common layer 152.

[0040] Similarly, the passive interposer 110 is at least as wide as or wider than at least two or more IC dies in the IC die 114 of the second common layer 154. For example, as Figure 1As illustrated, the second surface 126 of the passive interposer 110 covers the entirety of adjacent sides 144 of at least two IC dies in the IC die 114. In some other examples, the second surface 126 of the passive interposer 110 covers the entirety of adjacent sides 142 of all IC dies in the IC die 114 of the second common layer 152.

[0041] The following is about Figures 3L to 3P The passive interposer 110, discussed further, typically includes at least a back-to-office (BEOL) region fabricated in the substrate. The BEOL region may include three to fifteen layers of complex wiring forming metal interconnects that carry power, ground, and signal transmissions across the passive interposer. The metal interconnects (i.e., the circuitry of the passive interposer 110) are typically formed by alternately stacking oxide layers (for insulation purposes) and metal layers (for interconnection). Vias are formed between the layers to connect the patterned metal lines, thus completing the wiring. The metal interconnects are formed of copper or other good electrical conductors. The interconnects terminate at a first surface 124 of the passive interposer 110, on which a hybrid bonding layer 122 is formed to connect with the mating hybrid bonding layer 122 of the first common layer 152. When the substrate is completely removed to leave the BEOL region as a complete passive interposer 110, the opposite ends of the interconnects terminate at the second surface 126 of the passive interposer 110, on which a hybrid bonding layer 122 is formed to connect with the mating hybrid bonding layer 122 of the second common layer 154. In the example where the substrate is completely removed after the BEOL region has been fabricated, the BEOL region itself defines both opposite surfaces 124 and 126 of the passive interposer 110 on which the hybrid bonding layer 122 is formed.

[0042] As described above, the hybrid bonding layer 122 physically and electrically couples adjacent dies 112, 114 of the first common layer 152 and the second common layer 154 to the first surface 124 and the second surface 126 of the passive interposer layer 110. Each hybrid bonding layer 122 includes exposed metal and exposed dielectric material. The exposed metal is connected to the circuitry of the connected structures, such as the functional circuitry of the IC die and wiring in the BEOL region. Hybrid bonding includes forming non-metal-to-non-metal bonds and forming metal-to-metal bonds. Non-metal-to-non-metal bonds can be fusion bonds. Pressure and heat can be used to form metal-to-metal bonds to form eutectic metal bonds. In one example, a hybrid bond is formed by bonding the dielectric material around the bonding pads to first fix the passive interposer layer 110 and the IC dies 112, 114, and then fusing the metal material of the bonding pads together to create an electrical interconnect between the functional circuitry of the IC dies 112, 114 and the circuitry (i.e., interconnect wiring) of the passive interposer layer 110. The dielectric material surrounding the bonding pads is selected from materials suitable for hybrid bonding to another dielectric material. Materials suitable for hybrid bonding include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), and combinations thereof.

[0043] Although the first public layer 152 includes at least one IC die 112, the first public layer 152 may optionally include multiple IC dies 112. Figure 1 The example depicted shows three IC dies 112. Each IC die 112 within the first common layer 152 may include circuitry with the same or different functionality compared to at least one other IC die 112 of the first common layer 152. When one or more additional layers are stacked on the first common layer 152, the IC dies of the additional layers may include circuitry with the same or different functionality compared to at least one other IC die 112 of the first common layer 152.

[0044] IC die 112 can be configured as a memory IC die, a computing IC die, a voice IC die, or other desired IC die. When configured as a memory die, IC die 112 includes memory circuitry, such as volatile memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or other suitable volatile memory types. Optionally, the memory circuitry of IC die 112 can be non-volatile memory, such as ferroelectric random access memory (FeRAM) and magnetoresistive random access memory (MRAM), or other suitable non-volatile memory types. When configured as a computing die, IC die 112 includes a CPU core and / or a GPU core. The functional circuitry of the computing die may also include SMU circuitry. The SMU is circuitry configured to monitor thermal and power conditions and adjust power and cooling to keep IC die 112 operating within specifications. The functional circuitry of the computing die may also include DFX controller IP circuitry. The DFX circuitry provides management of hardware or software triggered events. For example, DFX circuitry can pull portions of the bitstream from memory and deliver them to ICAP. DFX circuitry also assists with customizable logic decoupling and startup events for each reconfigurable partition. When included in the functional circuitry of IC die 112, GPU cores typically include math engine circuitry. Math engine circuitry is typically designed for task-specific computations, such as those used in data center computing, high-performance computing, and AI / ML computations. Along with the accelerated computing core, the functional circuitry of IC die 112 may also include SMU circuitry and DFX circuitry.

[0045] One or more IC dies in IC die 112 may be configured as active interposer dies. IC dies 112 configured as active interposer dies may include memory controller circuitry and cache memory circuitry. Active interposer dies may further include on-chip network (NOC) circuitry; peripheral component interconnect (PCIe) circuitry; memory physical layer (PHY) circuitry configured to communicate with a memory stack; die-to-die PHY configured to communicate with other IC dies; and I / O PHY configured to communicate with electronics located remote from the chip package 100.

[0046] IC die 114 can be configured as described above with reference to IC die 112. Each IC die 114 within the second common layer 154 may include circuitry having the same or different functions compared to at least one other IC die 114 in the second common layer 154. IC die 114 may additionally have circuitry having the same or different functions compared to at least one other IC die 112 in the first common layer 152. One of the IC dies in all IC dies 112, 114 may also optionally be configured as a chiplet.

[0047] In one example, one of the IC dies in IC die 114, which includes the second common layer 154 of the IC die, may be a logic die. One of the IC dies in IC die 112, which includes the first common layer 152 of the IC die, may optionally be configured as a memory.

[0048] Chip composite 150 may optionally include silicon block 120 mounted to the top surface of the IC die (shown as IC die 112, first common layer 152) furthest from the package substrate 104. Silicon block 120 has no functional or routing circuitry and is utilized such that the overall height of the assembled chip composite can be similar to the overall height of a single die, for example, approximately 800 μm. Silicon block 120 may alternatively or additionally be used to match the height of optional adjacent chip composites 170 within the chip package 100, providing structural rigidity and / or facilitating good thermal transfer of the chip composite 150.

[0049] Figure 2 This is a block diagram of a method 200 for manufacturing a chip composite (such as the chip composite 150 described above or other suitable chip composites). Method 200 can be extended to include forming a chip package, such as the chip package 100 described above or other suitable chip package. Figures 3A to 3K The chip composite 150 is depicted at different manufacturing stages, while Figures 3L to 3P Alternative versions of the passive interposer 110 at different manufacturing stages are depicted, which alternative versions of the passive interposer 110 can be used as the passive interposer 110 in method 200.

[0050] Method 200 begins at operation 202, where an IC die 114 is mounted on a first carrier substrate 302 to form a second common layer 154, as follows. Figures 3A to 3BAs illustrated, the IC die 114 can be mounted on the first carrier substrate 302 using die attachment tape, diffusion bonding, or other suitable mounting techniques. In one example, the carrier substrate 302 is coupled to the back side of the IC die 114 to form a second common layer 154, such that the active side of the IC die 114 faces away from the carrier substrate 302. The second common layer 154 of the IC die 114 bonded to the carrier substrate 302 typically forms a reconstructed wafer.

[0051] Operation 202 may include depositing dielectric material 118 in the gap space between IC dies 114, such as Figure 3C As illustrated. The dielectric material 118 can be a gap-filling oxide or other suitable dielectric material. In one example, the dielectric material 118 is a silicon-based dielectric material, such as SiO, SiN, etc. The carrier substrate 302 may extend beyond the outer side of the outermost IC die 114 within the second common layer 154, such that the dielectric material 118 is also disposed laterally outside the outermost IC die 114 of layer 154.

[0052] At operation 204, a hybrid bonding layer 122 is formed on the exposed surface of the IC die 114 of the second common layer 154, such as... Figure 3D As illustrated, as described above, the hybrid bonding layer 122 includes exposed metal pads and exposed dielectric material. The exposed metal pads are connected to bonding pads exposed on adjacent sides 144 of the IC die 114 via vias and lines formed within the hybrid bonding layer 122. The bonding pads are connected to the functional circuitry of the IC die 114.

[0053] At operation 206, the passive interposer 110 is mounted onto the IC die 114 of the second common layer 154, as follows. Figure 3E and Figure 3F As illustrated, the passive interposer 110 can be mounted to the IC die 114 of the second common layer 154 using wafer-to-wafer mounting or other techniques. In one example, the IC die 114 of the second common layer 154 is co-bonded to the passive interposer 110. The passive interposer 110 includes a BEOL region 304 fabricated on a substrate 306. The substrate 306 can be silicon or other types of wafers on which wiring interconnects can be formed using BEOL technology. The BEOL technology used to form the wiring interconnects results in wiring densities of 20 nm pitch and below.

[0054] At operation 208, the substrate 306 of the passive interposer 110 is thinned to form a thinned interposer 308, as shown below. Figure 3GAs illustrated. Substrate 306 can be thinned to less than 50% or even less than 10% of the original thickness of substrate 308 before thinning. Substrate 306 can be thinned by grinding, etching, milling or other suitable techniques. Substrate 306 can optionally be completely removed, leaving only the BEOL region 304 as the thinned interlayer 308.

[0055] Now for reference Figures 3L to 3P Additional details are provided regarding the thinning of substrate 306 performed at operation 208. (See also...) Figure 3L As illustrated, the passive interposer 110 includes a BEOL region 304 formed on a substrate 306. The BEOL region 304 includes interconnect wiring 310 formed from patterned metal layers that form lines 316 and vias 318 in a dielectric layer 320. No transistors or other active circuitry are present in the BEOL region 304. The wiring 310 connects to bonding pads 312, 314 formed on opposite sides of the BEOL region 304. Bonding pad 312 is later connected to bonding pads formed in a hybrid bonding layer 122, while bonding pad 314 is later connected to bonding pads formed in the hybrid bonding layer 122 disposed on opposite sides of the passive interposer 110, or to vias 322 formed through the substrate 306.

[0056] After the BEOL region 304 is formed, the substrate 306 is thinned or completely removed. Figure 3M The illustration shows one version of the passive interposer 110, in which the substrate 306 is completely removed. (See diagram) Figure 3M As illustrated, substrate 306 has been thinned to form a thinned substrate 308 by removing portion 324 of substrate 306, shown in dashed lines. The thinned substrate 308 includes through-silicon vias (TSVs) connected to bonding pads 312 formed in the BEOL region 304. The exposed surface of the BEOL region 304 forms a first surface 124 of the completed passive interposer 110, while the exposed surface of the thinned substrate 308 forms a second surface 126 of the completed passive interposer 110.

[0057] Subsequently, a hybrid bonding layer 122 is formed on the first surface 124 and the second surface 126 of the passive interposer layer 110, such as Figure 3N As illustrated. It should be noted that after the passive interposer 110 has been bonded to an adjacent structure using one of the hybrid bonding layers 122, another hybrid bonding layer of the hybrid bonding layers 122 can be formed on the passive interposer 110.

[0058] Figure 3NEach of the hybrid bonding layers 122 illustrated includes wiring 332 formed by patterned lines and vias. Wiring 332 terminates at bonding pads 330, 334, which are formed of copper or other suitable material. The patterned lines and vias of wiring 332 are electrically isolated from each other by a plurality of dielectric layers 336. The dielectric layers 336 are formed of materials suitable for hybrid bonding, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, etc.

[0059] When a hybrid bonding layer 122 contacts another hybrid bonding layer 122, the exposed dielectric layer 336 of one hybrid bonding layer 122 fused to the exposed dielectric layer 336 of the other hybrid bonding layer 122, thereby combining the two hybrid bonding layers 122 to form a single hybrid bonding layer 122 that holds the bonding structure together. Subsequently, pressure and heat can be used to form a metal-to-metal bond to form a eutectic metal bond between the bonding pads 330 currently in contact with each other within the combined hybrid bonding layers 122. The fusion of the metallic material of the bonding pads 330 creates an electrical interconnect between the wiring of the passive interposer 110 and the functional circuitry bonded to the IC die of the passive interposer 110.

[0060] Figure 3O The illustration shows one version of the passive interposer 110, in which the substrate 306 is completely removed. (See diagram) Figure 3O As shown in the figure, substrate 306 is completely removed as indicated by the dashed line, leaving only the BEOL region 304 as the entire passive interposer 110.

[0061] Subsequently, a hybrid bonding layer 122 is formed on the first surface 124 and the second surface 126 of the passive interposer 110, which are currently defined by opposite sides of the BEOL region 304. On the second surface 126 of the passive interposer 110, bonding pads 334 of the wiring 310 are formed on the exposed bonding pads 314 of the wiring 332, as shown. Figure 3P As illustrated. At this point, the passive interposer layer 110 is ready to be mixed-bonded to adjacent structures (such as the bare dies 112, 114 of adjacent common layers 152, 154).

[0062] Return to reference Figure 2 At operation 210 and as Figure 3H As illustrated, a hybrid bonding layer 122 is formed on the passive interposer layer 110. Although Figure 3H The passive interposer 110 shown in the figure includes a thinned substrate (such as...) Figure 3M (308 in the diagram), but the passive interposer 110 may alternatively have a substrate 306 and include only the BEOL region 304 (as shown in the diagram). Figure 3O (As shown in the diagram).

[0063] At operation 212, the IC die 112 of the first common layer 152 is mixed and bonded to the passive interposer 110, as follows: Figure 3I As shown in the diagram. At operation 214, dielectric material 118 can be used to fill the gap space between IC dies 112, such as... Figure 3J As illustrated. In optional operation 216, optional silicon block 120 can be disposed above IC die 112 of the first common layer 152, as shown. Figure 3K As illustrated, silicon block 120 can be attached to IC die 112 of first common layer 152 by fusion bonding, die attachment tape, adhesive or other suitable techniques.

[0064] Method 200 continues at operation 218 by monolithizing individual chip composites 150 from the reconstructed wafer. Each chip composite 150 can be sold as a unit and shipped to another manufacturer, which will use the chip composite 150 to manufacture chip package 100. If the chip composite 150 is the desired end product, method 200 can end after monolithization. If the chip package 100 is the desired end product, method 200 continues at operation 220, in which the chip composite 150 is mounted to the interposer 102 (or alternatively directly to the package substrate 104) using solder connectors 106 or by another suitable technique to form the chip package 100. Optionally, at operation 220, one or more additional chip composites 170 can be mounted to the interposer 102 (or alternatively directly to the package substrate 104). Also optionally, at operation 220, the chip package 100 can be mounted to the PCB 130 to form the electronic device 160.

[0065] Figure 4 This is a schematic cross-sectional view of another example of a chip package 400. The chip package 400 can be configured as a memory device, such as a high-bandwidth memory (HBM) device. The chip package 400 includes at least one integrated circuit (IC) chip composite 450 configured as a memory device and at least one chip composite 470 configured as a logic device, both of which are mounted on an interposer 102 (or alternatively directly mounted to a package substrate 104). The chip composite 450 utilizes the same passive interposer 110 disposed between two layers of the IC die as described above. The chip package 400 may optionally include one or more additional chip composites 450, 470 also mounted on the interposer 102 (or alternatively directly mounted to a package substrate 104).

[0066] Chip complex 450 includes one or more IC dies 112 configured as computing dies. IC dies 112 include a central processing unit (CPU) core and / or a graphics processing unit (GPU) core. The functional circuitry of the computing die may also include system management unit (SMU) circuitry. The SMU is circuitry configured to monitor thermal and power conditions and adjust power and cooling to keep the IC die 112 operating within specifications. The functional circuitry of the computing die may also include Dynamic Function Exchange (DFX) controller IP circuitry. DFX circuitry provides management of hardware or software-triggered events. For example, DFX circuitry can pull portions of a bitstream from memory and deliver them to an Internal Configuration Access Port (ICAP). DFX circuitry also assists with customizable logic decoupling and startup events for each reconfigurable partition. When included in the functional circuitry of IC die 112, GPU cores typically include math engine circuitry. Math engine circuitry is typically designed for task-specific computations, such as those used in data center computing, high-performance computing, and AI / ML computations. Along with the accelerated computing core, the functional circuitry of IC die 112 may also include SMU circuitry and DFX circuitry. IC die 112 communicates with the memory circuitry of chip composite 450 via wiring formed in or on the interposer layer 102. Chip composite 450 includes a first side 432 and an opposing second side 434. The first side 432 faces away from the packaging substrate 104. The first side 432 may optionally be connected to a thermal management device ( Figure 4 (Not shown in the image) are connected. The second side 434 of the chip composite 450 is coupled to the top surface 136 of the interposer 102 via solder interconnect 106 (or, in the absence of interposer 102, to the top surface 140 of the package substrate 104).

[0067] The bottom surface 138 of the interposer 102 may be coupled to the top surface 140 of the package substrate 104. The bottom surface 138 of the interposer 102 is coupled to the top surface 140 of the package substrate 104 via solder interconnects 108 or other suitable interconnects. The bottom surface 146 of the package substrate 104 may be coupled to the top surface 128 of the printed circuit board (PCB) 130, thereby forming an electronic device 460. The bottom surface 146 of the package substrate 104 is coupled to the top surface 128 of the PCB 130 via solder interconnects 148 (such as a ball grid array) or other suitable interconnects. The electronic device 460 is any of the devices described above with reference to electronic device 160.

[0068] The chip composite 450 includes a memory stack 410, at least one IC die 112 disposed in a first common layer 152, and a plurality of IC dies 114 disposed in a second common layer 154. Layers 152 and 154 are disposed on opposite sides of the passive interposer layer 110. The chip composite 150 may optionally include additional layers of one or more IC dies disposed on one or both sides of the passive interposer layer 110. The chip composite 150 may also optionally include one or more additional passive interposers 110 disposed between the layers as needed. A dielectric material 118 may be disposed between the IC dies within the common layer to increase structural rigidity and reduce the likelihood of warping of the chip composite 150.

[0069] The memory stack 410 comprises a stack of one or more memory IC dies 412. Although in Figure 4 The illustrated memory stack 410 shows two memory IC dies 412, but the memory stack 410 may include four, five, six, seven, eight, or more memory IC dies 412 stacked in a single column. Alternatively, the memory IC dies 412 may be stacked in two or more columns, wherein the width of a row of memory IC dies 412 spanning multiple columns does not exceed the width of the passive interposer layer 110. The memory IC dies 412 are held together within the memory stack 410 by hybrid bonding (e.g., by using a hybrid bonding layer 122 disposed between adjacent memory IC dies 412). Each memory IC die 412 includes memory circuitry, such as volatile memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or other suitable volatile memory types. Optionally, the memory circuitry of the memory IC die 412 may be non-volatile memory, such as ferroelectric random access memory (FeRAM) and magnetoresistive random access memory (MRAM), or other suitable non-volatile memory types.

[0070] Memory IC die 412 communicates with compute die 112 of chip composite 470 via interposer 102. Memory controller circuitry may reside on one of the IC dies 114, 112 of chip composite 470, or within one of the compute dies 112 of chip composite 450. In one example, the memory controller circuitry resides on at least one of the IC dies 114 configured as active interposer dies, while at least one of the IC dies 112 is configured as a compute die.

[0071] The passive interposer 110 is typically at least as wide as or wider than the memory IC die 142, which advantageously increases the area available for signal, ground, and power interconnects (i.e., bridging area). For example, as Figure 4As illustrated, the first surface 124 of the passive interposer 110 covers the entirety of the adjacent sides 442 of the memory IC die 412. Similarly... Figure 4 As illustrated, the second surface 126 of the passive interposer 110 covers the entirety of one IC die 114 disposed in the second common layer 154 adjacent to the passive interposer 110. In some other examples where multiple IC dies 114 exist in the second common layer 154, the second surface 126 of the passive interposer 110 covers the entirety of at least two of the more or even all IC dies 114 in the second common layer 154. The passive interposer 110 may consist only of wiring formed in the BEOL region, or may additionally include a thinned substrate with TSV.

[0072] As described above, the hybrid bonding layer 122 physically and electrically couples the IC dies 112, 114, 412 to each of the other IC dies and / or passive interposers 110 of the chip composite 450. Figure 4 In the example depicted, the IC die 114 of the second common layer 154 is hybrid-bonded to the passive interposer 110 using a hybrid bonding layer 122, the passive interposer 110 is hybrid-bonded to the memory stack 410 using the hybrid bonding layer 122, and the memory stack 410 is hybrid-bonded to the IC die 112 of the first common layer 152 using the hybrid bonding layer 122. Optional silicon blocks 120 may be fused or otherwise secured to the IC die 112 of the first common layer 152.

[0073] Figures 5 to 7 It is possible Figure 4 The diagram illustrates different chip composites 550, 650, and 750 used in place of chip composite 450 in the chip package 400. Chip composites 550, 650, and 750 are largely the same as chip composite 450, except that the memory stack 410, the first common layer 152 of the IC die 114, and the second common layer 154 of the IC die 112 are located in different positions within the chip composite.

[0074] First go to Figure 5 The illustrated chip composite 550 includes at least one or more passive interposers 110, two or more IC dies 112 of a first common layer 152, and two or more IC dies 114 of a second common layer 154. The chip composite 550 has a first side 532 and a second side 534. The second side 534 is configured to be mounted on a package substrate 104 and / or the interposer 102 using solder interconnects 108 / 106. The chip composite 550 includes a memory stack 410, which includes one or more memory IC dies 412. Figure 5Four memory IC dies 412 are shown, but one to eight or more memory IC dies 412 can alternatively be used. The IC dies 412 are bonded together, for example, using a hybrid bonding layer 122. (See above reference) Figure 4 Additional details about memory stack 410 are described.

[0075] Continue to refer to Figure 5 One side of the memory stack 410 defines a second side 534 of the chip composite 550. This side of the memory stack 410 is hybrid-bonded to a passive interposer 110 using a hybrid bonding layer 122. The passive interposer 110 is hybrid-bonded to an IC die 114 of a second common layer 154 using the hybrid bonding layer 122. The IC die 114 of the second common layer 154 is hybrid-bonded to an IC die 112 of a first common layer 152 using the hybrid bonding layer 122. Optional silicon blocks 120 may be fused-bonded or otherwise attached to the IC die 112 of the first common layer 152.

[0076] Figure 6 Another example of a chip composite 750 is depicted. Chip composite 650 has a first side 632 and a second side 634. The second side 634 is configured to be mounted on a package substrate 104 or an interposer 102 using solder interconnects 108 / 106. Chip composite 650 includes a memory stack 410, which includes one or more memory IC dies 412. Figure 6 Four memory IC dies 412 are shown, but one to eight or more memory IC dies 412 may alternatively be used. The IC dies 412 are bonded together, for example, by using a hybrid bonding layer 122.

[0077] Chip composite 650 includes at least one or more passive interposers 110, two or more IC dies 112 of a first common layer 152, and two or more IC dies 114 of a second common layer 154. One side of the IC dies 114 of the second common layer 154 defines a second side 634 of chip composite 650. The other side of the IC dies 114 of the second common layer 154 is hybrid bonded to a memory stack 410 using a hybrid bonding layer 122. The memory stack 410 is hybrid bonded to the IC dies 112 of the first common layer 152 using the hybrid bonding layer 122. Optional silicon blocks 120 may be fused or otherwise fixed to the IC dies 112 of the first common layer 152.

[0078] Figure 7Another example of a chip composite 750 is depicted. The chip composite 750 has a first side 732 and a second side 734. The second side 734 is configured to be mounted on an optional interposer 102 or package substrate 104 using solder interconnects 106 / 108. The chip composite 750 includes a memory stack 410 comprising one or more memory IC dies 412. Figure 7 Four memory IC dies 412 are shown, but one to eight or more memory IC dies 412 may alternatively be used. The IC dies 412 are bonded together, for example, by using a hybrid bonding layer 122.

[0079] Chip composite 750 includes at least one or more passive interposers 110, two or more IC dies 112 of a first common layer 152, and two or more IC dies 114 of a second common layer 154. One side of the IC dies 114 of the second common layer 154 defines a second side 734 of chip composite 750. The other side of the IC dies 114 of the second common layer 154 is hybrid bonded to the IC dies 112 of the first common layer 152 using a hybrid bonding layer 122. The IC dies 112 of the first common layer 152 are hybrid bonded to the memory stack 410 using the hybrid bonding layer 122. Optional silicon block 120 ( Figure 7 (Not shown) can be fused or otherwise fixed to the side of memory stack 410 opposite to the first common layer 152.

[0080] Figure 8 This is a block diagram of a method 800 for manufacturing chip complexes (such as chip complex 550, 750 or other similar chip complexes). Method 800 can be extended to form chip packages, such as chip package 400 or other suitable chip packages. Figures 9A to 9G Chip composites 550 (750) at different manufacturing stages are depicted.

[0081] Method 800 begins at operation 802, in which the memory stack 410 is mounted on the first carrier substrate 302, as... Figure 9A As illustrated, the memory stack 410 can be mounted on the first carrier substrate 302 using die attachment tape, diffusion bonding, or other suitable mounting techniques. As described above, the memory stack 410 includes one or more memory IC dies 412. Although in Figure 9AThe illustrated memory stack 410 shows four memory IC dies 412, but the memory stack 410 may include four, five, six, seven, eight, or more memory IC dies 412 stacked in a single column. Alternatively, the memory IC dies 412 may be stacked in two or more columns. The memory IC dies 412 are held together within the memory stack 410 by hybrid bonding (e.g., by using a hybrid bonding layer 122 disposed between adjacent memory IC dies 412).

[0082] At operation 804, the passive interposer layer 110 is mounted onto the memory stack 410, as follows: Figure 9B and Figure 9C As illustrated, the passive interposer 110 can be mounted to the memory stack 410 using wafer-to-wafer mounting or other techniques. In one example, the memory stack 410 is hybrid-bonded to the passive interposer 110, for instance, using a hybrid bonding layer 122. As described above, the passive interposer 110 includes a BEOL region 304 fabricated on a substrate 306. The substrate 306 can be silicon or other types of wafers on which wiring interconnects can be formed using BEOL technology. The BEOL technology used to form the wiring interconnects results in wiring densities of 80 nm pitch and below.

[0083] At operation 806, the substrate 306 of the passive interposer 110 is thinned to form a thinned interposer 308, as shown below. Figure 9D As illustrated. Substrate 306 can be thinned to less than 50% or even less than 10% of the original thickness of substrate 308 before thinning. Substrate 306 can be thinned by grinding, etching, milling or other suitable techniques. Substrate 306 can optionally be completely removed, leaving only the BEOL region 304 as the thinned interlayer 308.

[0084] At operation 808, one or more IC dies 114 are mounted onto the passive interposer 110, such as... Figure 9E As illustrated. IC dies 114 can be arranged in a common layer 154 before being mounted on a passive interposer 110, for example, by forming a reconstructed wafer using a carrier substrate 902, wherein dielectric material 118 is disposed between adjacent IC dies 114. IC dies 114 can be attached to the carrier substrate 902 by fusion bonding, die attachment tape, or other suitable techniques. Although in Figure 9E Not shown in the figure, but IC die 114 is attached to passive interposer 110 using hybrid bonding (e.g., by using hybrid bonding layer 122).

[0085] At operation 810, one or more IC dies 112 are mounted onto the common layer 154 of IC die 114, such as... Figure 9FAs illustrated, IC die 112 can be disposed in a common layer 152. IC die 112 of the common layer 152 can be secured to IC die 114 of the common layer 154 using hybrid bonding (e.g., by using hybrid bonding layer 122). Once IC die 112 is mounted to the common layer 154 of IC die 112, the gap between IC dies 114 is filled with dielectric material 118.

[0086] The chip composite 550 can be accomplished by providing solder interconnects 106 on the memory IC die 412 forming the second side 534 of the chip composite 550. Alternatively, the chip composite 750 can be accomplished by providing solder interconnects 106 on the common layer 154 of the IC die 112 forming the second side 734 of the chip composite 750.

[0087] Method 800 continues at operation 812 by monolithizing individual chip composites 550 (750) from the reconstructed wafer. Each chip composite 550 (750) can be sold as a unit and shipped to another manufacturer that will use the chip composite 550 (750) to manufacture chip package 400. If the chip composite 550 (750) is the desired end product, method 800 can end after monolithization. If the chip package 400 is the desired end product, method 800 continues at operation 814, in which the chip composite 550 (750) is mounted to an optional interposer 102 and package substrate 104 using solder joints 106 / 108 or by another suitable technique to form chip package 400. Optionally, at operation 816, one or more additional chip composites 470 can be mounted to the interposer 102 and / or package substrate 104. Alternatively, at operation 816, the chip package 400 can be mounted to the PCB 130 to form an electronic device 460.

[0088] Figure 10 This is a block diagram of a method 1000 for manufacturing a chip composite (such as chip composite 650 or other similar chip composites). Method 1000 can be extended to form a chip package, such as chip package 400 or other suitable chip package. Figures 11A to 11F The chip composite 650 is depicted at different manufacturing stages.

[0089] Method 1000 begins at operation 1002, in which the memory stack 410 is mounted on the first carrier substrate 302, as... Figure 11A As illustrated, the memory stack 410 can be mounted on the first carrier substrate 302 using die attachment tape, diffusion bonding, or other suitable mounting techniques. As described above, the memory stack 410 includes one or more memory IC dies 412. Although in Figure 11A The illustrated memory stack 410 shows four memory IC dies 412, but the memory stack 410 may include four, five, six, seven, ten, or more memory IC dies 412 stacked in a single column. Alternatively, the memory IC dies 412 may be stacked in two or more columns. The memory IC dies 412 are held together within the memory stack 410 by hybrid bonding (e.g., by using a hybrid bonding layer 122 disposed between adjacent memory IC dies 412).

[0090] At operation 1004, the passive interposer layer 110 is mounted onto the memory stack 410, as follows: Figure 11B As illustrated, the passive interposer 110 can be mounted to the memory stack 410 using wafer-to-wafer mounting or other techniques. In one example, the memory stack 410 is hybrid-bonded to the passive interposer 110, for instance, using a hybrid bonding layer 122. As described above, the passive interposer 110 includes a BEOL region 304 fabricated on a substrate 306. The substrate 306 can be silicon or other types of wafers on which wiring interconnects can be formed using BEOL technology. The BEOL technology used to form the wiring interconnects results in wiring densities of 100 nm pitch and below.

[0091] At operation 1006, the substrate 306 of the passive interposer 110 is thinned to form a thinned interposer 308, as shown below. Figure 11C As illustrated. Substrate 306 can be thinned to less than 50% or even less than 10% of the original thickness of substrate 308 before thinning. Substrate 306 can be thinned by grinding, etching, milling or other suitable techniques. Substrate 306 can optionally be completely removed, leaving only the BEOL region 304 as the thinned interlayer 308.

[0092] At operation 1008, one or more IC dies 112 are mounted onto the passive interposer layer 110, such as... Figure 11D As illustrated, IC dies 112 can be disposed in a common layer 152 prior to mounting on a passive interposer 110, for example, by forming a reconstructed wafer using a carrier substrate 1100, wherein dielectric material 118 is disposed between adjacent IC dies 112. IC dies 112 can be attached to the carrier substrate 1100 by fusion bonding, die attachment tape, or other suitable techniques. Although in Figure 11D Not shown in the figure, but IC die 112 is attached to passive interposer 110 using hybrid bonding (e.g., by using hybrid bonding layer 122).

[0093] At operation 1010, on the side of memory stack 410 opposite to the common layer 152 of IC die 114, one or more IC dies 112 are mounted onto memory stack 410, as follows: Figure 11E As illustrated, the IC die 114 can be disposed in a common layer 154. This can be achieved by using hybrid bonding (e.g., by using hybrid bonding layer 122). Figure 11E (Not shown in the image) The IC die 114 of the common layer 154 is secured to the exposed memory IC die 412 of the memory stack 410. Once the IC dies 114 are mounted to the memory stack 410, the gaps between the IC dies 114 are filled with dielectric material 118, such as... Figure 11F As shown in the diagram.

[0094] Method 1000 continues at operation 1012 by monolithizing individual chip composites 650 from the reconstructed wafer. Each chip composite 650 can be sold as a unit and shipped to another manufacturer, which will use the chip composite 650 to manufacture chip package 400. If the chip composite 650 is the desired end product, method 1000 can end after monolithization. If the chip package 400 is the desired end product, method 1000 continues at operation 1014, in which the chip composite 650 is mounted to the interposer 102 and / or the package substrate 104 using solder connections 106 / 108 or by another suitable technique to form the chip package 400. Optionally, at operation 1016, one or more additional chip composites 470 may be mounted to the interposer 102 (or alternatively, the package substrate 104). Alternatively, at operation 1016, the chip package 400 can be mounted to the PCB 130 to form an electronic device 460.

[0095] Figure 12 This is a block diagram of a method 1200 for manufacturing a chip composite (such as chip composite 650 or other similar chip composites). Method 1200 can be extended to form a chip package, such as chip package 400 or other suitable chip package. Figures 13A to 13G The chip composite 650 at different manufacturing stages is depicted.

[0096] Method 1200 begins with operation 1202, in which a plurality of IC dies 112 are mounted on a first carrier substrate 302, such as Figure 13A As illustrated, the IC die 112 can be back-mounted to the first carrier substrate 302 by diffusion bonding or other suitable techniques. The IC die 112 diffusely bonded to the carrier substrate 302 typically forms a reconstructed wafer.

[0097] At operation 1204, a passive interposer 110 is mounted onto the IC die 112 that is diffusely bonded to the carrier substrate 302, as follows. Figure 13B As illustrated, a passive interposer 110 can be mounted to an IC die 112 defining a common layer 152 using wafer-to-wafer mounting or other techniques. In one example, the IC die 112 is mounted, for example, using a hybrid bonding layer 122 (… Figure 13B (Not shown) is mixed and bonded to the passive interposer 110. As described above, the passive interposer 110 includes BEOL regions 304 fabricated on a substrate 306. The substrate 306 may be silicon or other types of wafers on which wiring interconnects can be formed using BEOL technology. The BEOL technology used to form the wiring interconnects results in wiring densities of 120 nm pitch and below.

[0098] At operation 1206, the substrate 306 of the passive interposer 110 is thinned to form a thinned interposer 308, as shown below. Figure 13C As illustrated. Substrate 306 can be thinned to less than 50% or even less than 12% of its original thickness before thinning. Substrate 306 can be thinned by grinding, etching, milling, or other suitable techniques. Substrate 306 can optionally be completely removed, leaving only the BEOL region 304 as the thinned interposer layer 308. After thinning or removing substrate 306 at operation 1206, a hybrid bonding layer 122 is formed on the exposed side of the passive interposer layer 110 away from the carrier substrate 302.

[0099] At operation 1208, the memory stack 410 is mounted onto the passive interposer layer 110, as follows. Figure 13D As illustrated. For example, memory stack 410 is hybrid-bonded to passive interposer 110 using hybrid bonding layer 122. Memory stack 410 may include temporary carrier substrate 1302. Memory IC dies 412 of memory stack 410 are secured together within memory stack 410 by hybrid bonding (e.g., by using hybrid bonding layer 122 disposed between adjacent memory IC dies 412 and passive interposer 110).

[0100] At operation 1210, multiple IC dies 114 are mounted on the side of the memory stack 410 opposite to the passive interposer layer 110, as follows: Figure 13F As shown in the diagram. At operation 1212, the gap between the IC dies 114 is filled with dielectric material 118, as illustrated. Figure 13G As illustrated. The temporary carrier substrate 302 can also be removed at either operation 1208 or operation 1210.

[0101] Method 1200 continues at operation 1214 by monolithizing individual chip composites 650 from the reconstructed wafer. Each chip composite 650 can be sold as a unit and shipped to another manufacturer, which will use the chip composite 650 to manufacture chip package 400. If the chip composite 650 is the desired end product, method 1200 can end after monolithization. If the chip package 400 is the desired end product, method 1200 continues at operation 1216, in which the chip composite 650 is mounted to an optional interposer 102 and / or package substrate 104 using solder joints 106 / 108 or by another suitable technique to form chip package 400. Optionally, at operation 1218, one or more additional chip composites 470 can be mounted to the interposer 102 and / or package substrate 104. Also optionally, at operation 1218, chip package 400 can be mounted to PCB 130 to form electronic device 460.

[0102] Using a hybrid wafer-on-chip hybrid bonding process, the active side of a common layer IC die is bonded to metal bonding pads exposed on a hybrid bonding layer formed opposite to the BEOL side of the substrate. The entire surface of each common layer IC die is bonded to the hybrid bonding layer of the substrate, which significantly increases the area available for interconnection between wiring in the substrate and the bonding pads of the second common layer IC die.

[0103] The techniques disclosed above can be expressed in the following non-limiting embodiments. Chip complexes, chip packages, and electronic devices are all examples of integrated circuit (IC) devices.

[0104] Example 1. An integrated circuit (IC) chip composite, the IC chip composite comprising: a passive interposer including interconnects formed in a back-end process (BEOL) region; at least a first IC die of a first common layer, the first IC die of the first common layer being co-bonded to a first side of the passive interposer; and at least two or more second IC dies of a second common layer, the at least two or more second IC dies of the second common layer being co-bonded to a second side of the passive interposer.

[0105] Example 2. According to the IC chip composite described in Example 1, the passive interposer layer covers the entire first IC die.

[0106] Example 3. According to the IC chip composite described in Example 2, the passive interposer layer covers the entirety of the second IC die among the plurality of first IC dies present in the first common layer.

[0107] Example 4. According to the IC chip composite of Example 2, wherein the passive interposer layer covers the entirety of the first IC die among the plurality of second IC dies present in the second common layer.

[0108] Example 5. According to the IC chip composite of Example 4, wherein the passive interposer layer covers the entirety of the second IC die among the plurality of first IC dies present in the second common layer.

[0109] Example 6. The IC chip composite according to Example 1, wherein the passive interposer includes: a thinned substrate; and a via formed through the thinned substrate, the via being coupled to the interconnect.

[0110] Example 7. The IC chip composite according to Example 6, wherein the passive interposer layer includes passive wiring and does not contain transistors.

[0111] Example 8. An IC chip composite according to Example 1, wherein the BEOL region defines the first side and the second side of the passive interposer.

[0112] Example 9. According to the IC chip composite of Example 1, the IC chip composite further includes: a silicon block disposed above the first IC die.

[0113] Example 10. The IC chip composite according to Example 1, wherein the first IC die is a memory die.

[0114] Example 11. The IC chip composite according to Example 1, wherein the first IC die is a logic die.

[0115] Example 12. According to the IC chip composite of Example 1, the IC chip composite further includes an active-passive interposer die stacked with the passive interposer.

[0116] Example 13. An integrated circuit (IC) chip package, the IC chip package comprising: a package substrate; and a chip composite mounted to the package substrate, the chip composite comprising: a passive interposer; at least a first IC die of a first common layer, the first IC die of the first common layer being co-bonded to a first side of the passive interposer; and at least two or more second IC dies of a second common layer, the at least two or more second IC dies of the second common layer being co-bonded to a second side of the passive interposer.

[0117] Example 14. The chip package according to Example 13, wherein the passive interposer layer covers the entirety of the first IC die present in the first common layer and all the second IC dies present in the second common layer.

[0118] Example 15. The chip package according to Example 14, wherein the substrate includes passive wiring and does not contain transistors.

[0119] Example 16. A chip package according to Example 15, wherein the passive interposer includes: an interconnect disposed in the BEOL region of a thinned substrate; and a via formed through the thinned substrate and coupled to the interconnect.

[0120] Example 17. The chip package according to Example 15, wherein the passive interposer layer includes: an interconnect disposed in the BEOL region, the BEOL region including the first side and the second side of the passive interposer layer.

[0121] Example 18. The chip package according to Example 13, wherein the first IC die is a memory die or a logic die.

[0122] Example 19. A method for forming a chip composite, the method comprising: fixing a plurality of IC dies forming a first common layer to a temporary carrier substrate; co-bonding the IC dies of the first common layer to a first side of a passive interposer; thinning a second side of the passive interposer; co-bonding IC dies of a second common layer to the second side of the passive interposer; and removing the temporary carrier substrate.

[0123] Example 20. According to the method of Example 19, wherein mixing and bonding the IC die of the first common layer to the first side of the passive interposer layer includes performing a wafer-to-wafer mixed bonding process; and wherein mixing and bonding the IC die of the second common layer to the first side of the passive interposer layer includes performing a chip-to-wafer mixed bonding process.

[0124] Example 21. An integrated circuit (IC) memory chip composite, the IC memory chip composite comprising: a passive interposer; a plurality of memory IC dies stacked together, one of the memory IC dies being co-bonded to a first side of the passive interposer; and at least two or more IC dies of a first common layer, the at least two or more IC dies of the first common layer being co-bonded to a second side of the passive interposer.

[0125] Example 22. An IC memory chip composite according to Example 21, wherein the passive interposer layer covers the entirety of the memory IC die.

[0126] Example 23. An IC memory chip composite according to Example 22, wherein the passive interposer layer covers the entirety of one of the two or more IC dies present in the first common layer.

[0127] Example 24. An IC memory chip composite according to Example 22, wherein the passive interposer layer covers the entirety of all IC dies present in the first common layer.

[0128] Example 25. According to the IC memory chip complex of Example 24, the IC memory chip complex further includes: at least two or more IC dies in a second common layer, wherein the at least two or more IC dies in the second common layer are mixed and bonded to the IC dies present in the first common layer.

[0129] Example 26. An IC memory chip composite according to Example 25, wherein at least one of the IC dies in the first common layer and the second common layer includes a memory controller circuit.

[0130] Example 27. An IC memory chip composite according to Example 26, wherein at least one of the IC dies in the first common layer and the second common layer includes logic circuitry coupled to the at least one IC die including memory controller circuitry.

[0131] Example 28. An IC memory chip composite according to Example 21, wherein the passive interposer includes: an interconnect disposed in the BEOL region of a thinned substrate; and a via formed through the thinned substrate and coupled to the interconnect.

[0132] Example 29. An IC memory chip composite according to Example 28, wherein the substrate includes passive wiring and does not contain transistors.

[0133] Example 30. An IC memory chip composite according to Example 21, wherein the passive interposer layer includes: an interconnect disposed in a BEOL region, the BEOL region including a first side and a second side of the passive interposer layer.

[0134] Example 31. An integrated circuit (IC) chip package, the IC chip package comprising: a package substrate; one or more logic IC dies mounted on the package substrate; and a chip composite mounted to the package substrate and communicatively coupled to the one or more logic IC dies via the package substrate, the chip composite comprising: a passive interposer; a plurality of memory IC dies stacked together, one of the memory IC dies being co-bonded to a first side of the passive interposer; and at least two or more IC dies of a first common layer, the at least two or more IC dies of the first common layer being co-bonded to a second side of the passive interposer.

[0135] Example 32. The chip package according to Example 31, wherein the passive interposer layer covers the entirety of the memory IC die.

[0136] Example 33. The chip package according to Example 32, wherein the passive interposer layer covers the entirety of one of the two or more IC dies present in the first common layer.

[0137] Example 34. The chip package according to Example 32, wherein the passive interposer layer covers the entirety of all IC dies present in the first common layer.

[0138] Example 35. According to the chip package of Example 34, the IC memory chip composite further includes: at least two or more IC dies in a second common layer, wherein the at least two or more IC dies in the second common layer are mixed and bonded to the IC dies present in the first common layer.

[0139] Example 36. The chip package according to Example 35, wherein at least one of the IC dies in the first common layer and the second common layer includes a memory controller circuit.

[0140] Example 37. The chip package according to Example 36, wherein at least one of the IC dies in the first common layer and the second common layer includes logic circuitry coupled to the at least one IC die including memory controller circuitry.

[0141] Example 38. A chip package according to Example 31, wherein the passive interposer includes: an interconnect disposed in the BEOL region of a thinned substrate; and a via formed through the thinned substrate and coupled to the interconnect.

[0142] Example 39. The chip package according to Example 38, wherein the substrate includes passive wiring and does not contain transistors.

[0143] Example 40. The chip package according to Example 31, wherein the passive interposer layer includes: an interconnect disposed in the BEOL region, the BEOL region including the first side and the second side of the passive interposer layer.

[0144] While the foregoing describes embodiments of the present invention, other and further embodiments of the present invention may be designed without departing from the basic scope of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. An integrated circuit (IC) chip complex, the IC chip complex comprising: a passive interposer comprising interconnects formed in a back end of line (BEOL) region; at least a first IC die of a first common layer hybrid bonded to a first side of the passive interposer; and at least two or more second IC dies of a second common layer hybrid bonded to a second side of the passive interposer.

2. The IC chip complex of claim 1, wherein, the passive interposer comprising: a thinned substrate; and a via formed through the thinned substrate, the via coupled to the interconnects.

3. The IC chip complex of claim 1, wherein, the BEOL region defining the first side and the second side of the passive interposer.

4. The IC chip complex of claim 1, the IC chip complex further comprising: a silicon block disposed above the first IC die.

5. The IC chip complex of claim 1, wherein, the first IC die is a memory die.

6. The IC chip complex of claim 1, wherein, the first IC die is a logic die.

7. An integrated circuit (IC) chip package, the IC chip package comprising: a substrate; and a chip complex mounted to the substrate, the chip complex comprising: a passive interposer; at least a first IC die of a first common layer hybrid bonded to a first side of the passive interposer; and at least two or more second IC dies of a second common layer hybrid bonded to a second side of the passive interposer.

8. The IC chip complex of claim 1 or 7, wherein, the passive interposer covers an entirety of the first IC die.

9. The IC chip complex of claim 8, wherein, the passive interposer covers an entirety of a second IC die present in the first common layer.

10. The IC chip complex of claim 8, wherein, the passive interposer covers an entirety of a first of the at least two or more second IC dies present in the second common layer.

11. The IC chip complex of claim 8, wherein, the passive interposer covers an entirety of a second of the at least two or more second IC dies present in the second common layer.

12. The chip package of claim 9, wherein, the substrate comprises passive wiring without the presence of transistors.

13. The chip package of claim 12, wherein, the passive interposer comprising: interconnects disposed in a BEOL region of a thinned substrate; and a via formed through the thinned substrate, the via coupled to the interconnects.

14. The chip package of claim 12, wherein, the passive interposer comprising: interconnects disposed in a BEOL region, the BEOL region comprising the first side and the second side of the passive interposer.

15. The chip package of claim 7, wherein, the first IC die is a memory die or a logic die.

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