Chip, chip package and computing device

Abstract

The invention relates to the field of semiconductors, and provides a chip, a chip package and computing equipment. The chip comprises a plurality of waveguide links, each waveguide link comprises a lower-layer waveguide, an intermediate-layer waveguide and an upper-layer waveguide, and the intermediate-layer waveguides are coupled to the lower-layer waveguides and the upper-layer waveguides respectively to achieve optical connection of the lower-layer waveguides and the upper-layer waveguides; wherein the lower layer waveguide comprises a first section, a bending part and a second section, and the bending part is configured to be connected with the first section and the second section; the first segment of the lower layer waveguide and the upper layer waveguide are respectively coupled to the intermediate layer waveguide to realize the optical connection.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductors, and more specifically, to chips, chip packages, and computing devices. BACKGROUND

[0002] Waveguide links in a photonic integrated circuit can enable transmission of optical signals for use in optical interconnects and the like. SUMMARY

[0003] The present application provides a chip, a chip package, and a computing device.

[0004] According to a first aspect of the present application, a chip is provided, comprising: a plurality of waveguide links, the waveguide links comprising a lower layer waveguide, an intermediate layer waveguide, and an upper layer waveguide, the intermediate layer waveguide being coupled to the lower layer waveguide and the upper layer waveguide respectively to enable optical connection of the lower layer waveguide and the upper layer waveguide; wherein the lower layer waveguide comprises a first segment, a curved portion, and a second segment, the curved portion being configured to connect the first segment and the second segment; the first segment of the lower layer waveguide and the upper layer waveguide being coupled to the intermediate layer waveguide to enable the optical connection.

[0005] In some embodiments, a size of an optical mode spot of the lower layer waveguide is smaller than a size of an optical mode spot of the upper layer waveguide.

[0006] In some embodiments, the chip further comprises a substrate, the plurality of waveguide links comprises a first waveguide link and a second waveguide link, a projection of the upper layer waveguide of the first waveguide link and the lower layer waveguide of the second waveguide link on a plane in which the substrate lies has an overlapping region.

[0007] In some embodiments, a material of the intermediate layer waveguide comprises nitrogen and silicon.

[0008] In some embodiments, a material of the upper layer waveguide comprises nitrogen and silicon.

[0009] In some embodiments, the plurality of waveguide links comprises a first waveguide link, the first waveguide link comprises an optical detector, the optical detector being coupled to one of the upper layer waveguide and the lower layer waveguide of the first waveguide link.

[0010] In some embodiments, the plurality of waveguide links comprises a first waveguide link, the first waveguide link comprises an optical detector and an optical modulator, the optical detector being coupled to the lower layer waveguide of the first waveguide link, the optical modulator being coupled to the upper layer waveguide of the first waveguide link.

[0011] In some embodiments, the plurality of waveguide links includes a first waveguide link including an optical detector coupled to the upper waveguide of the first waveguide link and an optical modulator coupled to the lower waveguide of the first waveguide link.

[0012] According to a second aspect of the present application, a chip package is provided, comprising: an interposer; a plurality of semiconductor chips optically connected to the interposer, wherein the number of the plurality of semiconductor chips is at least 4; a photonic interconnect chip optically connected to the interposer; wherein each of the plurality of semiconductor chips is configured to be optically connected to the photonic interconnect chip via the interposer respectively, such that any two of the plurality of semiconductor chips achieve optical signal communication; wherein the photonic interconnect chip employs the chip according to the first aspect of the present application.

[0013] According to a third aspect of the present application, the computing device comprises the chip according to the first aspect of the present application.

[0014] The various aspects, features, advantages of embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The above aspects, features, advantages of the present application will become more apparent from the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a top view of a chip according to an embodiment of the present application.

[0016] Figure 2 is a cross-sectional view of a chip according to an embodiment of the present application.

[0017] Figure 3 is a top view of a chip according to an embodiment of the present application.

[0018] Figure 4 is a cross-sectional view of a chip package according to some embodiments of the present application.

[0019] Figure 5 is a top view of a chip package according to an embodiment of the present application.

[0020] Figure 6 is a cross-sectional view of a photonic interconnect chip according to an embodiment of the present application.

[0021] Figure 7 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0022] Figure 8 is a chip package according to an embodiment of the present application, and shows the coupling relationship of waveguide links. DETAILED DESCRIPTION

[0023] To facilitate understanding of the various aspects, features, and advantages of the technical solution of this invention, the invention will be described in detail below with reference to the accompanying drawings. It should be understood that the various embodiments described below are for illustrative purposes only and are not intended to limit the scope of protection of this invention.

[0024] According to one aspect of the invention, such as Figure 1 A chip 500 was proposed. Figure 1 A top view of chip 500 is shown, including: multiple waveguide links 510, each waveguide link 510 including a lower waveguide 511, an intermediate waveguide 513, and an upper waveguide 515. The intermediate waveguide 513 is coupled to the lower waveguide 511 and the upper waveguide 515 respectively to achieve optical connection between the lower waveguide 511 and the upper waveguide 515. The lower waveguide 511 includes a first segment 5112, a bend 5114, and a second segment 5116. The bend 5114 is configured to connect the first segment 5112 and the second segment 5116. The first segment 5112 of the lower waveguide 511 and the upper waveguide 515 are coupled to the intermediate waveguide 513 respectively to achieve the optical connection.

[0025] The bend 5114 allows the waveguide link to change direction and extend to different regions. For example, the optical mode size of the lower waveguide is smaller than that of the upper waveguide. That is, the bend is provided in the waveguide layer (lower waveguide) with the smaller mode size. As a result, the bend 5114 of the lower waveguide 511 has a smaller turning radius, and the lower waveguide 511 or the bend 5114 can be arranged more densely without optical interference.

[0026] like Figure 1 As shown, the intermediate waveguide 513 has tapered waveguides at both ends, and the first segment 5112 of the lower waveguide 511 may include tapered waveguides. Furthermore, the upper waveguide 515 may also include tapered waveguides at its ends. Figure 1 (Not shown).

[0027] Figure 2 A cross-sectional view of chip 500 is shown, illustrating a waveguide link in which the first segment 5112 of the lower waveguide and the upper waveguide 515 are coupled to the intermediate waveguide 513 to achieve the optical connection. The figure also shows that chip 500 includes a substrate 550 and a buried oxide layer 560. In a direction perpendicular to the substrate 550, the lower waveguide 511, the intermediate waveguide 513, and the upper waveguide 515 are arranged sequentially from closest to farthest from the substrate 550.

[0028] Combination Figures 1-2The lower waveguide 511, the intermediate waveguide 513 and the upper waveguide 515 are respectively coupled with the intermediate waveguide 513. Exemplarily, the coupling between the first section 5112 of the lower waveguide and the intermediate waveguide 513 can be evanescent wave coupling, and the coupling between the upper waveguide 515 and the intermediate waveguide 513 can also be evanescent wave coupling.

[0029] For the case where a large number of waveguide links 510 need to be arranged, the waveguides in the waveguide links are arranged in layers, i.e., the lower waveguide and the upper waveguide, so as to increase the arrangement density of the waveguide links 510. The lower waveguide 511 and the upper waveguide 515 of different waveguide links 510 have sufficient spacing in the vertical direction (the direction perpendicular to the substrate), so that it can be considered that there is no optical interference.

[0030] In some embodiments, as shown in FIG. 5A, the chip 500 includes a plurality of waveguide links 510. Exemplarily, the plurality of waveguide links 510 includes a first waveguide link 510a and a second waveguide link 510b. Figure 3 As shown in FIG. 5B, a top view of the chip 500, the plurality of waveguide links includes a first waveguide link 510a and a second waveguide link 510b. The upper waveguide 515 of the first waveguide link 510a and the lower waveguide 511 of the second waveguide link 510b have an overlapping area in the projection on the plane where the substrate is located. Since the upper waveguide 515 of the first waveguide link 510a and the lower waveguide 511 of the second waveguide link 510b have sufficient distance in the vertical direction (the direction perpendicular to the substrate), for example, the distance therebetween is greater than the optical coupling distance, the optical interference therebetween can be ignored, i.e., even if the two waveguide links transmit optical signals at the same time, they will not cause crosstalk. Exemplarily, the lower waveguide 511 is a silicon waveguide. Figure 3 Another waveguide link 510c is also exemplified, and the upper waveguide 515 thereof and the lower waveguide 511 of the second waveguide link 510b also have an overlapping area in the projection on the plane where the substrate is located.

[0031] Exemplarily, the lower waveguide 511 is a silicon waveguide.

[0032] In some embodiments, the material of the intermediate waveguide 513 contains nitrogen element and silicon element.

[0033] In some embodiments, the material of the upper waveguide 515 contains nitrogen element and silicon element.

[0034] In some embodiments, the plurality of waveguide links includes a first waveguide link, and the first waveguide link includes a light detector coupled to one of the upper waveguide and the lower waveguide of the first waveguide link.

[0035] In some embodiments, the plurality of waveguide links includes a first waveguide link, and the first waveguide link includes a light detector coupled to the lower waveguide of the first waveguide link and a light modulator coupled to the upper waveguide of the first waveguide link.

[0036] In some embodiments, the plurality of waveguide links includes a first waveguide link, the first waveguide link including a photodetector and an optical modulator, the photodetector being coupled to the upper waveguide of the first waveguide link and the optical modulator being coupled to the lower waveguide of the first waveguide link.

[0037] According to one aspect of the invention, such as Figure 4 A chip package 100 is proposed, comprising: an interposer 110; a plurality of semiconductor chips 120 optically connected to the interposer 110, wherein the plurality of semiconductor chips include a first semiconductor chip 120a and a second semiconductor chip 120b; and a photonic interconnect chip 130 optically connected to the interposer 110; wherein the first semiconductor chip 120a and the second semiconductor chip 120b are optically connected to the photonic interconnect chip 130 via the interposer 110, so that the first semiconductor chip 120a and the second semiconductor chip 120b can achieve optical signal communication.

[0038] The optical connection between the first semiconductor chip 120a and the second semiconductor chip 120b enables them to communicate optical signals, avoiding the delays and energy losses associated with electrical signal communication. Optical channels are provided in the photonic interconnect chip 130 and the interposer 110 for propagating optical signals. The photonic interconnect chip 130 can be designed with a more complex waveguide arrangement, while the interposer 110 can have a relatively simple waveguide arrangement. Appropriate manufacturing methods can be selected based on manufacturing costs and process requirements, and the two can be manufactured separately. The interposer 110 can have a larger area than the photonic interconnect chip 130, thereby supporting both the photonic interconnect chip 130 and the semiconductor chip 120.

[0039] Thus, the intermediary 110 and the photonic interconnect chip 130 respectively serve as optical connections, enabling communication between the first semiconductor chip 120a and the second semiconductor chip 120b. Furthermore, the optical connection of the semiconductor chip 120 to the intermediary 110 avoids losses associated with electrical bonding and circuit transmission.

[0040] exist Figure 4 In this configuration, the intermediary 110 is configured to carry the plurality of semiconductor chips 120 and the photonic interconnect chip 130. The intermediary 110 has a first surface and a second surface opposite to the first surface. In some embodiments, such as... Figure 4The plurality of semiconductor chips 120 and the photonic interconnect chip 130 are all located on the same surface of the interposer 110, such as the first surface. In some other embodiments, the photonic interconnect chip 130 is located on the first surface of the interposer 110, and the plurality of semiconductor chips 120 are located on the second surface of the interposer 110.

[0041] In some embodiments, the semiconductor chip 120 and the photonic interconnect chip 130 can be mounted on the intermediary 110 by means of a bonding material, which can be an organic material, a metallic material, a solder, etc.

[0042] Exemplarily, the intermediary 110 includes a first waveguide 111; the semiconductor chip 120 includes a second waveguide 121, the second waveguide 121 being optically connected to the first waveguide 111; and the photonic interconnect chip 130 includes a third waveguide 131, the third waveguide 131 being optically connected to the first waveguide 111. Figure 4 In the process, the first semiconductor chip 120a and the second semiconductor chip 120b are each connected to the photonic interconnect chip 130 through an intermediary 110. The photonic interconnect chip 130 plays an interconnecting role, realizing the optical connection between the first semiconductor chip 120a and the second semiconductor chip 120b.

[0043] For example, such as Figure 4 The first semiconductor chip 120a is optically connected via its second waveguide 121 (121a) to a corresponding first waveguide 111 (111a) in the intermediary 110, which in turn is optically connected to a third waveguide 131 of the photonic interconnect chip 130. The second semiconductor chip 120b is optically connected via its second waveguide 121 (121b) to a corresponding first waveguide 111 (111b) in the intermediary 110, which in turn is optically connected to the third waveguide 131 of the photonic interconnect chip 130. Thus, the first semiconductor chip 120a and the second semiconductor chip 120b have an optically connected path.

[0044] In some implementations, the photonic interconnect chip 130 is manufactured using semiconductor processes, while the intermediate 110 can be manufactured based on a glass substrate or other means, and can be completed separately according to appropriate processes, thereby reducing costs.

[0045] In some embodiments, the semiconductor chip 120 is optically connected to the intermediary 110, which can be achieved using at least one of evanescent wave coupling and grating coupler coupling. For example, the first waveguide 111 in the intermediary 110 is optically connected to the second waveguide 121 in the semiconductor chip 120 via evanescent wave coupling. Alternatively, a grating coupler can be configured at the waveguide end of the first waveguide 111, and a grating coupler can be configured at the waveguide end of the second waveguide 121. The first waveguide 111 and the second waveguide 121 can be aligned using their respective grating couplers to achieve coupling.

[0046] In some embodiments, the photonic interconnect chip 130 is optically connected to the intermediary 110, including optical connection by at least one of the following methods: evanescent wave coupling and grating coupler coupling. For example, the third waveguide 131 in the photonic interconnect chip 130 is optically connected to the first waveguide 111 in the intermediary 110 by evanescent wave coupling and grating coupler coupling.

[0047] Figure 5 It is illustrated schematically. Figure 4 A top view of chip package 100 shows semiconductor chip 120 connected to photonic interconnect chip 130 via first waveguide 111 in intermediary 110. Each semiconductor chip 120 and photonic interconnect chip 130 can be connected via a suitable number of first waveguides 111. Figure 5 Only some of the first waveguides 111 are schematically shown. In some embodiments, Figure 5 Any two semiconductor chips 120 are configured to achieve optical communication; for example, each of the two semiconductor chips 120 is connected to a photonic interconnect chip 130, via a corresponding third waveguide in the photonic interconnect chip 130. Figure 5 (Not shown) to achieve optical connection. Combined Figure 4 as well as Figure 5 By configuring a sufficient number of third waveguides 131, optical connection (optical communication) between any two semiconductor chips 120 can be achieved.

[0048] See Figure 6 In some embodiments, the plurality of third waveguides 131 in the photonic interconnect chip 130 are arranged in at least two layers. Exemplarily, the projections of the third waveguides in different layers onto the surface of the photonic interconnect chip 130 may intersect. The photonic interconnect chip 130 has a smaller area than the interposer 110; arranging the waveguides in layers within the photonic interconnect chip 130 allows it to accommodate more waveguides per unit area. Furthermore, the interposer 110 itself can have a larger area, making it suitable for accommodating more semiconductor chips 120.

[0049] In some embodiments, the plurality of third waveguides in the photonic interconnect chip 130 are arranged in at least two layers, the at least two layers comprising a first layer, a second layer; the plurality of semiconductor chips 120 comprises a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a fourth semiconductor chip; the first semiconductor chip is optically connected to the mediator via the third waveguides in the first layer, thereby connected to the second semiconductor chip through the mediator; and the third semiconductor chip is optically connected to the mediator via the third waveguides in the second layer, thereby connected to the fourth semiconductor chip through the mediator.

[0050] The mediator 110 comprises a semiconductor substrate or a glass substrate, or an organic material substrate. The semiconductor chips 120 and the photonic interconnect chip 130 can be fixed / mounted to the mediator 110 by suitable means, such as using bumps, solder material, organic adhesive, etc.

[0051]

Semiconductor chip

[0052] Exemplarily, the electro-optic conversion unit can comprise a modulator to convert an electrical signal into an optical signal. Exemplarily, the semiconductor chip 120 can be optically coupled with a laser or an optical fiber, so as to input an optical signal to the semiconductor chip 120, or output an optical signal from the semiconductor chip 120. Exemplarily, a waveguide can be used to propagate an optical signal, and serves as a channel for information propagation. Exemplarily, the opto-electric conversion unit can comprise an optical detector for converting an optical signal into an electrical signal, which can comprise, for example, a photodiode. Exemplarily, the semiconductor chip 120 comprises a light source, light generated by the light source can be coupled to a waveguide, and can also be modulated by an electrical signal. The light source can be a laser integrated in the semiconductor chip 120, or a light-emitting diode.

[0053] In some embodiments, the semiconductor chip 120 can comprise two chip or die packages. For example, referring to Figure 7 , the semiconductor chip 120 can be bonded by a first chip 140 and a second chip 150, the first chip 140 comprising a conductive channel 1215 extending from a first surface of the first chip 140 to a second surface opposite to the first surface, wherein the second chip 150 is disposed on the first surface of the first chip 140, and the second surface of the first chip 140 faces the mediator 110 (the mediator 110 can refer to Figure 4). The first chip 140 can include at least one optical coupling structure 1213, which can be optically coupled with an optical fiber, so as to input an optical signal to the first chip 140 or output an optical signal from the first chip 140.

[0054]

Photonic interconnection chip

[0055] In some embodiments, the photonic interconnection chip includes a plurality of the third waveguides, and the plurality of the third waveguides are arranged in at least two layers. Thus, although the photonic interconnection chip 110 has a small area (relative to the interposer 110), it can still provide a sufficient number of waveguides.

[0056]

Interposer

[0057] In some embodiments, the waveguides in the interposer 110 can be polymer waveguides, which can be formed by etching a polymer material layer to form a polymer waveguide.

[0058] In some embodiments, the waveguides in the interposer 110 can be glass waveguides, which can be formed based on a glass substrate, for example, by a method of laser writing, changing the refractive index of a local region in the glass substrate, thereby forming the waveguide.

[0059] In some embodiments, the waveguides in the interposer 110 can be silicon waveguides, silicon nitride waveguides. For example, in the case of forming the waveguides based on a Silicon-On-Insulator (SOI) substrate, which includes a back substrate, an insulating layer, and a top layer of silicon, the waveguides can be formed based on etching the top layer of silicon. For example, the waveguides can be formed by depositing a silicon nitride layer and etching the silicon nitride layer.

[0060] In some embodiments, the interposer 110 includes a conductive wiring layer, which can be used for transmission of electrical signals and can also be used to provide power to various types of chips. For example, the semiconductor chips 120 can be electrically connected to the interposer 110 as needed for functionality.

[0061] In one exemplary embodiment, a method of manufacturing a chip package is provided, which includes: providing an interposer 110; mounting a plurality of semiconductor chips 120 to the interposer 110 such that the plurality of semiconductor chips 120 are optically connected to the interposer 110; and mounting a photonic interconnect chip 130 to the interposer 110 such that the photonic interconnect chip 130 is optically connected to the interposer 110. The chip package 100 in the present embodiment can be manufactured by the above chip package method.

[0062] In some embodiments, the photonic interconnect chip 130 can employ the chip 500 in the present embodiment.

[0063] As Figure 8 For example, in the chip package 100, the first semiconductor chip 120a is optically connected to a corresponding first waveguide 111 (111a) in the interposer 110 through its second waveguide 121 (121a), which is optically connected to a waveguide link 510 of the photonic interconnect chip 130. The second semiconductor chip 120b is optically connected to a corresponding first waveguide 111 (111b) in the interposer 110 through its second waveguide 121 (121b), which is optically connected to a waveguide link 510 of the photonic interconnect chip 130. In this way, the first semiconductor chip 120a and the second semiconductor chip 120b have an optically connected path.

[0064] In Figure 8 the details of the waveguide link 510 are not shown (the details of the waveguide link 510 can be found inFigures 1-2 ). Exemplarily, a first waveguide 111 (111a) of the intermediary 110 is optically connected to an upper layer waveguide in the waveguide link 510, for example, by evanescent wave coupling; a first waveguide 111 (111b) of the intermediary 110 can be optically connected to a lower layer waveguide of the waveguide link 510, for example, by evanescent wave coupling.

[0065] According to an aspect of the present application, a computing device is provided, which comprises the chip 500 in the embodiments of the present application.

[0066] Those skilled in the art should understand that the above disclosure is only an embodiment of the present application, and of course cannot limit the right scope of the patent protection claimed by the present application, and the equivalent changes made according to the embodiments of the present application still fall within the scope of the claims of the present application.

Claims

1. A chip, comprising: Multiple waveguide links, each waveguide link including a lower waveguide, an intermediate waveguide, and an upper waveguide, wherein the intermediate waveguide is coupled to the lower waveguide and the upper waveguide respectively to achieve optical connection between the lower waveguide and the upper waveguide; The lower waveguide includes a first segment, a bend, and a second segment, wherein the bend is configured to connect the first segment and the second segment. The first segment of the lower waveguide and the upper waveguide are respectively coupled to the middle waveguide to achieve the optical connection.

2. The chip as described in claim 1, wherein, The optical mode size of the lower waveguide is smaller than that of the upper waveguide.

3. The chip as described in claim 1, wherein, The chip also includes a substrate, and the plurality of waveguide links include a first waveguide link and a second waveguide link. The upper waveguide of the first waveguide link and the lower waveguide of the second waveguide link have overlapping regions when projected onto the plane where the substrate is located.

4. The chip as described in claim 1, wherein, The intermediate waveguide is made of nitrogen and silicon.

5. The chip as described in claim 1, wherein, The upper waveguide is made of nitrogen and silicon.

6. The chip as claimed in claim 1, wherein, The plurality of waveguide links includes a first waveguide link, the first waveguide link including a photodetector coupled to one of the upper waveguide and the lower waveguide of the first waveguide link.

7. The chip as claimed in claim 1, wherein, The plurality of waveguide links include a first waveguide link, the first waveguide link including a photodetector and an optical modulator, the photodetector being coupled to the lower waveguide of the first waveguide link, and the optical modulator being coupled to the upper waveguide of the first waveguide link.

8. The chip as claimed in claim 1, wherein, The plurality of waveguide links include a first waveguide link, the first waveguide link including a photodetector and an optical modulator, the photodetector being coupled to the upper waveguide of the first waveguide link, and the optical modulator being coupled to the lower waveguide of the first waveguide link.

9. A chip package, comprising: Intermediary; Multiple semiconductor chips are optically connected to the intermediary, wherein the number of the multiple semiconductor chips is at least four; Photonic interconnect chip, optically connected to the intermediary; Each of the plurality of semiconductor chips is configured to be optically connected to the photonic interconnect chip via the intermediary, such that any two of the plurality of semiconductor chips can communicate optical signals. The photonic interconnect chip is a chip as described in any one of claims 1-6.

10. A computing device comprising the chip as described in any one of claims 1-8.

Images