Data error correction method and device of solid state storage device, and storage medium

Abstract

The application provides a data error correction method and device of a solid-state storage device, and a storage medium, comprising: acquiring data read-write characteristics of a plurality of different data partitions in the solid-state storage device; for each data partition, inputting the data read-write characteristics into an LDPC parameter prediction model of the solid-state storage device, and receiving target LDPC parameters output by the LDPC parameter prediction model, wherein the target LDPC parameters make an error correction cost value determined by an error correction cost function in the LDPC parameter prediction model minimum; and using the target LDPC parameters to perform data error correction processing on the corresponding data partition. Embodiments of the application predict the LDPC parameters with the minimum error correction cost value by using the LDPC parameter prediction model based on the data read-write characteristics of the data partitions in the solid-state storage device, so that the LDPC parameters can be dynamically adjusted based on the differences in the data read-write characteristics, thereby improving the data error correction efficiency and reducing the error correction cost.

Description

Technical Field

[0001] This application relates to the field of solid-state storage technology, specifically to a data error correction method and device for solid-state storage devices, and a storage medium. Background Technology

[0002] LDPC (Low-density parity-check) codes are widely used in SSDs (Solid State Disks) due to their low redundancy and high error correction capability, and are used to correct bit errors caused by flash memory fatigue, charge leakage, etc.

[0003] However, LDPC error correction engines typically use fixed LDPC codes, which are difficult to adapt to the different error characteristics of different data blocks and storage areas in SSDs, resulting in low data error correction efficiency. Summary of the Invention

[0004] The embodiments of this application provide a data error correction method, device, and storage medium for solid-state storage devices, aiming to improve the data error correction efficiency of solid-state storage devices.

[0005] In a first aspect, embodiments of this application provide a data error correction method for a solid-state storage device, the data error correction method for the solid-state storage device comprising:

[0006] Obtain the data read / write characteristics of multiple different data partitions in a solid-state storage device;

[0007] For each data partition, the data read / write characteristics are input into the LDPC parameter prediction model of the solid-state storage device, and the target LDPC parameters output by the LDPC parameter prediction model are received. Among multiple LDPC parameters, the error correction cost value determined by substituting the target LDPC parameters into the error correction cost function in the LDPC parameter prediction model is the smallest.

[0008] Using the target LDPC parameters, data error correction is performed on the corresponding data partitions.

[0009] In the above embodiments, based on the data read and write characteristics of data partitions in solid-state storage devices, the LDPC parameter prediction model is used to predict the LDPC parameter with the lowest error correction cost, so that the LDPC parameter can be dynamically adjusted according to different data read and write characteristics, thereby improving data error correction efficiency and reducing error correction cost.

[0010] In one embodiment, the LDPC parameter prediction model is generated through the following steps:

[0011] Obtain the first historical data read / write characteristics for the first historical time period, and the first historical target LDPC parameters corresponding to the first historical data read / write characteristics;

[0012] The first historical data read / write features are input into a preset initial model so that the initial model can output predicted LDPC parameters.

[0013] Substituting the predicted LDPC parameters into the error correction cost function in the LDPC parameter prediction model yields the first error correction cost value, and substituting the first historical target LDPC parameters into the error correction cost function in the LDPC parameter prediction model yields the second error correction cost value.

[0014] Based on the difference between the first error correction value and the second error correction value, the model parameters in the initial model are optimized to obtain the LDPC parameter prediction model.

[0015] In the above embodiments, an error correction cost function that quantifies reliability, performance and efficiency is used as the basis for parameter tuning. The LDPC parameter prediction model is obtained through model training, so that the LDPC parameter prediction model predicts LDPC parameters with the goal of minimizing the error correction cost.

[0016] In one embodiment, the target LDPC parameters include code length, quasi-cyclic code expansion factor, and parity check matrix column weight;

[0017] The error correction cost value determined by the error correction cost function is based on the weighted sum of redundancy overhead, decoding latency, and error correction failure rate.

[0018] The redundancy overhead is determined based on the code length and the quasi-cyclic code expansion factor, the decoding delay is determined based on the code length and the quasi-cyclic code expansion factor, and the error correction failure rate is obtained by fitting the historical error correction failure rate of the first historical period.

[0019] The model parameters in the initial model include: hyperparameters of the gradient boosting decision tree used to output the predicted LDPC parameters, and weights used when weighting the redundancy overhead, the decoding delay, and the error correction failure rate.

[0020] In the above embodiments, by optimizing the hyperparameters of the gradient boosting decision tree, as well as the weights used when weighting the summation of redundancy overhead, decoding latency, and error correction failure rate, the LDPC parameter prediction model aims to predict LDPC parameters with the goal of minimizing the error correction cost.

[0021] In one embodiment, after performing parameter tuning on the model parameters in the initial model, the method further includes:

[0022] Obtain the latest preset number of second historical data read / write features in the solid-state storage device, and the second historical target LDPC parameters corresponding to the second historical data read / write features;

[0023] Using the second historical data read / write characteristics and the second historical target LDPC parameters, the weights used when performing a weighted summation of the redundancy overhead, the decoding latency, and the error correction failure rate are iteratively updated.

[0024] In the above embodiments, by fine-tuning the weights used when weighting and summing redundancy overhead, decoding latency, and error correction failure rate, the LDPC parameter prediction model is dynamically updated, so that the prediction accuracy of the LDPC parameter prediction model is maintained at a high level, and the computational overhead and risk of dynamic updates are reduced.

[0025] In one embodiment, the data error correction method for the solid-state storage device further includes:

[0026] The application scenario type of the solid-state storage device is determined, wherein the application scenario type includes at least one of data center scenario and consumer-grade scenario;

[0027] Based on the application scenario type, a size constraint relationship is determined, wherein the size constraint relationship is used to constrain the size relationship between the weights used when weighted summing of the redundancy overhead, the decoding delay, and the error correction failure rate.

[0028] In the above embodiments, based on the application scenario type of solid-state storage devices, size constraints are determined to constrain the size relationship between the weights used when weighted summing of redundancy overhead, decoding latency, and error correction failure rate. This makes the model learning process no longer a black-box exploration, but a principled and directional "white-box" optimization, thereby improving the application scenario adaptability of the LDPC parameter prediction model.

[0029] In one embodiment, determining the application scenario type of the solid-state storage device includes:

[0030] Obtain the operating intensity, read / write queue depth, read / write ratio, and temperature change curve of the solid-state storage device;

[0031] Based on the workload, the read / write queue depth, the read / write ratio, and the temperature change curve, the application scenario type of the solid-state storage device is determined.

[0032] In the above embodiments, the application scenario type of the solid-state storage device is more accurately determined by comprehensively judging the working intensity, read / write queue depth, read / write ratio, and temperature change curve of the solid-state storage device.

[0033] In one embodiment, the step of performing data error correction processing on the corresponding data partition using the target LDPC parameters includes:

[0034] Obtain the flash memory type of the corresponding data partition;

[0035] Determine the redundancy requirement of the corresponding data partition based on the flash memory type;

[0036] If the redundancy requirement is less than the preset requirement threshold, the parity check matrix matching the target LDPC parameters is subjected to sparse matrix transformation, and the processed parity check matrix is ​​used to perform data error correction on the corresponding data partition.

[0037] If the redundancy requirement is greater than or equal to the requirement threshold, the corresponding data partition is processed for data error correction using the verification matrix matched by the target LDPC parameters.

[0038] In the above embodiments, the redundancy requirement of the data partition is determined, and based on whether the redundancy requirement is less than a preset requirement threshold, it is decided whether to perform sparse matrix transformation on the parity check matrix matching the target LDPC parameters, thereby balancing the computational cost and reliability of data error correction.

[0039] In one embodiment, determining the redundancy requirement of the corresponding data partition based on the flash memory type includes:

[0040] Obtain the preset demand level associated with the flash memory type;

[0041] Determine the current erase / write count, raw bit error rate, data retention time, and operating temperature of the corresponding data partition;

[0042] The current data stability of the corresponding data partition is determined based on the number of erase / write cycles, the original bit error rate, the data retention time, and the operating temperature.

[0043] By utilizing the data stability, the preset demand is adjusted to obtain the redundancy demand of the corresponding data partition.

[0044] In the above embodiments, the redundancy requirement of the corresponding data partition is determined by comprehensively considering the preset requirement associated with the flash memory type, the current number of erase / write cycles of the data partition, the original bit error rate, the data retention time, and the operating temperature, so that the determined redundancy requirement is more in line with the actual needs of the corresponding data partition.

[0045] Secondly, embodiments of this application provide a data error correction device for a solid-state storage device, the data error correction device for the solid-state storage device comprising:

[0046] The acquisition module is used to acquire the data read and write characteristics of multiple different data partitions in a solid-state storage device;

[0047] The prediction module is used to input the data read and write characteristics into the LDPC parameter prediction model of the solid-state storage device for each data partition, and to receive the target LDPC parameters output by the LDPC parameter prediction model. Among multiple LDPC parameters, the error correction cost value determined by substituting the target LDPC parameters into the error correction cost function in the LDPC parameter prediction model is the smallest.

[0048] The processing module is used to perform data error correction processing on the corresponding data partition using the target LDPC parameters.

[0049] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores a computer program configured to be executed by the processor to implement the data error correction method for a solid-state storage device as described in any of the preceding claims.

[0050] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program configured to be executed by a processor to implement the data error correction method for a solid-state storage device as described in any of the preceding claims.

[0051] Fifthly, embodiments of this application provide a computer program product, including a computer program or instructions, which are executed by a processor to implement the data error correction method for a solid-state storage device as described in any of the preceding claims.

[0052] The beneficial effects of the embodiments of this application are as follows:

[0053] In the embodiments of this application, based on the data read and write characteristics of data partitions in a solid-state storage device, the LDPC parameter prediction model is used to predict the LDPC parameter with the lowest error correction cost, so that the LDPC parameter can be dynamically adjusted based on different data read and write characteristics, thereby improving data error correction efficiency and reducing error correction cost. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a schematic flowchart of an embodiment of the data error correction method for a solid-state storage device provided in this application;

[0056] Figure 2 This is a schematic flowchart of another embodiment of the data error correction method for a solid-state storage device provided in the embodiments of this application;

[0057] Figure 3 This is a schematic flowchart of another embodiment of the data error correction method for a solid-state storage device provided in the embodiments of this application;

[0058] Figure 4 This is a schematic flowchart of another embodiment of the data error correction method for a solid-state storage device provided in the embodiments of this application;

[0059] Figure 5 This is a schematic diagram of an embodiment of the data error correction device for a solid-state storage device provided in this application;

[0060] Figure 6 This is a schematic diagram of an embodiment of the electronic device provided in this application. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, in the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0062] In related technologies, the data error correction schemes for solid-state storage devices may have the following problems:

[0063] (1) Low error correction efficiency:

[0064] The error characteristics of different data blocks (such as user data, metadata, and logs) in solid-state storage devices vary significantly: user data (hot data) is accessed frequently and has a low error rate, while metadata (cold data) has not been updated for a long time and has a high cumulative error rate. However, the data error correction schemes in related technologies use uniform parameters (such as a fixed code length of 1024 bits and a code rate of 8 / 9), which results in excessive redundancy for hot data (wasting storage capacity) and insufficient redundancy for cold data (high error correction failure rate).

[0065] (2) Waste of storage costs:

[0066] To cover the worst-case error scenarios for all data blocks (such as the high error rate of some flash memory under the maximum number of erase and write cycles), the data error correction schemes in related technologies need to adopt high redundancy parameters globally (such as code rate 7 / 8), which leads to the overall storage capacity being redundantly occupied, resulting in a reduction in the actual usable capacity of solid-state storage devices and an increase in hardware costs.

[0067] (3) Difficulty in adapting to new storage media:

[0068] Some flash memory technologies increase density through multi-layer stacking (e.g., 200 layers or more), but charge leakage between adjacent layers can cause vertically correlated errors (the bit flipping of cells in the same word line is correlated). Data error correction schemes in related technologies only design check matrices for in-plane (two-dimensional) errors and cannot dynamically enhance vertical check constraints, resulting in a decreased success rate for correcting vertically correlated errors (experiments show that the success rate of data error correction schemes in related technologies for correcting vertically correlated errors is 20%-30% lower than that for in-plane errors).

[0069] In response, this application provides a data error correction method, device, and storage medium for solid-state storage devices to at least partially solve the above-mentioned problems.

[0070] In a first aspect, embodiments of this application provide a data error correction method for a solid-state storage device. Based on the data read and write characteristics of data partitions in the solid-state storage device, the LDPC parameter prediction model is used to predict the LDPC parameter with the lowest error correction cost, so that the LDPC parameter can be dynamically adjusted based on different data read and write characteristics, thereby improving the data error correction efficiency and reducing the error correction cost.

[0071] Specifically, refer to Figure 1 , Figure 1 A schematic flowchart illustrating one embodiment of a data error correction method for solid-state storage devices. Figure 1 The data error correction method for the solid-state storage device may include:

[0072] 101. Obtain the data read / write characteristics of multiple different data partitions in a solid-state storage device.

[0073] In the embodiments of this application, the solid-state storage device is a storage device based on semiconductor flash memory media, such as a solid-state drive (SSD), a universal flash storage (UFS) device, or any device that uses NAND (Not-AND) flash memory as the storage medium.

[0074] Data partitioning refers to the division of storage areas within a solid-state storage device based on logical or physical attributes. These partitions exhibit different characteristics due to their purpose, access patterns, or physical state. Data partitioning is not limited to logical partitions visible to users (such as the C drive and D drive in an operating system), but can be further refined to specific areas managed within the solid-state storage device's controller. For example, data partitioning may include: SLC (Single-Level Cell) mode partitions for caching frequently written data; TLC (Triple-Level Cell) and QLC (Quad-Level Cell) mode partitions for long-term storage of user data; over-provisioning (OP) partitions for wear leveling and garbage collection; and sets of high-wear and low-wear blocks divided according to program / erase cycles. This fine-grained partitioning provides the physical basis for subsequent targeted error correction strategies.

[0075] Data read / write characteristics refer to a set of one or more quantitative metrics that comprehensively describe the overall state of a data partition (such as one or more physical blocks) in terms of physical reliability, intrinsic data properties, and usage patterns. These characteristics are continuously monitored and updated by the firmware within the solid-state storage device controller and are associated with the metadata of each data partition.

[0076] In some embodiments of this application, data read / write characteristics may include error type distribution, bit flip frequency, data entropy value, access frequency, etc.

[0077] Error type distribution refers to the quantified proportion of bit errors occurring in a data partition across different physical causes within a statistical period. Its significance lies in revealing the main loss mechanisms of NAND media, as different types of errors suggest different physical degradation sources. In the embodiments of this application, two basic error types are primarily focused on:

[0078] Random single-bit flips refer to the discrete and irregular distribution of erroneous bits in physical space. This is usually associated with transient and probabilistic events such as random thermal leakage of charge and read noise.

[0079] Burst multi-bit flip: refers to a high concentration of erroneous bits in physical space, such as occurring within several adjacent memory cells. This is often associated with more severe, localized physical damage, such as cell-to-cell interference or wear-out breakdown.

[0080] The specific process of obtaining the error type distribution is completed collaboratively by the ECC (Error Correction Code) engine in the solid-state storage device controller and the firmware. When a read operation is performed, the ECC engine not only corrects errors but also generates a map of the error bit locations. The feature monitoring module in the firmware analyzes this map; the analysis process is as follows:

[0081] Statistical period: A sliding window, such as "last N times (e.g., 100 times)" read operation, is used to ensure the real-time nature of the statistical results.

[0082] Type identification: The monitoring module analyzes the topology of the error bit location map. A proximity threshold is set; for example, if the physical distance between two error bits is less than 3 units, they are grouped into one error cluster. Ultimately, isolated error bits are counted as "random errors," while error clusters with a size greater than 1 are counted as "burst errors."

[0083] Proportion Calculation: Based on the total number of error bits of the two types, calculate the "Random Error Proportion" and the "Burst Error Proportion", for example, {Random Error Proportion: 80%, Burst Error Proportion: 20%}.

[0084] In some embodiments of this application, a "weighted error severity scoring" scheme is proposed to further improve the accuracy of feature representation. This scheme not only counts error types but also assigns them different weights. For example, a random single-bit flip has a weight of 1, while a burst error containing L bits has a weight of 5×L. Thus, the final error type distribution is not a simple proportion but a comprehensive score. This score can more sensitively reflect the occurrence of more destructive burst errors, because burst errors are often a stronger harbinger of impending data partition failure.

[0085] Bit flip frequency measures the rate at which data within a data partition becomes corrupted over time. It reflects the long-term degradation trend of the charge retention capability of storage cells. In the embodiments of this application, it is calculated as "the average number of bit flips in the statistical data partition over the past 30 days." Specifically, the firmware adds a "cumulative number of error-corrected bits" and a "first write timestamp" field to the metadata of each data partition in the Flash Translation Layer (FTL) mapping table. Each time the data partition is read and successfully corrected, the firmware adds the number of corrected bits to this field. The bit flip frequency is then periodically calculated by a background task as: (current cumulative number of error-corrected bits) / (current time - first write timestamp).

[0086] In some embodiments of this application, to make the bit flip frequency more timely and adaptable, a scheme of "adaptive frequency calculation under dynamic observation window" is proposed. This scheme abandons the fixed "30-day" statistical period and instead links the length of the observation window to the "access popularity" of the data.

[0087] For data partitions identified as hot data, the observation window is shortened to 7 days.

[0088] For data partitions identified as warm data, the observation window remains at 30 days.

[0089] For data partitions identified as cold data, the observation window is extended to 90 days to make the calculation of bit flip frequency more intelligent. For frequently changing hot data, a shorter window can quickly capture the latest changes in its health status; while for long-term static cold data, a longer window can smooth out short-term noise and provide a more stable and representative assessment of the long-term degradation rate, thereby making predictions and decisions based on this frequency more accurate.

[0090] Data entropy, derived from information theory, measures the randomness and uncertainty of data content. Its significance lies in the fact that data with higher entropy (such as encrypted or compressed data) has lower internal redundancy and appears more like random noise. This poses a challenge to advanced error correction algorithms based on data correlation, potentially increasing the difficulty of error correction. Data entropy can be calculated using the information entropy algorithm. However, performing a complete Shannon entropy calculation for each data block consumes significant processor resources. Therefore, a low-overhead estimation method is used in the implementation: when data is written to the controller's internal buffer, the firmware samples the data block in segments, for example, extracting only the header 256 bytes, then calculates the byte frequency distribution of this sample, and estimates the entropy of the entire data block accordingly.

[0091] In some embodiments of this application, a scheme for "zero-overhead entropy characterization based on hardware compression ratio" is proposed. This scheme utilizes a hardware transparent compression engine built into the solid-state storage device controller. Data is compressed in real time by this engine before being written to NAND flash memory. There is a strong negative correlation between the data compression ratio and the information entropy value: the lower the data entropy value, the higher its internal patterns and redundancy, and therefore the higher the compression ratio; conversely, random data with high entropy values ​​is almost impossible to compress, and the compression ratio approaches 1. Therefore, the firmware can directly obtain the compression ratio calculated by the hardware compression engine for each data block and use it as an inverse characterization index of the data entropy value, thereby obtaining a very effective measure of data randomness with almost zero additional computational overhead, thus improving the efficiency of obtaining the data entropy value.

[0092] Access popularity measures how frequently a data partition is accessed. Based on the number of accesses in the last 30 days, data access popularity is divided into three levels:

[0093] Hot data: Number of visits > 100 times / day.

[0094] Temperature data: 10 to 100 times / day.

[0095] Cold data: <10 times / day.

[0096] In its implementation, FTL maintains an access counter for each data partition. Each time a read or write request hits that partition, the counter is incremented. A background daemon runs daily, iterating through all access counters, categorizing data partitions by access frequency based on preset thresholds, and then resetting the access counters to begin a new statistical cycle.

[0097] 102. For each data partition, the data read and write characteristics are input into the LDPC parameter prediction model of the solid-state storage device, and the target LDPC parameters output by the LDPC parameter prediction model are received. Among the multiple LDPC parameters, the error correction cost value determined by substituting the target LDPC parameters into the error correction cost function in the LDPC parameter prediction model is the smallest.

[0098] In the embodiments of this application, the LDPC (Low-Density Parity-Check) parameter prediction model is a decision framework whose core function is to select the most suitable "target LDPC parameter" for the current data partition based on the input data read and write characteristics. The LDPC parameter prediction model has a built-in error correction cost function.

[0099] In the embodiments of this application, LDPC parameters may include code length, quasi-cyclic code expansion factor, and parity check matrix column weight. Code length refers to the total number of bits (data bits + parity bits) in an error-correcting code block. A longer code length theoretically results in better error correction performance (law of large numbers effect), but hardware implementation becomes more complex, and decoding latency may be higher. The quasi-cyclic code expansion factor is a key parameter of quasi-cyclic (QC) LDPC codes. It determines the number of times the parity check matrix is ​​"copied" and "shifted" to generate the final large parity check matrix. A larger quasi-cyclic code expansion factor results in a higher code rate and lower redundancy. The parity check matrix column weight refers to the number of "1"s in each column of the parity check matrix. A larger parity check matrix column weight usually provides stronger error correction capabilities, especially against burst errors, but decoding complexity may also increase. It can be seen that these parameters collectively determine the error correction capability, redundancy overhead, and decoding complexity of LDPC codes, i.e., the error correction cost of LDPC codes.

[0100] The target LDPC parameters refer to the set of LDPC parameters that, after evaluation by the LDPC parameter prediction model, are determined to have the minimum error correction cost under the current data read and write characteristics.

[0101] The error correction cost function is a multi-objective evaluation function used to quantify the overall cost (i.e., error correction cost value) of adopting a certain set of LDPC parameters. This function aims to balance the three core dimensions of the error correction scheme: reliability, performance, and efficiency. In some embodiments of this application, the error correction cost function can be constructed as a weighted summation formula: Error correction cost value = w_r × redundancy overhead + w_l × decoding latency + w_f × error correction failure rate, where w_r, w_l, and w_f are adjustable weight coefficients. Redundancy overhead reflects the additional storage space cost added for error correction, and is usually inversely proportional to the code rate; decoding latency reflects the time required to execute the error correction algorithm, affecting read performance; and the error correction failure rate is the probability that the LDPC code cannot successfully correct errors under the current original bit error rate, directly related to data reliability.

[0102] Redundancy overhead is a quantitative metric that measures the cost of a data error correction scheme in terms of storage space efficiency. Redundancy overhead can be determined based on the code length and the quasi-cyclic code expansion factor, for example, by the formula R = (L × K) / L_total. Here, R is the redundancy overhead, L is the code length, K is the quasi-cyclic code expansion factor, and L_total is the total length of the data block, that is, the total length of user data that needs to be protected by ECC within a logical data block.

[0103] Decoding latency is a quantitative metric that measures the impact of a data error correction scheme on read performance. Decoding latency can be determined based on the code length and the quasi-cyclic code spreading factor, for example, by the formula D = L / K × T_cycle. Here, D is the decoding latency, L is the code length, K is the quasi-cyclic code spreading factor, and T_cycle is the clock cycle.

[0104] Error correction failure rate refers to the probability that a data error correction scheme can successfully correct errors and output correct data. The error correction failure rate can be obtained by fitting historical error correction failure rates over a specific historical period. For example, the historical error correction failure rates of solid-state storage devices under different LDPC parameters can be obtained within a certain historical period to fit a curve showing the relationship between LDPC parameters and historical error correction failure rates. By substituting the LDPC parameters currently input to the error correction cost function into the curve, the corresponding historical error correction failure rate can be determined and used as the error correction failure rate in the error correction cost function.

[0105] As can be seen, step 102 essentially involves introducing data read and write features as dynamic input and aiming to minimize the overall error correction cost to output target LDPC parameters, thereby intelligently matching the optimal error correction strategy.

[0106] 103. Use the target LDPC parameters to perform data error correction on the corresponding data partitions.

[0107] In the embodiments of this application, in the step of performing data error correction processing using target LDPC parameters, a parameter configuration instruction corresponding to the target LDPC parameters can be generated using a microcode engine and sent to the register of the LDPC error correction unit via a dedicated control bus (such as a Serial Peripheral Interface (SPI)) for data error correction processing of the corresponding data partition.

[0108] As can be seen, in the above embodiments of this application, a dynamic adaptive data error correction scheme is proposed. By generating data read and write characteristics for each data partition in the solid-state storage device, and by using an LDPC parameter prediction model that aims to minimize the error correction cost, the optimal error correction scheme is tailored for each data partition, so as to improve the overall operating efficiency, reliability and economy of the solid-state storage device.

[0109] In some embodiments of this application, reference is made to Figure 2 ,exist Figure 1 Based on the illustrated embodiment, the LDPC parameter prediction model can be generated through the following steps:

[0110] 201. Obtain the first historical data read / write characteristics of the first historical period, and the first historical target LDPC parameters corresponding to the first historical data read / write characteristics.

[0111] In the embodiments of this application, the first historical period refers to a specific time window or a series of test phases used to collect training data. For example, the first historical period may be the complete lifecycle of a solid-state storage device in a laboratory environment, through accelerated aging tests and simulations of various typical user workloads (such as database applications, video streaming, operating system startup, etc.), to ensure that the collected data can cover all states from brand new flash memory to end-of-life flash memory.

[0112] The first historical data read / write features are at least a portion of the training dataset for the LDPC parameter prediction model. The first historical target LDPC parameter is the label of the training dataset. The first historical target LDPC parameter can be set based on human experience and is considered to be the choice with the lowest error correction cost under the given conditions.

[0113] 202. Input the first historical data read and write features into the preset initial model so that the initial model can output the predicted LDPC parameters.

[0114] In the embodiments of this application, the initial model is the initial form of the LDPC parameter prediction model before training begins. It contains a series of adjustable model parameters, which are typically randomly initialized or set to preset values ​​in the initial state. The initial model performs forward propagation calculations on the first historical data read / write features input, thereby outputting the predicted LDPC parameters.

[0115] In some embodiments of this application, the initial model may employ a Gradient Boosting Decision Tree (GBDT). This is a powerful ensemble learning model that effectively handles tabular data with complex nonlinear relationships by iteratively training a series of weak learners (decision trees) and weighting and combining their results. The model parameters requiring parameter tuning in the initial model may include the hyperparameters of the GBDT and the weights used in the error correction cost function when weighting and summing redundant overhead, decoding latency, and error correction failure rate.

[0116] The hyperparameters of GBDT define the structure and learning process of the GBDT model, for example:

[0117] Number of trees: The total number of decision trees included in the ensemble.

[0118] Learning rate: A factor that reduces the contribution of each tree to the final result, used to prevent overfitting.

[0119] Maximum tree depth: The maximum number of layers in a single decision tree, controlling the complexity of the model. In parameter tuning, techniques such as grid search or Bayesian optimization are typically used to find the optimal combination in a predefined hyperparameter space, so that the overall predictive performance of the model (with the goal of minimizing the error correction cost) is optimal.

[0120] The weights used in the error correction cost function when weighted summing of redundancy overhead, decoding latency, and error correction failure rate are not fixed hyperparameters, but are considered part of the LDPC parameter prediction model and are learned and optimized together. In some embodiments of this application, a parallel, small neural network can be constructed, whose input is also data read / write features, and whose output is the weights used when weighted summing of redundancy overhead, decoding latency, and error correction failure rate. This neural network is jointly trained with GBDT to calibrate the weights used when weighted summing of redundancy overhead, decoding latency, and error correction failure rate through parameter tuning.

[0121] 203. Substitute the predicted LDPC parameters into the error correction cost function in the LDPC parameter prediction model to obtain the first error correction cost value, and substitute the first historical target LDPC parameters into the error correction cost function in the LDPC parameter prediction model to obtain the second error correction cost value.

[0122] In the embodiments of this application, the first error correction cost value and the second error correction cost value can be calculated using the error correction cost function:

[0123] First error correction cost: The cost calculated by substituting the predicted LDPC parameters into the error correction cost function. This value reflects the theoretical cost of the model's current decision.

[0124] The second error correction cost is the cost calculated by substituting the LDPC parameters of the first historical objective into the error correction cost function. This value reflects the expected theoretical cost of the model's current decision.

[0125] 204. Based on the difference between the first and second error correction values, the model parameters in the initial model are optimized to obtain the LDPC parameter prediction model.

[0126] In the embodiments of this application, parameter tuning specifically refers to using gradient-based optimization algorithms, such as the Adaptive Moment Estimation optimizer, to update the model parameters in the initial model through backpropagation. The loss function used in parameter tuning is the difference between the first error correction cost and the second error correction cost, or the absolute value of the difference between the first error correction cost and the second error correction cost.

[0127] By iteratively executing steps 202, 203, and 204 on the entire training dataset, the model parameters will converge toward an LDPC parameter that can output an LDPC parameter with an extremely low error correction cost for any input feature, thus obtaining the LDPC parameter prediction model.

[0128] As can be seen, in the above embodiments of this application, an error correction cost function that quantifies reliability, performance and efficiency is used as the basis for parameter tuning. The LDPC parameter prediction model is obtained through model training, so that the LDPC parameter prediction model predicts LDPC parameters with the goal of minimizing the error correction cost value.

[0129] In some embodiments of this application, after parameter tuning of the model parameters in the initial model, the method may further include: obtaining the latest preset number of second historical data read / write features in the solid-state storage device, and the second historical target LDPC parameters corresponding to the second historical data read / write features; and using the second historical data read / write features and the second historical target LDPC parameters, iteratively updating the weights used when performing weighted summation on redundancy overhead, decoding latency, and error correction failure rate.

[0130] The latest preset quantity indicates that the second historical data read / write feature is not static data, but data maintained within the firmware of the solid-state storage device and continuously updated over time. In some embodiments of this application, a circular buffer is provided in the solid-state storage device. Taking a preset quantity of 1000 as an example, the circular buffer can store the latest 1000 second historical data read / write features in the solid-state storage device, as well as the second historical target LDPC parameters corresponding to the second historical data read / write features.

[0131] As solid-state storage devices age (e.g., increased write cycles leading to higher error correction failure rates) or load changes (e.g., switching from random to sequential writes), the accuracy of the target LDPC parameters output by the LDPC parameter prediction model decreases. Therefore, by utilizing second historical data read / write characteristics and second historical target LDPC parameters, the weights used in the weighted summation of redundancy overhead, decoding latency, and error correction failure rate can be iteratively updated. This fine-tuning of the weights used in the weighted summation of redundancy overhead, decoding latency, and error correction failure rate allows for dynamic updates of the LDPC parameter prediction model, maintaining high prediction accuracy while reducing the computational overhead and risk of dynamic updates.

[0132] In some embodiments of this application, reference is made to Figure 3 ,exist Figure 1 or Figure 2 Based on the illustrated embodiment, the data error correction method for solid-state storage devices may further include:

[0133] 301. Determine the application scenario type of the solid-state storage device, wherein the application scenario type includes at least one of the following: data center scenario and consumer-grade scenario.

[0134] In the embodiments of this application, the application scenario type is a macro-level classification of the expected operating environment and load characteristics of solid-state storage devices. The application scenario types include at least:

[0135] Data center scenario: Equipment in this scenario is typically used in enterprise-level servers, cloud storage, and other similar environments. The core requirements are extreme data integrity and reliability, as well as stable and predictable service quality. Tolerance for occasional, short-term performance fluctuations is low.

[0136] Consumer-grade scenarios: Devices in this scenario are mostly personal computers, game consoles, etc. Users are more concerned with the intuitive experience brought by sudden read and write speeds and are more sensitive to cost. Although data reliability is also required, it is usually a lower priority than extreme response speed.

[0137] In some embodiments of this application, the methods for determining the application scenario type can be divided into static configuration and dynamic identification:

[0138] Static configuration: Before a solid-state storage device leaves the factory, the application scenario type is permanently written as an identifier into a non-volatile storage area of ​​the device, such as the firmware information area, based on its product model and target market. The solid-state storage device's controller reads this identifier during initialization to determine the application scenario type.

[0139] Dynamic Identification: After deployment, the application scenario type is dynamically identified at runtime through the load analysis module within the firmware. This load analysis module continuously monitors key read / write metrics over a period of time (e.g., the most recent hour), such as read / write ratio, random / sequential access ratio, average queue depth, and read / write size distribution. By matching these metrics with preset scenario feature templates, it autonomously determines whether the current scenario is closer to a data center scenario (e.g., high queue depth, continuous small-block random writes) or a consumer-grade scenario (e.g., sudden large-block sequential reads, long periods of idle time), thereby determining the application scenario type of the solid-state storage device. This approach gives solid-state storage devices greater environmental adaptability; for example, some users may repurpose solid-state storage devices intended for the data center market for consumer-grade scenarios.

[0140] 302. Based on the application scenario type, determine the size constraint relationship, whereby the size constraint relationship is used to constrain the size relationship between the weights used when weighted summing of redundancy overhead, decoding latency, and error correction failure rate.

[0141] In the embodiments of this application, the size constraint is used to constrain the relationship between the weights used when performing a weighted summation of redundancy overhead, decoding latency, and error correction failure rate. That is, during parameter tuning during model training and iterative updates of the weights, the relationship between the weights used when performing a weighted summation of redundancy overhead, decoding latency, and error correction failure rate must satisfy this size constraint. In this way, the size constraint can guide the learning direction of model training and weight iterative updates to adapt to the different needs of users in different application scenarios.

[0142] Taking a data center scenario as an example, data reliability is a high priority. Therefore, the weight w_f of the error correction failure rate should be dominant, much larger than the weight w_l of decoding latency and the weight w_r of redundancy overhead. The size constraint can be set as: w_f ≥ α × w_l and w_f ≥ β × w_r, where α and β are constants greater than 1, for example, α = 10 and β = 10. This ensures that regardless of the data read / write characteristics, the LDPC parameter prediction model will strive to avoid decisions that could lead to data loss when calculating the error correction cost.

[0143] Taking a consumer-grade application scenario as an example, user experience (i.e., response speed) is crucial. Therefore, the decoding latency weight w_l should have a high priority. Simultaneously, redundancy overhead w_r is directly related to cost and needs attention. The size constraint can be set as: w_l > w_f and w_l > w_r. This size constraint, while ensuring basic reliability, allows the LDPC parameter prediction model to prioritize target LDPC parameters that result in lower latency.

[0144] As can be seen from the above embodiments of this application, based on the application scenario type of solid-state storage devices, the size constraint relationship is determined to constrain the size relationship between the weights used when weighted summing of redundancy overhead, decoding latency, and error correction failure rate. This makes the model learning process no longer a black-box exploration, but a principled and directional "white-box" optimization, thereby improving the application scenario adaptability of the LDPC parameter prediction model.

[0145] In some embodiments of this application, the dynamic identification process of application scenario types is described in detail. Specifically, determining the application scenario type of a solid-state storage device may include: acquiring the workload, read / write queue depth, read / write ratio, and temperature change curve of the solid-state storage device; and determining the application scenario type of the solid-state storage device based on the workload, read / write queue depth, read / write ratio, and temperature change curve.

[0146] Workload refers to the load pressure on a solid-state storage device per unit of time. In some embodiments of this application, workload can be characterized by both input / output operations per second (IOPS) and data throughput (MB / s). High and sustained workload is often a hallmark of data center scenarios.

[0147] Read / write queue depth reflects the level of concurrent requests on the host system, indicating the number of read / write commands waiting for the solid-state storage device to process at any given time. In data center scenarios, due to concurrent access by multiple users and threads, a high and stable read / write queue depth is typically maintained. However, in consumer-grade scenarios, queue depth is usually lower and fluctuates drastically.

[0148] The read-write ratio refers to the ratio of the amount of data read to the amount of data written over a period of time, or the ratio of the number of read commands to the number of write commands. Typical write-intensive applications (such as database logging) are characteristic of data center scenarios, while read-intensive applications (such as game loading and media playback) are more common in consumer scenarios.

[0149] Temperature change curves are time-series data that reflect the thermal behavior characteristics of solid-state storage devices over a period of time. For example, temperature change curves can be obtained by periodically (e.g., every minute) reading data from temperature sensors built into NAND flash memory chips and recording these readings to form a time series.

[0150] In some embodiments of this application, a lightweight machine learning classifier-based approach can be used to determine the application scenario type of the solid-state storage device based on workload, read / write queue depth, read / write ratio, and temperature change curve. Specifically, this may include the following steps:

[0151] Model selection: Choose a classifier model with minimal computational and storage overhead to ensure efficient operation on resource-constrained solid-state storage device controllers. Examples include a pre-trained decision tree or support vector machine (SVM).

[0152] Feature vector construction: Combine the above-obtained metrics (e.g., workload, read / write queue depth, read / write ratio, and temperature change curve in the past hour) into a feature vector.

[0153] Offline training and deployment: During product development, a large amount of operational data and corresponding application scenario type labels from real data center and consumer environments can be collected. This data is then used to train the classifier model. After training, the classifier model parameters are stored in the firmware of a solid-state storage device.

[0154] Online classification: When a solid-state storage device is running, the load analysis module in the firmware periodically constructs the current feature vector and inputs it into a fixed classifier model. The output of the classifier model is the most likely application scenario type. For example, an output of "0" represents a consumer-grade scenario, and an output of "1" represents a data center scenario.

[0155] In some embodiments of this application, in the step of determining the application scenario type of a solid-state storage device based on workload, read / write queue depth, read / write ratio, and temperature change curve, more information (such as temperature mean and variance, temperature change rate, power cycle frequency, etc.) can be introduced to determine a more accurate application scenario type.

[0156] Temperature mean and variance: In data center scenarios, solid-state storage devices typically operate 24 / 7 in temperature-controlled server rooms, resulting in a stable, relatively high temperature with low variance. In consumer-grade scenarios, solid-state storage devices experience frequent power-on / off cycles and hibernation / wake-up, leading to a lower temperature mean but a much higher variance.

[0157] The rate of temperature change is determined by calculating the first derivative of the temperature change curve. In consumer-grade scenarios, solid-state storage devices experience a dramatic temperature rise when powered on or loading large applications, forming a steep temperature gradient, while shutdown or idleness leads to rapid cooling. In data center scenarios, the temperature change of solid-state storage devices is much gentler.

[0158] Power cycle frequency can be determined by identifying large, periodic "cooling-heating" patterns in the temperature profile and counting the number of power cycles in a solid-state storage device. A higher power cycle frequency is characteristic of consumer-grade applications.

[0159] As can be seen, the mean and variance of temperature, the rate of temperature change, and the power cycling frequency can all be determined based on the temperature change curve. Furthermore, by combining the mean and variance of temperature, the rate of temperature change, and the power cycling frequency, the application scenario type of solid-state storage devices can be identified more accurately, thereby making the predictions of the LDPC parameter prediction model more accurate.

[0160] In some embodiments of this application, reference is made to Figure 4 ,exist Figures 1 to 3 Based on any of the embodiments shown, data error correction processing of the corresponding data partitions using the target LDPC parameters may include:

[0161] 401. Obtain the flash memory type of the corresponding data partition.

[0162] In the embodiments of this application, flash memory type refers to the technical specifications of the basic unit constituting the physical storage medium of a solid-state storage device, primarily defined by the number of data bits that each physical storage cell can store. Flash memory types may include, for example:

[0163] Single-Level Cell (SLC): Each cell stores 1 bit of data, offering the highest reliability, longest erase / write life, and fastest read / write speed.

[0164] Multi-Level Cell (MLC): Each cell stores 2 bits of data.

[0165] Triple-Level Cell (TLC): Each cell stores 3 bits of data.

[0166] Quad-Level Cell (QLC): Each cell stores 4 bits of data, offering the highest storage density, but with relatively the lowest reliability, lifespan, and performance.

[0167] In some embodiments of this application, the solid-state storage device may employ a hybrid storage architecture, with a portion of the physical space configured as a high-performance SLC cache, while the majority of the space consists of TLC or QLC. The flash translation layer (FTL) inside the solid-state storage device maintains a mapping table from logical addresses to physical addresses. This mapping table not only records the physical page address but also includes the type attribute of the physical block (e.g., marked as SLC or TLC mode). Therefore, when a read request for a specific data partition is received, the type of flash memory on which the data partition is currently stored can be determined by querying the FTL.

[0168] 402. Determine the redundancy requirement of the corresponding data partition based on the flash memory type.

[0169] In the embodiments of this application, redundancy requirement is a quantified scale value, ranging from, for example, 0 to 100. This scale value comprehensively characterizes the strength of error correction capability required by a data partition to resist data errors at the current moment. A higher redundancy requirement means that the partition is highly susceptible to bit flips and requires a lower code rate and stronger error correction capability ECC (Error Correction Code) scheme; conversely, a lower redundancy requirement indicates that the partition is in good condition and a higher code rate and lower overhead ECC scheme can be selected to improve performance and storage efficiency.

[0170] In some embodiments of this application, since the data stored in data partitions of different flash memory types are usually inconsistent, for example, SLC type data partitions are usually used to store hot data, while QLC type data partitions are usually used to store cold data, a corresponding preset demand degree can be pre-associated for different flash memory types, so that the corresponding preset demand degree is used as the redundancy demand degree of the corresponding data partition to match the different requirements of different data partitions for error correction cost.

[0171] In some embodiments of this application, step 402 may include: obtaining a preset demand level associated with the flash memory type; determining the current erase / write count, raw bit error rate, data retention time, and operating temperature of the corresponding data partition; determining the current data stability of the corresponding data partition based on the erase / write count, raw bit error rate, data retention time, and operating temperature; and using the data stability to correct the preset demand level to obtain the redundancy demand level of the corresponding data partition.

[0172] Write / erase cycles: This refers to the total number of programming and erasing operations that a data partition has undergone since it left the factory. This is the most direct indicator of the cumulative wear and tear on a flash memory cell.

[0173] Raw bit error rate (RBER): This refers to the probability of bit errors occurring when data is read directly from a flash memory cell without any ECC error correction. This value is calculated in real time by the number of raw error bits reported by the ECC decoder during the read operation.

[0174] Data retention time: This refers to the time elapsed since the last successful write of data to the data partition. Because electrical charge naturally leaks over time, this parameter reflects the cumulative risk of data retention errors.

[0175] Operating temperature: This refers to the current operating temperature of the NAND chip as measured by the internal temperature sensor of the solid-state storage device. High temperatures significantly accelerate charge leakage and exacerbate various noise effects, making them a key environmental factor affecting data reliability.

[0176] It can be seen that the number of erase / write cycles, the original bit error rate, the data retention time, and the operating temperature together depict the real-time health status of the data partition.

[0177] Data stability is a comprehensive health score, with a value range of 0 to 100. This score integrates erase / write cycles, raw bit error rate, data retention time, and operating temperature into a single, comprehensive indicator reflecting the current level of data reliability using a multivariate function. Higher data stability indicates less susceptibility to errors; conversely, lower stability indicates a high-risk data state. Its calculation formula can be a weighted linear model:

[0178] Data stability = 100 - (W_pe × F_pe + W_rber × F_rber + W_ret × F_ret + W_temp × F_temp)

[0179] Where F_pe, F_rber, F_ret, and F_temp are the number of erase / write cycles, the original bit error rate, the data retention time, and the operating temperature, respectively. W_pe, W_rber, W_ret, and W_temp are the weighting coefficients for each item, which can be obtained based on previous tests.

[0180] In the step of adjusting the preset demand level using data stability, the redundancy demand level of the corresponding data partition can be calculated using the following formula:

[0181] Redundancy requirement = Preset requirement × (1 + (50 - data stability) / 50)

[0182] It can be seen that when the data stability is ideal (100), the correction factor in parentheses is less than 1, which reduces the redundancy requirement. When the data stability is extremely poor (0), the correction factor is greater than 1, which increases the redundancy requirement. When the data stability is moderate (50), the correction factor is 1, and the redundancy requirement is equal to the preset requirement, thus making the calculated redundancy requirement more in line with the actual needs.

[0183] In some embodiments of this application, read interference errors and write interference errors may also be introduced in the step of determining data stability.

[0184] Read interference errors refer to bit errors caused by frequent read operations on the word line containing a particular memory cell, resulting in unexpected changes in the charge state of adjacent, unselected memory cells. A significant characteristic of this type of error is that the erroneous bits often exhibit high locality or clustering in physical space, concentrating around the frequently read "victim cell".

[0185] Write interference errors refer to bit errors caused by the strong electric field generated during programming (writing data) of a target memory cell, which unexpectedly disturbs the charge state of adjacent memory cells. Similar to read interference errors, its error mode also exhibits physically localized clustering characteristics.

[0186] Specifically, when the solid-state storage device controller performs a read operation, its built-in ECC (Error Correction Code) engine is not only responsible for correcting bit errors, but also for generating an accurate "error bit map". A "spatial error correlation analysis module" within the firmware processes the error bit map in real time to extract information about the intensity of interference errors.

[0187] The specific implementation of this spatial error correlation analysis module includes:

[0188] Error topology analysis: The spatial error correlation analysis module traverses the error bit location map and uses a proximity criterion (e.g., physical distance within 3 memory cells) to identify the spatial relationships between error bits. If multiple error bits satisfy this criterion, they are grouped into an "error cluster".

[0189] Interference Intensity Index Calculation: Based on the statistical information of error clusters, a comprehensive "interference intensity index" is calculated. The formula for this index is as follows:

[0190] Interference intensity index = (W_cluster_size × Σ (cluster size)) 2 () + W_cluster_count × total number of clusters) / total number of error bits

[0191] Here, "cluster size" refers to the number of erroneous bits contained within a single erroneous cluster. "W_cluster_size" and "W_cluster_count" are weighting coefficients used to adjust the penalty for large and frequently occurring clusters. A higher value indicates a more severe clustering error caused by localized interference.

[0192] Subsequently, this "interference intensity index" was treated as a new independent variable and integrated into the data stability calculation formula. The revised data stability calculation model is as follows:

[0193] Data stability = 100 - (W_pe × F_pe + W_rber × F_rber + W_ret × F_ret + W_temp × F_temp + W_disturb × F_disturb)

[0194] Where F_disturb is the interference intensity index. W_disturb is the weighting coefficient of the interference intensity index, which can be obtained based on previous tests.

[0195] It can be seen that by introducing the interference intensity index, a more accurate data stability can be determined, thus making the data stability more consistent with the actual situation of the corresponding data partition.

[0196] 403. If the redundancy requirement is less than the preset requirement threshold, perform sparse matrix transformation on the check matrix matching the target LDPC parameters, and use the processed check matrix to perform data error correction on the corresponding data partition.

[0197] In the embodiments of this application, the demand threshold is a key decision boundary used to distinguish between the data partition containing "high-reliability data" and the data partition containing "standard / low-reliability data." The demand threshold can be set to, for example, 2. The sparse matrix algorithm, which uses a sparse matrix as its core data structure, reduces storage requirements and computational complexity by storing and processing only non-zero elements, requiring a compressed storage structure. This algorithm is an irregular algorithm, characterized by a low computation-to-memory ratio and memory access trajectory dependence on the sparse structure. Different sparse structure characteristics require corresponding storage schemes and parallel algorithms. Therefore, by performing sparse matrix transformation processing, the number of non-zero elements in the parity matrix can be reduced, lowering computational complexity.

[0198] In some embodiments of this application, if the redundancy requirement is greater than or equal to the requirement threshold, the corresponding data partition is corrected using the check matrix matched by the target LDPC parameters. That is, the check matrix matched by the target LDPC parameters is not subjected to sparse matrix transformation to ensure that the data correction has high reliability.

[0199] As can be seen, in the above embodiments of this application, the redundancy requirement of the data partition is determined, and based on whether the redundancy requirement is less than the preset requirement threshold, it is decided whether to perform sparse matrix transformation on the parity check matrix matching the target LDPC parameters, thereby taking into account both the computational cost and reliability of data error correction.

[0200] Secondly, referring to Figure 5 Based on the data error correction method for solid-state storage devices described in the above embodiments, this application provides a data error correction device 500 for solid-state storage devices. The data error correction device 500 is used to execute the steps in any embodiment of the data error correction method for solid-state storage devices described above. For example, the data error correction device 500 may include:

[0201] The acquisition module 501 is used to acquire the data read and write characteristics of multiple different data partitions in a solid-state storage device;

[0202] The prediction module 502 is used to input the data read and write characteristics into the LDPC parameter prediction model of the solid-state storage device for each data partition, and to receive the target LDPC parameters output by the LDPC parameter prediction model. Among the multiple LDPC parameters, the error correction cost value determined by substituting the target LDPC parameters into the error correction cost function in the LDPC parameter prediction model is the smallest.

[0203] The processing module 503 is used to perform data error correction processing on the corresponding data partition using the target LDPC parameters.

[0204] Thirdly, embodiments of this application provide an electronic device that integrates a data error correction apparatus for any of the solid-state storage devices provided in the embodiments of this application. The electronic device includes a processor and a memory, the memory storing a computer program configured to be executed by the processor to implement the data error correction method for the solid-state storage device as described in any of the above embodiments.

[0205] Fourthly, embodiments of this application provide an electronic device that integrates a data error correction device for any of the solid-state storage devices provided in embodiments of this application. For example... Figure 6 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically:

[0206] The electronic device may include components such as a processor 601 with one or more processing cores, a memory 602 with one or more computer-readable storage media, a power supply 603, and an input unit 604. Those skilled in the art will understand that... Figure 6 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein:

[0207] The processor 601 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 602, and by calling data stored in the memory 602, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 601 may include one or more processing cores; preferably, the processor 601 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 601.

[0208] The memory 602 can be used to store software programs and modules. The processor 601 executes various functional applications and data processing by running the software programs and modules stored in the memory 602. The memory 602 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 602 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 602 may also include a memory controller to provide the processor 601 with access to the memory 602.

[0209] The electronic device also includes a power supply 603 that supplies power to the various components. Preferably, the power supply 603 can be logically connected to the processor 601 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. The power supply 603 may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components.

[0210] The electronic device may also include an input unit 604, which can be used to receive input digital or character information and generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function control.

[0211] Although not shown, the electronic device may also include a display unit, etc., which will not be described in detail here. Specifically, in the embodiments of this application, the processor 601 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 602 according to the following instructions, and the processor 601 runs the application programs stored in the memory 602 to realize various functions, such as the functions in the data error correction method of the solid-state storage device as described in any of the preceding claims.

[0212] Fifthly, embodiments of this application provide a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk, etc. The computer-readable storage medium stores a computer program configured to be executed by a processor to implement the data error correction method for a solid-state storage device as described in any of the preceding claims.

[0213] Sixthly, embodiments of this application provide a computer program product, including a computer program or instructions, which are executed by a processor to implement the data error correction method for a solid-state storage device as described in any of the preceding claims.

[0214] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method of data error correction for a solid state storage device, the method comprising: The data error correction method of the solid-state storage device comprises: obtaining data read-write characteristics of a plurality of different data partitions in the solid-state storage device; for each data partition, inputting the data read-write characteristics into an LDPC parameter prediction model of the solid-state storage device, and receiving a target LDPC parameter output by the LDPC parameter prediction model, wherein among a plurality of LDPC parameters, the target LDPC parameter has a minimum error correction cost value determined by an error correction cost function in the LDPC parameter prediction model; using the target LDPC parameter to perform data error correction processing on the corresponding data partition; the LDPC parameter prediction model is generated by the following steps: obtaining first historical data read-write characteristics of a first historical period, and first historical target LDPC parameters corresponding to the first historical data read-write characteristics; inputting the first historical data read-write characteristics into a preset initial model to output predicted LDPC parameters by the initial model; substituting the predicted LDPC parameters into an error correction cost function in the LDPC parameter prediction model to obtain a first error correction cost value, and substituting the first historical target LDPC parameters into the error correction cost function in the LDPC parameter prediction model to obtain a second error correction cost value; according to the difference between the first error correction cost value and the second error correction cost value, performing parameter optimization processing on the model parameters in the initial model, thereby obtaining the LDPC parameter prediction model; the target LDPC parameter includes code length, quasi-cyclic code expansion factor, and check matrix array weight; the error correction cost value determined by the error correction cost function is determined based on the weighted sum result among redundancy overhead, decoding delay, and error correction failure rate; wherein the redundancy overhead is determined based on the code length and the quasi-cyclic code expansion factor, the decoding delay is determined based on the code length and the quasi-cyclic code expansion factor, and the error correction failure rate is fitted based on the historical error correction failure rate of the first historical period; the model parameters in the initial model include: hyperparameters of gradient boosting decision trees for outputting the predicted LDPC parameters, and weights used when performing weighted sum on the redundancy overhead, the decoding delay, and the error correction failure rate.

2. The data error correction method of a solid state storage device according to claim 1, wherein, After the parameter optimization processing on the model parameters in the initial model, further comprising: obtaining the latest preset number of second historical data read-write characteristics in the solid-state storage device, and second historical target LDPC parameters corresponding to the second historical data read-write characteristics; using the second historical data read-write characteristics and the second historical target LDPC parameters to iteratively update the weights used when performing weighted sum on the redundancy overhead, the decoding delay, and the error correction failure rate.

3. The data error correction method of a solid state storage device according to claim 1, wherein, The data error correction method of the solid-state storage device further comprises: determining the application scenario type of the solid-state storage device, wherein the application scenario type comprises at least one of a data center scenario and a consumer-level scenario; Determine a size constraint relationship based on the application scenario type, wherein the size constraint relationship is used to constrain a size relationship between weights used when performing weighted summation on the redundancy overhead, the decoding delay, and the error correction failure rate.

4. The data error correction method of a solid state storage device according to claim 3, wherein, The determining of the application scenario type of the solid state storage device comprises: Obtaining a working intensity, a read-write queue depth, a read-write ratio, and a temperature change curve of the solid state storage device; Determining the application scenario type of the solid state storage device based on the working intensity, the read-write queue depth, the read-write ratio, and the temperature change curve.

5. The data error correction method of a solid state storage device according to claim 1, wherein, The data error correction processing of the corresponding data partition using the target LDPC parameter comprises: Obtaining a flash memory type of the corresponding data partition; Determining a redundancy requirement degree of the corresponding data partition according to the flash memory type; If the redundancy requirement degree is less than a preset requirement degree threshold, performing sparse matrix conversion processing on a check matrix matched with the target LDPC parameter, and performing data error correction processing on the corresponding data partition using the processed check matrix; If the redundancy requirement degree is greater than or equal to the requirement degree threshold, performing data error correction processing on the corresponding data partition using the check matrix matched with the target LDPC parameter.

6. The data error correction method of a solid state storage device according to claim 5, wherein, The determining of the redundancy requirement degree of the corresponding data partition according to the flash memory type comprises: Obtaining a preset requirement degree associated with the flash memory type; Determining a current erase-write number, an original bit error rate, a data retention time, and a working temperature of the corresponding data partition; Determining a current data stability degree of the corresponding data partition according to the erase-write number, the original bit error rate, the data retention time, and the working temperature; Correcting the preset requirement degree using the data stability degree to obtain the redundancy requirement degree of the corresponding data partition.

7. An electronic device, comprising: The electronic device comprises a processor and a memory, and the memory stores a computer program configured to be executed by the processor to implement the data error correction method of the solid state storage device according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program configured to be executed by a processor to implement the data error correction method of the solid state storage device according to any one of claims 1 to 6.

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