Light emitting diode and light emitting device

Abstract

The invention provides a light-emitting diode and a light-emitting device.The light-emitting diode at least comprises a semiconductor laminated layer, a first insulating layer and an electrode structure, the electrode structure comprises a first electrode and a second electrode, and a groove exposing the upper surface of the first insulating layer is formed between the first electrode and the second electrode; the second insulating layer is partially arranged in the groove and extends towards the two ends so as to cover the upper surfaces of a part of the first electrode and a part of the second electrode respectively. According to the technical scheme, physical isolation is formed by arranging the second insulating layer, a welding flux bridging short circuit path is blocked, the risk of direct contact of welding flux is reduced, and the problem of short circuit caused by direct contact of metal electrodes in the current welding process of a small-size Micro-LED is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode and a light-emitting device. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device whose basic structure includes a PN junction between P-type and N-type semiconductors. When a forward voltage is applied to the LED, electrons and holes recombine at the junction of the PN junction, releasing energy. This energy is emitted in the form of photons, forming light radiation.

[0003] Micro-LED display technology, with its advantages of ultra-high resolution, high brightness, and low power consumption, has become an important development direction in the field of new displays. Compared with the conventional structure, flip-chip displays are widely used in the Micro-LED field due to their ability to handle high current density and high light extraction efficiency. However, as the size of Micro-LED chips decreases, the electrode spacing between the n-type semiconductor side and the p-type semiconductor side becomes smaller and smaller, which significantly increases the risk of solder overflow during the chip-to-circuit bonding process, leading to the risk of chip short circuits and failures.

[0004] Therefore, in the chip design and manufacturing process, there is an urgent need to provide an improved technical solution that addresses the shortcomings of the existing technologies. Summary of the Invention

[0005] In view of the defects and shortcomings of the existing LED chips, this application provides a light-emitting diode and a light-emitting device to achieve good physical insulation between electrodes and improve chip yield.

[0006] To achieve the above and other related objectives, in a first aspect, this application provides a light-emitting diode, comprising at least:

[0007] A semiconductor stack, wherein the semiconductor stack comprises, in sequence, a first semiconductor layer, an active layer, and a second semiconductor layer;

[0008] A first insulating layer is at least partially disposed above the semiconductor stack and has a first opening exposing the first semiconductor layer and a second opening exposing the second semiconductor layer;

[0009] The electrode structure includes a first electrode and a second electrode. The first electrode is electrically connected to the first semiconductor layer through the first opening, and the second electrode is electrically connected to the second semiconductor layer through the second opening. A groove is provided between the first electrode and the second electrode to expose the upper surface of the first insulating layer.

[0010] A second insulating layer is partially disposed in the groove and extends to both sides to cover the upper surfaces of a portion of the first electrode and a portion of the second electrode, respectively.

[0011] Secondly, this application also provides a light-emitting diode, comprising at least:

[0012] A semiconductor stack, wherein the semiconductor stack comprises, in sequence, a first semiconductor layer, an active layer, and a second semiconductor layer;

[0013] A first insulating layer is at least partially disposed above and on the sidewalls of the semiconductor stack, and has a first opening exposing the first semiconductor layer and a second opening exposing the second semiconductor layer;

[0014] The electrode structure includes a first electrode and a second electrode. The first electrode is electrically connected to the first semiconductor layer through the first opening, and the second electrode is electrically connected to the second semiconductor layer through the second opening. A groove is provided between the first electrode and the second electrode, exposing the upper surface of the first insulating layer. The width of the groove ranges from 2 μm to 5 μm. The first electrode and the second electrode extend toward the sidewall of the light-emitting diode and at least partially cover the sidewall of the first insulating layer.

[0015] A second insulating layer is partially disposed in the groove and extends to both ends to cover the upper surfaces of a portion of the first electrode and a portion of the second electrode, respectively. The ratio of the total area covered by the second insulating layer on the electrode structure to the area of ​​the upper surface of the electrode structure ranges from 25% to 75%.

[0016] Thirdly, this application also provides a light-emitting device, the light-emitting device comprising:

[0017] Packaging substrate;

[0018] At least one light-emitting diode is disposed on the surface of the packaging substrate, and the packaging substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode provided by the above technical solution.

[0019] Compared with the prior art, the light-emitting diode and light-emitting device provided in this application have at least the following beneficial effects:

[0020] The light-emitting diode provided in this application forms physical isolation by setting a second insulating layer between the first electrode and the second electrode, blocking the short circuit path of solder bridging. The solder is electrically connected to the circuit through the electrode surfaces at both ends, which is equivalent to increasing the distance between the electrodes on both sides of the solder and reducing the risk of direct contact between the solder. This technical solution solves the problem of short circuit caused by direct electrical contact between metal electrodes during the current welding process of small-sized Micro-LEDs. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of solder overflow and short circuit in a light-emitting diode in the prior art;

[0022] Figure 2 This is a schematic diagram of the planar structure of a light-emitting diode provided in Embodiment 1 of this application;

[0023] Figure 3 for Figure 2 Schematic diagram of the structure along section AA;

[0024] Figure 4 for Figure 3 Schematic diagram of the structure along section BB;

[0025] Figure 5 This is a schematic diagram of the planar structure of the light-emitting diode provided in Embodiment 2 of this application;

[0026] Figure 6 for Figure 5 Schematic diagram of the structure along section CC;

[0027] Figure 7 for Figure 5 Schematic diagram of the structure along section DD;

[0028] Figure 8 This is a schematic diagram of the structure of the light-emitting device provided in Embodiment 3 of this application.

[0029] List of reference numerals in the attached diagram:

[0030] 10. Substrate; 20. Bonding layer; 30. Semiconductor stack; 310. First semiconductor layer; 320. Active layer; 330. Second semiconductor layer; 40. Transparent conductive layer; 50. First insulating layer; 610. First electrode; 610a. First edge; 620. Second electrode; 620a. Second edge; 70. Groove; 80. Second insulating layer;

[0031] OP1, First opening; OP2, Second opening;

[0032] 101. Packaging substrate; 102. Light-emitting element. Detailed Implementation

[0033] See Figure 1 In the prior art, due to the small size of Micro-LEDs, the distance between the first electrode 610 and the second electrode 620 is also relatively small. During die bonding, solder paste can easily overflow between the two electrodes, causing a short circuit. In view of the above-mentioned defects in the prior art and the background art, this application provides a light-emitting diode and a light-emitting device, the light-emitting diode comprising at least:

[0034] A semiconductor stack, wherein the semiconductor stack comprises, in sequence, a first semiconductor layer, an active layer, and a second semiconductor layer;

[0035] A first insulating layer is at least partially disposed above the semiconductor stack and has a first opening exposing the first semiconductor layer and a second opening exposing the second semiconductor layer;

[0036] The electrode structure includes a first electrode and a second electrode. The first electrode is electrically connected to the first semiconductor layer through the first opening, and the second electrode is electrically connected to the second semiconductor layer through the second opening. A groove is provided between the first electrode and the second electrode to expose the upper surface of the first insulating layer.

[0037] A second insulating layer is partially disposed in the groove and extends to both ends to cover the upper surfaces of a portion of the first electrode and a portion of the second electrode, respectively.

[0038] By setting a second insulating layer between the first and second electrodes to form physical isolation, the short-circuit path of solder bridging is blocked. The solder is electrically connected to the circuit through the electrode surfaces at both ends, which is equivalent to increasing the distance between the electrodes on both sides of the solder and reducing the risk of direct contact between the solder. This technical solution solves the problem of short circuit caused by direct electrical contact between metal electrodes during the current welding process of small-sized Micro-LEDs.

[0039] In some embodiments, the first insulating layer is also disposed on the sidewall of the semiconductor stack.

[0040] In some embodiments, the first electrode and / or the second electrode extend toward the sidewall of the light-emitting diode and at least partially cover the sidewall of the first insulating layer. By extending the electrode structure to the chip sidewall, the surface area of ​​the die-bonding electrodes is effectively increased, improving the chip's bonding characteristics.

[0041] In some embodiments, the material of the second insulating layer includes one or more of benzocyclobutene, epoxy resin, silicone resin, or polyimide. The second insulating layer uses an organic material to achieve its bonding layer function.

[0042] In some embodiments, the material of the first insulating layer includes one or more of Al2O3, TiO2, SiN, TiN, or SiO2. The second insulating layer is made of an inorganic material with good structural stability and insulating properties, effectively isolating the solder of the two end electrodes and preventing impurities and moisture from entering, thus protecting the internal structure of the chip.

[0043] In some embodiments, the material of the second insulating layer is the same as the material of the first insulating layer.

[0044] In some embodiments, a first direction is defined as the direction from the first electrode to the second electrode on the projection surface, and a second direction is perpendicular to the first direction; the groove has a spacing d0 in the first direction, and the light-emitting diode has a chip length and a chip width in the first direction and the second direction, respectively; wherein the spacing d0 ranges from 2μm to 5μm, and the ratio of the spacing d0 to the chip length is between 5% and 30%. By reasonably controlling the distance between the electrodes, the current spreading effect is optimized while ensuring that the solder cannot bridging.

[0045] In some embodiments, the distance by which the second insulating layer extends along the first direction to cover the first electrode is d3, and the distance by which the second insulating layer extends along the first direction to cover the second electrode is d4, wherein d0 + d3 + d4 ≥ 5 μm. The coverage size of the second insulating layer on the electrode structure surface is controlled to balance insulation requirements and light-emitting area loss.

[0046] In some embodiments, the second insulating layer extends from the groove to both ends, covering the upper surface of the electrode structure. Along the top view direction of the light-emitting diode, the edge of the second insulating layer in the first direction lies within the edge range of the upper surface of the electrode structure. This prevents the second insulating layer from excessively extending in the first direction, which could affect the current injection and heat dissipation performance of the electrode, further balancing insulation requirements with light-emitting area loss.

[0047] In some embodiments, along the top view direction of the light-emitting diode, the edge of the second insulating layer in the second direction is located outside the edge range of the upper surface of the electrode structure, and the edge of the second insulating layer has a distance d5 from the edge of the upper surface of the electrode structure, where 0 < d5 ≤ 3 μm. The edge of the second insulating layer extends beyond the edge of the electrode structure to prevent edge peeling of the insulating layer.

[0048] In some embodiments, the ratio of the total area covered by the second insulating layer over the electrode structure to the upper surface area of ​​the electrode structure ranges from 25% to 75%. This ensures that the second insulating layer provides sufficient coverage and physical isolation from the electrode structure.

[0049] In some embodiments, the groove has a depth h2, where 1 μm ≤ h2 ≤ 10 μm. The groove depth is also the thickness of the portion of the electrode structure above the first insulating layer. This parameter is controlled to achieve good current spreading and to ensure the filling quality and structural strength of the second insulating layer within the groove.

[0050] In some embodiments, the second insulating layer has a coverage thickness h1, which is the thickness from the upper surface of the electrode structure to the upper surface of the second insulating layer, where 0 < h1 ≤ 4 μm. This avoids an increase in thermal resistance due to an excessively thick second insulating layer, achieving a balance between insulation performance, structural strength, and electrical performance.

[0051] In some embodiments, the single-sided dimension of the light-emitting diode ranges from 1 μm to 50 μm.

[0052] This application also provides a light-emitting diode, comprising at least:

[0053] A semiconductor stack, wherein the semiconductor stack comprises, in sequence, a first semiconductor layer, an active layer, and a second semiconductor layer;

[0054] A first insulating layer is at least partially disposed above and on the sidewalls of the semiconductor stack, and has a first opening exposing the first semiconductor layer and a second opening exposing the second semiconductor layer;

[0055] The electrode structure includes a first electrode and a second electrode. The first electrode is electrically connected to the first semiconductor layer through the first opening, and the second electrode is electrically connected to the second semiconductor layer through the second opening. A groove is provided between the first electrode and the second electrode, exposing the upper surface of the first insulating layer. The width of the groove ranges from 2 μm to 5 μm. The first electrode and the second electrode extend toward the sidewall of the light-emitting diode and at least partially cover the sidewall of the first insulating layer.

[0056] A second insulating layer is partially disposed in the groove and extends to both ends to cover the upper surfaces of a portion of the first electrode and a portion of the second electrode, respectively. The ratio of the total area covered by the second insulating layer on the electrode structure to the area of ​​the upper surface of the electrode structure ranges from 25% to 75%.

[0057] This application also provides a light-emitting device, the light-emitting device comprising:

[0058] Packaging substrate;

[0059] At least one light-emitting diode is disposed on the surface of the packaging substrate, and the packaging substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode provided by the above technical solution.

[0060] The following embodiments, namely Embodiments 1 to 3, illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0061] The composition and dopants of each layer in the semiconductor laser element described in this application can be analyzed using any suitable method, such as secondary ion mass spectrometry (SIMS). The thickness of each layer in the semiconductor laser element described in this application can be analyzed using any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM), in conjunction with, for example, the depth positions of each layer on a SIMS image.

[0062] Example 1:

[0063] This embodiment provides a light-emitting diode, which, from bottom to top, includes a semiconductor stack 30, a first insulating layer 50 disposed above the semiconductor stack 30, a first electrode 610 and a second electrode 620 located on the first insulating layer 50, and a second insulating layer 80 disposed in a groove 70 between the first electrode 610 and the second electrode 620, wherein the second insulating layer 80 extends to both ends to cover the upper surfaces of a portion of the first electrode 610 and a portion of the second electrode 620, respectively.

[0064] Figures 2 to 4 The figures show a top view and a cross-sectional view along AA and BB of the light-emitting diode provided in this embodiment. The following describes each structural layer of the light-emitting diode provided in this embodiment in detail with reference to the figures.

[0065] See Figures 2 to 4 The substrate 10 can serve as the epitaxial growth substrate and can be made of a conductive, insulating, or light-transmitting material with excellent thermal conductivity, such as a sapphire substrate, silicon carbide substrate, gallium nitride substrate, zinc oxide substrate, gallium arsenide substrate, or silicon substrate. In this embodiment, the substrate 10 is a surface-patterned sapphire substrate to improve epitaxial quality, prevent delamination or peeling during subsequent processes or use, and reduce scattering of light emitted from the semiconductor stack 30. Further, the horizontal projection of the substrate 10 is rectangular, with the long side of the rectangular projection pointing to a first direction, i.e., the direction from the first electrode to the second electrode, and the chip having a chip length in the first direction; the short side of the rectangular projection pointing to a second direction, and the chip having a chip width in the second direction.

[0066] See also Figures 2 to 4 A bonding layer 20 is disposed between the substrate 10 and the semiconductor stack 30. The bonding layer 20 is made of an organic insulating material, such as benzocyclobutene, epoxy resin, silicone resin, or polyimide, to achieve electrical isolation between the substrate 10 and the semiconductor stack 30 and to provide good adhesion. Furthermore, the thickness of the bonding layer 20 is between 100 nm and 3000 nm.

[0067] See also Figures 2 to 4 The semiconductor stack 30 sequentially includes a first semiconductor layer 310, an active layer 320, and a second semiconductor layer 330. The first semiconductor layer 310 is composed of a III-V or II-VI compound semiconductor and is doped with N-type dopants such as Si, Ge, Sn, Se, or Te, serving as an N-type semiconductor layer to provide electrons for recombination light emission. The second semiconductor layer 330 is composed of a III-V or II-VI compound semiconductor and is doped with P-type dopants such as Mg, Zn, Ca, Sr, or Ba, serving as a P-type semiconductor layer to provide holes for recombination light emission. The active layer 320 may have any structure, but is not limited to, a single-well structure, a multi-well structure, a single quantum well structure, or a multi-quantum well structure, for electron and hole recombination light emission.

[0068] See also Figures 2 to 4 A transparent conductive layer 40 is formed on the semiconductor stack 30. This transparent conductive layer 40 serves as a current channel, allowing the current to spread as widely as possible across the surface of the second semiconductor layer 330, thereby improving luminous efficiency. The material of the transparent conductive layer 40 can be ITO (indium tin oxide), ZnO (zinc oxide), AZO (aluminum-doped zinc oxide), or IZO (indium zinc oxide). Further, the transparent conductive layer 40 is made of ITO, with a thickness between 10 nm and 200 nm. This material has high transparency and low light absorption, while also possessing high conductivity and low resistance, ensuring effective current transmission.

[0069] See also Figures 2 to 4A first insulating layer 50 is formed above the transparent conductive layer 40 and the semiconductor stack 30. The first insulating layer 50 has a first opening OP1 exposing the first semiconductor layer 310 and a second opening OP2 exposing the second semiconductor layer 330. The first electrode 610 is electrically connected to the first semiconductor layer 310 through the first opening OP1, and the second electrode 620 is electrically connected to the second semiconductor layer 330 through the second opening OP2. The first insulating layer 50 can be a single layer of insulating material or a DBR structure to reflect light of different specific wavelengths. For example, it can use a SiO2 / TiO2 multilayer stack structure, or it can use Al2O3, TiO2, SiN, TiN, or SiO2 materials. Furthermore, the total thickness of the first insulating layer 50 is between 0.5μm and 5.0μm to ensure that it is sufficient to withstand the working voltage and avoid electrical breakdown, while preventing cracks or peeling caused by thermal expansion coefficient mismatch due to excessive thickness of the first insulating layer 50. Furthermore, the first insulating layer 50 also covers the sidewalls of the semiconductor stack 30 to achieve insulation and protection of the semiconductor structure it covers.

[0070] See also Figures 2 to 4 A first electrode 610 and a second electrode 620 are formed on the first insulating layer 50. The first electrode 610 is electrically connected to the first semiconductor layer 310 through a first opening OP1, and the second electrode 620 is electrically connected to the second semiconductor layer 330 through a second opening OP2. The first electrode 610 and the second electrode 620 not only fill the interior of the openings but also extend to cover a portion of the upper surface of the first insulating layer 50. Therefore, a groove 70 is formed between the first electrode 610 and the second electrode 620, exposing the upper surface of the first insulating layer 50. Further, the first electrode 610 and the second electrode 620 can be made of the same material, including a single film of a single material or an alloy of at least two materials selected from Au, Sn, Ni, Pb, Ag, In, Cr, Ge, Si, Ti, W, and Pt, or a multilayer structure including a combination of these materials. For Micro-LED chips, such as... Figure 1 As shown, the size of the groove 70 will also be reduced accordingly, which will significantly increase the risk of solder overflow during the chip soldering process with the circuit, leading to the risk of chip short circuit and failure. Optionally, the first electrode 610 extends towards the sidewall of the light-emitting diode and at least covers a portion of the sidewall of the first insulating layer 50. Optionally, the second electrode 620 extends towards the sidewall of the light-emitting diode and at least covers a portion of the sidewall of the first insulating layer 50. By extending at least one electrode structure to the chip sidewall, the surface area of ​​the chip die-bonding electrode is effectively increased, and the solder has a sufficiently large contact area with the electrode structure on the sidewall, improving the chip soldering characteristics. Further, both the first electrode 610 and the second electrode 620 extend towards the sidewall of the light-emitting diode and both cover a portion of the sidewall of the first insulating layer 50.

[0071] See also Figures 2 to 4 The second insulating layer 80 is formed in the groove 70 and extends to both ends to cover the upper surfaces of part of the first electrode 610 and part of the second electrode 620 respectively. By forming the second insulating layer 80 between the first electrode 610 and the second electrode 620 to form physical isolation, the solder bridging short circuit path is blocked. The solder is electrically connected to the circuit through the electrode surfaces at both ends, for example, through the electrodes located on the sidewall of the chip. This is equivalent to increasing the distance between the electrodes on both sides of the solder, reducing the risk of direct contact between the solder and effectively solving the problem of short circuit caused by direct electrical contact of metal electrodes during the current soldering process of small-sized Micro-LEDs.

[0072] In some embodiments, the material of the second insulating layer 80 is benzocyclobutene, epoxy resin, silicone resin or polyimide, and the second insulating layer 80 can be made of organic materials to achieve its multiple functions of bonding and insulation.

[0073] In some embodiments, the material of the second insulating layer 80 is the same as that of the first insulating layer 50, such as inorganic insulating materials such as Al2O3, TiO2, SiN, TiN or SiO2, to effectively isolate the solder of the two electrode ends and prevent impurities and moisture from entering, thus protecting the internal structure of the chip.

[0074] In some implementations, see Figure 2 and Figure 3 The groove 70 has a spacing d0 in the first direction, which is the distance between the two electrodes, where d0 ≥ 2μm, and the ratio of spacing d0 to chip length is between 5% and 30%. By reasonably controlling the distance between the electrodes, the current spreading effect is optimized while ensuring that the solder cannot bridge. Further, the spacing d0 ≥ ranges from 2μm to 5μm. As an example, the spacing d0 can be 2.5μm, 3.0μm, 3.5μm, 4.0μm, or 5.0μm. If the spacing d0 is less than 2μm, it may cause the electrodes to short-circuit, and the existing process also limits the formation of smaller spacing dimensions; if the spacing is too large, for example, exceeding 5μm, it is equivalent to reducing the electrode contact area, affecting current conduction. Further, the spacing d0 of the groove 70 is always consistent in the second direction. That is, the first edge 610a of the first electrode 610 is parallel to the second edge 620a of the second electrode 620. Understandably, the first edge 610a and the second edge 620a can be parallel to the second direction or at a certain angle to the second direction, and the appropriate electrode shape and structure can be set according to the actual chip shape and size.

[0075] In some implementations, see also Figure 2 and Figure 3The second insulating layer 80 extends along the first direction to cover the first electrode 610 at a distance d3, and extends along the first direction to cover the second electrode 620 at a distance d4, where d0 + d3 + d4 ≥ 5 μm. Further, d3 = d4, meaning the second insulating layer 80 symmetrically covers the upper surfaces of the first electrode 610 and the second electrode 620, and the physical isolation distance between the two electrodes is equal. It is understandable that, depending on the different sizes of the first electrode 610 and the second electrode 620, the distances d3 and d4 of the second insulating layer 80 covering the upper surface of the first electrode 610 and the second electrode 620 can be different, controlling the coverage size of the second insulating layer 80 on the electrode structure surface to balance insulation requirements and light-emitting area loss. As an example, when the width d0 of the groove 70 is 2μm, d3+d4 shall not be less than 3μm, such as 3.5μm, 4.0μm, 4.5μm or 5.0μm, to ensure that the physical insulation dimension of the second insulating layer 80 is not less than 5μm.

[0076] In some implementations, see also Figure 2 and Figure 3 The second insulating layer 80 extends from the groove 70 to both ends, covering the upper surface of the electrode structure. Along the top view direction of the light-emitting diode, the edge of the second insulating layer 80 in the first direction lies within the edge range of the upper surface of the electrode structure. The physical insulating dimension of the second insulating layer 80 should not exceed the length of the chip itself to leave sufficient electrode contact area and ensure good electrical contact of the chip. If the second insulating layer 80 extends excessively into the chip sidewall in the first direction, it may affect the current injection and heat dissipation performance of the electrodes. Controlling the coverage dimension of the second insulating layer 80 on the upper surfaces of the first electrode 610 and the second electrode 620 further balances insulation requirements with electrical contact area loss.

[0077] In some implementations, see Figure 2 and Figure 4 Along the top view direction of the light-emitting diode, the edge of the second insulating layer 80 in the second direction is located outside the edge range of the upper surface of the electrode structure, and the edge of the second insulating layer 80 has a distance d5 from the edge of the upper surface of the electrode structure, 0 < d5 ≤ 3 μm. The edge of the second insulating layer 80 extends beyond the edge of the electrode structure to prevent the edge of the insulating layer from peeling off.

[0078] In some implementations, see Figure 2The ratio of the total area of ​​the second insulating layer 80 covering the electrode structure to the upper surface area of ​​the electrode structure is greater than 25%, ensuring that the second insulating layer 80 provides sufficient coverage and physical isolation distance to the electrode structure. Since the second insulating layer 80 extends beyond the edge of the electrode structure in the second direction, the total area of ​​the second insulating layer 80 covering the electrode structure is proportional to d3, d4, and the lengths of the first electrode 610 and the second electrode 620. Furthermore, the ratio of the total area of ​​the second insulating layer 80 covering the electrode structure to the upper surface area of ​​the electrode structure is less than 80%, ensuring sufficient exposed electrode contact area on the chip sidewalls and upper surface.

[0079] In some implementations, see Figure 3 and Figure 4 The groove 70 has a depth h2, where 1μm ≤ h2 ≤ 10μm. The groove depth is also the thickness of the portion of the electrode structure above the first insulating layer 50. The first electrode 610 and the second electrode 620 have the same thickness, so the groove 70 has the same depth, for example, it can be 1.5μm, 2.0μm, 4.0μm, 6.0μm or 8.0μm. This electrode deposition thickness can achieve a good current spreading effect, and the depth dimension of the resulting groove 70 is conducive to achieving good deposition or filling quality of the second insulating layer 80 inside the groove 70.

[0080] In some implementations, see also Figure 3 and Figure 4 The second insulating layer 80 has a coverage thickness h1, which is the thickness from the upper surface of the electrode structure to the upper surface of the second insulating layer 80, where 0 < h1 ≤ 4 μm. As an example, the coverage thickness h1 can be 1 μm, 2 μm, 2.5 μm, or 3 μm. The coverage thickness h1 does not need to be excessively thick, for example, exceeding 4 μm, as this would increase material costs and reduce production efficiency. Furthermore, a coverage thickness h1 between 0.5 μm and 3 μm is preferable to achieve a balance between insulation performance, structural strength, and electrical performance. If h1 is too thin, its structural strength cannot be guaranteed, and interlayer peeling will negatively impact its insulation performance.

[0081] This embodiment also provides a method for manufacturing a light-emitting diode, including the following steps:

[0082] S1: Provide a growth substrate, namely substrate 10. In this embodiment, a surface-patterned sapphire substrate is used.

[0083] S2: A bonding layer 20 is formed on the substrate 10, and the bonding layer 20 is patterned to improve its bonding effect on the semiconductor stack 30.

[0084] S3: Epitaxial growth is performed by metal-organic chemical vapor deposition, and the thickness and doping concentration of each layer are precisely controlled to grow the first semiconductor layer 310, the active layer 320 and the second semiconductor layer 330 in sequence.

[0085] S4: A transparent conductive layer 40 is formed on the second semiconductor layer 330 using electron beam evaporation or sputtering processes, for example, by depositing a 10nm to 200nm thick ITO material using physical vapor deposition or chemical vapor deposition to improve the current transmission performance on the P side.

[0086] S5: A first insulating layer 50 is formed above and on the sidewalls of the transparent conductive layer 40 and the exposed semiconductor stack. For example, an inorganic insulating material such as Al2O3, TiO2, SiN, TiN or SiO2 is used. The insulating layer is then patterned by photolithography and etching. The first insulating layer 50 covering the first semiconductor layer 310 is partially etched away to form a first opening OP1. The first insulating layer 50 covering the second semiconductor layer 330 is partially etched away to form a second opening OP2, so as to facilitate the subsequent deposition of the electrode structure.

[0087] S6: A first electrode 610 and a second electrode 620 are formed on the insulating layer 60 by electroplating, physical vapor deposition, or chemical vapor deposition, etc., with a distance of not less than 2 μm between the two electrodes. The first electrode 610 and the second electrode 620 may be made of the same material, including a single material or an alloy of at least two materials selected from Au, Sn, Ni, Pb, Ag, In, Cr, Ge, Si, Ti, W, and Pt, or a multilayer structure including a combination of them. The first electrode 610 and the second electrode 620 are respectively formed in the first opening OP1 and the second opening OP2, and extend to both ends to cover a portion of the upper surface and sidewalls of the first insulating layer 50.

[0088] S7: A second insulating layer 80 is formed at the groove 70 between the first electrode 610 and the second electrode 620. The second insulating layer 80 covers a distance of not less than 5μm on the chip along the first direction to ensure sufficient physical isolation and prevent short circuit of the chip caused by solder contact.

[0089] Optionally, the second insulating layer 80 can be an organic bonding material, such as benzocyclobutene, epoxy resin, silicone resin, or polyimide.

[0090] Optionally, the second insulating layer 80 can be an inorganic insulating material, such as Al2O3, TiO2, SiN, TiN or SiO2.

[0091] S8: Soldering and encapsulation process is performed. Solder paste contacts the first electrode 610 and the second electrode 620 exposed at both ends, respectively. Effective isolation is achieved through the second insulating layer 80.

[0092] The light-emitting diode provided in this embodiment is a flip-chip light-emitting diode, which is particularly suitable for small-sized Micro-LEDs with a single-side dimension ranging from 1μm to 50μm. The product size can be, for example, a square shape or a rectangular shape of similar size, such as 10μm×10μm, 10μm×15μm, 10μm×25μm, 25μm×25μm, or 35μm×35μm, but is not particularly limited to this.

[0093] Example 2:

[0094] This embodiment also provides a light-emitting diode, which, from bottom to top, includes a semiconductor stack 30, a first insulating layer 50 disposed above the semiconductor stack 30, a first electrode 610 and a second electrode 620 located on the first insulating layer 50, and a second insulating layer 80 disposed in a groove 70 between the first electrode 610 and the second electrode 620, wherein the second insulating layer 80 extends to both ends to cover the upper surfaces of a portion of the first electrode 610 and a portion of the second electrode 620, respectively.

[0095] Figures 5 to 7 The figures show a top view and a cross-sectional view along CC and DD of the LED provided in this embodiment. The similarities with the technical solution of Embodiment 1 will not be repeated here. The differences between this embodiment and Embodiment 1 will be described in detail below with reference to the accompanying drawings.

[0096] See Figures 5 to 7 As can be seen, the first electrode 610 and the second electrode 620 are deposited only on the upper surface of the first insulating layer 50. The second insulating layer 80 fills the groove 70 between the electrodes and extends to cover part of the electrode structure. The edge of the second insulating layer 80 is a certain distance from the edge of the electrode structure to allow solder paste to form an electrical path. Although enlarging the size of the first electrode 610 and the second electrode 620 until they are deposited to the sidewall of the chip can give the solder paste a sufficiently large contact area, the electrode structure does not need to be deposited to the sidewall of the first insulating layer 50, provided that good contact can be formed. This also reduces chip quality problems caused by sidewall electrode peeling. By forming a second insulating layer 80 with a suitable coverage area between the first electrode 610 and the second electrode 620 to form physical isolation, the solder bridging short circuit path is blocked. The solder is electrically connected to the circuit through the electrode surfaces at both ends, reducing the risk of direct contact between the solder. The technical solution provided in this embodiment also solves the problem of short circuit caused by direct electrical contact between metal electrodes during current soldering.

[0097] Example 3:

[0098] See Figure 8This embodiment provides a light-emitting device, which is a flip-chip LED product, including a packaging substrate 101; at least one light-emitting element 102 disposed on the surface of the packaging substrate 101, and the packaging substrate 101 is electrically connected to the electrode structure of the light-emitting diode. The light-emitting element 102 is the light-emitting diode provided in Embodiment 1 or Embodiment 2 of this application.

[0099] In summary, the light-emitting diode and light-emitting device provided in this application effectively overcome the various shortcomings of the prior art and have high industrial application value.

[0100] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A light emitting diode, characterized by, At least comprising: a semiconductor stack, the semiconductor stack comprising a first semiconductor layer, an active layer, and a second semiconductor layer in sequence; a first insulating layer, at least partially disposed above the semiconductor stack, and having a first opening portion exposing the first semiconductor layer and a second opening portion exposing the second semiconductor layer; an electrode structure comprising a first electrode and a second electrode, the first electrode being electrically connected with the first semiconductor layer through the first opening portion, the second electrode being electrically connected with the second semiconductor layer through the second opening portion, and the first electrode and the second electrode having a groove exposing an upper surface of the first insulating layer therebetween; a second insulating layer, partially disposed in the groove and extending to both ends to cover upper surfaces of part of the first electrode and part of the second electrode, respectively.

2. The light emitting diode of claim 1, wherein, The first insulating layer is also disposed on the sidewall of the semiconductor stack.

3. The light emitting diode of claim 1, wherein, The first electrode and / or the second electrode extend toward the sidewall of the light emitting diode and at least partially cover the sidewall of the first insulating layer.

4. The light emitting diode of claim 1, wherein, The first direction is defined as the direction from the first electrode to the second electrode on the projection surface, and the second direction is perpendicular to the first direction; the groove has a spacing d0 in the first direction, and the light emitting diode has a chip length and a chip width in the first direction and the second direction, respectively; wherein the spacing d0 is in the range of 2 μm to 5 μm, and the ratio of the spacing d0 to the chip length is between 5% and 30%.

5. The light emitting diode of claim 4, wherein, The distance covered by the second insulating layer along the first direction to the first electrode is d3, and the distance covered by the second insulating layer along the first direction to the second electrode is d4, wherein d0+d3+d4≥5 μm.

6. The light emitting diode of claim 4, wherein, The second insulating layer extends from the groove to both ends to cover the upper surface of the electrode structure, and in the overhead direction of the light emitting diode, the edge of the second insulating layer in the first direction is within the edge range of the upper surface of the electrode structure.

7. The light emitting diode of claim 6, wherein, In the overhead direction of the light emitting diode, the edge of the second insulating layer in the second direction is outside the edge range of the upper surface of the electrode structure, and the edge of the second insulating layer has a distance d5 from the edge of the upper surface of the electrode structure, 0 < d5 ≤ 3 μm.

8. The light emitting diode of claim 1, wherein, The ratio of the total area covered by the second insulating layer above the electrode structure to the area of the upper surface of the electrode structure is in the range of 25% to 75%.

9. The light emitting diode of claim 1, wherein, The groove has a depth h2, 1 μm ≤ h2 ≤ 10 μm.

10. The light emitting diode of claim 9, wherein, The second insulating layer has a coverage thickness h1, which is the thickness from the upper surface of the electrode structure to the upper surface of the second insulating layer, 0 < h1 ≤ 4 μm.

11. The light emitting diode of claim 1, wherein, The single side dimension of the light emitting diode is in the range of 1 μm to 50 μm.

12. A light emitting diode, comprising: At least comprising: a semiconductor stack, the semiconductor stack comprising a first semiconductor layer, an active layer, and a second semiconductor layer in sequence; a first insulating layer, at least partially disposed above the semiconductor stack and sidewall, and having a first opening portion exposing the first semiconductor layer and a second opening portion exposing the second semiconductor layer; An electrode structure includes a first electrode and a second electrode, the first electrode is electrically connected with the first semiconductor layer through the first opening part, the second electrode is electrically connected with the second semiconductor layer through the second opening part, the first electrode and the second electrode have a groove exposing the upper surface of the first insulating layer therebetween, the groove has a width ranging from 2 μm to 5 μm; the first electrode and the second electrode extend to the sidewall direction of the light emitting diode and at least partially cover the sidewall of the first insulating layer; A second insulating layer is partially disposed in the groove and extends to both ends to cover the upper surface of part of the first electrode and part of the second electrode respectively, the ratio of the total area covered by the second insulating layer above the electrode structure to the area of the upper surface of the electrode structure ranges from 25% to 75%.

13. A light-emitting device, characterized in that, The light emitting device includes: A packaging substrate; At least one light emitting diode is disposed on the surface of the packaging substrate, the packaging substrate is electrically connected with the electrode structure of the light emitting diode; the light emitting diode is the light emitting diode according to any one of claims 1-12.

Images