A method for removing silicon substrate from a chip based on C2W bonding

Abstract

The application provides a silicon substrate removing method based on C2W bonding in a chip, and belongs to the technical field of electro-optical modulators.The method comprises the following steps: forming a waveguide core on a substrate, and depositing a first passivation layer, wherein the first passivation layer covers the substrate and the waveguide core; forming metal grooves on two sides of the waveguide core, and forming metal electrodes in the metal grooves; depositing a second passivation layer, wherein the second passivation layer covers the metal electrodes and the first passivation layer; performing opening on the metal electrodes to form a hole structure; forming a protective layer on a region corresponding to the metal electrodes above the second passivation layer, and the protective layer covers the metal electrodes through the hole structure; bonding a region corresponding to the waveguide core above the second passivation layer with a chip; removing the silicon substrate in the chip after bonding; and removing the protective layer.The scheme shortens the device preparation time and reduces the cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electro-optical modulators, and in particular to a method for removing a silicon substrate in a chip based on C2W bonding. BACKGROUND

[0002] Compared with traditional silicon optical technology, silicon optical technology based on silicon nitride (SiN) material has many single advantages such as low loss, wide spectrum, and large optical power. Therefore, SiN gradually becomes an important platform for CMOS-compatible ultra-low-loss photonic integration. However, due to the lack of electro-optical properties of SiN, it is difficult to realize high-efficiency active devices such as electro-optical modulators.

[0003] Lithium niobate (LN) crystal is known as the "silicon" in the field of photonics due to its excellent electro-optical, nonlinear optical, acousto-optical, and photorefractive properties. However, its etching process is complex and incompatible with CMOS technology, which poses a great challenge to mass production.

[0004] Heterogeneous integration of SiN and thin film lithium niobate (TFLN) can fully utilize the high light transmittance of SiN as an optical waveguide medium. Meanwhile, based on the performance advantages of TFLN such as high optoelectronic bandwidth, it can meet the demand of 200Gbps / lane and higher speed applications. Chip to wafer (C2W) bonding can avoid etching process and achieve compatibility with CMOS technology.

[0005] After C2W bonding, chemical solution corrosion or dry etching is needed to remove the silicon substrate on the chip to ensure the modulation performance of TFLN.

[0006] Existing technology forms a protective layer after bonding. The electrode on the wafer needs to be protected by the protective layer, while the chip area needs to be exposed for subsequent silicon substrate removal. Deposition of a protective layer over the entire surface can be used, and then the protective layer in the chip area is removed using photolithography and etching. Alternatively, photoresist can be applied first, the photoresist in the wafer electrode area is removed using photolithography, then a protective layer is deposited, and finally the protective layer is stripped.

[0007] Regardless of deposition followed by etching or stripping process, photolithography is unavoidable. However, after bonding, the chip is several hundred microns higher than the wafer. If a spin coater is used, the glue layer will be uneven and bubbles will occur due to the blockage of the chip. If a spray coater is used, the utilization rate of photoresist is low, usually between 5% and 15%, and the equipment cost is higher compared to the spin coater.

[0008] On the other hand, there is a large step between the chip and the wafer, and two photolithographies are generally needed, which is time-consuming and costly, and the overlay accuracy also affects the product. The double-sided exposure machine can also be used, but the cost of the machine is higher than that of the ordinary photolithography machine. SUMMARY

[0009] Therefore, the embodiments of the present application provide a method for removing silicon substrate in a chip based on C2W bonding, which at least partially solves the problem that the protection layer is not uniform and the cost of preparing the protection layer is high due to the fact that the chip is higher than the wafer by hundreds of microns after bonding.

[0010] The embodiments of the present application provide a method for removing silicon substrate in a chip based on C2W bonding, which comprises the following steps:

[0011] forming a waveguide core on a substrate and depositing a first passivation layer, wherein the first passivation layer covers the substrate and the waveguide core;

[0012] forming a metal groove on both sides of the waveguide core and forming a metal electrode in the metal groove;

[0013] depositing a second passivation layer, wherein the second passivation layer covers the metal electrode and the first passivation layer;

[0014] forming a hole structure by opening a hole above the metal electrode;

[0015] forming a protection layer on the second passivation layer corresponding to the metal electrode, wherein the protection layer covers the metal electrode through the hole structure;

[0016] bonding the area on the second passivation layer corresponding to the waveguide core with a chip, wherein the chip is provided with a silicon substrate on the side away from the bonding area;

[0017] removing the silicon substrate in the chip after bonding;

[0018] removing the protection layer.

[0019] According to a specific implementation manner of the embodiments of the present application, the step of forming a waveguide core on a substrate comprises the following steps:

[0020] depositing a waveguide layer on the substrate;

[0021] etching the waveguide layer to form the waveguide core.

[0022] According to a specific implementation manner of the embodiments of the present application, the step of forming a metal electrode in the metal groove comprises the following steps:

[0023] depositing a metal, the metal covering the first passivation layer and the metal slot;

[0024] etching the metal on the first passivation layer, the metal in the metal slot forming the metal electrode.

[0025] According to a specific implementation manner of the embodiment of the present application, the bonding the region above the second passivation layer corresponding to the waveguide core and the chip comprises:

[0026] cleaning and plasma activating the region above the second passivation layer corresponding to the waveguide core and the chip in sequence;

[0027] pre-bonding the region above the second passivation layer corresponding to the waveguide core and the chip at room temperature to form a pre-bonding device;

[0028] annealing the pre-bonding device at 50-120℃ for 6-12h to complete the bonding.

[0029] According to a specific implementation manner of the embodiment of the present application, the removing the silicon substrate in the chip comprises:

[0030] removing the silicon substrate in the chip by a wet etching or dry etching process.

[0031] According to a specific implementation manner of the embodiment of the present application, the removing the silicon substrate in the chip comprises:

[0032] grinding the silicon substrate in the chip to reduce the thickness of the silicon substrate to 20-40μm;

[0033] removing the silicon substrate after grinding by a wet etching or dry etching process.

[0034] According to a specific implementation manner of the embodiment of the present application, the removing the silicon substrate in the chip comprises:

[0035] dry etching the silicon substrate in the chip to a thickness of 5-20μm;

[0036] removing the remaining silicon substrate by a wet etching process.

[0037] According to a specific implementation manner of the embodiment of the present application, the thickness of the protective layer is 5-100μm.

[0038] According to a specific implementation manner of the embodiment of the present application, the removing the protective layer comprises:

[0039] removing the protective layer by soaking with a chemical liquid, the chemical liquid being N-methyl pyrrolidone or acetone.

[0040] According to a specific implementation manner of the embodiment of the application, the chip further comprises an electro-optic material layer and a silicon oxide layer, the electro-optic material layer is bonded with a region above the second passivation layer corresponding to the waveguide core, and the silicon oxide layer is located between the electro-optic material layer and the silicon substrate.

[0041] Advantages:

[0042] The method for removing a silicon substrate in a chip based on C2W bonding in the embodiment of the application mainly comprises forming a protective layer before C2W bonding and then removing the silicon substrate. In the scheme of the application, there is no step on the wafer before bonding, the glue layer (protective layer) is uniform and no bubbles or other adverse phenomena occur by using a glue spreader; in addition, a glue sprayer is not needed, the utilization rate of photoresist is improved, and the cost of device preparation is reduced.

[0043] On the other hand, there is no step on the wafer before bonding, only one photoetching is needed, the time is shortened, the cost is reduced, and the influence of overlay accuracy on the product is not considered; in addition, a double-sided exposure machine is not needed, and the cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0045] Figure 1 A flow chart of the method for removing a silicon substrate in a chip based on C2W bonding according to an embodiment of the application;

[0046] Figure 2 A schematic diagram of depositing a waveguide layer according to an embodiment of the application;

[0047] Figure 3 A schematic diagram of forming a waveguide core according to an embodiment of the application;

[0048] Figure 4 A schematic diagram of forming a first passivation layer according to an embodiment of the application;

[0049] Figure 5 A schematic diagram of forming a metal slot according to an embodiment of the application;

[0050] Figure 6 A schematic diagram of depositing a metal according to an embodiment of the application;

[0051] Figure 7A schematic diagram of forming a metal electrode according to an embodiment of the present application;

[0052] Figure 8 A schematic diagram of forming a second passivation layer according to an embodiment of the present application

[0053] Figure 9 A schematic diagram of forming a hole structure according to an embodiment of the present application

[0054] Figure 10 A schematic diagram of forming a protection layer according to an embodiment of the present application

[0055] Figure 11 A schematic diagram of bonding according to an embodiment of the present application

[0056] Figure 12 A schematic diagram of removing a silicon substrate according to an embodiment of the present application

[0057] Figure 13 A schematic diagram of removing a protection layer according to an embodiment of the present application

[0058] Figure 14 Another schematic diagram of bonding according to an embodiment of the present application

[0059] Figure 15 Another schematic diagram of removing a silicon substrate according to an embodiment of the present application

[0060] In the figure: 1, wafer substrate; 2, waveguide layer; 3, waveguide core; 4, metal groove; 5, metal electrode; 6, hole structure; 7, protection layer; 8, electro-optical material layer; 9, silicon oxide layer; 10, silicon substrate. DETAILED DESCRIPTION

[0061] The embodiments of the present application will be described in detail with reference to the drawings, wherein:

[0062] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the scope of the present application. Although the present application has been described in detail with reference to the examples, those skilled in the art will appreciate that the application can be implemented in other ways. The design and implementation details of the present application can be modified or changed in different ways without departing from the spirit and scope of the present application. Therefore, the scope of the present application should be subject to the scope of the claims of the present application.

[0063] It is to be appreciated that various aspects described herein are described in the context of examples. It should be appreciated that the aspects described herein can be embodied in a wide variety of forms and that any specific structure and / or function described herein is merely illustrative. Based on the teachings herein one skilled in the art should appreciate that an aspect described herein can be implemented independently of any other aspects and that an aspect described herein can be implemented both as any claim dependent on another and as an independent claim. An aspect can be implemented apart from, and independent of, any other aspect or claim. One skilled in the art should appreciate that an aspect described herein can be implemented and / or fabricated during different stages of certain processes without relying on other aspects described herein. Indeed, the examples can be implemented and / or fabricated at one stage or during

[0064] It is also to be understood that the present application can be practiced with more than one type of communication media. For example, the present application can be practiced with wireless communication media, wired communication media, or both.

[0065] In addition, in the following description, numerous specific details are provided for a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the aspects described herein can be practiced without one or more of these specific details.

[0066] Embodiments of the present application provide a method for removing silicon substrate in a chip based on C2W bonding, which is described in detail below with reference to the accompanying drawings. Figures 1 to 13

[0067] In one embodiment, the method comprises:

[0068] Step S101, forming a waveguide core 3 on a substrate and depositing a first passivation layer covering the substrate and the waveguide core 3;

[0069] Step S102, forming a metal slot 4 on both sides of the waveguide core 3, and forming a metal electrode 5 in the metal slot 4;

[0070] Step S103, depositing a second passivation layer covering the metal electrode 5 and the first passivation layer;

[0071] Step S104, forming a hole structure 6 by opening a hole above the metal electrode 5;

[0072] Step S105, forming a protective layer 7 on the second passivation layer corresponding to the metal electrode 5, the protective layer 7 covering the metal electrode 5 through the hole structure 6;

[0073] ​In step S106, a region corresponding to the waveguide core 3 on the second passivation layer is bonded with a chip, and a side of the chip away from the bonded region is provided with a silicon substrate 10.

[0074] In step S107, the silicon substrate 10 in the chip is removed after bonding.

[0075] In step S108, the protective layer 7 is removed.

[0076] In the embodiment, for the removal of the silicon substrate 10, a method of forming a protective layer 7 before C2W bonding and then removing the silicon substrate 10 is proposed. In the method of the embodiment, there is no step on the wafer before bonding, and the glue layer (protective layer 7) is uniform and has no bubbles and other defects by using a glue spreader. In addition, a glue sprayer is not needed, which improves the utilization rate of photoresist and reduces the cost of device preparation. On the other hand, there is no step on the wafer before bonding, and only one photoetching is needed, which shortens the time and reduces the cost, and the impact of overlay accuracy on the product is also not considered. In addition, a double-sided exposure machine is not needed, which reduces the cost.

[0077] In specific implementation, the substrate on which the waveguide core 3 is formed is provided as a wafer substrate 1.

[0078] In one embodiment, referring to Figure 2 and Figure 3 the waveguide core 3 is formed on the substrate, which includes:

[0079] depositing a waveguide layer 2 on the substrate;

[0080] etching the waveguide layer 2 to form the waveguide core 3.

[0081] In specific implementation, the waveguide layer 2 can be provided as a SiN layer. Silicon nitride (SiN) material has many single advantages such as low loss, wide spectrum, and large optical power. Specifically, SiN has a wide transparent spectrum range from ultraviolet to mid-infrared, which makes it very suitable for different wavelength optical communication systems; in the commonly used waveband (such as 1.3 μm and 1.55 μm) of optical communication, SiN waveguide can achieve lower propagation loss, which is crucial for maintaining signal strength and reducing noise; SiN material exhibits higher nonlinear optical effects, which can more effectively respond to small amplitude electrical signal changes, thereby improving modulation efficiency and supporting high-speed data transmission; the deposition and other processing steps of SiN can be well integrated into the existing complementary metal oxide semiconductor (CMOS) microelectronic manufacturing process, which is convenient for mass production and integrated design.

[0082] Further, the thickness of the waveguide layer 2 can be set to 50-800 nm. Etching is performed on the waveguide layer 2 to form a plurality of waveguide cores 3.

[0083] In a specific implementation, the depositing the first passivation layer comprises:

[0084] depositing the first passivation layer to a first preset thickness, and performing chemical mechanical polishing (CMP) on the first passivation layer to reduce the first preset thickness to a second preset thickness, wherein the structure after the chemical mechanical polishing is shown in Figure 4 forming a first passivation layer on the waveguide core 3.

[0085] Specifically, for the first passivation layer, the first passivation layer can be a silicon oxide layer 9. The second preset thickness can be set to 50-200 nm, where the thickness refers to the thickness of the passivation layer above the waveguide core 3. The first preset thickness can be adjusted according to specific process requirements.

[0086] Further, referring to Figure 5 the metal grooves 4 are formed on both sides of the waveguide core 3, comprising:

[0087] The metal grooves 4 are formed on both sides of the waveguide core 3 by etching process, and the bottom of the metal grooves 4 extends to the inside of the substrate. Preferably, the metal grooves 4 can be set to a square structure, and the width of the metal grooves 4 is set to 20-300 μm.

[0088] In one embodiment, referring to Figure 6 and Figure 7 the metal electrodes 5 are formed in the metal grooves 4, comprising:

[0089] depositing a metal, wherein the metal covers the first passivation layer and the metal grooves 4, and the structure after the metal is deposited is shown in Figure 6

[0090] etching the metal on the first passivation layer, and the metal in the metal grooves 4 forms the metal electrodes 5.

[0091] In a specific implementation, the metal is deposited in an entire surface, so the metal grooves 4 and the upper surface of the first passivation layer are covered by the metal. The thickness of the deposited metal can be set to 0.5-1.5 μm. For the metal on the first passivation layer, the metal is needed to be removed, and only the metal in the metal grooves 4 is reserved to form the metal electrodes 5. The metal on the first passivation layer can be removed by etching process, and the structure formed is shown in Figure 7 . Figure 7 The waveguide core 3 and the metal electrodes 5 inare arranged in a spaced manner, but the arrangement manner of the waveguide core 3 and the metal electrodes 5 is not limited to that shown in the figure.

[0092] Further, for the second passivation layer, the second passivation layer can be a silicon oxide layer 9. The depositing the second passivation layer comprises:

[0093] depositing a second passivation layer to a third preset thickness, and performing chemical mechanical polishing (CMP) on the second passivation layer, so that the third preset thickness is reduced to a fourth preset thickness, and the structure after the chemical mechanical polishing is shown in Figure 8 A passivation layer is formed on the waveguide core 3.

[0094] Specifically, the fourth preset thickness can be set to 50-200 nm. Here, the thickness refers to the total thickness of the first passivation layer and the second passivation layer above the waveguide core 3. If the thickness is less than 50 nm, the bonding success rate will decrease. If the thickness is greater than 200 nm, the electro-optical material will not be able to modulate the waveguide core 3.

[0095] In an embodiment, referring to Figure 9 For the hole structure 6 formed by opening holes above the metal electrode 5, the hole structure 6 is a hole penetrating through the passivation layer above the metal electrode 5 to expose the metal electrode 5. The shape of the hole structure 6 can be set to a square or a rectangle, and the size of the hole structure 6 is in the range of 60-100 μm, that is, the length of the side of the square or the rectangle is set to 60-100 μm. When opening holes, holes can be opened above part of the metal electrode 5, so as to facilitate subsequent packaging wire bonding.

[0096] In an embodiment, the protective layer 7 can be set to photoresist or bonding glue, etc., and deposition etching or stripping process can be used. Generally, a relatively thick protective glue is needed to ensure that the protective glue is not completely consumed during etching, so as to protect the metal electrode 5 in the PIC wafer which has been opened. Therefore, the thickness of the protective glue is related to the thickness of the silicon substrate 10 which needs to be removed, and the thickness is generally set to 5-100 μm.

[0097] In specific implementation, after the whole layer of the protective layer 7 is formed, the area corresponding to the waveguide core 3 needs to be exposed to reserve the area for bonding, that is, the area corresponding to the waveguide core 3 is not provided with the protective layer 7. The whole layer of the protective layer 7 can be etched by using a photoetching process to remove the protective layer 7 above the area corresponding to the waveguide core 3, and the structure shown in Figure 10 is shown, and then direct bonding can be performed. Therefore, before bonding, there is no step on the wafer, and only one photoetching is needed, which shortens the time, reduces the cost, and also eliminates the influence of overlay accuracy on the product. In addition, a double-sided exposure machine is not needed, which reduces the cost.

[0098] In an embodiment, referring to Figure 11 bonding the area above the second passivation layer and corresponding to the waveguide core 3 and the chip, comprising:

[0099] cleaning and plasma activating the area above the second passivation layer and corresponding to the waveguide core 3 and the chip in sequence;

[0100] Pre-bonding the chip and the wafer at room temperature to form a pre-bonding device;

[0101] Annealing the pre-bonding device at 50-120℃ for 6-12h to complete the bonding.

[0102] In implementation, the size of the chip in C2W bonding is 1mm*1mm-12mm*12mm. The chip and the wafer need to be cleaned and plasma-activated before bonding, and then pre-bonded at room temperature, and annealed at 50-120℃ for 6-12h.

[0103] In one embodiment, the chip further comprises an electro-optic material layer 8 bonded to the region on the second passivation layer corresponding to the waveguide core 3, and a silicon oxide layer 9 between the electro-optic material layer 8 and the silicon substrate 10.

[0104] In implementation, the electro-optic material can be lithium niobate material with a thickness of 300-400nm, the thickness of the silicon oxide can be set to 0.5-2μm, and the thickness of the silicon substrate 10 is 500-675μm.

[0105] In one embodiment, referring to Figure 12 , the removing the silicon substrate 10 in the chip comprises:

[0106] Removing the silicon substrate 10 in the chip by a wet etching or dry etching process.

[0107] In implementation, the wet etching can use chemical liquid (such as KOH, TMAH, etc.) for wet etching, and for dry etching, for example, xenon fluoride is used for dry etching.

[0108] Further, in the process of removing the silicon substrate 10 by wet etching or dry etching, in order to protect the metal electrode 5, the thickness of the protective layer 7 needs to ensure that the metal electrode 5 is not damaged, therefore, the thickness of the protective layer 7 is set to 50-100μm.

[0109] In one embodiment, the removing the silicon substrate 10 in the chip comprises:

[0110] Grinding the silicon substrate 10 in the chip to reduce the thickness of the silicon substrate 10 to 20-40μm;

[0111] Removing the ground silicon substrate 10 by a wet etching or dry etching process.

[0112] In the embodiment, a part of the thickness of the silicon substrate 10 is removed by a grinding process, and then wet etching or dry etching is performed, so as to reduce the thickness of the protective layer 7, reduce the wet etching and dry etching time, and reduce the cost of wet etching and dry etching materials. In addition, the probability of the occurrence of micro-pyramid structure due to anisotropic etching in the wet etching process can be reduced, so as to greatly reduce the etching rate.

[0113] Further, the thickness of the protective layer 7 is 5-10 μm. Since a part of the thickness of the silicon substrate 10 is removed by the grinding process, the thickness of the silicon substrate 10 to be etched or etched is reduced, and thus the thickness of the protective layer 7 can be correspondingly reduced.

[0114] In an embodiment, the removing the silicon substrate 10 in the chip comprises:

[0115] Dry etching is performed on the silicon substrate 10 in the chip, and the thickness of the silicon substrate 10 is etched to 5-20 μm.

[0116] The remaining silicon substrate 10 is removed by a wet etching process.

[0117] For the removal of the silicon substrate 10, after only dry etching, the surface morphology of the lower silicon oxide is poor, which has an influence on the electro-optical material modulation waveguide core 3 layer. When only wet etching is used, the etching of silicon by TMAH and KOH is anisotropic, and micro-pyramid structure is prone to occur in the etching process, which will greatly reduce the etching rate. Therefore, in the embodiment, a part of the silicon substrate 10 is etched by dry etching, and then the remaining silicon substrate 10 is etched by wet etching. The method of the embodiment can improve the surface morphology of the silicon oxide after dry etching alone, and reduce the time required for wet etching alone.

[0118] In an embodiment, the thickness of the protective layer 7 is 5-100 μm. The thickness of the protective layer 7 is related to the method of removing the silicon substrate 10, and the thickness of the protective layer 7 can be adjusted according to the specific method of removing the silicon substrate 10.

[0119] In an embodiment, referring to Figure 13 , the removing the protective layer 7 comprises:

[0120] The protective layer 7 is removed by soaking in a chemical liquid, and the chemical liquid is N-methyl pyrrolidone or acetone.

[0121] In an embodiment, the processing of the protective layer 7 is complicated, and in addition, the protective layer 7 is generally made of photoresist or bonding glue. If the wet etching time is too long, there is a possibility of penetration of TMAH / KOH, and thus the bonding can be performed first, and then the hole can be opened above the metal electrode 5. Specifically, the method comprises:

[0122] After the deposition of the second passivation layer, i.e. before Figure 8 the opening of the holes above the metal electrodes 5, the region of the second passivation layer corresponding to the waveguide core 3 is bonded to the chip (C2W bonding) using the passivation layer (silicon oxide layer 9) above the metal electrodes 5 as a mask. The structure after the bonding is shown in Figure 14 Both the chip and the wafer are cleaned and plasma activated before the bonding. The pre-bonding is performed at room temperature, and the annealing is performed at 50-300°C for 1-12h, thus completing the whole bonding process.

[0123] In this embodiment, since there is no protection layer 7, the silicon substrate 10 can be removed by wet etching using chemical solutions (such as KOH, TMAH, etc.) or dry etching. The structure after the removal of the silicon substrate 10 is shown in Figure 15 .

[0124] Then, holes are opened above the metal electrodes 5, with a size of 60-100μm for subsequent packaging wire bonding. The structure after the opening of the holes is shown in Figure 13 .

[0125] In this embodiment, since the opening operation above the metal electrodes 5 is not performed before the bonding, the protection layer 7 is not needed when removing the silicon substrate 10, thus reducing the process steps. Moreover, the silicon oxide above the metal electrodes 5 has better resistance to TMAH / KOH.

[0126] The embodiments provided by the present application can solve the problem of complicated processing of the protection layer 7 by two methods. The first method is to form the protection layer 7 before the C2W bonding. Since there is no step on the wafer before the bonding, the uniformity of the glue layer is good and there are no bubbles or other defects. Moreover, the use of a spray coater is not needed, thus improving the utilization rate of the photoresist and reducing the cost. On the other hand, since there is no step on the wafer before the bonding, only one photoetching is needed, thus shortening the time and reducing the cost. Moreover, the use of a double-sided exposure machine is not needed, thus reducing the cost. The second method is to open holes above the metal electrodes 5 after the C2W bonding. By this method, the protection layer 7 is not needed when removing the silicon substrate 10, thus reducing the process steps. Moreover, the silicon oxide above the metal electrodes 5 has better resistance to TMAH / KOH.

[0127] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for removing silicon substrate from a chip based on C2W bonding, characterized in that, The method includes: A waveguide core is formed on a substrate, and a first passivation layer is deposited, the first passivation layer covering the substrate and the waveguide core; Metal grooves are formed on both sides of the waveguide core, and metal electrodes are formed in the metal grooves. A second passivation layer is deposited, which covers the metal electrode and the first passivation layer; An opening is made above the metal electrode to form a hole structure; A protective layer is formed above the second passivation layer in the region corresponding to the metal electrode, and the protective layer covers the metal electrode through the hole structure; The region above the second passivation layer corresponding to the waveguide core is bonded to the chip, and a silicon substrate is provided on the side of the chip away from the bonding region; The silicon substrate in the chip is removed after bonding. Remove the protective layer.

2. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that, The formation of the waveguide core on the substrate includes: Deposit a waveguide layer on the substrate; The waveguide layer is etched to form the waveguide core.

3. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that, The process of forming a metal electrode within the metal tank includes: Deposit metal, the metal covering the first passivation layer and the metal trench; The metal on the first passivation layer is etched, and the metal in the metal trench forms the metal electrode.

4. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that, The step of bonding the region above the second passivation layer corresponding to the waveguide core to the chip includes: The region above the second passivation layer corresponding to the waveguide core and the chip are sequentially cleaned and plasma activated. The region above the second passivation layer corresponding to the waveguide core and the chip are pre-bonded at room temperature to form a pre-bonded device. The pre-bonded device is annealed at 50-120°C for 6-12 hours to complete the bonding.

5. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that, The removal of the silicon substrate from the chip includes: The silicon substrate in the chip is removed by a wet etching or dry etching process.

6. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that, The removal of the silicon substrate from the chip includes: The silicon substrate in the chip is polished to reduce its thickness to 20-40 μm; The polished silicon substrate is removed by a wet etching or dry etching process.

7. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that, The removal of the silicon substrate from the chip includes: The silicon substrate in the chip is dry etched to a thickness of 5-20 μm; The remaining silicon substrate is removed by a wet etching process.

8. The method for removing silicon substrate from a chip based on C2W bonding according to any one of claims 5 to 7, characterized in that, The thickness of the protective layer is 5-100 μm.

9. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that, The removal of the protective layer includes: The protective layer is removed by soaking in a chemical solution, wherein the chemical solution is N-methylpyrrolidone or acetone.

10. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that, The chip further includes an electro-optic material layer and a silicon oxide layer. The electro-optic material layer is bonded to the region above the second passivation layer corresponding to the waveguide core. The silicon oxide layer is located between the electro-optic material layer and the silicon substrate.

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