A three-dimensional hall strip array, a manufacturing method and a circuit interconnection method thereof

Abstract

The application discloses a three-dimensional Hall strip array and a manufacturing method and a circuit interconnection method thereof. A plurality of electrode pieces in a specific arrangement form, a magnetic multilayer film connected with the electrode pieces and an insulating layer with good fluidity at high temperature are prepared on a silicon-based integrated circuit in sequence. A Hall strip connected with the electrode pieces and the insulating layer and the metal electrode part above the Hall strip are reserved. The magnetic multilayer film and the insulating layer are etched to form a Hall strip structure, and the insulating layer is made to flow and cover the film edge through heat treatment. The magnetic multilayer film and the insulating layer connected with the next group of electrodes and slightly larger in size are regrown, and the above steps are repeated to obtain a plurality of stacked Hall strip structures connected with different groups of electrodes in sequence, so that the three-dimensional Hall strip array is realized. Each layer of the Hall strip structure can be closely interconnected with the integrated circuit through the electrode piece. The three-dimensional Hall strip array obtained by the application can be used in storage and calculation integrated computing, and a storage and calculation integrated chip with high integration is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and relates to a three-dimensional structure of a device and a manufacturing method thereof, in particular to a three-dimensional Hall bar array, a manufacturing method thereof and a circuit interconnection method. BACKGROUND

[0002] In a traditional computer system, the storage unit and the computing unit are separated, resulting in a "memory wall" and a "power wall" between the CPU and the memory, which limits the improvement of computer performance. The Hall bar is a new type of magnetic electronic device with storage and computing functions, which can be used to realize the integration of computing and storage chips, and is expected to reduce the power consumption caused by data transfer and greatly improve the performance of computers.

[0003] However, the Hall bar array in the prior art is mostly two-dimensional structure, and the manufacturing process is very limited, and the size of the finished Hall bar array can only reach microns. Compared with the nanometer process of other types of memory chips, the Hall bar array is obviously lagging behind in area and integration. Therefore, it is urgent to propose a new Hall bar array structure and a manufacturing method to reduce the size of the finished product. SUMMARY

[0004] In view of the deficiencies of the prior art, the present application proposes a three-dimensional Hall bar array, a manufacturing method thereof and a circuit interconnection method, which realizes a high-integration storage and computing integrated chip through a three-dimensional structure design, reduces the array area and the array wiring complexity, and overcomes the shortcomings of the two-dimensional Hall bar when applied to the manufacturing of the storage and computing integrated chip.

[0005] A three-dimensional Hall bar array includes n stacked Hall bar structures, n≥2.

[0006] The Hall bar structure from bottom to top is an electrode, a cross-shaped magnetic multilayer film and an insulating layer wrapped outside the magnetic multilayer film. The electrode includes an input electrode and an output electrode, wherein the input electrode is arranged at the two ends symmetrical to the cross-shaped magnetic multilayer film, and the output electrode is arranged at the other two ends. The electrodes of the n Hall bar structures are arranged in a specific manner and are located on the same integrated circuit surface and connected to the internal circuit of the integrated circuit. The electrodes of different Hall bar structures are parallel to each other and do not overlap in position. The size of the cross-shaped magnetic multilayer film in the Hall bar structure from bottom to top gradually increases.

[0007] The electrodes of the Hall bar structure are connected to the internal circuit interface through the via hole, the input electrode is perpendicular to the cross-shaped multilayer film port connected thereto, and the two input electrodes are parallel to each other and have opposite directions; the output electrode is perpendicular to the cross-shaped multilayer film port connected thereto, and the two output electrodes are parallel to each other and have opposite directions.

[0008] As preferred, the cross-shaped magnetic multilayer film is sequentially from bottom to top: a bottom metal isolation layer, a heavy metal layer, a ferromagnetic layer and a top metal isolation layer.

[0009] As preferred, the bottom metal isolation layer is Ta with a thickness of 2 nm, the heavy metal layer is Pt with a thickness of 5 nm, the ferromagnetic layer is Co / Pt stack structure with a thickness of 1 nm Co and a thickness of 0.3 nm Pt, and the top metal isolation layer is Ta with a thickness of 3 nm.

[0010] As preferred, the insulating layer of the topmost Hall bar structure is used to prevent oxidation of the three-dimensional Hall bar array, and the insulating layer in the remaining Hall bar structures is used to prevent short circuit or electromagnetic interference between the Hall bar structures.

[0011] A method for manufacturing and circuit interconnection of a three-dimensional Hall bar array, specifically comprising the following steps:

[0012] Step 1: growing n electrode groups on the surface of a silicon-based integrated circuit, each electrode group including 4 electrode pieces distributed on the 4 vertices of a cross, and the electrode pieces at the same vertex of the cross in different electrode groups are parallel to each other and do not overlap in position. From the center of the cross outward, they are the 1st to the nth electrode groups.

[0013] Step 2: using magnetron sputtering to prepare a first magnetic multilayer film interconnected with the first electrode group on the surface of the silicon-based integrated circuit, and then growing a first insulating layer on the first magnetic multilayer film.

[0014] Step 3: taking the position of the first electrode group as an endpoint, etching the first magnetic multilayer film and the first insulating layer prepared in step 2 into a cross-shaped structure, and in the etching process, the first electrode group, the first magnetic multilayer film and the first insulating layer on the surface thereof are retained, and then the first insulating layer is heat treated to flow and wrap around the edges of the first magnetic multilayer film and the edges of the first electrode group below, and a flat surface is obtained, obtaining a first Hall bar.

[0015] Step 4: using magnetron sputtering to prepare a second magnetic multilayer film interconnected with the second electrode group on the first Hall bar, and the size of the second magnetic multilayer film is slightly larger than that of the first magnetic multilayer film, then growing a second insulating layer on the second magnetic multilayer film, and then taking the position of the second electrode group as an endpoint, etching the second magnetic multilayer film and the second insulating layer, and in the etching process, the second electrode group, the second magnetic multilayer film and the second insulating layer on the surface thereof are retained, and then the second insulating layer is heat treated to flow and wrap around the edges of the second magnetic multilayer film and the edges of the second electrode group below, and a flat surface is obtained, obtaining a second Hall bar.

[0016] Step 5, and so on until a three-dimensional Hall strip array with n layers of Hall strips is obtained.

[0017] Preferably, the insulating layer is a solid insulating material with good fluidity at high temperature, which can soften and flow after heat treatment to wrap the surface of the magnetic multilayer film and obtain a flat surface.

[0018] The present application has the following advantages:

[0019] The three-dimensional Hall strip array designed in the present application has a smaller footprint than the existing two-dimensional structure, which can improve the integration level of the compute-in-memory circuit. The electrode group is grown on the surface of the silicon-based integrated circuit, and the three-dimensional Hall strip array is fabricated, which can realize close interconnection with the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A schematic diagram of the three-dimensional Hall strip array in the embodiment is shown.

[0021] Figure 2 A schematic diagram of the three-dimensional Hall strip array in the embodiment is shown.

[0022] Figure 3 A schematic diagram of the magnetic multilayer film in the embodiment is shown. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the present application will be further described below in combination with the drawings in the embodiment of the present application. Clearly, the following described embodiments are only a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0024] In the description of the present application, it should be understood that the terms "upper", "lower", "peripheral", "apex", "surface" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0025] As shown in Figure 1 A three-dimensional Hall strip array includes 2 layers of Hall strip structures.

[0026] The first Hall bar structure 2 comprises first and second input electrodes 4 and 5, first and second output electrodes 6 and 7, a first cross-shaped magnetic multilayer film connected to the electrodes, and a first insulating layer covering the surface of the first cross-shaped magnetic multilayer film. The first and second input electrodes 4 and 5 are located at two non-adjacent ends of the first cross-shaped magnetic multilayer film, and the first and second output electrodes 6 and 7 are located at the other two ends.

[0027] The second Hall bar structure 3 comprises third and fourth input electrodes 8 and 9 and third and fourth output electrodes 10 and 11 grown on the surface of the silicon-based integrated circuit 1 and outside the first Hall bar structure 2, a second cross-shaped magnetic multilayer film connected to the electrodes, and a second insulating layer covering the surface of the second cross-shaped magnetic multilayer film. The third and fourth input electrodes 8 and 9 are located at two non-adjacent ends of the second cross-shaped magnetic multilayer film, and the third and fourth output electrodes 10 and 11 are located at the other two ends. The third and fourth input electrodes 8 and 9 are parallel to the first and second input electrodes 4 and 5, respectively, and the third and fourth output electrodes 10 and 11 are parallel to the first and second output electrodes 6 and 7, respectively.

[0028] The first insulating layer is grown on the surface of the first cross-shaped magnetic multilayer film and can flow to cover the edges of the first cross-shaped magnetic multilayer film through heat treatment, thereby insulating and protecting the first cross-shaped magnetic multilayer film and obtaining a flat surface for subsequent layering of the Hall bar structure. In addition, the first insulating layer can prevent electromagnetic interference between the first cross-shaped magnetic multilayer film and the second cross-shaped magnetic multilayer film and avoid short circuiting due to external excitation during interconnection of the three-dimensional Hall bar array and the integrated circuit. The second insulating layer is grown on the surface of the second cross-shaped magnetic multilayer film and can prevent oxidation of the entire three-dimensional Hall bar array in addition to insulating and protecting the second cross-shaped magnetic multilayer film.

[0029] The electrodes of different Hall bar structures are parallel to each other and maintain a certain distance, and the insulating layer between different Hall bar structures plays an insulating protection role, thereby achieving interconnection of the Hall bar array and the integrated circuit while preventing magnetic interaction between adjacent Hall bar devices and short circuiting when an external excitation is applied.

[0030] A method for manufacturing and circuit interconnection of a three-dimensional Hall bar array, specifically comprising the following steps:

[0031] Step 1: Grow a first electrode group and a second electrode group on the silicon-based integrated circuit 1. The first electrode group includes first and second input electrodes 4 and 5, and first and second output electrodes 6 and 7, distributed at the four vertices of the cross-shaped structure. The second electrode group includes third and fourth input electrodes 8 and 9, which are parallel to the first and second input electrodes 4 and 5, respectively, and third and fourth output electrodes 10 and 11, which are parallel to the first and second output electrodes 6 and 7, respectively. Both electrode groups are connected to the internal components of the integrated circuit.

[0032] Step 2: On the silicon-based integrated circuit 1, a first magnetic multilayer film 12 interconnected with the first and second input electrodes 4 and 5, and the first and second output electrodes 6 and 7 is fabricated by magnetron sputtering, as shown below. Figure 2 As shown. The magnetic multilayer film, from bottom to top, consists of: a bottom metal isolation layer, a heavy metal layer, a ferromagnetic layer, and a top metal isolation layer. The bottom metal isolation layer is made of Ta with a thickness of 2 nm, the heavy metal layer is made of Pt with a thickness of 5 nm, the ferromagnetic layer is a Co / Pt stacked structure with a thickness of 1 nm and a thickness of 0.3 nm, and the top metal isolation layer is made of Ta with a thickness of 3 nm. Then, a first insulating layer 13 is grown on the first magnetic multilayer film 12. The insulating layer is made of a solid insulating material with good fluidity at high temperatures, such as phosphosilicate glass.

[0033] Step 3: Using the positions of the four electrodes as endpoints, apply adhesive, expose, develop, etch, and remove the adhesive from the first magnetic multilayer film 12 and the first insulating layer 13 prepared in Step 2. Then, soften and flow the first insulating layer 13 through heat treatment, thereby wrapping the edge of the first magnetic multilayer film 12 and obtaining a flat surface, forming the first Hall strip structure 2.

[0034] Step 4: On the first Hall strip structure 2, a second magnetic multilayer film 14 is fabricated by magnetron sputtering to interconnect with the third and fourth input electrodes 8 and 9 and the third and fourth output electrodes 10 and 11. Since the four electrodes are located on the periphery of the first Hall strip structure 2, the area of ​​the second magnetic multilayer film 14 should be slightly larger than that of the first magnetic multilayer film 12 to achieve interconnection with the electrodes. Then, a second insulating layer 15 is grown on the second magnetic multilayer film 14. Using the locations of the four electrodes as endpoints, etching and heat treatment are performed to obtain the second Hall strip structure 3. This completes a three-dimensional Hall strip array with two stacked Hall strip structures. Furthermore, the electrodes of this three-dimensional Hall strip array are directly formed on the surface of the silicon-based integrated circuit and connected to the circuit interface, enabling direct and tight interconnection between the three-dimensional Hall strip array and the integrated circuit.

[0035] The technical solution of the present invention has been described above based on the preferred embodiments shown. However, the scope of protection of the present invention is not limited to these specific embodiments. Any substitutions, modifications, and improvements conceived by those skilled in the art within the principles of the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A three-dimensional Hall strip array, characterized in that: It includes n stacked Hall strip structures, where n=2; The Hall strip structure, from bottom to top, consists of electrodes, a cross-shaped magnetic multilayer film, and an insulating layer wrapped around the outer surface of the magnetic multilayer film. The electrodes include input electrodes and output electrodes, with the input electrodes located at the two symmetrical ends of the cross-shaped magnetic multilayer film and the output electrodes located at the other two ends. The electrodes of the n Hall strip structures are all located on the same integrated circuit surface and connected to the inside of the integrated circuit. The electrodes of different Hall strip structures are parallel to each other and do not overlap. The size of the cross-shaped magnetic multilayer film in the Hall strip structure gradually increases from bottom to top. The electrodes of the Hall strip structure are connected to the internal interface of the circuit through vias. In the Hall strip structure, the input electrode is perpendicular to the cross-shaped multilayer film port connected to it, and the two input electrodes are parallel to each other and have opposite lead-out directions. The output electrode is perpendicular to the cross-shaped multilayer film port connected to it, and the two output electrodes are parallel to each other and have opposite lead-out directions. The cross-shaped magnetic multilayer film consists of, from bottom to top: a bottom metal isolation layer, a heavy metal layer, a ferromagnetic layer, and a top metal isolation layer.

2. The three-dimensional Hall strip array as described in claim 1, characterized in that: The bottom metal isolation layer is made of Ta with a thickness of 2nm, the heavy metal is made of Pt with a thickness of 5nm, the ferromagnetic layer is made of Co / Pt stacked structure with a thickness of 1nm and a thickness of 0.3nm, and the top metal isolation layer is made of Ta with a thickness of 3nm.

3. The three-dimensional Hall strip array as described in claim 1, characterized in that: The insulating layer of the topmost Hall strip structure is used to prevent oxidation of the entire three-dimensional vertically stacked Hall strip structure; the insulating layers in the remaining Hall strip structures are used to prevent short circuits or electromagnetic interference between Hall strip structures.

4. A method for fabricating a three-dimensional Hall bar array, characterized in that: This method is used to fabricate a three-dimensional Hall bar array as described in any one of claims 1 to 3, and specifically includes the following steps: Step 1: Grow two electrode groups on the surface of a silicon-based integrated circuit. Each electrode group includes four electrode sheets distributed at the four vertices of a cross shape. The electrode sheets located at the same vertex of the cross shape in different electrode groups are parallel to each other and their positions do not overlap. From the center of the cross shape outwards, they are the first and second electrode groups. Step 2: On the surface of a silicon-based integrated circuit, a first magnetic multilayer film interconnected with the first electrode group is prepared by magnetron sputtering, and then a first insulating layer is grown on the first magnetic multilayer film. Step 3: Using the location of the first electrode group as the endpoint, etch the first magnetic multilayer film and the first insulating layer prepared in step 2 into a cross-shaped structure. During the etching process, retain the first electrode group, the first magnetic multilayer film and the first insulating layer on its surface. Then, heat-treat the first insulating layer to make it flow and wrap around the edge of the first magnetic multilayer film and obtain a flat surface, thus obtaining the first Hall strip. Step 4: On the first Hall bar, a second magnetic multilayer film interconnected with the second electrode group is prepared by magnetron sputtering. Then, a second insulating layer is grown on the second magnetic multilayer film. Then, the second magnetic multilayer film and the second insulating layer are etched with the position of the second electrode group as the endpoint. During the etching process, the second electrode group, the second magnetic multilayer film and the second insulating layer on its surface are retained. Then, the second insulating layer is heat-treated to wrap around the outer surface of the second magnetic multilayer film to obtain the second Hall bar. Thus, a three-dimensional Hall bar array with two Hall bars stacked is obtained, and the electrode plates on the four ports of each Hall bar are connected to the internal interface of the silicon-based integrated circuit.

5. The method for fabricating a three-dimensional Hall bar array as described in claim 4, characterized in that: The insulating layer is a material that is fluid at high temperatures. After heat treatment, it can soften and flow to wrap around the edge of the magnetic multilayer film.

6. The method for fabricating a three-dimensional Hall bar array as described in claim 4, characterized in that: The insulating layer is made of phosphosilicate glass.

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