Optical signal blocker for photonic chips

Abstract

The invention relates to an optical signal blocker for a photonic chip. A structure for a photonic chip including an optical signal blocker and a method of forming such a structure. The structure includes a semiconductor substrate, an optical signal blocker including a first metal sheet and a plurality of openings in the first metal sheet, and a waveguide core between the semiconductor substrate and the optical signal blocker. The waveguide core includes a portion overlapping the optical signal blocker.

Description

Technical Field

[0001] This disclosure relates to photonic chips, and more specifically to the structure of a photonic chip including an optical signal blocker and a method for forming such a structure. Background Technology

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication systems and data computing systems. A photonic chip includes a photonic integrated circuit that incorporates photonic components, such as modulators, polarizers, and couplers, for manipulating light received from a light source (e.g., an optical fiber or laser).

[0003] An edge coupler (also known as a spot size converter) is a type of photonic device commonly used to couple light of a given mode from a light source to a photonic integrated circuit. An edge coupler may include a portion of a waveguide core defining an inverse taper with a pointed tip. The narrow end of the inverse taper at the tip is positioned adjacent to the light source. The wide end of the inverse taper is connected to another portion of the waveguide core that guides and routes the light to the photonic integrated circuit.

[0004] As light travels from the light source to the edge coupler, the gradual change in the cross-sectional area of ​​the inverted cone supports the mode transformation and mode size variation associated with mode conversion. Initially, the inverted cone cannot fully confine the incident mode received from the light source because the cross-sectional area of ​​the tip is significantly smaller than the mode size. Therefore, a considerable proportion of the electromagnetic field of the incident mode is distributed around the tip of the inverted cone. As the width of the inverted cone increases, it eventually becomes able to support the entire incident mode.

[0005] Multi-project wafer services allow for the fabrication of multiple photonic integrated circuit designs for different customers on a single wafer. This provides a cost-effective mechanism for customers with smaller projects or research efforts to access manufacturing facilities without incurring the full cost of a complete set of masks. While the wafer is being shipped to a particular customer, macros or designs for other customers may be accessible.

[0006] There is a need for improved structures for photonic chips, including optical signal blockers, and methods for forming such structures. Summary of the Invention

[0007] In an embodiment of the present invention, a structure for a photonic chip is provided. The structure includes: a semiconductor substrate; an optical signal blocker including a metal sheet and a first plurality of openings located in the first metal sheet; and a waveguide core located between the semiconductor substrate and the optical signal blocker. The waveguide core includes a portion overlapping the optical signal blocker.

[0008] In an embodiment of the present invention, a structure for a photonic chip is provided. The structure includes: a semiconductor substrate; an optical signal blocker including a plurality of metallic features; and a waveguide core located between the semiconductor substrate and the optical signal blocker. The waveguide core includes a portion overlapping with the optical signal blocker.

[0009] In an embodiment of the present invention, a method for forming a structure for a photonic chip is provided. The method includes: forming a waveguide core; and forming an optical signal blocker, the optical signal blocker including a metal sheet and a plurality of openings located in the metal sheet. The waveguide core is disposed between a semiconductor substrate and the optical signal blocker, and the waveguide core includes a portion overlapping the optical signal blocker. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, the same reference numerals denote the same features in the various views.

[0011] Figure 1 This is a top view of the structure of the initial manufacturing stage of the processing method according to an embodiment of the present invention.

[0012] Figure 1A It is roughly along Figure 1 The cross-sectional view taken from line 1A-1A in the diagram.

[0013] Figure 2 Is Figure 1 , 1A A top view of the structure during the manufacturing stage of the subsequent processing methods.

[0014] Figure 2A It is roughly along Figure 2 The cross-sectional view taken from line 2A-2A in the diagram.

[0015] Figure 3 Is Figure 2 , 2A A top view of the structure during the manufacturing stage of the subsequent processing methods.

[0016] Figure 3A It is roughly along Figure 3 The cross-sectional view taken from line 3A-3A in the diagram.

[0017] Figure 4 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0018] Figure 5 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0019] Figure 6 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0020] Figure 7 This is a top view of the structure according to an alternative embodiment of the present invention.

[0021] Figure 7A It is roughly along Figure 7 The cross-sectional view taken from line 7A-7A in the diagram. Detailed Implementation

[0022] refer to Figure 1 , 1A According to an embodiment of the present invention, the structure 10 for a photonic chip includes a waveguide core 12 located on and above dielectric layers 14, 16, and a semiconductor substrate 18. In an embodiment, dielectric layers 14 and 16 may be made of a dielectric material such as silicon dioxide, and the semiconductor substrate 18 may be made of a semiconductor material such as monocrystalline silicon. The waveguide core 12 is separated from the semiconductor substrate 18 by the dielectric material of the intermediate dielectric layers 14 and 16, which serve as low-refractive-index claddings between the waveguide core 12 and the semiconductor substrate 18. In an alternative embodiment, dielectric layer 16 may be omitted, such that only dielectric layer 14 is positioned between the waveguide core 12 and the semiconductor substrate 18.

[0023] In one embodiment, the waveguide core 12 may be made of a material having a refractive index greater than that of silicon dioxide. In another embodiment, the waveguide core 12 may be made of a dielectric material such as silicon nitride. In an alternative embodiment, the waveguide core 12 may be made of different dielectric materials such as silicon oxynitride or aluminum nitride. In an alternative embodiment, the waveguide core 12 may be made of a semiconductor material such as monocrystalline silicon, amorphous silicon, or polycrystalline silicon. In an alternative embodiment, other materials such as group III-V compound semiconductors or polymers may be used to form the waveguide core 12.

[0024] In one embodiment, the waveguide core 12 can be formed by patterning a layer using photolithography and etching processes. In another embodiment, an etching mask can be formed over the layer to be patterned using photolithography, and the unmasked portion of the layer can be etched away using etching. The masked portion of the layer determines the patterned shape of the waveguide core 12. In another embodiment, the waveguide core 12 can be formed by patterning a deposited layer made of its constituent material (e.g., silicon nitride). In an alternative embodiment, the waveguide core 12 can be formed by patterning a semiconductor material (e.g., single-crystal silicon) of a device layer on a silicon-on-insulator substrate, in which the underlying dielectric layer 14 is a buried oxide layer, and the dielectric layer 16 is omitted. In an alternative embodiment, the waveguide core 12 can be a rib waveguide or a slot waveguide, rather than a ridge waveguide as in the representative embodiment.

[0025] Waveguide core 12 may include a longitudinal axis 21, a tapered portion 20 configured to serve as an edge coupler 24, and a width dimension W1. Waveguide core 12 has a cross-sectional profile defined by the width dimension W1 and its thickness. The width dimension W1 and the cross-sectional profile may vary along the length of the tapered portion 20. Waveguide core 12 terminates at a facet 26; more specifically, the width dimension W1 and the cross-sectional profile of waveguide core 12 narrow along the length of the tapered portion 20, with the width dimension being narrowest at facet 26. The tapered portion 20 of waveguide core 12 can be connected to a photonic integrated circuit of a photonic chip via a portion 22 of waveguide core 12, allowing access from a light source 44, such as an optical fiber or laser, at facet 26. Figure 3 The waveguide core 12 receives light and transmits it to the photonic integrated circuit via the edge coupler 24. The portion 22 of the waveguide core 12 can have a constant width dimension W1 and cross-sectional profile. The mode evolution of light propagating through the tapered portion 20 of the edge coupler 24 can be adiabatic or substantially adiabatic because the changes in the width dimension W1 and associated cross-sectional profile of the tapered portion 20 are slow and smooth enough that coupling and radiation losses to other modes are negligible or below operationally acceptable levels.

[0026] refer to Figure 2 , 2A The same reference numerals refer to Figure 1 , 1A The same features are present in the waveguide core 12, and in subsequent manufacturing stages, a dielectric layer 30 can be formed over the waveguide core 12. The dielectric layer 30 can be made of a dielectric material such as silicon dioxide that has been deposited and planarized. The edge coupler 24 can be fully embedded in the dielectric layer 30, which provides a low refractive index cladding.

[0027] A back-end process stack 32 can be formed above structure 10. The back-end process stack 32 may include a metallization layer having a dielectric layer 34 made of a dielectric material (e.g., silicon dioxide, silicon nitride, tetraethyl silicon silicate, or tetraethyl fluorinated silicon silicate). The back-end process stack 32 may include multiple metallization layers, including dielectric layers in a layer stack disposed above the dielectric layer 30.

[0028] An optical signal blocker 36 can be formed in a metallization layer of a back-end process stack 32 including a dielectric layer 34. The optical signal blocker 36 overlaps with a portion of the waveguide core 12 disposed between the optical signal blocker 36 and the semiconductor substrate 18. In an embodiment, the optical signal blocker 36 may overlap with a portion of a portion 22 of the waveguide core 12. In an embodiment, the metallization layer including the dielectric layer 34 and the optical signal blocker 36 may be the metallization layer closest to the waveguide core 12. In an alternative embodiment, the metallization layer including the dielectric layer 34 and the optical signal blocker 36 may not be the closest to the waveguide core 12, and an additional dielectric layer associated with one or more intermediate metallization layers of the back-end process stack 32 may be positioned between the optical signal blocker 36 and the waveguide core 12. The optical signal blocker 36 has a width dimension W2 greater than the width dimension W1 of the waveguide core 12, which allows the optical signal blocker 36 to fully overlap with a portion of the waveguide core 12.

[0029] In an embodiment, the optical signal blocker 36 may be a sheet 42 including a plurality of openings 40 distributed within the outer periphery of the sheet 42. The openings 40 extend through the sheet 42 as perforations. In an embodiment, the sheet 42 may be planar and have a uniform thickness, and the openings 40 may extend completely through the sheet 42 as perforations. In an embodiment, the sheet 42 of the optical signal blocker 36 may have a planar lower surface facing the waveguide core 12 and a planar upper surface facing away from the waveguide core 12, and each opening 40 may extend from the planar upper surface to the planar lower surface. In an embodiment, the openings 40 in the sheet 42 may be patterned. In an embodiment, the openings 40 in the sheet 42 may be distributed in rows and columns of a two-dimensional array. In an embodiment, the sheet 42 may be centered above the overlapping portion of the waveguide core 12.

[0030] The perforated sheet 42 of the optical signal blocker 36 can be made of metal (e.g., copper or aluminum). A metallization layer including the dielectric layer 34 and the optical signal blocker 36 can be formed using a damascene process employing deposition, polishing, photolithography, and etching techniques. Specifically, the dielectric layer 34 can be deposited and patterned using photolithography and etching processes to define trenches filled with planar metal (e.g., copper or aluminum) to define the optical signal blocker 36. In an embodiment, the opening 40 can have a rectangular or square shape when viewed from a perspective perpendicular to the semiconductor substrate 18. In an alternative embodiment, the opening 40 can have a non-rectangular shape when viewed from a perspective perpendicular to the semiconductor substrate 18. In an embodiment, the opening 40 in the sheet 42 can have a critical size greater than or equal to 1 micrometer. In an embodiment, the opening 40 in the sheet 42 can have a critical size in the range of 1 micrometer to 10 micrometers.

[0031] In this embodiment, the overlapping portions of the waveguide core 12, particularly the overlapping portions of the segments 22 of the waveguide core 12, can be laterally positioned between rows of adjacent pairs of openings 40. The distance D between the plate 42 of the optical signal blocker 36 and the overlapping portions of the waveguide core 12 is selected such that the optical signal blocker 36 can block and absorb light propagating from the edge coupler 24 to the photonic integrated circuit, and / or block and absorb light propagating from the photonic integrated circuit to the edge coupler 24. Light can interact with electrons in the metal of the plate 42 of the optical signal blocker 36 via a plasma mechanism to block and absorb propagating light.

[0032] In an embodiment, the density of the openings 40 in the sheet 42 (i.e., the ratio of solid material to opening space) can be less than or equal to 0.5 to optimize the light-blocking capability of the optical signal blocker 36. The optical signal blocker 36 can provide high light absorption over a short length range, thus featuring a compact footprint. Compared to a solid sheet, the optical signal blocker 36 also features improved manufacturability due to the presence of openings 40 through the sheet 42.

[0033] In an alternative embodiment, the optical signal blocker 36 can be deployed over different types of photonic devices. Specifically, the optical signal blocker 36 can be deployed over passive photonic devices or active photonic devices.

[0034] refer to Figure 3 , 3A The same reference numerals refer to Figure 2 , 2AThe same features are present in the back-end stack 32, which can be formed above the metallization layer including the optical signal blocker 28 in subsequent manufacturing stages. The additional metallization layer may include a stack of dielectric layers 45, 46 located above the dielectric layer 34. The dielectric layer 48 may be formed to replace a removed portion of the back-end stack 32 directly above the edge coupler 24. The dielectric layer 48 may be made of a uniform dielectric material (e.g., silicon dioxide).

[0035] The light source 50 may be positioned adjacent to the facet 26 of the edge coupler 24. The light source 50 may include a light output 52 aligned with the facet 26 of the edge coupler 24 and configured to provide light in a mode propagation direction toward the facet 26 of the edge coupler 24. In an embodiment, the light source 50 may be an optical fiber, such as a single-mode fiber, including a tip portion positioned adjacent to the facet 26 of the edge coupler 24. An optical signal blocker 36 blocks the passage of light between the light source 50 and the photonic integrated circuit.

[0036] In an alternative embodiment, light source 50 may be a laser chip including a semiconductor laser configured to output light in the infrared wavelength range from light output 52. In an embodiment, the laser chip may include a laser made of a III-V compound semiconductor material. In an embodiment, the laser chip may include an indium phosphide / indium gallium arsenide phosphide laser configured to generate continuous laser light in the infrared wavelength range. In an alternative embodiment, light source 50 may include a photonic bump having an internal steering mirror and an internal lenticular mirror that cooperate to collimate and focus light received from the optical fiber and provide the collimated, focused light to the edge coupler 24.

[0037] Optical signal blocker 36 can be used to selectively block one or more optical inputs and outputs on a photonic chip, and thus prevent light transmission to certain photonic components on the photonic chip and / or prevent light transmission from certain photonic components on the photonic chip. Optical signal blocker 36 can be deployed in a photonic chip of a wafer manufactured by a multi-project wafer service, which includes photonic chips manufactured on wafers for different customers. Light blocking of selected optical inputs and outputs of the photonic chip can be used to ensure proprietary photonic components for different customers by making macros or designs unavailable for different customers. Optical signal blocker 36 can also be used in photonic integrated circuits to prevent stray light effects and / or to absorb light in selected optical paths.

[0038] refer to Figure 4Furthermore, according to an alternative embodiment, the optical signal blocker 36 can be laterally shifted so that the openings 40 in the sheet 42 are aligned with the waveguide core 12 in an overlapping relationship. In this embodiment, the openings 40 aligned with the waveguide core 12 can be arranged in a row. The alignment of the waveguide core 12 with the openings 40 can reduce the amount of metal directly above and aligned with the waveguide core 12.

[0039] refer to Figure 5 Furthermore, according to an alternative embodiment, the optical signal blocker 36 can be displaced upwards, such that the optical signal blocker 36 is formed in a metallization layer associated with the dielectric layer 45 instead of in a metallization layer associated with the dielectric layer 34. The upward displacement of the optical signal blocker 36 can increase the distance D, which can introduce additional thickness of dielectric material between the overlapping portion of the waveguide core 12 and the optical signal blocker 36.

[0040] refer to Figure 6 Furthermore, according to an alternative embodiment, the optical signal blocker 36 may further include another piece 43 having an opening 41, which is formed in another metallization level of the back-end process stack 32. The opening 41 in piece 43 is similar to or the same as the opening 40 in piece 42. Piece 42 may be vertically disposed between the overlapping portion of piece 43 and waveguide core 12. In an embodiment, the opening 41 in piece 43 may overlap with the opening 40 in piece 42. In an embodiment, the opening 41 in piece 43 may not overlap with the opening 40 in piece 42. The presence of multiple pieces 42, 43 can enhance and strengthen the ability of the optical signal blocker 36 to block and absorb light propagating in the waveguide core 12, and thus prevent light from being transmitted to certain photonic components on the photonic chip and / or prevent light from being transmitted from certain photonic components on the photonic chip.

[0041] refer to Figure 7 , 7A According to an alternative embodiment, the optical signal blocker 36 may include a pattern of metal features 60 overlapping a portion of the waveguide core 12. In an embodiment, the metal features 60 of the optical signal blocker 36 may be arranged in rows and columns of a two-dimensional array. In an embodiment, the metal features 60 in each row of the array may have a uniform pitch. In an embodiment, the metal features 60 in each column of the array may have a uniform pitch. In an embodiment, one of the rows of metal features 60 may be aligned with the overlapping portion of the waveguide core 12. In an embodiment, the overlapping portion of the waveguide core 12 may be laterally positioned between adjacent pairs of rows of metal features 60. The metal features 60 of the optical signal blocker 36 effectively block and absorb light propagating in the waveguide core 12, and thus prevent light from being transmitted to certain photonic components on the photonic chip and / or prevent light from being transmitted from certain photonic components on the photonic chip.

[0042] The metal feature 60 may be formed in a pattern opposite to that of the opening 40 in the wafer 42. In an embodiment, the metal feature 60 may be square or rectangular when viewed from a perspective perpendicular to the semiconductor substrate 18. In an embodiment, the metal feature 60 may be circular or elliptical when viewed from a perspective perpendicular to the semiconductor substrate 18. In an embodiment, the metal feature 60 may have a uniform size. In an alternative embodiment, the optical signal blocker 36 may include an array of additional metal features formed in the metallization layers of the back-end process stack 32 above the metal feature 60.

[0043] The metallic feature 60 can be sized and positioned with a sufficiently small grating pitch to define a subwavelength grating that does not radiate or reflect light of the operating wavelength. For example, the periodicity of the metallic feature 60 can be less than half the wavelength of light propagating in the waveguide core 12. The dielectric material of the dielectric layer 34 is positioned in the space between the metallic features 60 such that a metamaterial structure can be defined, wherein the material constituting the metallic feature 60 has a higher refractive index than the dielectric material of the dielectric layer 34. The metamaterial structure can be considered as a homogeneous material with an effective refractive index between that of the material constituting the metallic feature 60 and the refractive index of the dielectric material constituting the dielectric layer 34.

[0044] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. The chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of intermediate or final products. The final product can be any product that includes integrated circuit chips, such as a computer product with a central processing unit or a smartphone.

[0045] References to terms modified by approximate language such as “approximately,” “about,” or “substantially” are not limited to the specified exact values ​​or conditions. In embodiments, approximate language may indicate a range of + / -10% of the value or condition.

[0046] The use of terms such as “vertical” and “horizontal” in this document is by way of example rather than limitation, in order to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to directions in the frame of reference perpendicular to the horizontal plane just defined. The term “lateral” refers to a direction within the horizontal plane in the frame of reference.

[0047] A feature that is “connected” or “coupled” to or with another feature can be directly connected or coupled to that other feature, or alternatively, one or more intermediate features may exist. If no intermediate feature exists, a feature can be “directly connected” or “directly coupled” to or with another feature. If at least one intermediate feature exists, a feature can be “indirectly connected” or “indirectly coupled” to or with another feature. A feature that is “on” or “in contact” with another feature can be directly on or in direct contact with that other feature, or alternatively, one or more intermediate features may exist. If no intermediate feature exists, a feature can be “directly” on or in direct contact with another feature. If at least one intermediate feature exists, a feature can be “indirectly” on or indirectly in contact with another feature. If a feature extends over and covers a portion of another feature, the different features can “overlap.”

[0048] The description of various embodiments of the present invention is given for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements relative to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a photonic chip, the structure comprising: a semiconductor substrate; an optical signal blocker comprising a first metal sheet and a first plurality of openings in the first metal sheet; and a waveguide core between the semiconductor substrate and the optical signal blocker, the waveguide core comprising a first portion overlapping the optical signal blocker. the first plurality of openings are arranged in a two-dimensional array having a plurality of rows and a plurality of columns.

2. The structure of claim 1, wherein, one of the rows overlaps the first portion of the waveguide core.

3. The structure of claim 2, wherein, the first portion of the waveguide core is positioned laterally between adjacent pairs of rows.

4. The structure of claim 2, wherein, the first metal sheet comprises copper or aluminum and the waveguide core comprises silicon nitride.

5. The structure of claim 1, wherein, the waveguide core comprises a second portion adjacent the first portion, the second portion terminating at a facet, and the structure further comprises:

6. The structure of claim 1, wherein, a light source adjacent the facet, the light source having a light output configured to provide light in a mode propagation direction toward the facet. the light source is an optical fiber.

7. The structure of claim 6, wherein, 8. The structure of claim 1, further comprising: a back end of line stack on the semiconductor substrate, wherein the first metal sheet of the optical signal blocker is disposed in the back end of line stack. the back end of line stack comprises a plurality of metallization levels, each metallization level having a dielectric layer, and the first metal sheet of the optical signal blocker is disposed in the dielectric layer of the metallization level closest to the semiconductor substrate.

9. The structure of claim 8, wherein, the first metal sheet of the optical signal blocker is spaced apart from the first portion of the waveguide core by a distance that allows the first metal sheet to block and absorb light propagating in the waveguide core.

10. The structure of claim 1, wherein, the optical signal blocker comprises a second metal sheet and a second plurality of openings in the second metal sheet, and the first metal sheet is disposed between the second metal sheet and the first portion of the waveguide core.

11. The structure of claim 1, wherein, the second plurality of openings are aligned with the first plurality of openings.

12. The structure of claim 11, wherein, the first plurality of openings have a critical dimension in a range between 1 micron and 10 microns.

13. The structure of claim 1, wherein, the first metal sheet has a ratio of solid material to open space less than or equal to 0.

5.

14. The structure of claim 1, wherein, 15. A structure for a photonic chip, the structure comprising: a semiconductor substrate; an optical signal blocker comprising a plurality of metal features; and a waveguide core between the semiconductor substrate and the optical signal blocker, the waveguide core comprising a portion overlapping the optical signal blocker. the plurality of metal features are arranged in a two-dimensional array having a plurality of rows and a plurality of columns.

16. The structure of claim 15, wherein, one of the rows overlaps the portion of the waveguide core.

17. The structure of claim 16, wherein, the portion of the waveguide core is positioned laterally between adjacent pairs of the rows.

18. The structure of claim 16, wherein, the plurality of metal features comprise copper or aluminum and the waveguide core comprises silicon nitride.

19. The structure of claim 15, wherein, 20. A method of forming a structure for a photonic chip, the method comprising: forming a waveguide core; and forming an optical signal blocker comprising a metal sheet and a plurality of openings in the metal sheet, ​ ​ The waveguide core is disposed between the semiconductor substrate and the optical signal blocker, and the waveguide core includes a portion that overlaps the optical signal blocker.

Images