PCIe controller, method for performance analysis of PCIe, and electronic device

Abstract

At least one embodiment of this disclosure provides a PCIe controller, a method for PCIe performance analysis, and an electronic device. The PCIe controller includes a data master path and a DMA engine, wherein the data master path is configured to transmit data; the DMA engine is configured to acquire performance analysis information associated with the data master path in real time, and to transmit the performance analysis information in real time to a bus communicating with the PCIe controller. This PCIe controller can facilitate the real-time acquisition of performance analysis information, thereby providing more reliable, more granular, or continuous performance analysis information, and improving the performance of PCIe performance analysis.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of computer technology, and more specifically, to PCIe controllers, methods for PCIe performance analysis, and electronic devices. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard used to connect various internal computer components (such as graphics cards, solid-state drives (SSDs), network cards, etc.), and has become a core technology for data transmission in modern computer systems.

[0003] In computer systems, PCIe can be used as an entry point for chips such as general-purpose graphics processing units (GPGPUs) or other computer chips. Because PCIe makes it easy to analyze request-response matching relationships, it is easier to analyze overall chip performance, bandwidth, and latency data by starting with PCIe, and to provide software engineers with information on the overall hardware transmission efficiency. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a high-speed PCIe controller for peripheral component interconnection, including a data master path and a direct memory access (DMA) engine, wherein the data master path is configured to transmit data; the DMA engine is configured to acquire performance analysis information associated with the data master path in real time, and to transmit the performance analysis information to a bus communicating with the PCIe controller in real time.

[0005] For example, in some embodiments, the DMA engine is also configured to: organize performance analysis information into at least one performance analysis chain, each performance analysis chain including corresponding performance analysis information and identification information; and transmit each performance analysis chain to the bus in real time.

[0006] For example, in some embodiments, for each performance analysis chain, the performance analysis information includes: a timestamp and at least one of device-to-host (D2H) performance data, host-to-device (H2D) performance data, and performance anomaly records, and the identification information includes: a start identifier and an end identifier, wherein the timestamp identifies the time corresponding to the performance analysis chain, the D2H performance data identifies the device-to-host performance data within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain, the H2D performance data identifies the host-to-device performance data within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain, the performance anomaly record identifies the transmission of a performance anomaly within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain, the start identifier is used to identify the start of the performance analysis chain, and the end identifier is used to identify the end of the performance analysis chain.

[0007] For example, in some embodiments, the PCIe controller further includes a performance data register configured to: receive data type configuration information, the data type configuration indicating target data to be included in the performance analysis chain, including at least one of D2H performance data, H2D performance data, and performance anomaly records; and string the target data into the performance analysis chain.

[0008] For example, in some embodiments, the performance data register is also configured to: receive operation type configuration information, which indicates the operation type of the target data; and string the target data corresponding to the operation type into the performance analysis chain.

[0009] For example, in some embodiments, D2H performance data and H2D performance data are associated with bandwidth and / or latency.

[0010] For example, in some embodiments, performance anomaly logs include the address and / or size of transmissions with latency greater than a threshold.

[0011] For example, in some embodiments, it further includes: a performance analysis chain number determination unit, configured to: determine the maximum number of performance analysis chains stored in the address space based on the size of the DMA engine's address space on the bus and the space occupied by a single performance analysis chain; and an overlay unit, configured to: in response to the number of performance analysis chains stored in the address space being greater than the maximum number, execute one of the following three overlay modes: overlay mode one, stopping the DMA engine from sending new performance analysis chain write requests to the bus; overlay mode two, overlaying the previous performance analysis chains stored in the address space with new performance analysis chains; and overlay mode three, overlaying the previous performance analysis chains stored in the address space with a predetermined number of new performance analysis chains.

[0012] For example, in some embodiments, the predetermined number of values ​​is obtained by software through registers.

[0013] For example, in some embodiments, the DMA engine is also configured to: acquire physical performance data of the PCIe physical layer in real time; and transmit the physical performance data to the bus in real time.

[0014] For example, in some embodiments, the physical performance data includes receiver-side physical performance data measured on the receiver side of the link between the host side and the device side, and the PCIe controller is located on the sender side of the link. The DMA engine is also configured to: send a read request for the receiver-side physical performance data to the receiver side; and transfer the receiver-side physical performance data to the receiver-side bus or the sender-side bus.

[0015] For example, in some embodiments, the PCIe controller is located in at least one of the device side and the host side, and the DMA engine in the PCIe controller located in one of the device side and the host side is also configured to transfer performance analysis information corresponding to write requests for performance analysis to the bus of the other of the device side and the host side, for example, the bus is a memory bus.

[0016] For example, in some embodiments, the PCIe controller is located on at least one of the device side and the host side, and the DMA engine in the PCIe controller located on the device side and the host side is further configured to transmit performance analysis information corresponding to a read request for performance analysis to a bus on the device side or a bus on the host side, wherein the bus is a control bus.

[0017] For example, in some embodiments, the bus includes at least one of a memory bus and a control bus.

[0018] At least one embodiment of this disclosure provides a method for performance analysis of high-speed PCIe for peripheral component interconnect, wherein the PCIe controller includes a data master path and a direct memory access (DMA) engine. The method includes: transmitting data through the data master path, acquiring performance analysis information of the PCIe controller in real time by the DMA engine, and transmitting the performance analysis information in real time to a bus communicating with the PCIe controller.

[0019] For example, in some embodiments, performance analysis information is carried in at least one performance analysis chain, and each performance analysis chain in the at least one performance analysis chain includes corresponding performance analysis information and identification information.

[0020] For example, in some embodiments, the method further includes: determining a maximum number of performance analysis chains stored in the address space based on the size of the DMA engine's address space on the bus and the space occupied by a single performance analysis chain; and in response to the number of performance analysis chains stored in the address space being greater than the maximum number, executing one of the following three overwrite modes: overwrite mode one, stopping the DMA engine from sending write requests for new performance analysis chains to the bus; overwrite mode two, overwriting the previous performance analysis chains stored in the address space with new performance analysis chains; and overwrite mode three, overwriting the previous performance analysis chains stored in the address space with a predetermined number of new performance analysis chains.

[0021] For example, in some embodiments, the method further includes: using a DMA engine to: acquire physical performance data of the PCIe physical layer in real time; and transmitting the physical performance data to the bus in real time.

[0022] For example, in some embodiments, the PCIe controller is located on at least one of the device side and the host side, and the method further includes: a DMA engine in the PCIe controller located on one of the device side and the host side: transmitting performance analysis information corresponding to a write request for performance analysis to the bus of the other of the device side and the host side; or transmitting performance analysis information corresponding to a read request for performance analysis to the bus on the device side or the bus on the host side, wherein the bus is a control bus.

[0023] At least one embodiment of this disclosure provides an electronic device including at least one processing unit and a memory; wherein the memory stores computer-readable instructions and is communicatively connected to at least one processing unit; the at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the method as described in any of the preceding claims.

[0024] At least one embodiment of this disclosure provides a computer-readable storage medium storing computer-readable instructions that, when executed by a processor, implement the method described in any of the preceding claims. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Clearly, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure.

[0026] Figure 1 A schematic diagram of a system architecture including a PCIe controller according to at least one embodiment of the present disclosure is shown;

[0027] Figure 2A schematic diagram of another system architecture including a PCIe controller is shown according to at least one embodiment of the present disclosure;

[0028] Figure 3 A schematic diagram of the structure of a performance analysis chain according to at least one embodiment of the present disclosure is shown;

[0029] Figure 4 A schematic diagram of the structure of a lookup table for calculating H2D and D2H performance data according to at least one embodiment of the present disclosure is shown;

[0030] Figure 5A A schematic diagram is shown showing the address space distribution of the performance analysis chain on the memory bus according to at least one embodiment of the present disclosure;

[0031] Figure 5B A schematic diagram is shown showing the address space distribution of the performance analysis chain on the control bus according to at least one embodiment of the present disclosure;

[0032] Figure 6 A further system architecture schematic diagram including a PCIe controller is shown according to at least one embodiment of the present disclosure;

[0033] Figure 7 A schematic diagram of a method for performance analysis of high-speed PCIe for peripheral component interconnection according to at least one embodiment of the present disclosure is shown;

[0034] Figure 8 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0035] Figure 9 A schematic diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure is shown;

[0036] Figure 10 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0037] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0038] To enable those skilled in the art to better understand this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of this disclosure to the specific shapes, hardware, connections, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can utilize the concepts of this disclosure to construct further embodiments not mentioned herein by reading this specification.

[0040] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0041] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0042] First, the abbreviations and related terms involved in this application are defined and explained.

[0043] Direct Memory Access (DMA): DMA is a technology in computer systems that allows peripherals to directly transfer data with memory. It uses a DMA controller (DMAC, also known as the DMA engine) to copy data from one address space to another, providing high-speed data transfer between peripherals and memory or between memory devices.

[0044] Performance analysis: PCIe performance analysis is a key process for evaluating its data transmission efficiency, bandwidth utilization, and latency performance.

[0045] It is understood that the terms defined above are merely exemplary definitions in specific application scenarios to better understand this application, and this disclosure is not limited thereto.

[0046] For PCIe controller performance analysis, the exemplary PCIe controller is designed with a static status register. This static status register records the PCIe controller's performance analysis data at the current timestamp in real time, and software engineers need to access the register one by one to read the performance analysis data at the current timestamp.

[0047] The inventors of this disclosure recognized during their research that the main drawback of the aforementioned exemplary PCIe controller design is that the recording of performance analysis data is static. The hardware only begins counting and compiling new performance analysis data for a new hardware cycle after the software engineer reads the performance analysis data at the current timestamp. This is detrimental to the software engineer's analysis of hardware performance, as they cannot establish a continuous perception of performance analysis data over a period of time. They can only perceive performance analysis data at different timestamps in a point-by-point manner using coarse-grained timestamps. Furthermore, if an abnormal performance degradation occurs during a certain period, it is inconvenient to pinpoint the specific cause of the problem.

[0048] In view of this, at least one embodiment of the present disclosure provides a PCIe controller that, in addition to the main data path for data transmission, incorporates a DMA engine to update real-time performance analysis information to the bus communicating with the PCIe controller in real time. This allows the software to have a near-infinite amount of performance analysis information to facilitate the software's evaluation of the overall hardware performance.

[0049] Figure 1 A schematic diagram of a system architecture including a PCIe controller according to at least one embodiment of the present disclosure is shown.

[0050] See Figure 1 The system architecture 100 includes a PCIe controller 102, which includes a DMA engine 104 and a main data path (not shown) for data transfer. Additionally, the system architecture 100 includes a bus 106 for communicating with the DMA engine 104. In at least one embodiment, the PCIe controller 102 may also include other components for implementing the PCIe standard, such as registers, caches, etc.

[0051] The DMA engine 104 is configured to acquire performance analysis information associated with the main data path of the PCIe controller in real time. For example, when data transfer occurs in the main data path, registers or other components within the PCIe controller can record or calculate data or information associated with the data transfer for performance analysis. In some examples, performance analysis information may include timestamps generated by timestamp registers, D2H performance data recorded by performance analysis data registers, H2D performance data, performance anomaly logs, etc., as described below.

[0052] As data is transmitted via the PCIe controller, performance analysis information can be generated in real time and received by the DMA engine 104.

[0053] See also Figure 1The DMA engine 104 transmits performance analysis information in real time to the bus 106, which communicates with the PCIe controller. See, for example... Figure 1 Once the DMA engine 104 receives the performance analysis information, it can transmit the performance analysis information to the bus.

[0054] In this way, the PCIe controller according to at least one embodiment of the present disclosure can update performance analysis information in real time to the bus communicating with the PCIe controller through its built-in DMA engine, thereby realizing unlimited recording and real-time acquisition of performance analysis information and improving the performance of PCIe performance analysis.

[0055] For example, in the design of an exemplary PCIe controller, the performance analysis process involves, for instance, sending data or requests on a PCIe link (such as the PCIe data master path) and performing tests or measurements to obtain performance analysis data; storing the performance analysis data in a static register; and allowing software engineers to read the performance analysis data from the static register via software. If multiple sets of performance analysis data are desired, the above process needs to be repeated multiple times.

[0056] In this scenario, performance analyses are intermittent, failing to provide continuous performance analysis data over a given period. Furthermore, the results of each analysis are stored in a finite number of static registers, making it impossible to record the current performance analysis results continuously in real time. In other words, although software can obtain multiple performance analysis results by repeating the above process, these results are discontinuous because each analysis requires waiting for the software to read the current performance analysis data from the registers before the next analysis can proceed, making it impossible to obtain continuous, real-time performance analysis data over a given period. Additionally, if performance analysis data is stored using an overwrite method, the finite number of static performance analysis registers will cause new data to overwrite older data, again preventing the acquisition of continuous, real-time performance analysis data.

[0057] Therefore, the performance analysis data obtained through the performance analysis process of the exemplary PCIe controller design described above is coarse-grained or discontinuous, and potentially cannot obtain the time corresponding to the performance analysis data, because it can only be known that the performance analysis data corresponds to a specific hardware cycle, but not the specific moment within that hardware cycle. Consequently, the obtained performance analysis data may be of little significance for performance analysis, which is detrimental to performance analysis.

[0058] In contrast, based on the above embodiments, the PCIe controller according to at least one embodiment of the present disclosure can facilitate the real-time acquisition of performance analysis information, thereby providing more reliable, more granular or continuous performance analysis information in time, and improving the performance of PCIe performance analysis.

[0059] The following describes the PCIe controller and other additional aspects of the system architecture that includes the PCIe controller.

[0060] Figure 2 A schematic diagram of another system architecture including a PCIe controller is shown according to at least one embodiment of the present disclosure. This other system architecture 200 may be as described in [reference needed]. Figure 1 A more detailed schematic diagram of the system architecture 100, or including other additional aspects.

[0061] See Figure 2 The other system architecture 200 includes a PCIe controller 202, which includes a DMA engine 204. Additionally, the system architecture 200 includes a memory bus 205 and a control bus 206 that communicate with the DMA engine 204.

[0062] See Figure 2 The described DMA engine 204 can be compared with [see also...] Figure 1 The DMA engine described is the same as or similar to 104. Also see... Figure 2 The memory bus 205 and control bus 206 described herein may be referenced. Figure 1 Example of bus 106 described.

[0063] See Figure 2 The described PCIe controller 202 is located on the device side. Of course, the embodiments disclosed herein are not limited thereto; see also... Figure 2 The PCIe controller 202 described can be located on the host side or on both the device side and the host side.

[0064] The host side can be the side that controls and manages the core, while the device side can be the side that is controlled as a terminal or peripheral. In some examples, the host can be a CPU, and the device can be a GPGPU, thus enabling the GPGPU to assist the CPU or the GPGPU to work collaboratively with the CPU.

[0065] See also Figure 2Data can be transferred between device side 216 and host side 219 via the main data path 218 of PCIe controller 202. For example, in the direction from host side 219 to device side 216, data can be transferred from host side 219 to device side 216 via host-to-device (H2D) data transfer unit 220. Alternatively, in the direction from device side 216 to host side 219, data can be transferred from device side 216 to host side 219 via device-to-host (D2H) data transfer unit 222. For example, in an example scenario where the host is a CPU and the device is a GPGPU, the GPGPU can communicate with the CPU via the main data path 218 to enable the GPGPU to assist the CPU or for the GPGPU and CPU to work collaboratively.

[0066] In some embodiments, during data transmission between the device side 216 and the host side 219, the PCIe controller 202 can measure and record relevant information or data about data transmission in the main data path 218, and record it, for example, in a register, to obtain the performance analysis information described above.

[0067] See Figure 2 The PCIe controller 202 may include a timestamp register 208, an H2D performance data register 212, a D2H performance data register 210, and a performance anomaly log register 214. The timestamp register 208, H2D performance data register 212, D2H performance data register 210, and performance anomaly log register 214 can respectively generate timestamps, H2D performance data, D2H performance data, and performance anomaly logs as performance analysis information or part thereof. After the performance analysis information is generated or recorded, the DMA engine 204 can receive or collect the performance analysis information. For example, it can be collected or organized in the form of a performance analysis chain as described below.

[0068] In some embodiments, performance analysis information may be carried in at least one performance analysis chain, and each performance analysis chain in the at least one performance analysis chain may include corresponding performance analysis information and identification information.

[0069] For example, timestamp register 208, H2D performance data register 212, D2H performance data register 210, and performance anomaly record register 214 can generate performance analysis information such as timestamps, H2D performance data, D2H performance data, and performance anomaly records in real time. This performance analysis information can be organized into various performance analysis chains. For example, each performance analysis chain can correspond to a different time or time period. According to at least one embodiment of this disclosure, the PCIe controller can distinguish and identify them, thereby allowing the corresponding performance analysis chain to be obtained based on the corresponding identification information, which helps software engineers perform performance analysis for the corresponding time period.

[0070] In some embodiments, for each performance analysis chain, the performance analysis information may include: a timestamp and at least one of device-to-host (D2H) performance data, host-to-device (H2D) performance data, and performance anomaly records.

[0071] In addition, the identification information may include: a start identifier and an end identifier.

[0072] Among them, the timestamp identifies the time corresponding to the performance analysis chain, the D2H performance data identifies the device-to-host performance data within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain, the H2D performance data identifies the host-to-device performance data within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain, the performance anomaly record identifies the transmission of performance anomalies within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain, the start identifier is used to identify the start of the performance analysis chain, and the end identifier is used to identify the end of the performance analysis chain.

[0073] Performance analysis information includes various types of information; however, the performance analysis information that software engineers are interested in or need to perform performance analysis varies at different times. A PCIe controller according to at least one embodiment of this disclosure provides a flexible performance analysis chain that can include different performance analysis information, thereby meeting the acquisition needs of corresponding performance analyses and providing flexibility and targeting in performance analysis information acquisition.

[0074] For example, in some cases, software engineers may only be interested in D2H performance data, H2D performance data, and performance anomaly records within performance anomaly logs. In such cases, a performance analysis chain that includes performance anomaly records can be selected (as described below). Figure 3 The performance analysis chain shown in (d) is not the performance analysis chain that includes D2H performance data, host-to-device H2D performance data, and performance anomaly records (as described below). Figure 3 The performance analysis chain shown in (a) enables flexible and targeted acquisition of performance analysis information.

[0075] Figure 3 A schematic diagram of the structure of a performance analysis chain according to at least one embodiment of the present disclosure is shown.

[0076] exist Figure 3 In the diagram, (a) through (g) illustrate different types of performance analysis chains. Each type of performance analysis chain includes a start identifier, a timestamp, and an end identifier, and each of these performance analysis chains has a different type because it includes one or more of D2H performance data, H2D performance data, and performance anomaly records.

[0077] It should be noted that, in Figure 3 In (a) through (g), the timestamps of the performance analysis chain are shown using two timestamp registers (timestamp register 0 and timestamp register 1). In this way, detailed time representation (e.g., including year, month, day, hour, minute, second, etc.) can be achieved. Of course, the embodiments of this disclosure are not limited to this; in some embodiments, timestamps can be recorded via one or more registers to provide time information that meets actual needs.

[0078] exist Figure 3 In the diagram, (a) shows a schematic diagram of the complete performance analysis chain. This performance analysis chain is called a complete performance analysis chain because it includes D2H performance data, H2D performance data, and performance anomaly records.

[0079] In contrast, Figure 3 The performance analysis chains shown in (b) to (g) differ in that they contain only one or both of D2H performance data, H2D performance data, and performance anomaly records, and are therefore called incomplete performance analysis chains. Specifically, in Figure 3 In the above, (b) only contains H2D performance data and performance anomaly log information. (c) only contains D2H performance data and performance anomaly log information. (d) only contains performance anomaly log information. (e) only contains D2H performance data. (f) only contains H2D performance data. (g) only contains both D2H performance data and H2D performance data.

[0080] See Figure 3 In section (a), the performance analysis chain mainly consists of five parts: start identifier, timestamp, H2D performance data, D2H performance data, performance anomaly record, and end identifier.

[0081] Timestamps, H2D performance data, D2H performance data, and performance anomaly records can be generated by their respective registers. As mentioned above, timestamps, H2D performance data, D2H performance data, and performance anomaly records can be generated by timestamp register 208, H2D performance data register 212, D2H performance data register 210, and performance anomaly record register 214, respectively.

[0082] In some embodiments, the PCIe controller may include performance data registers (such as H2D performance data register 212, D2H performance data register 210, and performance anomaly record register 214), which are configured to: receive data type configuration information, the data type configuration being used to indicate target data of at least one of D2H performance data, H2D performance data, and performance anomaly records to be included in the performance analysis chain; and string the target data into the performance analysis chain.

[0083] In this way, software users can configure the corresponding performance data registers as needed to select and generate performance analysis chains.

[0084] The following describes each part of the performance analysis chain.

[0085] Start and end identifiers facilitate the identification of the head and tail of the performance analysis chain at the current moment from the bus, distinguishing it from performance analysis chains at other moments. For example, the start identifier may contain the index information of the current performance analysis chain, and the end identifier may contain the number of performance anomaly records. It is understood that the number of performance anomaly records can be contained in the end identifier because the arrangement order of the various parts of the performance analysis chain is such that the end identifier is immediately adjacent to the performance anomaly record. However, embodiments of this disclosure are not limited to this; depending on the arrangement order, the end identifier may contain other information. For example, if the arrangement order of the various parts of the performance analysis chain is such that the end identifier is immediately adjacent to the H2D performance data, then the end identifier may contain the size of the H2D performance data.

[0086] In some embodiments, the start identifier and end identifier may each comprise 64 bits, wherein the high 32 bits of the start identifier are FFFF_FFFF and the high 32 bits of the end identifier are FFFF_FFFE. Of course, embodiments of this disclosure are not limited thereto, and the start identifier and end identifier may comprise other numbers of bits.

[0087] It should be noted that, regarding the index in the start identifier, the index of the first performance analysis chain can be 0, and the index is incremented by 1 for each subsequent performance analysis chain. In the example above, the performance analysis chain index occupies 32 bits, which is almost impossible to fully occupy in practical applications. Furthermore, in some embodiments, once all 32 bits are occupied, the counting can restart from 0. Additionally, the index in the start identifier also facilitates software calibration to ensure the correctness of the currently processed performance analysis chain, and it also helps to accurately determine the position of a performance analysis chain together with the timestamp.

[0088] Additionally, regarding the number of performance anomaly records in the end marker, this value can be 0 if no performance anomaly transmissions (trans) were received during this period. The number of performance anomaly records allows software to easily deduce how many performance anomaly transmissions exist within a single performance analysis chain.

[0089] The timestamp recorded in the timestamp register identifies the specific moment corresponding to each performance analysis chain, facilitating performance analysis and defining a unique time identity for each chain. Request timestamps can be recorded using a 64-bit register, or, for example, using two 32-bit registers (see [reference]). Figure 3 The timestamp register 0 and timestamp register 1 (hereinafter referred to as the timestamp register or timestamp request quantity register) shown in (a)-(g) are used to record the timestamp together. Each timestamp can be cleared after being inserted into the performance analysis chain.

[0090] For PCIe controllers, performance analysis can include analyzing bandwidth and latency from the host side to the device side; this performance data can be represented as H2D performance data or included within H2D performance data. Alternatively, performance analysis can include analyzing bandwidth and latency from the device side to the host side; this performance data can be represented as D2H performance data or included within D2H performance data. Therefore, in some embodiments, D2H performance data and H2D performance data can be associated with bandwidth and / or latency.

[0091] For the timestamp register, the time interval between each transmission performance analysis chain can be defined. The interval between the timestamp registers of two performance analysis chains is the defined time interval between each transmission performance analysis chain. During the time interval between each transmission performance analysis chain, H2D performance data and D2H performance data can be collected and fed into the corresponding performance analysis chain.

[0092] For H2D and D2H performance data, it can be correlated with bandwidth and / or latency. Bandwidth can be calculated as the number of bytes sent per unit time, and latency can be calculated by counting from the time the request is sent to the time the request is returned.

[0093] Figure 4 A schematic diagram of the structure of a lookup table for calculating H2D and D2H performance data according to at least one embodiment of the present disclosure is shown.

[0094] To obtain H2D and D2H performance data, a latency lookup table (LUT) can be maintained based on the outstanding transaction capacity of the data link transmission. For example, for a write request, if the outstanding transaction capacity is 256, a latency lookup table with 256 entries needs to be maintained. Each time a request is received, the timestamp corresponding to the request and an identifier (ID) used to map the request / response can be recorded. This ID can be used to establish the relationship between the request and the response; the ID can be carried when the request is sent and when the response is returned. Each time a request is received, the timestamp and ID are added to the latency lookup table, and the corresponding entry enable bit is set.

[0095] Whenever a response is received, the delay lookup table is looked up based on the ID to find the timestamp of the corresponding request. Then, based on the timestamp of the response collected when the response was received, the timestamp of the response is subtracted from the timestamp of the request to obtain the delay of the transmission.

[0096] Additionally, this latency can be used to calculate other computational H2D and D2H performance data, such as the maximum latency between two timestamps, the minimum latency between two timestamps, the average latency between two timestamps, and the bandwidth efficiency between two timestamps.

[0097] For example, the average delay between two timestamps can be achieved using an average delay calculation unit. For instance, the average delay can be recorded by a 64-bit average delay register. As mentioned above, the timestamp request quantity register can be 64 bits (e.g., implemented using two 32-bit registers), and both registers can be cleared after each timestamp is serialized into the performance analysis chain.

[0098] Specifically, upon receiving a response, the timestamp of the request is obtained through a latency lookup table. The overall latency of the transmission is calculated by subtracting the request timestamp from the response timestamp. This latency is then added to the value of the average latency register to obtain a new value for the average latency register. The timestamp request count register is then incremented by 1. After the time interval of the timestamp ends, the average latency register is divided by the timestamp request count register to obtain a new value for the average latency register. This new value is then used as the average latency between the two timestamps and chained into the performance analysis chain.

[0099] For example, the maximum latency can be calculated using a maximum latency calculation unit. For instance, when calculating the average latency, a maximum latency register can be maintained. This maximum latency register can be cleared each time its recorded maximum latency is entered into the performance analysis chain.

[0100] Specifically, after each new request and response results in the delay of a transmission, that delay is compared to the value of the maximum delay register. If the delay is greater than the value of the maximum delay register, the delay is updated in the maximum delay register. If the delay is less than or equal to the value of the maximum delay register, the value of the maximum delay register is retained. After the time interval of that timestamp ends, the current maximum delay register is chained into the performance analysis chain.

[0101] For example, minimum latency can be achieved using a minimum latency calculation unit. The specific aspects of minimum latency can be similar to those of maximum latency, and will not be elaborated upon here.

[0102] For example, bandwidth efficiency can be implemented using a bandwidth efficiency calculation unit. For instance, each time a new request arrives, the number of bytes carried by that request can be recorded and written to the bandwidth efficiency register. After the timestamp interval ends, the value of the bandwidth efficiency register can be chained into the performance analysis chain, and the value of the bandwidth efficiency register can be cleared to zero.

[0103] It is understood that the maximum latency between two timestamps, the minimum latency between two timestamps, the average latency between two timestamps, and the bandwidth efficiency between two timestamps, and their specific aspects, as described above, are merely exemplary. Furthermore, some or all of the maximum latency between two timestamps, the minimum latency between two timestamps, the average latency between two timestamps, and the bandwidth efficiency between two timestamps can be configured to be chained into the performance analysis chain as needed.

[0104] When calculating performance data such as D2H performance data, H2D performance data, and performance anomaly logs, operation types such as read operations, write operations, and atomic operations can be distinguished. Each type of operation can have performance data registers with the bandwidth and / or latency mentioned above. For example, the H2D performance data register can determine which performance data to include in the performance analysis chain based on different PCIe controller designs or different actual use cases. By selecting the read, write, or atomic operation type of the H2D performance data register, only a portion of the H2D performance data from the register can be selected and included in the performance analysis chain. This facilitates the filtering of the required H2D performance data, thereby avoiding unnecessary H2D performance data occupying actual address space.

[0105] Therefore, in some embodiments, the performance data register may also be configured to: receive operation type configuration information, which indicates the operation type of the target data; and chain the target data corresponding to the operation type into the performance analysis chain. In this way, target data of the appropriate operation type (such as D2H performance data, H2D performance data, or at least one of performance anomaly records) can be selected by configuration, instead of all types of target data, thereby reducing address space usage and minimizing information in the performance analysis that is meaningless for performance analysis.

[0106] In some examples, for performance data such as H2D and D2H, the performance data can be freely selected based on read, write, or atomic operation types. For instance, H2D performance data can be selected only for read operations, while D2H performance data can be selected only for write operations. This allows for a highly flexible performance analysis chain to meet various application requirements.

[0107] Performance anomaly records can be information about excessively delayed transmissions during a performance analysis chain. The number of performance anomaly records can be N, where N ≥ 0 and is an integer. The value of N is related to the transmission of performance anomaly records received at that time. As mentioned above, the value of N can be carried by an end marker. For example, if no performance anomaly record transmission is received within a timestamp interval, the number of performance anomaly records can be 0, and the end marker will also indicate that the number of performance anomaly records is 0.

[0108] Here, for a single request, the time difference between the request and the response is the latency of that request. In some embodiments, a threshold for performance-abnormal transmissions can be preset in a register. If the latency of a request exceeds this threshold, it can be determined that the request is a transmission with a performance-abnormal record. Then, information such as the address and / or memory access size of this transmission can be chained as a performance-abnormal record into the performance analysis chain to facilitate subsequent analysis by software engineers. Therefore, in some embodiments, a performance-abnormal record includes the address and / or size of transmissions with latency greater than the threshold.

[0109] Since the causes of performance anomalies in real systems can be quite complex, without recording the information related to these anomalies, performance analysis can only provide rough information such as large delays and low bandwidth efficiency at the corresponding timestamp intervals. It cannot determine the underlying reasons for the poor performance at those timestamp intervals; in other words, insufficient information is needed for performance analysis, leading to a failure to obtain crucial information about the performance anomalies. Therefore, in the above embodiment, recording the transmission information when performance anomalies occur provides useful evidence for performance analysis related to these anomalies, facilitating appropriate debugging by software engineers.

[0110] It is understandable that the above description Figure 3 The structure and formation process of the complete performance analysis chain are shown in (a) in the figure. Figure 3 The structure and formation process of the performance analysis chain shown in (b) to (g) can be compared with the structure and formation process of the complete performance analysis chain shown in (a). For example, whether it is the complete performance analysis chain shown in (a) or the incomplete performance analysis chain shown in (b) to (g), the performance data of read or write or atomic operation type can be freely selected.

[0111] Furthermore, the above description describes how performance data (such as H2D performance data register 212, D2H performance data register 210, and performance anomaly record register 214) are used to chain at least one of H2D performance data, D2H performance data, and performance anomaly records into a performance analysis chain based on corresponding configuration information, thereby obtaining a performance analysis chain. However, embodiments of this disclosure are not limited to this; the above functionality can be implemented using a DMA engine. For example, the DMA engine can receive H2D performance data, D2H performance data, and performance anomaly records, and chain at least one of these data into a performance analysis chain or organize it into a performance analysis chain based on corresponding configuration information. It is understood that implementing the above functionality using performance data registers can reduce the amount of data transfer between the performance data registers and the DMA, thereby reducing the resulting data transfer overhead.

[0112] In order for the DMA engine to transmit performance analysis information in real time to the bus communicating with the PCIe controller or to transmit performance analysis information in real time via the bus communicating with the PCIe controller, it is necessary to allocate address space on the bus for the DMA engine to place the performance analysis chain on the bus, thereby enabling the performance analysis chain to be transmitted on the bus.

[0113] In some embodiments, the bus may include a memory bus and a control bus.

[0114] Figure 5A A schematic diagram is shown showing the address space distribution of the performance analysis chain on the memory bus according to at least one embodiment of the present disclosure. Figure 5B A schematic diagram is shown showing the address space distribution of the performance analysis chain on the control bus according to at least one embodiment of the present disclosure.

[0115] See Figure 5A For the performance analysis chain located in address space 500 on the memory bus, a portion of the memory bus address space can be allocated to the DMA engine to enable the performance analysis chain to be transferred on the memory bus. For example, the performance analysis chain from timestamp 0 to timestamp M (M is a positive integer) can be located in the address space allocated to the memory bus of the DMA engine.

[0116] See Figure 5B For the performance analysis chain located in the address space distribution 550 on the control bus, a portion of the control bus's address space can be allocated to the DMA engine to enable the performance analysis chain to be transferred on the control bus. For example, the performance analysis chain from timestamp 0 to timestamp M (M is a positive integer) can be located in the address space allocated to the DMA engine's memory bus.

[0117] In some embodiments, the performance analysis chain can be configured to reside on the memory bus or the control bus, as well as the corresponding address space size, based on configuration registers. This allows for adaptation to various performance analysis needs.

[0118] In practical performance analysis, the performance analysis chain is usually placed on the memory bus for data transfer to memory. However, in some cases, it may be necessary to avoid the performance analysis chain accessing memory to prevent impacting memory performance. Therefore, in some embodiments, the performance analysis chain can be placed on the control bus.

[0119] exist Figure 5A and Figure 5B In this context, the maximum value of M depends on the size of the address space allocated to the DMA engine and the space occupied by a single performance analysis chain. In some embodiments, a performance analysis chain number determination unit can be set in the PCIe controller (e.g., within or outside the DMA engine). The performance analysis chain number determination unit can be configured to determine the maximum number of performance analysis chains stored in the address space based on the size of the DMA engine's address space on the bus and the space occupied by a single performance analysis chain.

[0120] For example, assuming the address space allocated to the DMA engine is 4MB, and the space occupied by a single performance analysis chain is 4KB, then the 4MB space can store a maximum of 4MB / 4KB = 1024 performance analysis chains.

[0121] There may be cases where the number of performance analysis chains exceeds the maximum number mentioned above. For example, the number of performance analysis chains may exceed 1024. In some embodiments, an overlay unit can be set in the PCIe controller (e.g., in the DMA engine, or outside the DMA engine). The overlay unit can be configured to execute one of the following overlay modes in response to the number of performance analysis chains stored in the address space exceeding the maximum number: Overlay mode one, stopping the DMA engine from sending write requests for new performance analysis chains to the bus; Overlay mode two, overwriting the previous performance analysis chains stored in the address space with new performance analysis chains; and Overlay mode three, overwriting the previous performance analysis chains stored in the address space with a predetermined number of new performance analysis chains.

[0122] Specifically, the first overlay mode is the performance analysis chain non-overlay mode. In this mode, once the address space allocated to the DMA engine is full, the DMA engine will no longer send new performance analysis chain requests, that is, it will not transmit performance analysis chains to the bus.

[0123] The second overlay mode is the performance analysis chain overlay mode. In this mode, once the address space allocated to the DMA engine is full, a loopback will be performed to send data from the low-order address to the high-order address, so that the new performance analysis chain will overwrite the information of the old performance analysis chain.

[0124] Overlay mode three is the specified performance analysis chain length mode. In this mode, for example, the length of the performance analysis chain to be sent (such as the number of performance analysis chains) can be specified by software through registers. If the DMA engine's address space is full, it will automatically loop back and send data from the lower address to the higher address. If the DMA engine's address space is not full, it will also automatically stop.

[0125] To address the issue that insufficient address space allocated to the DMA engine may lead to the performance analysis chain being overwritten, the above embodiments provide three different flexible and controllable overwriting modes: overwriting mode one (no overwriting, stop when full); overwriting mode two (loopback overwriting); and overwriting mode three (loopback overwriting with a fixed number of performance analysis chains), thereby meeting various application needs.

[0126] It should be noted that in actual use, because the memory address space is large, there is generally a large space that can be allocated to the performance analysis chain. If the allocated space is large, there is generally no need to consider the issue of overwriting.

[0127] As mentioned above, the PCIe controller can be located on at least one of the host side or the device side. The following is in conjunction with... Figure 6 Further description is required.

[0128] Figure 6 A further system architecture diagram including a PCIe controller is shown according to at least one embodiment of the present disclosure.

[0129] This is yet another system architecture, 600, which can be seen in [reference]. Figure 1 The system architecture described in 100 and / or see [reference] Figure 2 A more detailed schematic diagram of the described system architecture 200, or including other additional aspects. For example, this further system architecture 600 could be a system architecture where the PCIe controller is located on both the host and device sides.

[0130] See Figure 6On the device side, this additional system architecture 600 includes a PCIe controller 602, which may include a DMA engine 604, a timestamp register 608, a D2H performance data register 610, an H2D performance data register 612, a performance exception record register 614, a main data path 618, an H2D data transfer unit 620, and a D2H data transfer unit 622. Additionally, this additional system architecture 600 also includes a device-side memory bus 605 and a device-side control bus 606 that communicate with the DMA engine 604.

[0131] On the host side (e.g., shown as the CPU side), this additional system architecture 600 includes a PCIe controller 602', which may include a DMA engine 604', a timestamp register 608', a D2H performance data register 610', an H2D performance data register 612', a performance exception log register 614', a main data path 618', an H2D data transfer unit 620', and a D2H data transfer unit 622'. Additionally, this additional system architecture 600 also includes a CPU-side memory bus 605' and a CPU-side control bus 606' that communicate with the DMA engine 604'.

[0132] exist Figure 6 and Figure 2 as well as Figure 1 In this context, units or modules with the same name are identical or similar, and will not be elaborated further. Additionally, Figure 6 The device-side memory bus 605 and the CPU-side memory bus 605' can be used as Figure 2 An example of memory bus 205 in the example, and Figure 6 The device-side control bus 606 and the CPU-side control bus 606' can be used as Figure 2 Example of control bus 206 in the example.

[0133] See Figure 6 For PCIe, the PCIe interface (represented by the PCIe controller and the PCIe physical layer) serves as the chip's entry point, through which data transfer occurs between the CPU and devices (such as GPGPUs). Therefore, regardless of whether it's the device side or the CPU side, data transfer can occur via their memory bus or control bus, for example via... Figure 6 The data transmission direction of H2D or D2H is shown.

[0134] In at least one embodiment of this disclosure, the DMA engine is further configured to: acquire physical performance data of the PCIe physical layer in real time; and transmit the physical performance data to the bus in real time.

[0135] For PCIe, there is not only performance data for the PCIe and external bus interfaces (such as D2H performance data, H2D performance data, and performance anomaly records described above), but also performance data for the PCIe physical layer (referred to as physical performance data). See [link to relevant documentation] for details. Figure 6 The description includes physical performance data 626 of the PCIe physical layer 624 and / or physical performance data 626' of the PCIe physical layer 624'. Because the physical transmission links in practical applications of PCIe are relatively long, the probability of physical layer information quality problems occurring in PCIe links is higher compared to other data transmission protocols (such as Universal Chipset Interconnect (UCIe)). Therefore, more attention needs to be paid to physical performance data. Thus, in the above embodiment, by acquiring and transmitting the physical performance data of the PCIe physical layer in real time, performance analysis of the physical layer can be achieved.

[0136] In at least one embodiment of this disclosure, the physical performance data includes receiver-side physical performance data measured on the receiver side of a link between the host side and the device side, and the PCIe controller is located on the transmitter side of the link. The DMA engine is further configured to: send a read request for the receiver-side physical performance data to the receiver side; and transfer the receiver-side physical performance data to the receiver-side bus or the transmitter-side bus.

[0137] Regarding physical performance data, it includes receiver-side physical performance data measured at the receiver side (i.e., the RX side) in the link between the host side and the device side. In some embodiments, receiver-side physical performance data includes bit error rate data.

[0138] For example, bit error rate (BER) data can be measured on the RX side of the link, which is a crucial indicator for evaluating link quality. For instance, for H2D data transmission, BER data can be obtained on the device side, while for D2H data, it can only be obtained on the CPU side. Therefore, for scenarios requiring monitoring performance data on both sides of the chip, the PCIe controller described above needs to be installed on both the CPU and device sides. Figure 6 As shown, PCIe controllers (i.e., PCIe controller 602 on the device side and PCIe controller 602' on the CPU side) are provided on both the CPU side and the device side.

[0139] However, in practical applications, setting up the PCIe controller described above on both the CPU side and the device side can be expensive, and there may often be situations where only the device side has the performance analysis DMA engine. In such cases, based on the above embodiments, setting up a PCIe controller on a single side (such as the device side) can obtain receiver-side physical performance data such as bit error rate.

[0140] For example, see Figure 6 The device-side DMA engine 604 can initiate a read request to the CPU-side corresponding RX bit error rate data, and the received read response (including the corresponding bit error rate data) can be placed into the corresponding bus as needed, for example... Figure 6 The memory bus 605 on the device side and the memory bus 605' on the CPU side, the control bus 606 on the device side and the control bus 606' on the CPU side are provided for software personnel to access.

[0141] It should be noted that although the physical performance data obtained by setting the PCIe controller on the device side, such as the bit error rate, may cause some performance loss, this type of performance data may not be sensitive to the actual performance loss. What is more important is actually being able to read this data. Therefore, the above embodiments are of great significance for practical applications.

[0142] In some embodiments, the PCIe controller is located in at least one of the device side and the host side, and the DMA engine in the PCIe controller located in one of the device side and the host side is further configured to: transfer performance analysis information corresponding to write requests for performance analysis to the bus of the other of the device side and the host side.

[0143] A key characteristic of PCIe is that submitted requests (e.g., via POST) do not require a response; that is, write requests do not require a response. Therefore, the system architecture for performance analysis of PCIe in at least one embodiment of this disclosure differs significantly from other data transmission protocols. For example, see... Figure 6 In addition to sending performance analysis information to the device-side memory bus 605 or control bus 606, the device-side DMA engine 604 can also send performance analysis information to the CPU's (i.e., peer's) memory bus 605' or control bus 606' via D2H (for device-side performance analysis information). The CPU-side DMA engine 604' can perform similar operations, which will not be described in detail here.

[0144] It's important to note that this system architecture is unique to PCIe because, as mentioned above, PCIe has the characteristic that write requests do not require a response; therefore, the actual physical link bandwidth of PCIe is not occupied by write requests. In contrast, other data transfer protocols, such as UCIe, do not stipulate that write requests do not require a response. The following example, using D2H write requests sent to the CPU-side memory bus, illustrates the exemplary differences between the PCIe and UCIe system architectures.

[0145] For UCIe, such as D2H, after a write request is sent to the CPU-side memory bus, a corresponding write response is generated, which is actually returned through the H2D data transmission link. However, what we want to measure or test at this point is the performance data of the write request in the H2D direction, but the performance data itself has already affected our performance (e.g., the performance of memory access), so the performance data obtained is certainly not the most accurate performance data.

[0146] For PCIe, such as D2H write requests, after being sent to the CPU-side memory bus, a write response in the AXI protocol is generated. However, this write response is not transmitted through the actual PCIe link because the PCIe protocol stipulates that write requests do not require a response. Therefore, the CPU-side PCIe controller discards the write response upon receiving it. As for the AXI protocol write response, because AXI uses a 5-channel independent design, this performance data within the AXI range will not affect the performance of write requests in the H2D direction that are being measured. Therefore, this performance data is closer to the true value.

[0147] For PCIe, the main reason for performance limitations is that the actual physical link only has a transmit (TX) or RX direction, corresponding to two channels, TX and RX, so it cannot use the five independent channels designed in the AXI protocol. However, as mentioned above, because PCIe does not require write responses, compared to other data transmission protocols, only PCIe can adopt designs that, for example, send performance analysis information to the bus at the other end.

[0148] In this way, in the above embodiments, PCIe-based designs can be used, for example, to send performance analysis information corresponding to write requests to the bus on the other end, making the performance data closer to the true value.

[0149] In some embodiments, the bus can be a memory bus. For example, see... Figure 6 For the device-side DMA engine 604, it can transfer performance analysis information corresponding to write requests used for performance analysis to the CPU-side memory bus 605'. The principle of transferring performance analysis information corresponding to write requests used for performance analysis to the peer memory bus is described below.

[0150] First, we describe the difference between transmitting performance analysis information corresponding to write requests used for performance analysis to the memory bus on the other end and sending performance data directly to the memory bus on the side where the DMA engine is located via the DMA engine.

[0151] Consider a performance analysis scenario that measures write requests in the H2D direction. In this scenario, the CPU can send write requests to the device-side memory bus. However, at the same time, the performance analysis information is also generated by the device-side DMA engine 604 sending write requests to the device-side memory bus. Although the addresses of these two write requests are different, there can be situations where write requests access memory simultaneously. As a result, the performance analysis information sent by the device-side DMA engine 604 ultimately degrades the performance analysis process.

[0152] In at least one embodiment of this disclosure, the performance analysis information is real-time, and real-time performance analysis information can be obtained by triggering corresponding measurements based on a request for performance analysis (e.g., including the write or read requests for performance analysis described above).

[0153] It should be noted that, in at least one embodiment of this disclosure, the source of the request for performance analysis can be diverse. For example, the source can be the host side (e.g., CPU), the device side (GPGPU chip), or any embedded module with DMA capability, as long as they can provide the request for performance analysis. Different sources can be used for various scenarios, such as real-world scenarios and test scenarios.

[0154] For example, in a real-world scenario, the request could be a read or write request initiated by the host side to the device side, and vice versa. This allows for performance analysis in real-world scenarios. In one example, if you want to test the ability of a GPGPU chip to initiate read and write operations to the CPU host in a real-world scenario, the request could originate from a GPU core, thus providing performance analysis data on the GPU's transfer of data to the CPU. Similarly, in a test scenario, the request could be a read or write request initiated by a DMA module on the host side, and vice versa. This allows for performance analysis in test scenarios.

[0155] It's understandable that performance analysis in real-world scenarios can more accurately reflect the true performance of hardware compared to performance analysis in test scenarios.

[0156] The following describes the difference between transmitting performance analysis information corresponding to write requests used for performance analysis to the memory bus on the other end and sending performance data directly to the control bus on the side where the DMA engine is located via the DMA engine.

[0157] Firstly, for example, in a DMA engine scheme that distributes performance analysis information to either the memory bus or the control bus, the control bus is generally used for debugging when the memory bus fails. The control bus primarily transmits register information, and it has limitations on the size of the data transmitted and the burst length, so its transmission performance is not as good as the memory bus. Therefore, in scenarios with short timestamp intervals and long performance analysis chains, the control bus may not be able to effectively handle the tasks of data bus transmission.

[0158] Furthermore, the control bus is the space of the register bus, and its allocated address space is relatively small, typically 4MB, 8MB, or 16MB. Even assuming the total control bus space is 16MB, the vast majority of addresses correspond to actual functional register entities, and performance analysis information needs to be written to reserved non-functional readable and writable address space. Therefore, the actual space reserved for performance analysis information on the control bus is relatively small. In addition, because performance analysis information generally corresponds to data within a certain period, and subsequent performance analysis information is read only after the transmission is completely finished, it is generally required that performance analysis information (data in the performance analysis chain) not be overwritten. If the space reserved for performance analysis information on the control bus is small, it will result in insufficient storage of performance analysis information, failing to meet the requirements of performance analysis.

[0159] Based on the above principle description, it can be seen that for the DMA engine, in the destination of its performance analysis information (the memory bus and control bus on the side where the DMA engine is located, and the memory bus and control bus on the opposite side of the side where the DMA engine is located), the memory bus and control bus on the side where the DMA engine is located, as well as the control bus on the opposite side of the side where the DMA engine is located, all have the above-mentioned problems.

[0160] However, the aforementioned problem does not exist when using a DMA engine to send performance analysis information to the memory bus on the other side of the DMA engine. For example, in a scenario where performance analysis information is sent from the device-side DMA engine 604 to the CPU-side memory bus 605', since the CPU memory bus reads data from the CPU memory and writes it to the device-side memory, while the performance analysis information is written from the DMA engine to the CPU memory, the DMA engine performs a write operation, while the CPU itself performs a read operation. Since read and write operations use different addresses and channels, the probability of conflicts is greatly reduced, thus minimizing the impact of performance measurement on performance itself.

[0161] In this way, in the above embodiments, transmitting performance analysis information corresponding to write requests used for performance analysis to the memory bus at the other end can minimize the impact of performance analysis on performance (such as memory access performance).

[0162] In some embodiments, the PCIe controller is located on at least one of the device side and the host side, and the DMA engine in the PCIe controller located on the device side and the host side is further configured to: transmit performance analysis information corresponding to a read request for performance analysis to a bus on the device side or a bus on the host side, wherein the bus is a control bus.

[0163] Since PCIe only has the requirement of no response for a write request, and not a requirement for no response for a read request, sending performance analysis information to the memory bus for read request performance analysis would affect the impact of the performance analysis on memory access performance. Therefore, in the above embodiment, by transmitting the performance analysis information corresponding to the read request to the control bus, the impact of the performance analysis on memory access performance can be avoided.

[0164] It should be noted that the above Figure 6 The various aspects shown are merely exemplary and are not intended to limit the scope of this disclosure. For example, both the PCIe controllers on the device side and the CPU side can possess a DMA engine according to at least one embodiment of this disclosure, thereby enabling performance analysis by measuring corresponding performance analysis information on the device side or the CPU side, respectively. In practical applications, there may be scenarios where only the device side possesses the DMA engine. Based on the adjustment of the destination of the aforementioned performance analysis information, the performance analysis function can still be effectively utilized in such scenarios.

[0165] For the DMA engine described above, the following exemplary initialization process can be performed in actual use:

[0166] (1) Select a suitable performance analysis chain, such as Figure 3 As shown;

[0167] (2) Select the DMA engine to send to the memory bus or control bus;

[0168] (3) Select the size of the address space allocated to the DMA engine;

[0169] (4) Select the overlay mode for the DMA engine;

[0170] (5) The above (1)-(4) can be considered as the configuration work of the DMA engine. After the configuration work is completed, the DMA engine is started at any time when you want to start the DMA engine to realize the real-time transmission of the performance analysis chain.

[0171] Corresponding to the PCIe controller according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure also provides a method for performance analysis of high-speed PCIe for peripheral component interconnection.

[0172] Figure 7 A schematic diagram of a method for performance analysis of high-speed PCIe for peripheral component interconnection according to at least one embodiment of the present disclosure is shown.

[0173] This method 700 can be implemented by the DMA engine included in the PCIe controller.

[0174] See Figure 7 The method 700 includes steps S710 and S720.

[0175] In step S710, the performance analysis information of the PCIe controller is collected in real time.

[0176] In step S720, performance analysis information is transmitted in real time to the bus that communicates with the PCIe controller.

[0177] In this way, the method for performance analysis of high-speed PCIe peripheral component interconnect according to at least one embodiment of the present disclosure can facilitate the real-time acquisition of performance analysis information, thereby providing more reliable, time-granular or continuous performance analysis information and improving the performance of PCIe performance analysis.

[0178] The following describes some exemplary additional aspects of a method for performance analysis of high-speed PCIe peripheral component interconnect according to at least one embodiment of the present disclosure.

[0179] For example, in some embodiments, performance analysis information may be carried in at least one performance analysis chain, and each performance analysis chain in the at least one performance analysis chain includes corresponding performance analysis information and identification information.

[0180] For example, in some embodiments, the method may further include: determining a maximum number of performance analysis chains stored in the address space based on the size of the DMA engine's address space on the bus and the space occupied by a single performance analysis chain; and in response to the number of performance analysis chains stored in the address space being greater than the maximum number, performing one of the following three overwrite modes: overwrite mode one, stopping the DMA engine from sending write requests for new performance analysis chains to the bus; overwrite mode two, overwriting the previous performance analysis chains stored in the address space with new performance analysis chains; and overwrite mode three, overwriting the previous performance analysis chains stored in the address space with a predetermined number of new performance analysis chains.

[0181] For example, in some embodiments, the method may further include: the DMA engine: acquiring physical performance data of the PCIe physical layer in real time; and transmitting the physical performance data to the bus in real time.

[0182] For example, in some embodiments, the PCIe controller is located on at least one of the device side and the host side, and the method further includes: a DMA engine in the PCIe controller located on one of the device side and the host side: transmitting performance analysis information corresponding to a write request for performance analysis to the bus of the other of the device side and the host side; or transmitting performance analysis information corresponding to a read request for performance analysis to the bus on the device side or the bus on the host side, wherein the bus is a control bus.

[0183] Further exemplary aspects of the method for performance analysis of high-speed PCIe peripheral component interconnect according to at least one embodiment of the present disclosure can be found in conjunction with... Figures 1 to 6 The various aspects of the PCIe controller described will not be elaborated upon here.

[0184] Figure 8 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0185] like Figure 8 As shown, the electronic device 800 includes at least one processing unit 820 and a memory 810. The memory 810 stores computer-readable instructions and is communicatively connected to the processing unit 820. The processing unit 820 executes the computer-readable instructions stored in the memory 810 to implement the method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0186] For example, the memory 810 and the processing unit 820 can communicate with each other directly or indirectly. For example, in some examples, such as... Figure 8 As shown, the electronic device 800 may also include a system bus 830, through which the memory 810 and the processing unit 820 can communicate with each other. For example, the processing unit 820 can access the memory 810 through the system bus 830. For example, in other examples, components such as the memory 810 and the processing unit 820 can communicate through a network on-chip (NOC) connection.

[0187] For example, the processing unit 820 can control other components in the electronic device 800 to perform desired functions. The processing unit 820 can be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), tensor processor (TPU), network processor (NP), or graphics processor (GPU), or it can be a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0188] For example, memory 810 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0189] For example, one or more computer-readable instructions can be stored on memory 810, and processing unit 820 can execute computer-readable instructions to perform various functions. Various application programs and various data, such as instruction processing code and various data used and / or generated by application programs, can also be stored in the computer-readable storage medium.

[0190] For example, some computer instructions stored in memory 810 can perform one or more steps in accordance with the method described above when executed by processing unit 820.

[0191] For example, such as Figure 8 As shown, the electronic device 800 may further include an input interface 840 that allows external devices to communicate with the electronic device 800. For example, the input interface 840 may be used to receive instructions from external computer devices, users, etc. The electronic device 800 may also include an output interface 850 that enables the electronic device 800 to connect to one or more external devices. For example, the electronic device 800 can communicate via the output interface 850, etc.

[0192] It should be noted that the electronic device 800 according to at least one embodiment of the present disclosure is exemplary and not restrictive. Depending on the actual application needs, the electronic device 800 may also include other conventional components or structures. For example, in order to realize the necessary functions of the electronic device, those skilled in the art can set other conventional components or structures according to the specific application scenario. The embodiments of the present disclosure do not limit this.

[0193] At least one embodiment of this disclosure also provides a computer-readable storage medium. Figure 9 A schematic diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure is shown.

[0194] For example, such as Figure 9 As shown, the computer-readable storage medium 900 stores computer-readable instructions 910, which, when executed by a computer (including a processor), can implement the method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0195] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 900. Some of the computer-readable instructions stored on the computer-readable storage medium 900 may be, for example, instructions for implementing one or more steps in the methods described above.

[0196] For example, a computer-readable storage medium may include the storage component of a tablet computer, a hard disk of a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical disc read-only memory (CD-ROM), flash memory, or any combination of the above computer-readable storage media, or other suitable storage media. For example, computer-readable storage medium 900 may include the memory 810 in the electronic device 800 described above.

[0197] At least some embodiments of this disclosure also provide an electronic device. Figure 10 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown.

[0198] The electronic device according to at least one embodiment of the present disclosure can be implemented as, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers.

[0199] Figure 10 The electronic device 1000 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0200] For example, such as Figure 10As shown, in some examples, electronic device 1000 includes processor 1001, which may include the processor of any of the above embodiments (e.g., an SMT processor), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. Various programs and data required for the operation of the computer system are also stored in RAM 1003. Processor 1001, ROM 1002, and RAM 1003 are connected via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.

[0201] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although Figure 10 An electronic device 1000 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0202] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0203] In addition to the exemplary descriptions above, the following points should be noted regarding this disclosure:

[0204] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0205] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0206] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A high-speed PCIe controller for peripheral component interconnection, characterized in that, The PCIe controller includes: The main data path is configured to transmit data; and The direct memory access (DMA) engine is configured as follows: Real-time acquisition of performance analysis information associated with the main data pathway; and The performance analysis information is transmitted in real time to the bus that communicates with the PCIe controller. The performance analysis information is carried by at least one performance analysis chain, and the PCIe controller further includes a performance data register and a performance analysis chain number determination unit. The performance data register is configured as follows: Receive data type configuration information, wherein the data type configuration is used to indicate the target data to be included in the performance analysis chain, including at least one of device-to-host (D2H) performance data, host-to-device (H2D) performance data, and performance anomaly records; and The target data is then fed into the performance analysis chain; The performance analysis chain number determination unit is configured as follows: The maximum number of performance analysis chains stored in the address space is determined based on the size of the address space of the DMA engine on the bus and the space occupied by a single performance analysis chain.

2. The PCIe controller according to claim 1, characterized in that, Each performance analysis chain in the at least one performance analysis chain includes corresponding performance analysis information and identification information.

3. The PCIe controller according to claim 2, characterized in that, For each performance analysis chain, the performance analysis information includes: a timestamp and at least one of the D2H performance data, the H2D performance data, and the performance anomaly record, and the identification information includes: a start identifier and an end identifier. The timestamp identifies the moment corresponding to the performance analysis chain. The D2H performance data identifies the device-to-host performance data within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain. The H2D performance data identifies the host-to-device performance data within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain. The performance anomaly record identifies the transmission of a performance anomaly within the time interval between the timestamps of the performance analysis chain and another adjacent performance analysis chain. The starting identifier is used to identify the beginning of the performance analysis chain, and The end identifier is used to indicate the end of the performance analysis chain.

4. The PCIe controller according to claim 1, characterized in that, The performance data register is also configured as follows: Receive operation type configuration information, wherein the operation type configuration is used to indicate the operation type of the target data; and The target data corresponding to the operation type is chained into the performance analysis chain.

5. The PCIe controller according to claim 3, characterized in that, The D2H performance data is associated with the H2D performance data and bandwidth and / or latency.

6. The PCIe controller according to claim 3, characterized in that, The performance anomaly record includes the address and / or size of transmissions with latency greater than a threshold.

7. The PCIe controller according to claim 1, characterized in that, The PCIe controller also includes: The overlay unit is configured to perform one of the following three overlay modes in response to a number of performance analysis chains stored in the address space exceeding the maximum number: In overwrite mode one, the DMA engine is stopped from sending new performance analysis chain write requests to the bus; Overwrite mode two involves overwriting the previous performance analysis chain stored in the address space with the new performance analysis chain; and Overlay mode three involves overwriting the previous performance analysis chains stored in the address space with a predetermined number of new performance analysis chains.

8. The PCIe controller according to claim 1, characterized in that, The DMA engine is also configured as follows: Real-time acquisition of physical performance data of the PCIe physical layer; and The physical performance data is transmitted to the bus in real time.

9. The PCIe controller according to claim 8, characterized in that, The physical performance data includes receiver-side physical performance data measured at the receiver side of the link between the host side and the device side, and the PCIe controller is located at the transmitter side of the link. The DMA engine is also configured as follows: Send a read request for physical performance data of the receiving side to the receiving side; and The physical performance data of the receiving side is transmitted to the bus of the receiving side or the bus of the transmitting side.

10. The PCIe controller according to any one of claims 1-9, characterized in that, The PCIe controller is located in at least one of the device side and the host side, and the DMA engine in the PCIe controller located in one of the device side and the host side is further configured to: The performance analysis information corresponding to the write request used for performance analysis is transmitted to the bus of the other of the device side and the host side.

11. The PCIe controller according to claim 10, characterized in that, The bus is a memory bus.

12. The PCIe controller according to claim 1, characterized in that, The PCIe controller is located in at least one of the device side and the host side, and the DMA engine in the PCIe controller located in one of the device side and the host side is further configured to: The performance analysis information corresponding to the read request used for performance analysis is transmitted to the bus on the device side or the bus on the host side, wherein the bus is a control bus.

13. A method for performance analysis of high-speed PCIe for peripheral component interconnection, characterized in that, The PCIe controller includes a data master path and a direct memory access (DMA) engine, and the method includes: Data is transmitted through the main data path; and By the DMA engine: Real-time acquisition of performance analysis information associated with the main data pathway; and The performance analysis information is transmitted in real time to the bus that communicates with the PCIe controller. The performance analysis information is carried by at least one performance analysis chain, the PCIe controller further includes a performance data register and a performance analysis chain number determination unit, and the method further includes: From the performance data register: Receive data type configuration information, wherein the data type configuration is used to indicate the target data to be included in the performance analysis chain, including at least one of device-to-host (D2H) performance data, host-to-device (H2D) performance data, and performance anomaly records; and The target data is then fed into the performance analysis chain; The number of performance analysis chains is determined by the following unit: The maximum number of performance analysis chains stored in the address space is determined based on the size of the address space of the DMA engine on the bus and the space occupied by a single performance analysis chain.

14. The method according to claim 13, characterized in that, Each performance analysis chain in the at least one performance analysis chain includes corresponding performance analysis information and identification information.

15. The method according to claim 13, characterized in that, The method further includes: In response to the number of performance analysis chains stored in the address space being greater than the maximum number, one of the following three coverage modes is executed: In overwrite mode one, the DMA engine is stopped from sending new performance analysis chain write requests to the bus; Overwrite mode two involves overwriting the previous performance analysis chain stored in the address space with the new performance analysis chain; and Overlay mode three involves overwriting the previous performance analysis chains stored in the address space with a predetermined number of new performance analysis chains.

16. The method according to claim 13, characterized in that, The method further includes: By the DMA engine: Real-time acquisition of physical performance data of the PCIe physical layer; and The physical performance data is transmitted to the bus in real time.

17. The method according to any one of claims 13-16, characterized in that, The PCIe controller is located in at least one of the device side and the host side, and the method further includes: a DMA engine in the PCIe controller located in one of the device side and the host side. The performance analysis information corresponding to the write request used for performance analysis is transmitted to the bus of the other of the device side and the host side; or The performance analysis information corresponding to the read request used for performance analysis is transmitted to the bus on the device side or the bus on the host side, wherein the bus is a control bus.

18. An electronic device, characterized in that, The electronic device includes at least one processing unit and a memory; wherein... The memory stores computer-readable instructions and is communicatively connected to the at least one processing unit; The at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the method according to any one of claims 13-17.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-readable instructions that, when executed by a processor, implement the method according to any one of claims 13-17.

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