Printed circuit board and manufacturing method thereof

Abstract

The present disclosure relates to a printed circuit board and a method of manufacturing the same, the printed circuit board including: a frame having a through portion; the glass layer is at least partially arranged in the through part; a first insulating material filling at least a portion of a space between the frame and the glass layer; a second insulating material disposed on an upper side of the frame and the glass layer; and a third insulating material disposed on a lower side of the frame and the glass layer, and the first insulating material includes a material different from the second insulating material and the third insulating material.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0086013, filed on July 1, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2025-0013970, filed on February 4, 2025, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entireties by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a printed circuit board and a manufacturing method thereof. BACKGROUND

[0003] Efforts to improve the performance of electronic products are shifting from semiconductors to packaging, and products utilizing a glass substrate, such as a large-area substrate for servers, are attracting attention as next-generation technology. In terms of heat dissipation, warpage control, large area, and microcircuit implementation, a glass substrate can have advantages over an organic substrate formed using an epoxy resin material. However, a glass substrate can be broken due to the occurrence and propagation of cracks during processing or transportation. In this case, glass particles can enter the product through various paths such as processing equipment or chemicals, which can cause product defects. Therefore, there is a need to address the problem of cracks or breakage of glass. SUMMARY

[0004] An aspect of the present disclosure is to provide a printed circuit board including a glass layer and capable of effectively preventing cracks or breakage of glass and a manufacturing method thereof.

[0005] In one solution proposed in the present disclosure, at least a portion of a glass layer is disposed in a frame having a through portion, and in this case, a first insulating material filling at least a portion of a space between the frame and the glass layer is formed of a different material from second and third insulating materials respectively disposed on upper and lower sides of the frame and the glass layer.

[0006] For example, a printed circuit board according to an embodiment can include a frame having a through portion, a glass layer disposed at least partially within the through portion, a first insulating material filling at least a portion of a space between the frame and the glass layer, a second insulating material disposed on an upper side of the frame and the glass layer with respect to a thickness direction of the frame and the glass layer, and a third insulating material disposed on a lower side of the frame and the glass layer with respect to the thickness direction of the frame and the glass layer, the first insulating material can include a different material from the second and third insulating materials.

[0007] For example, a printed circuit board according to an embodiment may include: a glass layer; a frame spaced apart from and surrounding a side surface of the glass layer; a first insulating material filling at least a portion of the space between the glass layer and the frame; a second insulating material covering at least a portion of each of the upper surface of the glass layer, the upper surface of the frame, and the upper surface of the first insulating material; and a third insulating material covering at least a portion of each of the lower surface of the glass layer, the lower surface of the frame, and the lower surface of the first insulating material, wherein the first insulating material and the second insulating material may have physically distinct boundaries, and the first insulating material and the third insulating material may have physically distinct boundaries.

[0008] For example, a method for manufacturing a printed circuit board may include: preparing a frame having a through portion; disposing at least a portion of a glass layer within the through portion; filling at least a portion of the space between the frame and the glass layer with a first insulating material; forming a second insulating material on the upper side of each of the frame, the glass layer, and the first insulating material, the second insulating material comprising a material different from the first insulating material; and forming a third insulating material on the lower side of each of the frame, the glass layer, and the first insulating material, the third insulating material comprising a material different from the first insulating material.

[0009] For example, a printed circuit board according to an embodiment may include: a frame having a through portion; a glass layer at least partially disposed within the through portion, the sidewalls of the glass layer being spaced apart from the inner sidewalls of the through portion of the frame; a first insulating material filling at least a portion of the space between the frame and the glass layer; and a second insulating material configured to contact the surfaces of the frame and the glass layer, wherein the coefficient of thermal expansion of the first insulating material may be greater than the coefficient of thermal expansion of the glass layer, and the coefficient of thermal expansion of the second insulating material may be less than the coefficient of thermal expansion of the glass layer.

[0010] One advantage of this disclosure is that it provides a printed circuit board and a method for manufacturing the same, the printed circuit board including a glass layer and capable of effectively preventing cracks or breakage of the glass. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will be more clearly understood through the following specific embodiments in conjunction with the accompanying drawings, in which: Figure 1 It is a block diagram that schematically illustrates an example of an electronic device system; Figure 2 This is a schematic cross-sectional view illustrating an example of a printed circuit board; Figure 3 yesFigure 2 A schematic cut plan view of a printed circuit board taken along line A-A'; Figure 4 Schematic illustration of the work by Figure 2 The direction of various stresses generated by the frame, glass layer, and first to third insulating materials of the printed circuit board; Figures 5A to 5G It is a schematic representation of manufacturing. Figure 2 A process diagram of an example printed circuit board; Figure 6A and Figure 6B This is a schematic diagram illustrating an example of setting multiple glass layers in a frame with multiple through-sections; Figure 7 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 8 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 9 This is a schematic cross-sectional view illustrating another example of a printed circuit board; and Figure 10 This is a schematic cross-sectional view illustrating another example of a printed circuit board. Detailed Implementation

[0012] In the following description, this disclosure will be made with reference to the accompanying drawings. In the drawings, for the purpose of clearer description, the shape and size of the elements may be exaggerated or reduced.

[0013] Figure 1 This is a block diagram that schematically illustrates an example of an electronic device system.

[0014] Reference Figure 1 The electronic device 1000 houses a motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the motherboard 1010. These components are also connected to other electronic components, which will be described below, via various signal lines 1090.

[0015] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips and / or electronic components.

[0016] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the IEEE 802.11 series), Global Microwave Access Interoperability (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolved Data Optimized (Ev-DO), High Speed ​​Packet Access+ (HSPA+), High Speed ​​Downlink Packet Access+ (HSDPA+), High Speed ​​Uplink Packet Access+ (HSUPA+), Global System for Mobile Communications (GSM), Evolution of GSM with Enhanced Data Rates (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (LAN), 3G, 4G, and 5G protocols, and any other wireless or wired standards or protocols specified after the foregoing. However, network-related components 1030 are not limited to these and may also include components compatible with or operating according to any of a variety of other wireless or wired standards or protocols. In addition, network-related component 1030 can be combined with chip-related component 1020.

[0017] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components in the form of chip modules for various other purposes. Furthermore, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0018] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited to these and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0019] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, and server. However, electronic device 1000 is not limited to these, and can be any other electronic device capable of processing data in addition to the aforementioned electronic devices.

[0020] Figure 2 This is a schematic cross-sectional view of an example of a printed circuit board.

[0021] Figure 3 yes Figure 2 A schematic cut plan view of a printed circuit board taken along line A-A'.

[0022] Figure 4 Schematic illustration of the work by Figure 2 The direction of various stresses generated by the frame, glass layer, and first to third insulating materials of the printed circuit board.

[0023] Reference Figures 2 to 4The printed circuit board 100A according to an example embodiment may include: a frame 115 having a through portion H; a glass layer 111 at least partially disposed within the through portion H; a first insulating material 112 filling at least a portion of the space between the frame 115 and the glass layer 111; a second insulating material 113 disposed on the upper side of the frame 115 and the glass layer 111; and a third insulating material 114 disposed on the lower side of the frame 115 and the glass layer 111. The second insulating material 113 may cover at least a portion of each of the upper surface of the frame 115, the upper surface of the glass layer 111, and the upper surface of the first insulating material 112, and may, for example, contact at least a portion of each of the upper surface of the frame 115, the upper surface of the glass layer 111, and the upper surface of the first insulating material 112. The third insulating material 114 may cover at least a portion of the lower surface of the frame 115, the lower surface of the glass layer 111, and the lower surface of the first insulating material 112, and may, for example, contact at least a portion of the lower surface of the frame 115, the lower surface of the glass layer 111, and the lower surface of the first insulating material 112. Here, "upper" and "lower" are relative to the thickness direction of the frame 115 and the glass layer 111, and "upper / lower side" can be understood as upper / lower or upper / lower surface; correspondingly, "disposed on the upper / lower surface" does not exclude the case where it is disposed on the upper / lower surface.

[0024] like Figure 4 As shown, when the second insulating material 113 and the third insulating material 114 shrink during the process (e.g. Figure 4 When the middle arrow a is shown, tensile stress may occur in glass layer 111 (as shown in the middle arrow a). Figure 4 (As indicated by arrow b). In this case, cracks or fractures may occur at the corners of glass layer 111. To resolve cracks or fractures, compressive stresses generated by frame 115 and / or the first insulating material 112 (such as...) are required. Figure 4 (As indicated by arrow c). In this case, cracks or breakage in the glass layer 111 can be effectively prevented. From this perspective, the first insulating material 112 may comprise a material different from the second insulating material 113 and the third insulating material 114. Here, different materials may mean that the material composition, electrical properties (e.g., dielectric constant and dielectric strength), thermal properties (e.g., thermal conductivity and coefficient of thermal expansion), and mechanical properties (e.g., strength and flexibility) are different. For example, the basic components of the materials used in each insulating material may be different from each other, or even if each insulating material includes the same components, the mixing ratio of the components, the type and content of additives, and the material processing methods (e.g., curing conditions, particle distribution, mixing uniformity) may be different. Due to these differences, each insulating material may exhibit different characteristics in terms of electrical properties, thermal stability, environmental durability, physical strength, or suitability for manufacturing processes.

[0025] For example, the coefficient of thermal expansion of each of the second insulating material 113 and the third insulating material 114 may be less than the coefficient of thermal expansion of the glass layer 111. In this case, the aforementioned tensile stress (such as...) can be reduced. Figure 4 (As indicated by arrow b) Minimize. Additionally, the coefficient of thermal expansion of each of the frame 115 and the first insulating material 112 can be greater than the coefficient of thermal expansion of the glass layer 111. In this case, the aforementioned compressive stress (as shown by arrow b) can be effectively generated. Figure 4 (As indicated by arrow c). Therefore, cracks or breakage in the glass layer 111 can be effectively prevented. Here, the coefficient of thermal expansion (CTE) can be a physical property representing the degree to which a material expands or contracts with respect to temperature changes. This CTE can be measured by preparing multiple samples by separating the measurement target (e.g., each insulating material, frame, and / or glass layer) in the final product via physical cutting or chemical processing, and then using a thermomechanical analyzer (TMA), X-ray diffraction analysis (XRD), interferometer, digital image analysis, etc. The CTE can be compared by standardizing measurement conditions such as stress state, axial direction, thickness, and temperature range, and if the conditions differ, the data can be normalized or divided by a specific reference value to assess relative magnitudes.

[0026] As a more specific example, frame 115 may have a coefficient of thermal expansion of about 5 ppm / °C to about 30 ppm / °C, glass layer 111 may have a coefficient of thermal expansion of about 3 ppm / °C to about 10 ppm / °C, first insulating material 112 may have a coefficient of thermal expansion of about 10 ppm / °C to about 20 ppm / °C, and second insulating material 113 and third insulating material 114 may each have a coefficient of thermal expansion of about 2 ppm / °C to about 10 ppm / °C. For example, frame 115 may have a coefficient of thermal expansion of about 30 ppm / °C, glass layer 111 may have a coefficient of thermal expansion of about 7 ppm / °C, first insulating material 112 may have a coefficient of thermal expansion of about 15 ppm / °C, and each of second insulating material 113 and third insulating material 114 may have a coefficient of thermal expansion of about 5 ppm / °C. As another example, frame 115 may have a coefficient of thermal expansion of about 30 ppm / °C, glass layer 111 may have a coefficient of thermal expansion of about 4 ppm / °C, first insulating material 112 may have a coefficient of thermal expansion of about 15 ppm / °C, and each of second insulating material 113 and third insulating material 114 may have a coefficient of thermal expansion of about 3 ppm / °C. The coefficient of thermal expansion may be measured in the X / Y direction or in the Z direction at any of the following temperature conditions: below the glass transition temperature, from 25°C to 150°C, or from 150°C to 240°C.

[0027] Furthermore, each of the first insulating material 112, the second insulating material 113, and the third insulating material 114 may include an insulating resin and an inorganic filler, and in this case, the content ratio of the inorganic filler included in the first insulating material 112 may be less than the content ratio of the inorganic filler included in each of the second insulating material 113 and the third insulating material 114. For example, in the same cut cross section, the area ratio of the inorganic filler included in the first insulating material 112 may be less than the area ratio of the inorganic filler included in the second insulating material 113 and the area ratio of the inorganic filler included in the third insulating material 114, respectively. In this case, the coefficient of thermal expansion of the first insulating material 112 may be greater than the coefficient of thermal expansion of each of the second insulating material 113 and the third insulating material 114. Therefore, the aforementioned compressive stress (e.g., ...) can be effectively generated through the first insulating material 112. Figure 4 (As shown by arrow c), this effectively prevents cracks or breakages in glass layer 111. Here, the area ratio refers to the ratio of the area occupied by inorganic filler per unit area, and the area ratio can be measured by obtaining images of cross-sections cut along arbitrary directions using a scanning electron microscope or optical microscope, and then using image analysis software to distinguish and calculate the area of ​​the inorganic filler and the area of ​​the insulating resin. For example, inorganic fillers can be identified during analysis based on their contrast, color difference, or unique shape, and the areas of inorganic fillers in specific regions can be summed and converted into a ratio to the total cross-sectional area. Therefore, the area ratio of inorganic fillers for each type of insulating material can be compared. When the area ratios are nearly identical, values ​​at five arbitrary cut sections can be measured, and the average of the measured values ​​can then be compared.

[0028] Furthermore, the second insulating material 113 and the third insulating material 114 may include glass fibers (e.g., glass fabric, such as glass cloth) as core materials, while the first insulating material 112 may not include a core material such as glass fibers. In this case, the first insulating material 112 can be more easily formed in the space between the frame 115 and the glass layer 111, and process warpage can be controlled more effectively by the second insulating material 113 and the third insulating material 114. Additionally, the ratio (e.g., area ratio) of the inorganic filler content of each of the first insulating material 112, the second insulating material 113, and the third insulating material 114 can be more effectively satisfied. Furthermore, the coefficient of thermal expansion of each of the first insulating material 112, the second insulating material 113, and the third insulating material 114 can be more effectively satisfied. Therefore, cracking or breakage of the glass layer 111 can be effectively prevented.

[0029] Additionally, the frame 115 may comprise a material with excellent rigidity and may include, for example, a copper-clad laminate (CCL) or a bare copper-clad laminate (bare CCL). In this case, as described below, panel-level processes can be performed via the frame 115, thus facilitating process warpage control. Furthermore, by allowing the frame 115 to remain in the final substrate unit after the dicing process, structural warpage control is structurally advantageous. Additionally, by utilizing a material with a coefficient of thermal expansion greater than that of the glass layer 111 as the material of the frame 115, the aforementioned compressive stresses (such as...) can be generated. Figure 4 (As indicated by the middle arrow c), thereby more effectively preventing cracks or breakages in the glass layer 111 during the process.

[0030] As a more specific example, frame 115 may include epoxy resin, silica filler, and silica fabric; first insulating material 112 may include epoxy resin and silica filler; and each of second insulating material 113 and third insulating material 114 may include epoxy resin, silica filler, and silica fabric. Furthermore, to satisfy the aforementioned coefficient of thermal expansion relationship, glass layer 111 may preferably include SiO2, B2O3, Al2O3, Na2O, K2O, and / or CaO.

[0031] The first insulating material 112, the second insulating material 113, and the third insulating material 114 can be separate insulating layers with mutually distinguishable boundaries. For example, the first insulating material 112, the second insulating material 113, and the third insulating material 114 are each independent insulating layer, and there are easily distinguishable boundaries between them. For example, the first insulating material 112 may comprise a different material from the second insulating material 113 and the third insulating material 114, so that their boundaries are mutually distinguishable. Specifically, the first insulating material 112 and the second insulating material 113 may have physical boundaries with each other (e.g., boundaries that are physically distinct from each other), and the first insulating material 112 and the third insulating material 114 may have physical boundaries with each other. In this case, cracking or breakage of the glass layer 111 can be effectively prevented. In this case, the upper surface of the first insulating material 112 may be substantially coplanar with the upper surface of the glass layer 111, and the lower surface of the first insulating material 112 may be substantially coplanar with the lower surface of the glass layer 111. In this structure, the compressive stress (e.g., as described above) generated by the first insulating material 112 is effectively prevented. Figure 4 (As indicated by arrow c), cracking or breakage of the glass layer 111 can be more effectively prevented during the process. Additionally, undulations in the second insulating material 113 and the third insulating material 114 can be prevented. Therefore, flatness can be increased, which is more advantageous for realizing microcircuits.

[0032] Reference Figure 2The printed circuit board 100A according to the example embodiment may further include: a through-hole 131 penetrating the glass layer 111; a first connection via 132 penetrating the second insulating material 113 and connected to the upper side (e.g., the upper surface) of the through-hole 131; a second connection via 133 penetrating the third insulating material 114 and connected to the lower side (e.g., the lower surface) of the through-hole 131; a first interconnect layer 121 disposed on the upper surface of the second insulating material 113 and at least a portion of the first interconnect layer 121 connected to the first connection via 132; and / or a second interconnect layer 122 disposed on the lower surface of the third insulating material 114 and at least a portion of the second interconnect layer 122 connected to the second connection via 133. Therefore, various interconnect designs can be implemented. Additionally, various electrical connection paths can be provided. The first connection via 132 and the second connection via 133 can directly contact the upper and lower surfaces of the through-hole 131, respectively, and in this case, a thinner structure can be achieved.

[0033] The through-hole 131 can be a through-glass via (TGV). The through-hole 131 may include first seed layers m1 and m2, which have a multilayer structure formed by a sputtering process. For example, the through-hole 131 may include: first seed layers m1 and m2 disposed on the wall surface of the via penetrating the glass layer 111; and a first metal layer M disposed on the first seed layers m1 and m2 to fill at least a portion of the via. In this case, the first seed layers m1 and m2 may include a first layer m1 comprising a sputtered titanium layer and a second layer m2 comprising a sputtered copper layer (the second layer m2 is disposed on the first layer m1), and the first metal layer M may include an electroplated copper layer. Each of the vias and the through-holes 131 formed within the vias may have an hourglass shape in cross-section, but this disclosure is not limited thereto. The upper and lower surfaces of the through-hole 131 may be substantially coplanar with the upper and lower surfaces of the glass layer 111, respectively, but this disclosure is not limited thereto, and the upper and lower surfaces of the through-hole 131 may be more recessed inward than the upper and lower surfaces of the glass layer 111, respectively. The recessed spaces on the upper and lower surfaces of the through-hole 131 may be at least partially filled with the second insulating material 113 and the third insulating material 114, respectively.

[0034] Additionally, each of the first connection via 132 and the second connection via 133 may be a blind via (BV). The first connection via 132 may include a second seed layer n formed by an electroless plating process. For example, the first connection via 132 may include: a second seed layer n disposed on the wall surface of the first via that penetrates the second insulating material 113 and exposes the upper surface of the through via 131 (the second seed layer n may also be disposed on the exposed upper surface of the through via 131); and a second metal layer N disposed on the second seed layer n and filling at least a portion of the first via, and in this case, the second seed layer n may include a chemically plated copper layer, and the second metal layer N may include an electrolytically plated copper layer. In substantially the same manner, the second connection via 133 may include: a third seed layer disposed on the wall surface of the second via that penetrates the third insulating material 114 and exposes the lower surface of the through-hole 131 (the third seed layer may also be disposed on the exposed lower surface of the through-hole 131); and a third metal layer disposed on the third seed layer and filling at least a portion of the second via, wherein the third seed layer may include a chemically plated copper layer and the third metal layer may include an electrolytically plated copper layer. The first connection via 132 and the second connection via 133 may have a generally tapered shape in opposite directions in cross-section. For example, the first via and the first connection via 132 formed in the first via may have a generally tapered shape in cross-section where the width at their upper end is greater than the width at their lower end, and the second via and the second connection via 133 formed in the second via may have a generally tapered shape in cross-section where the width at their lower end is greater than the width at their upper end, but this disclosure is not limited thereto.

[0035] Reference Figure 2According to the example embodiment, the printed circuit board 100A may further include a first stacked layer 140 disposed on the upper side of the second insulating material 113 and a second stacked layer 150 disposed on the lower side of the third insulating material 114. The first stacked layer 140 may include: a plurality of first stacked insulating layers 141 stacked on the upper surface of the second insulating material 113; a plurality of first stacked interconnect layers 142 respectively disposed on the upper surface of the plurality of first stacked insulating layers 141 or within the plurality of first stacked insulating layers 141; and a plurality of first stacked via layers 143 respectively disposed within the plurality of first stacked insulating layers 141. The second stacked layer 150 may include: a plurality of second stacked insulating layers 151 stacked on the lower surface of the third insulating material 114; a plurality of second stacked interconnect layers 152 respectively disposed on the lower surface of the plurality of second stacked insulating layers 151 or within the plurality of second stacked insulating layers 151; and a plurality of second stacked via layers 153 respectively disposed within the plurality of second stacked insulating layers 151. Electrical connection paths from the top to the bottom of the substrate can be provided through multiple first stacked interconnect layers 142 and multiple second stacked interconnect layers 152, as well as multiple first stacked via layers 143 and multiple second stacked via layers 153. For example, the printed circuit board 100A according to an exemplary embodiment may include a glass layer 111, a first insulating material 112, a second insulating material 113 and a third insulating material 114, and a frame 115 as a core layer, and may have a multilayer substrate structure with first stacked layers 140 and second stacked layers 150 stacked on both sides of the core layer. Therefore, the printed circuit board 100A can be easily applied to large-area packaging substrates.

[0036] A first solder resist layer 161 having a plurality of first openings 161h that expose at least a portion of the uppermost first stacked interconnect layer 142 may be disposed on the upper surface of the uppermost first stacked insulating layer 141, and a second solder resist layer 162 having a plurality of second openings 162h that expose at least a portion of the lowermost second stacked interconnect layer 152 may be disposed on the lower surface of the lowermost second stacked insulating layer 151. A plurality of first electrical connection metals 181 connected to at least a portion of the exposed portion of the uppermost first stacked interconnect layer 142 may be disposed on the plurality of first openings 161h, and a plurality of second electrical connection metals 183 connected to at least a portion of the exposed portion of the lowermost second stacked interconnect layer 152 may be disposed on the plurality of second openings 162h. A first electronic component 171 and a second electronic component 172 connected to the plurality of first electrical connection metals 181 may be mounted on the upper surface of the first solder resist layer 161. For example, the printed circuit board 100A according to the example embodiment may have a package structure in which electronic components are mounted on a package substrate.

[0037] The components of the printed circuit board 100A will be described in more detail below with reference to the accompanying drawings.

[0038] Glass layer 111 may comprise glass, which is an amorphous solid. The glass may include, for example, pure silica (about 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, this disclosure is not limited to these, and alternative glass materials (e.g., fluorine glass, phosphate glass, chalcogenide glass, etc.) may also be used. Furthermore, other additives may be included to form a glass with specific physical properties. Such additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda ash), but also carbonates and / or oxides of magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as these and other elements. Glass layer 111 may be a layer distinct from organic insulating material layers (such as copper-clad laminates (CCL) and prepregs (PPG)) that include glass fibers (e.g., glass fabrics, such as glass cloth). For example, glass layer 111 may comprise a glass panel that can be scalable to a large area, such as a glass plate.

[0039] Each of the first insulating material 112, the second insulating material 113, and the third insulating material 114 may include an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabric, such as glass cloth) in these resins. For example, the first insulating material 112 may include adhesive sheets such as bonding sheets (BS), fillers, etc., but this disclosure is not limited thereto. Additionally, the second insulating material 113 and the third insulating material 114 may include non-photosensitive insulating materials (such as Ajinomoto laminate (ABF), prepreg (PPG)) or photosensitive insulating materials (such as photosensitive dielectric (PID)), but this disclosure is not limited thereto.

[0040] Frame 115 may include an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabric, such as glass cloth) in these resins. For example, the organic insulating material may be copper-clad laminate (CCL), bare CCL, etc., but this disclosure is not limited thereto. If desired, other materials besides organic insulating materials, such as ceramics or metals, may also be used as the material of frame 115, and in this case, the material may be selected considering the coefficient of thermal expansion. The through-portion H may penetrate the region between the upper and lower surfaces of frame 115. Frame 115 may be spaced apart from glass layer 111 and may surround the side surfaces of glass layer 111. The upper and lower surfaces of frame 115 may be substantially coplanar with the upper and lower surfaces of glass layer 111, respectively, and the upper and lower surfaces of frame 115 may also be substantially coplanar with the upper and lower surfaces of first insulating material 112, respectively. When the frame 115 includes copper foil, the upper and lower surfaces of the frame 115 can be determined by taking the copper foil into account.

[0041] Each of the first interconnect layer 121 and the second interconnect layer 122 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first interconnect layer 121 and the second interconnect layer 122 may perform various functions according to the design. For example, the first interconnect layer 121 and the second interconnect layer 122 may include signal patterns, power patterns, and ground patterns. These patterns may have various shapes, such as lines, planes, pads, etc. The first interconnect layer 121 and the second interconnect layer 122 may include electroless plating layers (e.g., electroless copper plating) and electrolytic plating layers (e.g., electrolytic copper plating).

[0042] Through-hole 131 may include metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Through-hole 131 may perform various functions depending on the design. For example, through-hole 131 may include grounding vias, power vias, and signal vias. Through-hole 131 may have a generally circular or generally elliptical shape in a plane, and may have a generally hourglass shape in cross-section, but this disclosure is not limited thereto. Through-hole 131 may include sputtered layers (e.g., multiple sputtered metal layers) and electroplated layers (e.g., electroplated copper layers). Multiple through-holes 131 may be provided.

[0043] Each of the first connection via 132 and the second connection via 133 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the first connection via 132 and the second connection via 133 may include not only a filled via that fills a via hole, but also a conformal via disposed along the wall surface of a via hole. The first connection via 132 and the second connection via 133 may perform various functions depending on the design. For example, the first connection via 132 and the second connection via 133 may include grounding vias, power vias, and signal vias. The first connection via 132 and the second connection via 133 may have a generally tapering shape in opposite directions in cross-section, but this disclosure is not limited thereto. Each of the first connection via 132 and the second connection via 133 may include an electroless plating layer (e.g., a chemically plated copper layer) and an electrolytic plating layer (e.g., an electrolytically plated copper layer). Each of the first connecting via 132 and the second connecting via 133 can be configured as multiple.

[0044] Each of the plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may include an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabric, such as glass cloth) in these resins. For example, the organic insulating material may be a non-photosensitive insulating material (such as Ajinomoto laminate (ABF) or prepreg (PPG)), but this disclosure is not limited thereto, and other polymeric materials may be used as the organic insulating material. Alternatively, the organic insulating material may be a photosensitive insulating material (such as photosensitive dielectric (PID)). The plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may include substantially the same organic insulating material, but this disclosure is not limited thereto. The plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may have the same number of layers, but this disclosure is not limited thereto. Each of the first stacked insulating layer 141 and the second stacked insulating layer 151 may include one or more layers, as needed.

[0045] Each of the plurality of first stacked interconnect layers 142 and the plurality of second stacked interconnect layers 152 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the plurality of first stacked interconnect layers 142 and the plurality of second stacked interconnect layers 152 may perform various functions according to the design. For example, the plurality of first stacked interconnect layers 142 and the plurality of second stacked interconnect layers 152 may include signal patterns, power patterns, and ground patterns. Each pattern may have various shapes, such as lines, planes, and pads. Each of the plurality of first stacked interconnect layers 142 and the plurality of second stacked interconnect layers 152 may include an electroless plating layer (e.g., a chemically plated copper layer) and an electrolytic plating layer (e.g., an electrolytically plated copper layer). The plurality of first stacked interconnect layers 142 and the plurality of second stacked interconnect layers 152 may have the same number of layers, but this disclosure is not limited thereto. Each of the first stacked interconnect layers 142 and the second stacked interconnect layers 152 may include one or more layers as needed.

[0046] Each of the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may include not only filled vias that fill through-holes, but also conformal vias disposed along the wall surface of through-holes. Each of the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may perform various functions according to design. For example, the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may include grounding vias, power vias, and signal vias. The plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may have a generally tapering shape in opposite directions in cross-section. Each of the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may include an electroless plating layer (e.g., a chemically plated copper layer) and an electrolytic plating layer (e.g., an electrolytically plated copper layer). The plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may have the same number of layers, but this disclosure is not limited thereto. As needed, each of the first stacked via layers 143 and the second stacked via layers 153 may include one or more layers.

[0047] The first solder resist layer 161 and the second solder resist layer 162 may comprise liquid solder resist or film solder resist, but this disclosure is not limited thereto, and other types of insulating materials such as ABF may be used. Surface treatment layers and / or metal bumps may be formed on the respective patterns exposed through the plurality of first openings 161h and the plurality of second openings 162h, as needed. Each pattern exposed through the plurality of first openings 161h and the plurality of second openings 162h may be solder mask defined (SMD) type and / or non-solder mask defined (NSMD) type, but this disclosure is not limited thereto. Each of the first openings 161h and the second openings 162h may be provided in multiples.

[0048] Multiple first electrical connection metals 181 and multiple second electrical connection metals 183 may be formed using low-melting-point metals (e.g., solders such as tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example, and the materials are not particularly limited thereto. The multiple first electrical connection metals 181 and multiple second electrical connection metals 183 may be solder balls, pins, etc. Each of the multiple first electrical connection metals 181 and multiple second electrical connection metals 183 may be formed by multiple layers or a single layer. When the multiple first electrical connection metals 181 and multiple second electrical connection metals 183 are formed by multiple layers, they may include copper pillars and solder, and when the multiple first electrical connection metals 181 and multiple second electrical connection metals 183 are formed by a single layer, they may include tin-silver solder, but this disclosure is not limited thereto. The multiple first electrical connection metals 181 may be used to mount a first electronic component 171 and a second electronic component 172, and the multiple second electrical connection metals 183 may be used to mount a printed circuit board 100A according to an example onto another substrate such as a motherboard.

[0049] Each of the first electronic component 171 and the second electronic component 172 may include active components and / or passive components. Active components may include various types of semiconductor chips, and passive components may include various types of chip components (such as chip capacitors or chip inductors). Passive components may also include integrated passive devices (IPDs). Each of the semiconductor chips may include an integrated circuit (IC) die in which hundreds to millions of components are integrated into a single chip. The integrated circuit die may be, for example: application processor (AP) chips, such as central processing units (e.g., CPUs), graphics processing units (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, microcontrollers; logic chips, such as field-programmable gate arrays (FPGAs), analog-to-digital converters, and application-specific integrated circuits (ASICs), but not limited thereto, and may also be memory chips (such as volatile memory (e.g., DRAM, high-bandwidth memory (HBM)), non-volatile memory (e.g., ROM, flash memory)) or other types of chips (such as power management ICs (PMICs)). Additionally, each of the first electronic component 171 and the second electronic component 172 may have multiple functions integrated into a single chip (such as a system-on-a-chip (SoC)).

[0050] Figures 5A to 5G It is a schematic representation of manufacturing. Figure 2 A process diagram of an example printed circuit board.

[0051] Reference Figure 5A A glass layer 111 can be prepared. The glass layer 111 can be in the form of a glass plate. Therefore, the glass layer 111 can be easily applied to large-area substrates. The glass layer 111 can have a generally rectangular shape in cross-section, and can have a generally square or generally rectangular shape in plane.

[0052] Reference Figure 5B A through-hole 131 penetrating the glass layer 111 can be formed. For example, the through-hole can be formed in the glass layer 111 by various methods such as laser processing, machining, and chemical processing. First seed layers m1 and m2 can be formed on the wall surfaces of the through-hole, and a first metal layer M filling at least a portion of the through-hole can be formed on the first seed layers m1 and m2, thereby forming the through-hole 131. The through-hole can be formed to penetrate the glass layer 111 and have a generally hourglass shape in cross-section. The first seed layers m1 and m2 can be formed using a sputtering process with materials including titanium and materials including copper. The first metal layer M can be formed using an electrolytic plating process with a material including copper. The plating on the upper and lower surfaces of the glass layer 111 can be removed by etching.

[0053] Reference Figure 5CAt least a portion of the glass layer 111 can be disposed within the through-portion H of the frame 115. For example, a strip 220 blocking the lower side of the through-portion H can be attached to the lower side of the frame 115, and then the glass layer 111 can be attached to the strip 220 exposed from the through-portion H. The frame 115 may have a clamp shape. The strip 220 may include polyimide (PI) or the like, but the material is not particularly limited thereto. The frame 115 having the through-portion H can be prepared before, simultaneously with, or after the preparation of the glass layer 111.

[0054] Reference Figure 5D The first insulating material 112 can be used to fill at least a portion of the space between the frame 115 and the glass layer 111. For example, the first insulating material 112 can be used to fill the remaining space of the through portion H. Additionally, a second insulating material 113, comprising a material different from the first insulating material 112, can be formed on the upper side of each of the frame 115, the glass layer 111, and the first insulating material 112. Planarization can be performed if necessary.

[0055] Reference Figure 5E The strip 220 can be removed, and a third insulating material 114 can be formed on the underside of each of the frame 115, the glass layer 111, and the first insulating material 112. The third insulating material 114 comprises a material different from the first insulating material 112. The second insulating material 113 and the third insulating material 114 may comprise substantially the same material. Planarization can be performed if necessary.

[0056] Reference Figure 5FA first connection via 132 and a first interconnect layer 121 may be formed. The first connection via 132 penetrates the second insulating material 113 and is connected to the upper surface of the through-hole 131. The first interconnect layer 121 is disposed on the upper surface of the second insulating material 113, and at least a portion of the first interconnect layer 121 is connected to the first connection via 132. Additionally, a second connection via 133 and a second interconnect layer 122 may be formed. The second connection via 133 penetrates the third insulating material 114 and is connected to the lower surface of the through-hole 131. The second interconnect layer 122 is disposed on the lower surface of the third insulating material 114, and at least a portion of the second interconnect layer 122 is connected to the second connection via 133. For example, a first via 132 can be formed by penetrating the second insulating material 113 and having a generally tapered shape in cross-section where the width at its upper end is greater than the width at its lower end. A second seed layer n can be formed on the wall surface of the first via 132 using a copper-based material through an electroless plating process, and a second metal layer N filling at least a portion of the first via 132 can be formed on the second seed layer n using a copper-based material through an electrolytic plating process. Similarly, a second via 133 can be formed by penetrating the third insulating material 114 and having a generally tapered shape in cross-section where the width at its lower end is greater than the width at its upper end. A third seed layer can be formed on the wall surface of the second via 133 using a copper-based material through an electroless plating process, and a third metal layer filling at least a portion of the second via 133 can be formed on the third seed layer using a copper-based material through an electrolytic plating process. When forming the first via 132 and the second via 133, the first interconnect layer 121 and the second interconnect layer 122 can also be formed together accordingly.

[0057] Reference Figure 5G A first stacked layer 140 and a second stacked layer 150 can be formed on the upper side of the second insulating material 113 and the lower side of the third insulating material 114, respectively. For example, by using a stacking process and a plating process, a plurality of first stacked insulating layers 141 and a plurality of second stacked insulating layers 151, a plurality of first stacked interconnect layers 142 and a plurality of second stacked interconnect layers 152, and a plurality of first stacked via layers 143 and a plurality of second stacked via layers 153 can be formed, thereby forming the first stacked layer 140 and the second stacked layer 150. In addition, a first solder resist layer 161 and a second solder resist layer 162 can be formed by a lamination process or a coating process. In addition, a plurality of first openings 161h and a plurality of second openings 162h can be formed in the first solder resist layer 161 and the second solder resist layer 162, respectively, by laser processing or photolithography. If necessary, a plurality of first electrical connection metals and a plurality of second electrical connection metals can be formed, and a first electronic component and a second electronic component can be mounted.

[0058] The printed circuit board 100A described above can be manufactured through a series of processes. Other details are substantially the same as those described in the printed circuit board 100A according to the above example embodiment.

[0059] Figure 6A and Figure 6B This is a schematic diagram illustrating an example of setting multiple glass layers in a frame with multiple through-sections.

[0060] Reference Figure 6A and Figure 6B The frame 115 may have multiple through-sections H, and multiple glass layers 111 may be respectively disposed in the multiple through-sections H. Each of the multiple glass layers 111 may have the above-described... Figures 5A to 5B The through hole 131 is formed by the manufacturing process described above, and can be used. Figure 5C In the manufacturing process, each of the plurality of glass layers 111 is disposed in each of the plurality of through-sections H. Then, the above-described process can be performed. Figures 5D to 5G The manufacturing process is used to produce a panel substrate comprising multiple printed circuit board (PCB) units 100A. Multiple PCBs 100A can then be obtained by cutting the space between multiple through-holes H. For example, multiple PCB units 100A can be manufactured together using panel-level processes, and multiple PCB units 100A can be separated individually using a splitting process. Therefore, this facilitates process warpage control and results in excellent productivity.

[0061] Other details are substantially the same as those described in the printed circuit board 100A and its manufacturing example according to the above example.

[0062] Figure 7 This is a schematic cross-sectional view illustrating another example of a printed circuit board.

[0063] Reference Figure 7 Compared to the printed circuit board 100A according to the above-described example embodiment, the printed circuit board 100B according to another example embodiment may further include a third electronic component 173 mounted on a first solder resist layer 161 via a plurality of first electrical connection metals 181. Additionally, the printed circuit board 100B may also include a first electronic component 191, a second electronic component 192, and a third electronic component 193, which are embedded in a plurality of first stacked insulating layers 141 and connected to at least a portion of at least a plurality of first stacked interconnect layers 142 via at least a portion of at least one of the plurality of first stacked via layers 143. For example, the printed circuit board 100B according to another example embodiment may be a board in which electronic components are embedded in stacked regions.

[0064] The components of another printed circuit board 100B will be described in more detail below with reference to the accompanying drawings.

[0065] The third electronic component 173 may include active and / or passive components. Active components may include various types of semiconductor chips, and passive components may include various types of chip components (such as chip capacitors or chip inductors). Passive components may also include integrated passive devices (IPDs). Each of the semiconductor chips may include an integrated circuit (IC) die in which hundreds to millions of components are integrated into a single chip. The integrated circuit die may be, for example: application processor (AP) chips, such as central processing units (e.g., CPUs), graphics processing units (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, microcontrollers; logic chips, such as field-programmable gate arrays (FPGAs), analog-to-digital converters, and application-specific integrated circuits (ASICs), but not limited thereto, and may also be memory chips (such as volatile memory (e.g., DRAM, high-bandwidth memory (HBM)), non-volatile memory (e.g., ROM, flash memory)) or other types of chips (such as power management ICs (PMICs)). The third electronic component 173 may also have the form of multiple functions integrated into a single chip (such as a system-on-a-chip (SoC)).

[0066] Each of the first electronic component 191, the second electronic component 192, and the third electronic component 193 may include an interconnect bridge, an active component, and / or a passive component. The interconnect bridge may transmit electrical signals between at least two of the first electronic component 171, the second electronic component 172, and the third electronic component 173 via high-density circuitry therein. The interconnect bridge may be a silicon bridge, an organic bridge, etc. Active components may include various types of semiconductor chips, and passive components may include various types of chip components (such as chip capacitors or chip inductors). Passive components may include integrated passive devices (IPDs). Each of the semiconductor chips may include an integrated circuit (IC) die in which hundreds to millions of components are integrated into a single chip. In this context, the integrated circuit die can be, for example: an application processor (AP) chip, such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller; a logic chip, such as a field-programmable gate array (FPGA), an analog-to-digital converter, and an application-specific integrated circuit (ASIC), but not limited thereto; and can be a memory chip (e.g., volatile memory (e.g., DRAM, high-bandwidth memory (HBM)), non-volatile memory (e.g., ROM, flash memory)) or other types of chips (e.g., power management IC (PMIC)). Additionally, each of the first electronic component 191, the second electronic component 192, and the third electronic component 193 may also have multiple functions integrated into a single chip (e.g., a system-on-a-chip (SoC)).

[0067] Other details are substantially the same as those described in the printed circuit board 100A and its manufacturing examples according to the above example embodiments.

[0068] Figure 8 This is a schematic cross-sectional view illustrating another example of a printed circuit board.

[0069] Reference Figure 8 Compared to the printed circuit board 100A according to the above-described example embodiment, the printed circuit board 100C according to another example embodiment may further include a fourth electronic component 194 and a fifth electronic component 195 embedded in the glass layer 111. For example, the fourth electronic component 194 and the fifth electronic component 195 may be respectively disposed in cavities C1 and C2 formed in the glass layer 111 and covered with a second insulating material 113, and may be connected to at least another portion of the first interconnect layer 121 through a third connection via 134 penetrating the second insulating material 113. Cavities C1 and C2 may be blind cavities penetrating a portion of the glass layer 111 from the upper surface of the glass layer 111, but may also be through cavities penetrating between the upper and lower surfaces of the glass layer 111 as needed. For example, the printed circuit board 100C according to another example embodiment may be a board having electronic components embedded in a core region.

[0070] The components of another printed circuit board 100C will be described in more detail below with reference to the accompanying drawings.

[0071] Each of the fourth electronic component 194 and the fifth electronic component 195 may include an interconnect bridge, an active component, and / or a passive component. The interconnect bridge may transmit electrical signals between the first electronic component 171 and the second electronic component 172 via high-density circuitry therein. The interconnect bridge may be a silicon bridge, an organic bridge, etc. Active components may include various types of semiconductor chips, and passive components may include various types of chip components (such as chip capacitors or chip inductors). Passive components may also include integrated passive devices (IPDs). Each semiconductor chip may include an integrated circuit (IC) die in which hundreds to millions of components are integrated into a single chip. In this context, the integrated circuit die can be, for example: an application processor (AP) chip, such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller; a logic chip, such as a field-programmable gate array (FPGA), an analog-to-digital converter, and an application-specific integrated circuit (ASIC), but not limited thereto; and can be a memory chip (e.g., volatile memory (e.g., DRAM, high-bandwidth memory (HBM)), non-volatile memory (e.g., ROM, flash memory)) or other types of chips (e.g., power management IC (PMIC)). Additionally, each of the fourth electronic element 194 and the fifth electronic element 195 may have multiple functions integrated into a single chip (e.g., a system-on-a-chip (SoC)).

[0072] The third connection via 134 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The third connection via 134 may include not only filled vias that fill the through-hole, but also conformal vias disposed along the wall surface of the through-hole. The third connection via 134 may perform various functions depending on the design. For example, the third connection via 134 may include grounding vias, power vias, and signal vias. The third connection via 134 may have a generally tapering shape in cross-section, with its upper end wider than its lower end, but this disclosure is not limited thereto. The third connection via 134 may include electroless plating (e.g., electroless copper plating) and electrolytic plating (e.g., electrolytic copper plating). Multiple third connection vias 134 may be provided.

[0073] The technical features of the printed circuit board 100C according to another example embodiment can also be applied to the printed circuit board 100B according to the other example described above. Other details are substantially the same as those described in the printed circuit board 100A and its manufacturing example according to the above example embodiment, and the printed circuit board 100B according to the other example described above.

[0074] Figure 9 This is a schematic cross-sectional view illustrating another example of a printed circuit board.

[0075] Reference Figure 9 Compared to the printed circuit board 100A according to the above-described example embodiment, the printed circuit board 100D according to another example embodiment can be constructed such that only a first stacked layer 140 comprising a plurality of first stacked insulating layers 141, a plurality of first stacked interconnect layers 142, and a plurality of first stacked via layers 143 exists, and the second stacked layer 150 comprising a plurality of second stacked insulating layers 151, a plurality of second stacked interconnect layers 152, and a plurality of second stacked via layers 153 can be omitted. In this case, a second solder resist layer 162 may be disposed on the lower surface of a third insulating material 114 and may have a plurality of second openings 162h that expose at least a portion of the second interconnect layer 122, and a plurality of second electrical connection metals 183 may be disposed on the plurality of second openings 162h and may be connected to at least a portion of the exposed second interconnect layer 122. In addition, the printed circuit board 100D may also include a fourth electronic component 194 and a fifth electronic component 195 embedded in a glass layer 111. For example, a fourth electronic component 194 and a fifth electronic component 195 may be disposed in cavities C1 and C2 formed in the glass layer 111, respectively, and may be covered with a second insulating material 113. They may be connected to at least another portion of the first interconnect layer 121 via third connection vias 134 penetrating the second insulating material 113, respectively. Each of cavities C1 and C2 may be a blind cavity penetrating a portion of the glass layer 111 from its upper surface, but may also be a through cavity penetrating between the upper and lower surfaces of the glass layer 111, if desired. For example, a printed circuit board 100D according to another example embodiment may have an asymmetric stacking structure, and electronic components may be embedded in the core region. A printed circuit board 100D according to another example embodiment may be an electronic component embedded board with an asymmetric stacking structure, which can be readily applied to interposers, etc.

[0076] The components of another printed circuit board 100D will be described in more detail below with reference to the accompanying drawings.

[0077] The asymmetric stacking structure can be formed such that, based on a core layer comprising a glass layer 111, a first insulating material 112, a second insulating material 113, a third insulating material 114, and a frame 115, stacked layers are formed only on the upper side of the core layer. However, this disclosure is not limited thereto, and if desired, the asymmetric stacking structure can be formed such that, based on a core layer comprising a glass layer 111, a first insulating material 112, a second insulating material 113, a third insulating material 114, and a frame 115, stacked layers can be formed only on the lower side of the core layer. Optionally, if desired, the asymmetric stacking structure can be formed such that, based on a core layer comprising a glass layer 111, a first insulating material 112, a second insulating material 113, a third insulating material 114, and a frame 115, stacked layers can be formed on both the upper and lower sides of the core layer, but the number of stacked layers on the upper side of the core layer and the number of stacked layers on the lower side of the core layer may be different.

[0078] Each of the fourth electronic component 194 and the fifth electronic component 195 may include an interconnect bridge, an active component, and / or a passive component. The interconnect bridge may transmit electrical signals between the first electronic component 171 and the second electronic component 172 via high-density circuitry therein. The interconnect bridge may be a silicon bridge, an organic bridge, etc. Active components may include various types of semiconductor chips, and passive components may include various types of chip components (such as chip capacitors or chip inductors). Passive components may include integrated passive devices (IPDs). Semiconductor chips may include integrated circuit (IC) dies in which hundreds to millions of components are integrated into a single chip. In this context, the integrated circuit die can be, for example: an application processor (AP) chip, such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller; a logic chip, such as a field-programmable gate array (FPGA), an analog-to-digital converter, and an application-specific integrated circuit (ASIC), but not limited thereto; and can be a memory chip (e.g., volatile memory (e.g., DRAM, high-bandwidth memory (HBM)), non-volatile memory (e.g., ROM, flash memory)) or other types of chips (e.g., power management IC (PMIC)). Additionally, each of the fourth electronic element 194 and the fifth electronic element 195 may have multiple functions integrated into a single chip (e.g., a system-on-a-chip (SoC)).

[0079] The third connection via 134 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The third connection via 134 may include not only filled vias that fill the through-hole, but also conformal vias disposed along the wall surface of the through-hole. The third connection via 134 may perform various functions depending on the design. For example, the third connection via 134 may include grounding vias, power vias, and signal vias. The third connection via 134 may have a generally tapering shape in cross-section, with its upper end wider than its lower end, but this disclosure is not limited thereto. The third connection via 134 may include electroless plating (e.g., electroless copper plating) and electrolytic plating (e.g., electrolytic copper plating). Multiple third connection vias 134 may be provided.

[0080] The technical features of the printed circuit board 100D according to another example embodiment can also be applied to the printed circuit board 100B and the printed circuit board 100C according to the other example embodiment described above. Other details are substantially the same as those described in the printed circuit board 100A and its manufacturing example according to one example embodiment described above, the printed circuit board 100B according to another example described above, and the printed circuit board 100C according to another example embodiment described above.

[0081] Figure 10 This is a schematic cross-sectional view illustrating another example of a printed circuit board.

[0082] Reference Figure 10 Compared to the printed circuit board 100A according to one example embodiment described above, the printed circuit board 100E according to another example embodiment can be constructed such that: the glass layer 111 may include a first glass layer 111-1 and a second glass layer 111-2 spaced apart from each other in the thickness direction. Additionally, the through-hole 131 may include a first through-hole 131-1 penetrating the first glass layer 111-1 and a second through-hole 131-2 penetrating the second glass layer 111-2. Furthermore, a conductive film 118 including conductive particles 118a electrically connecting the first through-hole 131-1 and the second through-hole 131-2 may be disposed between the first glass layer 111-1 and the second glass layer 111-2. For example, such a structure can be introduced when a thicker core layer is required.

[0083] In the following description, the components of another printed circuit board 100E will be described in more detail with reference to the accompanying drawings.

[0084] The conductive film 118 may include conductive particles 118a and insulating resin 118b. The conductive particles 118a may be metal particles and may include particles of, for example, gold (Au), silver (Ag), nickel (Ni), copper (Cu), and / or alloys thereof. If desired, the metal particles may be polymer particles having a metallic coating applied to their surface. The insulating resin 118b stably immobilizes the conductive particles 118a and provides the required mechanical strength and insulating properties. The insulating resin 118b may include thermosetting resins (such as epoxy resins) and thermoplastic resins (such as polyimide, polyethylene terephthalate, or polycarbonate). The conductive film 118 may include anisotropic conductive film (ACF) or anisotropic conductive paste (ACP), but this disclosure is not limited thereto. In addition to conductivity, such a conductive film may also provide properties such as adhesion, mechanical strength, and thermal stability.

[0085] The technical features of the printed circuit board 100E according to another example embodiment can also be applied to the printed circuit board 100B, the printed circuit board 100C, and the printed circuit board 100D according to the other example embodiment described above. Other details are substantially the same as those described in the printed circuit board 100A and its manufacturing example according to the other example embodiment described above, the printed circuit board 100B, the printed circuit board 100C, and the printed circuit board 100D according to the other example embodiment described above.

[0086] However, this disclosure is not limited thereto. In another example of a printed circuit board, the printed circuit board may include: a frame having a through portion; a glass layer at least partially disposed within the through portion, the sidewalls of the glass layer being spaced apart from the inner sidewalls of the through portion of the frame; a first insulating material filling at least a portion of the space between the frame and the glass layer; and a second insulating material configured to contact the surfaces of the frame and the glass layer, wherein the coefficient of thermal expansion of the first insulating material may be greater than the coefficient of thermal expansion of the glass layer, and the coefficient of thermal expansion of the second insulating material may be less than the coefficient of thermal expansion of the glass layer.

[0087] In this disclosure, thickness, width, length, spacing, depth, etc., can be measured using a scanning electron microscope, optical microscope, etc., based on a polished or cut cross-section of the printed circuit board. The cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the desired cross-section. When a value is not constant, it can be determined as the average of values ​​measured at any five points. The width of the upper and / or lower ends of a via can be measured in the thickness direction of the board on a cross-section cut along the central axis of the via. The depth of a via can be measured as the distance from the upper to the lower end of the via in the thickness direction of the board on a cross-section cut along the central axis of the via.

[0088] In this disclosure, the term "cover" can include covering a portion or the entirety of a structure, and can also include direct or indirect coverage. Furthermore, the term "fill" can include not only complete filling but also partial filling and general filling. For example, this could include situations where holes or gaps exist.

[0089] In this disclosure, "substantially / largely" can be determined by including process errors, positional deviations, and measurement errors that may occur during the manufacturing process. For example, the meaning of substantially the same linewidth, gap, thickness, height, etc., can include cases where they are exactly the same numerically, as well as cases where they have substantially similar values. Furthermore, "substantially having a particular shape" can include not only cases where they have exactly that shape, but also cases where they have approximately that shape. In addition, "substantially coplanar" can include not only cases where they are completely coplanar, but also cases where they are substantially coplanar.

[0090] Furthermore, "essentially the same materials" can mean not only completely identical materials, but also materials of the same type. Therefore, the composition of the materials can be substantially the same, but their specific composition ratios can differ slightly.

[0091] In this disclosure, the term "section" can refer to the shape when an object is cut vertically, or the shape when the object is viewed from a side view. Furthermore, the term "plane" can refer to the shape when an object is cut horizontally, or the shape when the object is viewed from a top or bottom view. In the context of a via, "section" can refer to the shape when the via is cut along its central axis.

[0092] In this disclosure, for convenience, the term "lower" in "lower side," "lower portion," and "lower surface" refers to a downward direction relative to the cross-section in the drawings, and the term "upper side," "upper portion," and "upper surface" refers to the opposite direction. Additionally, "side portion" and "side surface" are used to indicate directions perpendicular to the upper and lower surfaces. However, these directions are defined for ease of illustration, and the scope of the claims is not specifically limited by the description of these directions, and the concepts of "upper" and "lower" may be changed at any time.

[0093] In this disclosure, the term "connection" includes not only the concept of direct connection but also the concept of indirect connection, such as through adhesive layers. Furthermore, the term "electrical connection" includes both physical and non-physical connections. Additionally, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, the first component may be referred to as the second component, or similarly, the second component may be referred to as the first component.

[0094] The term "example embodiment" as used in this disclosure does not imply the same embodiment and is provided to explain different unique features. However, the example embodiments presented above do not preclude implementation through combinations of features with other example embodiments. For example, unless there is an interpretation contrary to or contradicting that of other example embodiments, content described in a particular example embodiment may be understood as an interpretation related to other example embodiments, even if it is not described in other example embodiments.

[0095] The terminology used in this disclosure is for the purpose of describing exemplary embodiments only and is not intended to limit the disclosure. In this context, the singular expression includes the plural expression unless the context clearly indicates otherwise.

Claims

1. A printed circuit board comprising: a frame having a through portion; a glass layer disposed at least partially within the through portion; a first insulating material filling at least a portion of a space between the frame and the glass layer; a second insulating material disposed above the frame and the glass layer with respect to a thickness direction of the frame and the glass layer; and a third insulating material disposed below the frame and the glass layer with respect to the thickness direction of the frame and the glass layer, wherein the first insulating material includes a different material from the second insulating material and the third insulating material. the second insulating material is in contact with at least a portion of an upper surface of each of the frame, the glass layer, and the first insulating material, and 2. The printed circuit board of claim 1, wherein, the third insulating material is in contact with at least a portion of a lower surface of each of the frame, the glass layer, and the first insulating material. the first insulating material, the second insulating material, and the third insulating material form respective insulating layers having boundaries distinct from each other therebetween, 3. The printed circuit board of claim 2, wherein, an upper surface of the first insulating material is substantially coplanar with an upper surface of the glass layer, and a lower surface of the first insulating material is substantially coplanar with a lower surface of the glass layer. the first insulating material includes a first insulating resin and a first inorganic filler, 4. The printed circuit board of claim 1, wherein, the second insulating material includes a second insulating resin, a second inorganic filler, and a first glass fiber, and the third insulating material includes a third insulating resin, a third inorganic filler, and a second glass fiber. the first insulating material does not include a glass fiber.

5. The printed circuit board of claim 4, wherein, in a given cut cross section, area ratios of the first inorganic filler included in the first insulating material are each smaller than an area ratio of the second inorganic filler included in the second insulating material and an area ratio of the third inorganic filler included in the third insulating material.

6. The printed circuit board of claim 4, wherein, the through portion penetrates a region between an upper surface and a lower surface of the frame, and 7. The printed circuit board of claim 1, wherein, the frame includes a copper-clad laminate or a bare copper-clad laminate. each of a coefficient of thermal expansion of the second insulating material and a coefficient of thermal expansion of the third insulating material is smaller than a coefficient of thermal expansion of the glass layer.

8. The printed circuit board of claim 1, wherein, each of a coefficient of thermal expansion of the frame and a coefficient of thermal expansion of the first insulating material is larger than the coefficient of thermal expansion of the glass layer.

9. The printed circuit board of claim 8, wherein, 10. The printed circuit board according to claim 1, further comprising: a through hole penetrating the glass layer; a first connection via penetrating the second insulating material and connected to an upper surface of the through hole; a second connection via penetrating the third insulating material and connected to a lower surface of the through hole; and a first interconnection layer disposed on an upper surface of the second insulating material, wherein at least a portion of the first interconnection layer is connected to the first connection via; and a second interconnection layer disposed on a lower surface of the third insulating material, wherein at least a portion of the second interconnection layer is connected to the second connection via. the through hole has a substantially hourglass shape in cross section, ​ 11. The printed circuit board of claim 10, wherein, ​ the first connection via has a substantially tapered shape in cross-section in which a width of an upper portion thereof is greater than a width of a lower portion thereof, and the second connection via has a substantially tapered shape in cross-section in which a width of a lower portion thereof is greater than a width of an upper portion thereof.

12. The printed circuit board of claim 11, wherein, the glass layer has a through-hole, the through-hole includes a first seed layer disposed on a wall surface of the through-hole and a first metal layer disposed on the first seed layer and filling at least a portion of the through-hole, the first seed layer includes a first layer including a sputtered titanium layer and a second layer disposed on the first layer and including a sputtered copper layer, and the first metal layer includes an electrolytic copper plating layer.

13. The printed circuit board of claim 12, wherein, the second insulating material has a first via-hole exposing an upper surface of the through-hole, the third insulating material has a second via-hole exposing a lower surface of the through-hole, the first connection via includes a second seed layer disposed on a wall surface of the first via-hole and the exposed upper surface of the through-hole and a second metal layer disposed on the second seed layer and filling at least a portion of the first via-hole, the second connection via includes a third seed layer disposed on a wall surface of the second via-hole and the exposed lower surface of the through-hole and a third metal layer disposed on the third seed layer and filling at least a portion of the second via-hole, and each of the second seed layer and the third seed layer includes an electroless copper plating layer, and each of the second metal layer and the third metal layer includes an electrolytic copper plating layer.

14. The printed circuit board of claim 10, further comprising: a first electronic component embedded in the glass layer; and a third connection via penetrating the second insulating material and connecting the first electronic component to at least another portion of the first interconnection layer, wherein the first electronic component includes at least one of an interconnection bridge, an active component, and a passive component.

15. The printed circuit board of claim 10, wherein, the glass layer includes a first glass layer and a second glass layer spaced apart from each other in the thickness direction, the through-hole includes a first through-hole penetrating the first glass layer and a second through-hole penetrating the second glass layer, and an electrically conductive film is disposed between the first glass layer and the second glass layer, the electrically conductive film including electrically conductive particles electrically connecting the first through-hole and the second through-hole.

16. The printed circuit board of claim 10, further comprising: a plurality of first build-up insulating layers stacked on an upper surface of the second insulating material; a plurality of first build-up interconnection layers respectively disposed on upper surfaces of the plurality of first build-up insulating layers or within the plurality of first build-up insulating layers; and a plurality of first build-up via layers respectively disposed within the plurality of first build-up insulating layers.

17. The printed circuit board of claim 16, further comprising: a second electronic component embedded within the plurality of first build-up insulating layers and connected to at least a portion of at least one of the plurality of first build-up interconnection layers via at least a portion of at least one of the plurality of first build-up via layers, wherein the second electronic component includes at least one of an interconnection bridge, an active component, and a passive component.

18. The printed circuit board of claim 16, further comprising: a first solder resist layer disposed on an upper surface of an uppermost one of the plurality of first build-up insulating layers and having a plurality of first openings respectively exposing at least a portion of an uppermost one of the plurality of first build-up interconnection layers; a second solder resist layer disposed on a lower surface of the third insulating material and having a plurality of second openings respectively exposing at least a portion of the second interconnection layer; a plurality of first electrical connection metals respectively disposed on the plurality of first openings and respectively connected to the exposed at least portion of the uppermost first build-up interconnection layer; an electronic component mounted on an upper surface of the first solder resist layer and connected to the plurality of first electrical connection metals; and a plurality of second electrical connection metals respectively disposed on the plurality of second openings and respectively connected to the exposed at least portion of the second interconnection layer, wherein the electronic component includes at least one of an active component and a passive component.

19. The printed circuit board of claim 16, further comprising: a plurality of second build-up insulating layers stacked on a lower surface of the third insulating material; a plurality of second build-up interconnection layers respectively disposed on or within the plurality of second build-up insulating layers; and a plurality of second build-up via layers respectively disposed within the plurality of second build-up insulating layers.

20. The printed circuit board of claim 19, further comprising: a first solder resist layer disposed on an upper surface of an uppermost one of the plurality of first build-up insulating layers and having a plurality of first openings respectively exposing at least a portion of an uppermost one of the plurality of first build-up interconnection layers; a second solder resist layer disposed on a lower surface of a lowermost one of the plurality of second build-up insulating layers and having a plurality of second openings respectively exposing at least a portion of a lowermost one of the plurality of second build-up interconnection layers; a plurality of first electrical connection metals respectively disposed on the plurality of first openings and respectively connected to the exposed at least portion of the uppermost first build-up interconnection layer; an electronic component mounted on an upper surface of the first solder resist layer and connected to the plurality of first electrical connection metals; and a plurality of second electrical connection metals respectively disposed on the plurality of second openings and respectively connected to the exposed at least portion of the second interconnection layer. ​ ​ a plurality of second electrically connecting metals respectively disposed on the plurality of second openings and respectively connected to the exposed at least part of the second build-up interconnection layer disposed at the lowermost side, wherein the electronic assembly comprises at least one of an active component and a passive component.

21. A printed circuit board, comprising: a glass layer; a frame spaced apart from the glass layer and surrounding a side surface of the glass layer; a first insulating material filling at least a portion of a space between the glass layer and the frame; a second insulating material covering at least a portion of an upper surface of each of the glass layer, the frame, and the first insulating material; and a third insulating material covering at least a portion of a lower surface of each of the glass layer, the frame, and the first insulating material, wherein the first insulating material and the second insulating material have a boundary physically distinguished from each other, and the first insulating material and the third insulating material have a boundary physically distinguished from each other. each of a coefficient of thermal expansion of the frame and a coefficient of thermal expansion of the first insulating material is greater than a coefficient of thermal expansion of the glass layer, and 22. The printed circuit board of claim 21, wherein, the coefficient of thermal expansion of the glass layer is greater than each of a coefficient of thermal expansion of the second insulating material and a coefficient of thermal expansion of the third insulating material.

23. The printed circuit board of claim 21, further comprising: a through-hole penetrating the glass layer; a first connection via penetrating the second insulating material and connected to an upper surface of the through-hole; a second connection via penetrating the third insulating material and connected to a lower surface of the through-hole; a first interconnection pattern disposed above the second insulating material and connected to the first connection via; and a second interconnection pattern disposed below the third insulating material and connected to the second connection via, wherein the through-hole has a substantially hourglass shape in cross-section, the first connection via and the second connection via have a substantially tapered shape in opposite directions in cross-section, the through-hole includes a first layer including a sputtered titanium layer and a second layer including a sputtered copper layer as seed layers, and each of the first connection via and the second connection via includes a chemical copper plating layer as a seed layer.

24. The printed circuit board of claim 23, further comprising: a build-up layer disposed above the second insulating material, or below the third insulating material, or above the second insulating material and below the third insulating material, wherein the build-up layer includes one or more build-up insulating layers, one or more build-up interconnection layers respectively disposed on or within the one or more build-up insulating layers, and one or more build-up via layers respectively disposed within the one or more build-up insulating layers.

25. A method for manufacturing a printed circuit board, comprising: preparing a frame having a through portion; disposing at least a portion of a glass layer within the through portion; ​ ​ filling at least a portion of a space between the frame and the glass layer with a first insulating material; forming a second insulating material over each of the frame, the glass layer, and the first insulating material, the second insulating material comprising a different material than the first insulating material; and forming a third insulating material under each of the frame, the glass layer, and the first insulating material, the third insulating material comprising a different material than the first insulating material.

26. The method for manufacturing a printed circuit board according to claim 25, wherein, each of a coefficient of thermal expansion of the frame and a coefficient of thermal expansion of the first insulating material is greater than a coefficient of thermal expansion of the glass layer, and the coefficient of thermal expansion of the glass layer is greater than each of a coefficient of thermal expansion of the second insulating material and a coefficient of thermal expansion of the third insulating material.

27. The method for manufacturing a printed circuit board of claim 25, the method further comprising: prior to disposing at least a portion of the glass layer within the through-portion, forming a through-hole that penetrates the glass layer, wherein the step of forming the through-hole comprises: forming a via that penetrates the glass layer and has a generally hourglass shape in cross-section; forming a first seed layer by sputtering a material comprising titanium and a material comprising copper on a wall surface of the via; and forming a first metal layer that fills at least a portion of the via by performing an electrolytic plating process on the first seed layer with a material comprising copper.

28. The method for manufacturing a printed circuit board of claim 27, the method further comprising: after forming the second insulating material and the third insulating material, forming a first connection via that penetrates the second insulating material and connects to an upper surface of the through-hole and a first interconnection layer that is disposed on an upper surface of the second insulating material and at least a portion of which connects to the first connection via; forming a second connection via that penetrates the third insulating material and connects to a lower surface of the through-hole and a second interconnection layer that is disposed on a lower surface of the third insulating material and at least a portion of which connects to the second connection via, wherein the step of forming the first connection via comprises: forming a first via hole that penetrates the second insulating material, the first via hole having a generally tapered shape in cross-section with a width of an upper portion thereof being greater than a width of a lower portion thereof; forming a second seed layer on a wall surface of the first via hole with a material comprising copper by an electroless plating process; and forming a second metal layer that fills at least a portion of the first via hole on the second seed layer with a material comprising copper by an electrolytic plating process, and the step of forming the second connection via comprises: forming a second via hole that penetrates the third insulating material, the second via hole having a generally tapered shape in cross-section with a width of a lower portion thereof being greater than a width of an upper portion thereof; forming a third seed layer on a wall surface of the second via hole with a material comprising copper by an electroless plating process; A third metal layer of material including copper is formed on the third seed layer by an electrolytic plating process to fill at least a portion of the second via hole.

29. The method for manufacturing a printed circuit board according to claim 28, the method further comprising: after forming the first and second connection vias and the first and second interconnection layers, forming a build-up layer over the second insulating material, or under the third insulating material, or over the second insulating material and under the third insulating material, wherein the step of forming the build-up layer comprises: forming one or more build-up insulating layers; forming one or more build-up interconnection layers, respectively disposed on or within the one or more build-up insulating layers; and forming one or more build-up via layers, respectively disposed within the one or more build-up insulating layers.

30. The method for manufacturing a printed circuit board according to claim 29, wherein, in the step of preparing the frame, the through portions are formed in a plurality, and in the step of disposing the glass layer, at least a portion of each of the plurality of glass layers is disposed in a respective one of the plurality of through portions, wherein the method further comprises: after forming the build-up layer, forming a plurality of printed circuit boards by cutting spaces between the plurality of through portions.

31. A printed circuit board, comprising: a frame having a through portion; a glass layer at least partially disposed within the through portion, a side wall of the glass layer being spaced apart from an inner side wall of the through portion of the frame; a first insulating material filling at least a portion of a space between the frame and the glass layer; and a second insulating material disposed to contact surfaces of the frame and the glass layer, wherein a coefficient of thermal expansion of the first insulating material is greater than a coefficient of thermal expansion of the glass layer, and a coefficient of thermal expansion of the second insulating material is less than the coefficient of thermal expansion of the glass layer.

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