Method for improving electrical transport properties of etched graphene quantum dots and device structure

Abstract

This invention discloses a method and device structure for improving the electrical transport properties of etched graphene quantum dots, belonging to the field of low-temperature transport testing technology. The method includes the following steps: fabricating etched graphene quantum dot devices; performing preliminary electrical transport characterization by cooling; and undergoing several cycles of "sample electrode grounding protection – heating to above 200K or room temperature – cooling again – electrical transport characterization" to improve the electrical transport properties of the device, enabling subsequent observation and manipulation of the quantum dot's fine charge stability map. The optimized method of this invention, through several heating and cooling thermal cycles, successfully adjusts the coulomb blocking region of the graphene quantum dots from hundreds of volts towards zero, facilitating the application of a gate voltage. Furthermore, the charge stability map of the two quantum dots is significantly optimized and improved, greatly increasing the yield of etched graphene quantum dot devices. In addition, the optimized method of this invention is simple to operate and has significant effects, making it suitable for widespread application.

Description

Technical Field

[0001] This invention relates to the field of low-temperature transport testing technology, and in particular to a method and device structure for improving the electrical transport properties of etched graphene quantum dots. Background Technology

[0002] Since May 20, 2019, the International System of Units (SI) based on fundamental physical constants has marked a complete transition from physical standards to quantum standards. This shift not only improves measurement accuracy but also significantly shortens the transmission chain. Electrical standards (such as resistance, voltage, and current) are important components of quantum metrology standards. Quantum standards for resistance and voltage have been established, while a quantum standard for current (based on the fundamental charge e and clock frequency f) is yet to be established. Currently, there are two main implementation schemes in metrology: the first is an indirect method, deriving current from quantum voltage and quantum resistance standards using Ohm's law; the other is to achieve quantum charge pumping using single-electron tunneling, which is the most direct and simplest method. Achieving quantum pump current using single-electron tunneling refers to periodically manipulating a single charge sequentially from the source end through a quantum dot to the drain end under radio frequency signal, forming a quantum charge pump I = e·f.

[0003] Previous attempts by the metrology community in metals and semiconductors have yielded numerous results, but none have yet met the requirements for establishing a quantum current benchmark. Graphene, with its unique linear dispersion and large inter-point energy spacing at the Dirac point, offers a new possibility for realizing a quantum current benchmark. The design scheme for graphene quantum dots is as follows: etching out the entire structure of the graphene quantum dot (including gates and constrictions), resulting in simple device fabrication and easy parallel integration. However, this etched graphene quantum dot system relies on the quality of mechanically exfoliated graphene, lacks good stability, and has a low fabrication success rate. Furthermore, it is prone to breakdown and burn-out under high gate voltage during subsequent low-temperature transport testing. Even if the device maintains good consistency with the expected etched pattern, the probability of observing a good quantum dot charge stability map is low, making subsequent quantum current pumping transport difficult. Summary of the Invention

[0004] The purpose of this invention is to provide a method and device structure for improving the electrical transport properties of etched graphene quantum dots, in order to partially solve the above-mentioned technical problems.

[0005] A first aspect of the present invention provides a method for improving the electrical transport properties of etched graphene quantum dots, comprising the following steps:

[0006] S1. Fabricating etched graphene quantum dot devices;

[0007] S2. Cooling down to perform preliminary electrical transport characterization;

[0008] S3. After the sample electrode is grounded and protected, it is brought to room temperature and then cooled down again for the second electrical transport characterization; after the sample electrode is grounded and protected, it is brought to room temperature and then cooled down again for the third electrical transport characterization; after the sample electrode is grounded and protected, it is brought to room temperature and then cooled down again for the fourth electrical transport characterization.

[0009] S4. After several heating and cooling cycles, the electrical transport properties of the etched graphene quantum dot device are improved, enabling subsequent observation and manipulation of the quantum dot's fine charge stability map.

[0010] Preferably, in step S2, the temperature is 300 mK.

[0011] Preferably, in step S2, the preliminary electrical transport characterization includes source-drain I-V DC testing and gate voltage testing. A diagram showing the regulation of graphene quantum dots.

[0012] Preferably, in step S3, the temperature rise to room temperature can be achieved using the following two methods:

[0013] (1) Set the flow of the liquid helium-free circulating gas path to 0% and maintain a flow rate of 6 K / min to heat the sample chamber to 300 K.

[0014] (2) After heating the sample chamber to 100 K at 6 K / min, fill it with helium to maintain positive pressure. Slowly and uniformly pull out the helium-3 test rod and place it on the horizontal sample rack at room temperature. The temperature can be slowly raised to about 300 K.

[0015] Preferably, in step S3, the second electrical transport characterization is performed by testing the gate voltage. A diagram showing the regulation of graphene quantum dots.

[0016] Preferably, in step S3, the third electrical transport characterization includes testing the gate voltage. The modulation diagram of graphene quantum dots and the charge stability diagram of dual quantum dots.

[0017] Preferably, in step S3, the fourth electrical transport characterization includes testing the gate voltage. The modulation diagram of graphene quantum dots and the charge stability diagram of dual quantum dots.

[0018] Preferably, in step S4, the improvement in electrical transport properties can be achieved by comparing the first, second, third, and fourth gate voltages. The modulation diagram of graphene quantum dots and the third and fourth dual quantum dot charge stability diagrams show that the Coulomb blocking range of etched graphene quantum dots gradually drifts from hundreds of volts to zero, and the hexagonal structure in the dual quantum dot charge stability diagram is clearer and more stable.

[0019] A second aspect of the present invention provides an etched graphene quantum dot device structure using the above-described method.

[0020] Preferably, the etched graphene quantum dot device structure includes: electrodes, an etched monolayer graphene double quantum dot sheet, and a doped silicon wafer with a 285nm SiO2 layer; wherein the etched monolayer graphene double quantum dot sheet structure includes source and drain terminals connected to the two quantum dots through a narrowed channel, the channel width being approximately tens of nanometers, consistent with the channel width between the two quantum dots, and a right-side gate voltage... The three interconnected gates work together to control the overall Fermi level of the quantum dot device. The gate voltage is located on the left side of the gate. and gate voltage The charge filling status of the two quantum dots can be controlled separately.

[0021] Therefore, the method and device structure of the present invention for improving the electrical transport properties of etched graphene quantum dots using the above-described structure have the following beneficial effects:

[0022] (1) The present invention provides a method and device structure for improving the electrical transport characteristics of etched graphene quantum dots. This method can not only effectively adjust the coulomb blocking range of etched graphene quantum dots from hundreds of volts to zero to facilitate the application of gate voltage, but also avoid the device being broken down and burned under high gate voltage.

[0023] (2) The dual quantum dot charge stability map measured at the same side gate voltage fixed point in the present invention is significantly improved and optimized. The hexagonal structure in the dual quantum dot charge stability map is clearer and more stable, which facilitates the subsequent application of radio frequency signals for charge pumping and other applications.

[0024] (3) In this invention, through several heating and cooling cycles, the original quantum dot devices with poor properties and difficult subsequent applications are optimized into practical devices with obvious quantum dot characteristics, which greatly improves the yield of etched graphene quantum dot devices.

[0025] (4) The optimization method of the present invention is simple to operate and has obvious effects. It can greatly improve the stability and ease of use of etched graphene quantum dot devices, and therefore is suitable for promotion.

[0026] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0027] Figure 1 A flowchart of a method for improving the electrical transport properties of etched graphene quantum dots provided by the present invention;

[0028] Figure 2 This is a schematic diagram of the etched graphene device structure in the embodiment;

[0029] Figure 3 The first cooling gate voltage in the embodiment A diagram illustrating the regulation of graphene quantum dots;

[0030] Figure 4 The second cooling gate voltage in the embodiment A diagram illustrating the regulation of graphene quantum dots;

[0031] Figure 5 The third cooling gate voltage in the embodiment A diagram illustrating the regulation of graphene quantum dots;

[0032] Figure 6 This is the third cooling fixation in the embodiment. The measured charge stability diagram of the two quantum dots;

[0033] Figure 7 The fourth cooling gate voltage in the embodiment A diagram illustrating the regulation of graphene quantum dots;

[0034] Figure 8 This is the fourth cooling fixation in the embodiment. The measured charge stability diagram of the two quantum dots. Detailed Implementation

[0035] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0036] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0037] Example

[0038] like Figure 1 As shown, the present invention provides a method for improving the electrical transport properties of etched graphene quantum dots, comprising the following steps:

[0039] S1. Fabrication of etched graphene quantum dot devices: such as Figure 2The diagram shows a fabricated graphene quantum dot device. The gray-white area represents the remaining graphene structure after etching. The source and drain terminals are connected to the two quantum dots through a narrowed channel with a width of approximately tens of nanometers, consistent with the channel width between the two quantum dots. The gate voltage is shown on the right. The three interconnected gates work together to control the overall Fermi level of the quantum dot device. The gate voltage is located on the left side of the gate. and gate voltage The charge filling of the two quantum dots is controlled separately. Here, conventional methods in the field are used to fabricate them: (1) mechanically peel off the monolayer graphene and place it on the silicon wafer; (2) expose the pattern to be etched with an electron beam and use reactive ion beam etching to etch the monolayer graphene into the desired quantum dot structure, which includes source drain, dual quantum dots and gate; (3) then evaporate metal electrodes and connect them to the low-temperature test sample stage with leads.

[0040] S2. Preliminary Electrical Transport Characterization During Cooling: The cryogenic test sample stage is mounted onto the Helium-3 cryogenic test rod. At room temperature, the sample area at the front end of the test rod is vacuum-sealed using a sleeve with silicone rubber (mechanical pump evacuates to approximately 1 Pa). At this point, a Keithley 2450 can be used to perform DC IV testing on the source and drain terminals of the quantum dot device. Observing linear IV proves that the sample has an ohmic contact and there is no potential barrier. The sample is grounded through a room temperature sample electrode box to prevent burnout during cooling. The molecular pump is turned on to further increase the vacuum level, and the vacuum level is read using an ionization gauge. After about 1 hour, the temperature drops to a lower level. At Pa, turn off the ionization gauge and molecular pump, and fill the sleeve with about 1 mL of helium as a cooling exchange gas. Then, fill the liquid-free helium refrigerator chamber with helium to maintain positive pressure and prevent a large amount of air from entering the chamber. The helium-3 cryogenic test rod can be inserted vertically and slowly, with a certain amount of helium inside the chamber as an exchange gas. The pressure difference between the chamber and the outside environment is about -0.3 bar. The pressure difference between the sleeve and the chamber can ensure that the sleeve will not fall off. Set the circulating gas flow rate to 100% to start cooling the chamber, from room temperature (300K) to 20K in about 6 hours. Then set the flow rate to 20% and cool for about 1-2 hours. The temperature drops to 6K; the chamber heating is turned on to maintain the chamber and test rod at 6K, and the mechanical pump and molecular pump are turned on to evacuate the sleeve. After about 3-4 hours, the vacuum reading of the ionization gauge drops to 6e-5 (a longer evacuation time is required if the chamber has not been used for a long time). The flow is set to 10% and the circulating gas pressure is about 5mbar. The chamber temperature drops to the lowest point of 1.5K. The adsorption pump on the helium-3 test rod is heated to 35K. After half an hour, the heating is turned off, and the adsorption pump starts to evacuate the helium-3 rod to cool it down. After half an hour, the temperature drops to about 300mK, which can be maintained for about 60 hours. At this time, the grid voltage can be tested. The SR830 outputs a 0.2V and 17.777Hz sinusoidal voltage signal by controlling the graphene quantum dots. A voltage divider of approximately 100μV is connected in series with a 50Ω resistor to the sample source. The drain current signal is then input to the SR830 current interface for computational amplification. The specific gate voltage... The modulation diagram of graphene quantum dots is as follows Figure 3 As shown, the gate voltage needs to be increased to about 100V to reach the current blocking region. Testing at this gate voltage is extremely easy to cause the sample to break down and burn out.

[0041] S3. After the sample electrode is grounded and protected, it is brought to room temperature and then cooled again for the second electrical transport characterization; after the sample electrode is grounded and protected, it is brought to room temperature and then cooled again for the third electrical transport characterization; after the sample electrode is grounded and protected, it is brought to room temperature and then cooled again for the fourth electrical transport characterization; the specific operating steps are as follows: [The text abruptly ends here, likely due to an incomplete sentence or a formatting error.] Reduce the temperature to zero and lower the source-drain voltage to 0V. Ground all sample electrodes through the room-temperature sample electrode box to prevent burnout during heating and cooling. Set the liquid helium circulation flow to 0% and maintain a flow rate of 6K / min to heat the sample chamber to 300K. Alternatively, you can directly heat the sample chamber to 300K, or heat it to 100K at 6K / min and then fill it with helium to maintain positive pressure. Slowly and uniformly remove the helium-3 test rod and place it on a horizontal sample holder at room temperature. You can also slowly heat it to approximately 300K. After heating to 300K, fill the helium-3 test rod sleeve with approximately 1mL of helium as an exchange gas and repeat the previous cooling operation. Retest the gate voltage after cooling to 300mK for the second time. The regulatory effect on graphene quantum dots, such as Figure 4 As shown, the current blocking interval can be seen from... Figure 3 The voltage was reduced from 100V to 40-55V, a significant decrease, reducing the risk of high gate voltage causing breakdown and burnout of the sample; the gate voltage was reduced. The temperature was lowered to zero, and the source-drain voltage was reduced to 0V. All electrodes of the sample were grounded through the room temperature sample electrode box to prevent burnout during the heating and cooling process. The heating and cooling operation of raising the temperature to room temperature and then lowering it back to 300mK was repeated. The gate voltage was tested after the third cooling to 300mK. The regulatory effect on graphene quantum dots, such as Figure 5 As shown, the current blocking range continues to decrease to 14-43V, with the fixed-side gate... Scan gate voltage and gate voltage The charge stability map of two quantum dots can be measured ( Figure 6 However, the graph is rather coarse, lacking detail, making it inconvenient to apply radio frequency signals for current pumping; the gate voltage Reduce the temperature to zero and reduce the source-drain voltage to 0V. Ground all sample electrodes through the room temperature sample electrode box to prevent them from burning out during the heating and cooling process. Repeat the heating and cooling operation of raising the temperature to room temperature and then lowering it back to 300mK.

[0042] S4. After several temperature cycling processes as described above, the electrical transport properties of the etched graphene quantum dot device are improved, enabling subsequent observation and manipulation of the quantum dot's fine charge stability map. After several temperature cycling processes in S3, the gate voltage is tested at 300mK. The regulatory effect on graphene quantum dots, such as Figure 7 As shown, there is no significant decrease in the current blocking range, and the fixed-side gate voltage... Scan gate voltage and gate voltage The charge stability map of two quantum dots can be measured ( Figure 8 The charge stability diagram of this device has been significantly optimized, and the hexagonal structure with dual quantum dot characteristics can be clearly seen, which is consistent with the theory. The details are clear, and radio frequency signals can be applied for subsequent current pumping output.

[0043] The graphene quantum dots in the etching system have similar effects to those of this invention, and both can refer to this method.

[0044] Analysis of the underlying physical mechanisms of this optimization method suggests that it may improve device quality through the following pathways:

[0045] (1) Strain relaxation: There is a difference in the coefficient of thermal expansion between graphene and the substrate. Repeated thermal cycling can release interfacial stress and reduce wrinkles and cracks.

[0046] (2) Impurity migration and pinning: The migration rate of impurity atoms decreases at low temperatures, but impurities may diffuse to grain boundaries or surfaces during the heating process, reducing scattering centers.

[0047] (3) Interface defect healing: Temperature cycling may induce local reconstruction of the graphene edge or interlayer van der Waals interface, enhancing electrical contact stability.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for improving the electrical transport properties of etched graphene quantum dots, characterized in that, Includes the following steps: S1. Fabricating etched graphene quantum dot devices; S2. Cool the device to a low temperature environment of 30mK~1.5K and perform preliminary electrical transport characterization; S3. Perform several thermal cycles on the device. Each thermal cycle includes: grounding all electrodes of the device for protection, heating to above 200K, and then cooling back to the low temperature environment. Perform corresponding electrical transport characterization on the device after each cooling. S4. After the thermal cycling treatment, the electrical transport characteristics of the device are improved, enabling the observation and manipulation of the fine charge stability map of the quantum dot.

2. The method according to claim 1, characterized in that, The preliminary electrical transport characterization in step S2 includes source-drain DC IV testing and gate voltage testing. V SG A diagram illustrating the regulation of graphene quantum dots; The electrical transport characterization in step S3 includes gate voltage. V SG Control plot and charge stability plot of dual quantum dots.

3. The method according to claim 1, characterized in that, The heating in step S3 is performed in one of the following ways: (a) In a liquid helium-free refrigeration system, the circulating gas flow rate is set to 0%, and the sample chamber is heated to 200K–300K at a rate of 4–8K / min. (b) After heating the sample chamber to 90-110K at 4-8K / min, fill it with helium to maintain positive pressure, slowly pull out the low-temperature test rod, place it horizontally in a room temperature environment and slowly heat it to 280-320K.

4. The method according to claim 1, characterized in that, The improvement in electrical transport characteristics is specifically manifested in the following ways: the Coulomb blocking range shifts from the hundred-volt level to zero, and a clearer and more stable hexagonal structure is presented in the dual quantum dot charge stability diagram.

5. The method according to claim 1, characterized in that, The thermal cycling process is performed 1-3 times, and after each thermal cycle, the electrical transport characterization shows that the Coulomb blockage region gradually drifts until the charge stability map of the two quantum dots presents a stable hexagonal structure.

6. An etched graphene quantum dot device for implementing the method according to any one of claims 1-5, characterized in that, include: Doped silicon substrate; A SiO2 layer formed on the substrate; A single-layer graphene dual quantum dot structure fabricated on the SiO2 layer by etching is described, the structure comprising: Source (S) and drain (D); Two quantum dots, Q1 and Q2, are connected to the source and drain via a narrowed channel; The three gate voltages located on the right side of the device and interconnected to control the overall Fermi level of the device are three finger gates. V SG ; Two gate voltages V, located to the left of the two quantum dots respectively, are used to independently control their charge filling. G1 and V G2 .

7. The etched graphene quantum dot device according to claim 6, characterized in that, The narrowed channel has a width of 20-100 nm and is consistent with the channel width between the two quantum dots Q1 and Q2.

8. The etched graphene quantum dot device according to claim 6, characterized in that, The thickness of the SiO2 is 285±5nm.

9. The etched graphene quantum dot device according to claim 6, characterized in that, The preparation of the single-layer graphene dual quantum dot structure includes: forming the structure by mechanically exfoliated single-layer graphene through reactive ion beam etching, and controlling the etching depth to completely penetrate the graphene layer to avoid residual material affecting the electrical transport properties.

10. A quantum current pumping device, characterized in that, The etched graphene quantum dot device according to any one of claims 6-9 is used to realize quantized current output based on single-electron tunneling under radio frequency signal control. ; in, e The fundamental charge constant, f For radio frequency drive power, I This refers to the quantum pump current output under radio frequency drive.

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