Industrial chip scale package for microelectronic devices

Abstract

The invention relates to industrial chip scale packaging for microelectronic devices. A microelectronic device (100) includes a die (102) having input / output (I / O) terminals (104) and a dielectric layer (106) on the die (102). The microelectronic device (100) includes a conductive strut (110) electrically coupled to the I / O terminal (104) and extending through the dielectric layer (106) to an exterior of the microelectronic device (100). Each post (110) includes a post (112) electrically coupled to one of the I / O terminals (104), and a head (114) contacting the post (112) at an end of the post (112) opposite the I / O terminal (104). The head (114) extends laterally beyond the post (112) in at least one lateral direction.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on October 4, 2018, with application number 201880075335.6 and title "Industrial Chip-Level Packaging for Microelectronic Devices". Technical Field

[0003] This disclosure relates generally to microelectronic devices, and more specifically to chip-level packaging in microelectronic devices. Background Technology

[0004] The size and cost of microelectronic devices are constantly decreasing. Furthermore, the density of components within microelectronic devices is increasing. As size shrinks, power and current density increase through input / output (I / O) structures such as bump bonding structures. This leads to higher temperatures and increases the risk of failure due to electromigration. Meeting both reliability and cost targets simultaneously remains challenging for packaging design. Summary of the Invention

[0005] In the described example, a microelectronic device has a die with input / output (I / O) terminals, a dielectric layer on the die, and pillars electrically coupled to the I / O terminals and extending through the dielectric layer to the exterior of the microelectronic device. The pillars are conductive. Each pillar includes a column and a head, the column being electrically coupled to one of the I / O terminals, and the head contacting the column at the end of the column opposite to the I / O terminal. The head extends laterally beyond the column in at least one lateral direction. Attached Figure Description

[0006] Figure 1 This is a cross-section of an example microelectronic device.

[0007] Figures 2A to 2L It is a cross-section of the microelectronic device depicted in the stage of the example formation method.

[0008] Figures 3A to 3F It is a cross-section of a microelectronic device depicted in a stage of another example formation method.

[0009] Figures 4A to 4F It is a cross-section of a microelectronic device depicted in a stage of another example formation method.

[0010] Figures 5A to 5G It is a cross-section of a microelectronic device depicted in a stage of another example formation method. Detailed Implementation

[0011] The accompanying drawings are not to scale. This specification is not limited to the order of the actions or events shown, as some actions or events may occur in a different order and / or simultaneously with other actions or events. Furthermore, some of the actions or events shown are optional for implementing the methods according to this specification.

[0012] The microelectronic device has a die with input / output (I / O) terminals. The die can be, for example, an integrated circuit, a discrete semiconductor device, or a microelectromechanical system (MEMS) device. The I / O terminals can include, for example, bonding pads, bonding regions of a redistribution layer (RDL), or bonding regions of a top interconnect layer. The microelectronic device includes a dielectric layer on the die. The dielectric layer can include, for example, an organic polymer, a silicone polymer, or an inorganic dielectric material. The microelectronic device further includes pillars electrically coupled to the I / O terminals. The pillars can directly contact the I / O terminals or can be electrically coupled to the I / O pads through a conductive material. The pillars extend through the dielectric layer to the exterior of the microelectronic device. The pillars are conductive. Each pillar includes at least one column electrically coupled to at least one of the I / O terminals. Each pillar further includes a head contacting the at least one column. The head is positioned on the end of the pillar opposite to the I / O terminal. The head extends laterally beyond the column in at least one lateral direction. The dielectric layer extends from the die to the head and laterally surrounds the pillar. In this specification, the terms "laterally" and "laterally" refer to a direction parallel to the plane of the die surface on which the I / O terminals are positioned.

[0013] Furthermore, in this specification, terms such as top, above, and above should not be construed as limiting the position or orientation of a structure or element, but should be used to provide spatial relationships between structures or elements.

[0014] In this specification, if an element is referred to as being connected to, coupled to, located on, or in contact with another element, the element may be directly connected to, directly coupled to, directly located on, or directly in contact with another element, or there may be intermediate elements present. Furthermore, in this specification, if an element is referred to as being directly connected to, directly coupled to, directly located on, or directly in contact with another element, there are no other intentionally placed intermediate elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner, for example, between and directly between, adjacent and directly adjacent, etc.

[0015] Figure 1This is a cross-section of an example microelectronic device. Microelectronic device 100 includes a die 102. Die 102 may contain at least one integrated circuit having a semiconductor substrate and interconnect regions. Alternatively, die 102 may contain at least one discrete semiconductor device, such as a power transistor. Further, die 102 may contain a MEMS device, such as an accelerometer. Other embodiments of die 102 are also within the scope of this example. Die 102 includes I / O terminals 104. I / O terminals 104 may be bonding pads electrically coupled to the interconnects of the microelectronic device. Alternatively, I / O terminals 104 may be bonding regions located above and electrically coupled to the RDL of the interconnects of the microelectronic device. Further, I / O terminals 104 may be bump pads in a bond-over-active (BOAC) structure of the microelectronic device. Other embodiments of I / O terminals 104 are also within the scope of this example. The size of I / O terminals 104 may vary across die 102, or its size may be uniform.

[0016] The microelectronic device 100 includes a dielectric layer 106 on a die 102. The dielectric layer 106 may comprise, for example, an organic polymer such as epoxy resin, cross-linked polyisoprene, polyimide, or methacrylate. Alternatively, the dielectric layer 106 may comprise a silicone polymer. Further, the dielectric layer 106 may comprise an inorganic dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, or aluminum oxide. The thickness 108 of the dielectric layer 106 may be, for example, from 5 micrometers to 100 micrometers.

[0017] Microelectronic device 100 includes pillars 110 electrically coupled to I / O terminals 104. Pillars 110 extend through dielectric layer 106 to the outside of microelectronic device 100. Each pillar 110 includes a column 112 electrically coupled to one of the I / O terminals 104. Figure 1 As depicted, the pillar 112 can directly contact the I / O terminal 104. Alternatively, the pillar 112 can be electrically coupled to the I / O terminal 104 via a conductive material (such as a seed layer for electroplating operations). The pillar 112 is conductive. The pillar 112 may have, for example, a copper core laterally surrounded by a pillar liner that reduces copper diffusion from the copper core into the dielectric layer 106. Alternatively, the pillar 112 may contain other metals, such as nickel, platinum, aluminum, tungsten, or gold, or other conductive materials, such as graphene or carbon nanotubes.

[0018] The support 110 further includes a head 114 on the column 112. Each column in the column 112 is contacted by at least one head in the head 114, and each head in the head 114 contacts at least one column in the column 112. The head 114 may contact the column 112 directly or through a conductive material (such as a diffusion barrier layer or part of a seed layer). The composition of the head 114 may be similar to or different from that of the column 112. An I / O terminal 104 is coupled to a first end of the column 112, and the head 114 contacts a second end of the column 112, the second end being positioned opposite the first end. Each head in the head 114 extends laterally beyond the column 112 contacted by the head 114 in at least one lateral direction and possibly in that lateral direction. The column 112 and the head 114 may have any configuration and may contain any material disclosed in the commonly assigned patent application serial number US16 / 030,371 filed July 9, 2018, which is incorporated herein by reference but is not acknowledged as prior art.

[0019] The support 110 may include a barrier layer 116 on the head 114. For example, the barrier layer 116 may contain nickel, palladium, platinum, titanium, tantalum, cobalt, tungsten, molybdenum, or zinc. The barrier layer 116 can advantageously reduce oxidation or contamination of the head 114.

[0020] The support 110 may further include a solder layer 118 on the barrier layer 116 or on the head 114 (in the case where the barrier layer 116 is omitted). The solder layer 118 is located on the exterior of the microelectronic device 100. For example, the solder layer 118 may contain tin, silver, bismuth, or other metals. The barrier layer 116 can advantageously reduce the formation of intermetallic compounds.

[0021] The dielectric layer 106 extends from the die 102 to the head 114 and may optionally extend further to the barrier layer 116 or the solder layer 118. A pillar 110 extends from the I / O terminal 104 through the dielectric layer 106 to the exterior of the microelectronic device 100. The dielectric layer 106 may advantageously provide support for the pillar 110 and provide protection for the die 102 during subsequent assembly and packaging operations.

[0022] Figures 2A to 2L This is a cross-section of the microelectronic device depicted during a stage of the example fabrication method. (Reference) Figure 2A The microelectronic device 200 includes a die 202. The die 202 may be part of a semiconductor wafer or a MEMS substrate. The semiconductor wafer or MEMS substrate may contain additional dies similar to the die 202 (in... Figure 2A(Not shown in the image). Alternatively, die 202 can be separated from other dies, for example, as a result of slicing die 202 off a semiconductor wafer or MEMS substrate.

[0023] Die 202 includes I / O terminals 204. I / O terminals 204 may primarily comprise aluminum or copper and may have a cover layer or under-bump metallization (UBM) layer of nickel, palladium, platinum, gold, or other metals. I / O terminals 204 may be electrically coupled to components in die 202 through through-holes 220 or other conductive structures in die 202.

[0024] A trench material layer 222 is formed on die 202, the trench material layer covering I / O terminals 204. The trench material layer 222 may contain a photosensitive polymer material, such as a photoresist containing polyisoprene, a photosensitive polyimide, a photosensitive epoxy resin such as SU-8, or a photoresist containing methacrylate. The trench material layer 222 may contain an organic resin, such as polymethyl methacrylate (PMMA) sensitive to electron beam radiation. The trench material layer 222 may be formed, for example, by spin coating or by application as a dry film.

[0025] The trench material layer 222 is exposed to patterned radiation 224, such as ultraviolet (UV) radiation from a photolithography tool. The patterned radiation 224 has a spatial distribution aligned with the spatial distribution of the I / O terminals 204. In one version of this example, where the photosensitive polymer material in the trench material layer 222 has a negative hue, the patterned radiation 224 can expose the trench material layer 222 in regions of the subsequently formed columnar trench sublayer 226, such as... Figure 2B As shown. Return to reference. Figure 2A ,like Figure 2A As depicted, the patterned radiation 224 can be isolated from the area of ​​the columnar trench 228 above the I / O terminal 204. In an alternative version of this example, where the photosensitive polymer material in the trench material layer 222 has a positive hue, the patterned radiation 224 can expose the trench material layer 222 in the area of ​​the columnar trench 228 and can be isolated from the area of ​​the subsequently formed columnar trench sublayer 226.

[0026] refer to Figure 2B The developing operation starts from Figure 2A The trench material layer 222 removes material from the columnar trenches 228 to form a columnar trench sublayer 226. The columnar trench sublayer 226 can be heated to remove volatile materials (such as solvents) and optionally increase cross-linking between polymer molecules in the columnar trench sublayer 226 to provide greater durability. The columnar trenches 228 in the columnar trench sublayer 226 expose I / O terminals 204.

[0027] Alternatively, laser ablation can be used to achieve this by... Figure 2A Material is removed from the trench material layer 222 to form the columnar trench sublayer 226. The use of a laser ablation process enables the columnar trench sublayer 226 to be formed from a wider range of materials (including non-photosensitive materials), which can advantageously reduce the manufacturing cost of the microelectronic device 200.

[0028] refer to Figure 2C A columnar liner 230 is formed on the columnar trench sublayer 226, the columnar liner extending into the columnar trench 228 and contacting the I / O terminal 204. The columnar liner 230 may include an adhesive sublayer that directly contacts the columnar trench sublayer 226 within the columnar trench 228. The adhesive sublayer may contain a metal with good adhesion to the columnar trench sublayer 226, such as titanium or titanium-tungsten, and may be formed by a sputtering process. The columnar liner 230 may also include a barrier sublayer that effectively reduces copper diffusion into the columnar trench sublayer 226. The barrier sublayer may contain, for example, titanium nitride or tantalum nitride, and may be formed by a reactive sputtering process or an atomic layer deposition (ALD) process. The columnar liner 230 may include a seed layer that provides a suitable conductive surface for subsequent electroplating operations. The seed layer may contain, for example, nickel or copper, and may be formed by a sputtering process or an evaporation process.

[0029] refer to Figure 2D A columnar layer 234 is formed on a columnar liner 230 using a columnar plating bath 232. The columnar layer 234 fills the columnar trenches 228 and extends adjacent to the columnar trenches 228 over a columnar trench sublayer 226. The columnar layer 234 may primarily comprise copper, for example, greater than 90% by weight. The columnar layer 234 may also comprise other metals, such as nickel, silver, or gold. The columnar plating bath 232 contains copper, for example, in the form of copper sulfate. The columnar plating bath 232 may contain additives, such as leveling agents; suppressors (sometimes called inhibitors); and accelerators (sometimes called whitening agents), to provide the desired low-thickness columnar layer 234 adjacent to the columnar trenches 228 over the columnar trench sublayer 226.

[0030] refer to Figure 2EThe columnar layer 234 and columnar liner 230 adjacent to the columnar trench 228 are removed above the columnar trench sublayer 226, leaving the columnar liner 230 and columnar layer 234 in the columnar trench 228 to provide columns 212. The columnar liner 230 extends around the lateral boundary of each column 212. The columnar layer 234 above the columnar trench sublayer 226 can be removed, for example, by a copper chemical mechanical polishing (CMP) process using a polishing pad and a copper-removing slurry. The columnar liner 230 above the columnar trench sublayer 226 can also be removed by a copper CMP process or by a selective wet etching process. See reference... Figures 2C to 2E The disclosed method for forming columnar objects 212 is sometimes referred to as an inlay process, specifically a copper inlay process.

[0031] refer to Figure 2F A head groove sublayer 236 is formed above the columnar groove sublayer 226. The head groove sublayer 236 has head grooves 238 that expose the top of the columnar column 212. Each head groove in the head grooves 238 extends laterally beyond the top of the columnar column 212 exposed by the head groove 238 in at least one lateral direction. The composition of the head groove sublayer 236 can be similar to that of the columnar groove sublayer 226. Furthermore, it can be constructed using a method similar to that referenced... Figure 2A and Figure 2B The disclosed process sequence for forming the columnar trench sublayer 226 is used to form the head trench sublayer 236.

[0032] refer to Figure 2G A head liner 240 is formed on a head trench sublayer 236, the head liner extending into the head trench 238 and contacting the columnar liner 212. The head liner 240 may have a sublayer structure and composition similar to that of the columnar liner 230, namely, a binder sublayer comprising titanium or titanium-tungsten, a barrier sublayer comprising titanium nitride or tantalum nitride, and a seed layer comprising nickel or copper. The sublayers of the head liner 240 may be formed using processes similar to those used to form the sublayers of the columnar liner 230, namely, sputtering, reactive sputtering, or ALD processes, as well as sputtering or evaporation processes.

[0033] A head layer 244 is formed on the head liner 240 using a head plating process employing a head plating bath 242. The head layer 244 fills the head trench 238 and extends adjacent to the head trench 238 above a head trench sublayer 236. The head layer 244 may primarily comprise copper and may have a composition similar to that of the columnar layer 234. The head plating bath 242 comprises copper and may contain... Figure 2DAdditives similar to those in columnar plating bath 232, namely, leveling agents, inhibitors and promoters, are used to provide a desired low-thickness head layer 244 above the head trench sublayer 236 adjacent to the head trench 238.

[0034] refer to Figure 2H The head layer 244 and head liner 240 adjacent to the head trench 238 are removed above the head trench sublayer 236, leaving the head liner 240 and head layer 244 in the head trench 238 to provide the head 214. The head liner 240 extends around the lateral boundary of each head 214. The head layer 244 and head liner 240 can be removed from the head trench sublayer 236 by a copper CMP process, optionally followed by a wet etching process. The head 214 is electrically connected to pillars 212. The pillars 212 combined with the head 214 provide pillars 210 for the microelectronic device 200. The pillar liner 230 can advantageously reduce copper diffusion from the pillar layer 234 into the pillar trench sublayer 226. Similarly, the head liner 240 can advantageously reduce copper diffusion from the head layer 244 into the head trench sublayer 236. Copper diffusion into the columnar trench sublayer 226 or the head trench sublayer 236 can reduce the reliability of the microelectronic device 200.

[0035] refer to Figure 2I A barrier layer 216 is formed on the head 214 using a barrier plating process in a barrier plating tank 246. The barrier layer 216 is part of the support 210. The barrier plating process can be an electroless process. The barrier layer 216 can have the following characteristics as shown in the reference. Figure 1 The barrier layer 116 has the composition disclosed. The barrier plating bath 246 may contain nickel in the form of nickel sulfate, and may contain other metals in the form of metal salts, to form the desired composition of the barrier layer 216. The barrier layer 216 is an assembly of the pillar 210. Other methods of forming the barrier layer 216 are also within the scope of this example.

[0036] refer to Figure 2J The barrier layer 216 is exposed to a liquid solder source 248 containing molten solder, which forms a solder layer 218 on the barrier layer 216. The solder layer 218 is part of the pillar 210. The liquid solder source 248 can be pumped onto the microelectronic device 200 to expose the barrier layer 216 to the molten solder. Alternatively, the microelectronic device 200 can be immersed in the molten solder of the liquid solder source 248 to expose the barrier layer 216 to the molten solder. The solder layer 218 may have the following characteristics as referenced... Figure 1 The solder layer 118 is disclosed to contain tin, silver, bismuth, or other metals. The solder layer 218 is an assembly of the support 210.

[0037] refer to Figure 2KThe microelectronic device 200 is assembled onto a circuit substrate 250. For example, the circuit substrate 250 may be a printed circuit board (PCB) or a ceramic wiring substrate. The circuit substrate 250 has conductive pads 252 positioned on an insulating layer 254. The pads 252 may be die pads, leads, traces, wiring, or other conductive components of the circuit substrate 250. The pads 252 may primarily comprise copper and may optionally comprise gold, nickel, or other metals to provide a suitable surface for solder joints. The insulating layer 254 may be a glass fiber reinforced plastic (FRP) board, a ceramic substrate, or other insulating medium. The microelectronic device 200 is assembled onto the circuit substrate 250 by contacting the solder layer 218 with the pads 252 and heating the solder layer 218 to form a solder connection between the pillar 210 and the pads 252.

[0038] Figure 2L A microelectronic device 200 assembled onto a circuit substrate 250 is depicted. A solder layer 218 provides solder connections between pillars 210 and pads 252. A combination of a pillar trench sublayer 226 and a head trench sublayer 236 provides a dielectric layer 206. The pillar trench sublayer 226 laterally surrounds pillars 212. The head trench sublayer 236 laterally surrounds heads 214. In this example, the dielectric layer 206 extends from die 202 to a barrier layer 216, laterally surrounding pillars 212 and heads 214. The dielectric layer 206 advantageously provides support for pillars 210 and provides protection for die 202 during and after assembly onto the circuit substrate 250, and during use of the assembled microelectronic device 200.

[0039] Figures 3A to 3F This is a cross-section of a microelectronic device depicted in a stage of another example fabrication method. (Reference) Figure 3A The microelectronic device 300 includes a die 302. The die 302 may be part of a semiconductor wafer or a MEMS substrate, or it may be a discrete component. The die 302 includes I / O terminals 304. The configuration of the I / O terminals 304 may be similar to that in the reference [reference]. Figure 2A The composition disclosed for the I / O terminal 204. The die 302 may include conductive members 320 that electrically couple the I / O terminal 304 to one or more components in the die 302.

[0040] A dielectric layer 306 is formed on die 302. The dielectric layer 306 is formed as a columnar trench 328 having exposed I / O terminals 304. The dielectric layer is further formed as having one or more head trenches 338 leading to the columnar trenches 328. In this example, the head trenches 338 lead to two columnar trenches 328.

[0041] like Figure 3AAs described herein, a dielectric layer 306 can be formed by a first additive manufacturing process, which uses an adhesive jetting apparatus 358 to place dielectric material 356 on a die 302 to form at least a portion of the dielectric layer 306. In this specification, the additive manufacturing process places the dielectric material 356 within a desired region and does not place the dielectric material 356 outside the desired region, making it unnecessary to remove a portion of the placed dielectric material 356 to produce the final desired shape of the dielectric layer 306. The additive manufacturing process allows the dielectric layer 306 to be formed without photolithography, thereby advantageously reducing manufacturing costs and complexity. Examples of additive manufacturing processes suitable for forming the dielectric layer 306 include adhesive jetting, material jetting, directional energy deposition, material extrusion, powder bed melting, sheet lamination, vat photopolymerization, direct laser deposition, electrostatic deposition, laser sintering, and photopolymerization extrusion.

[0042] In one version of this example, dielectric layer 306 may comprise an organic polymer, such as epoxy resin, benzocyclobutene (BCB), polyimide, or acrylic acid. In another version, dielectric layer 306 may comprise a silicone polymer. In a further version, dielectric layer 306 may comprise an inorganic dielectric material, such as silicon dioxide, silicon nitride, boron nitride, or aluminum oxide. The inorganic dielectric material may be implemented as sintered or as particles of inorganic material with a polymer binder.

[0043] The dielectric layer 306 can be heated after the dielectric material 356 is placed to remove volatile materials from the dielectric layer 306 or to crosslink the polymer material in the dielectric layer 306. The dielectric layer 306 can be heated, for example, by a radiant heating process, a hot plate heating process, a furnace heating process, or a forced air convection heating process.

[0044] refer to Figure 3B A pillar liner 360 is formed on dielectric layer 306, the pillar liner extending into head groove 338 and pillar groove 328 and contacting I / O terminal 304. The pillar liner 360 may have a similar design to the reference design. Figure 2C The columnar liner 230 discloses a layer structure and composition, namely, a binder sublayer comprising titanium or titanium-tungsten, a barrier sublayer comprising titanium nitride or tantalum nitride, and a seed layer comprising nickel or copper. The columnar liner 360 can be formed by any of the processes disclosed with reference to the columnar liner 230, namely sputtering, reactive sputtering, or ALD processes, as well as sputtering or evaporation processes.

[0045] refer to Figure 3CA pillar layer 362 is formed on the pillar liner 360, the pillar layer filling the pillar grooves 328 and the head grooves 338 and extending on the pillar liner 360 adjacent to the head grooves 338. The pillar layer 362 can be formed by an electroplating process. The pillar layer 362 may primarily comprise copper, i.e., greater than 90% by weight of copper. The pillar layer 362 may optionally comprise other metals, such as nickel, silver, or gold.

[0046] refer to Figure 3D The pillar layer 362 and pillar liner 360 adjacent to the head trench 338 above the dielectric layer 306 are removed, leaving the pillar layer 362 and pillar liner 360 in the pillar trench 328 and head trench 338 to provide the pillar 312 and head 314 of the pillar 310, respectively. The pillar layer 362 and pillar liner 360 can be removed from the head trench 338 above the dielectric layer 306, for example, by a CMP process, an etch-back process, or a combination thereof. See reference Figures 3B to 3D The disclosed method for forming the column 312 and the head 314 is sometimes referred to as a double-stacking process. Compared with other methods for forming the column 310, the double-stacking process can provide reduced manufacturing costs and complexity.

[0047] refer to Figure 3E A barrier layer 316 is formed on the head 314. If another head 314 exists in the microelectronic device 300, another barrier layer 316 is formed on the other head. The barrier layer 316 may have the following characteristics as shown in the reference. Figure 1 The composition disclosed in the barrier layer 116, namely, may include nickel, palladium, platinum, titanium, tantalum, cobalt, tungsten, molybdenum, or zinc, and may be as described in the reference. Figure 2I The barrier layer 216 is formed as disclosed. The barrier layer 316 is a component of the pillar 310, i.e., formed by using an electroless plating process with a barrier plating bath.

[0048] A solder layer 318 is formed on the barrier layer 316. The solder layer 318 can be formed by a second additive manufacturing process, such as a material extrusion process using material extrusion equipment 366 to apply solder paste 364 onto the barrier layer 316. The solder layer 318 can be heated to remove volatile materials or reduce the resistance between the solder layer 318 and the barrier layer 316. The solder layer 318 is an assembly of the pillar 310. Another solder layer 318 can be formed on another barrier layer 316, if present in the microelectronic device 300.

[0049] refer to Figure 3FThe microelectronic device 300 is assembled onto a circuit substrate 350. The circuit substrate 350 has conductive pads 352 positioned on an insulating layer 354. The microelectronic device 300 is assembled onto the circuit substrate 350 by contacting a solder layer 318 with the pads 352 and heating the solder layer 318 to form a solder connection between the pillar 310 and the pads 352. A dielectric layer 306 can provide a reference for the microelectronic device 300. Figure 2L The advantages disclosed are similar to those of providing support for the pillar 310 and protection for the die 302 during and after assembly to the circuit substrate 350 and during use of the assembled microelectronic device 300.

[0050] Figures 4A to 4F This is a cross-section of a microelectronic device depicted in a stage of another example fabrication method. (Reference) Figure 4A The microelectronic device 400 includes a die 402. The die 402 may be part of a workpiece containing other devices, or it may be a discrete workpiece containing only the die 402. The die 402 includes at least one I / O terminal 404. The configuration of the I / O terminal 404 may be similar to that referenced in [reference]. Figure 2A The composition disclosed for the I / O terminal 204 is such that it may primarily comprise aluminum or copper and may have a capping layer or UBM layer of nickel, palladium, platinum, gold or other metals.

[0051] A dielectric layer 406 is formed on die 402. The dielectric layer 406 is formed as a pillar trench 428 having exposed I / O terminals 404. The dielectric layer is further formed as having a head trench 438 leading to the pillar trench 428. The dielectric layer 406 may have additional pillar trenches (not shown) exposing additional I / O terminals (not shown), and may have additional head trenches (also not shown) leading to the additional pillar trenches. Figure 4A As depicted, at least a portion of the dielectric layer 406 can be formed by a first additive manufacturing process, such as a directional energy process for depositing dielectric material 456 onto a die 402 using a directional energy device 458. The directional energy process delivers the dielectric material 456 to the die 402 in the form of microparticles or nanoparticles via an inert gas flow, and melts the dielectric material 456 onto the die 402 using directional thermal energy (e.g., directional thermal energy from a focused laser beam). The dielectric layer 406 may include a reference... Figure 3A The dielectric layer 306 may contain any of the materials disclosed herein, i.e., may contain organic polymers (such as epoxy resin, BCB, polyimide or acrylic acid), may contain silicone polymers, or may contain inorganic dielectric materials (such as silicon dioxide, silicon nitride, boron nitride or aluminum oxide), wherein the inorganic dielectric material is optionally embodied as sintered or inorganic material particles with polymer binders.

[0052] refer to Figure 4B Conductive material 468 is disposed in pillar trench 428 and head trench 438 to form at least a portion of pillar conductor 470. The pillar conductor 470 in pillar trench 428 provides a pillar 412 for pillar 410 of microelectronic device 400. The pillar conductor 470 in head trench 438 provides a head 414 for pillar 410. Figure 4B As depicted, conductive material 468 can be placed in columnar trenches 428 and head trenches 438 via a second additive manufacturing process (such as an electrostatic deposition process using electrostatic deposition equipment 472). Other additive manufacturing processes can be used to form columnar materials 412 and head 414. Conductive material 468 may comprise metal nanoparticles, such as copper, gold, silver, or aluminum nanoparticles. Conductive material 468 may comprise carbon nanotubes, graphene, or other graphitic materials. In one version of this example, columnar materials 412 and head 414 can be formed via separate additive manufacturing processes using different conductive materials. Columnar materials 412 or head 414 can be heated to remove volatile materials (such as solvents or carrier liquids) to melt the conductive particles of conductive material 468 together, or the metal in conductive material 468 can be melted to form an alloy in columnar materials 412 or head 414. The metal nanoparticles in the conductive material 468 can melt or thaw at a temperature significantly lower than the melting temperature of bulk metals with the same composition, which can advantageously reduce the thermal degradation of the microelectronic device 400.

[0053] refer to Figure 4C In the first contact region 474 and the second contact region 476, a barrier layer 416 is formed on the head 414. The composition of the barrier layer 416 can be similar to... Figure 1 The composition of the barrier layer 116 is disclosed. For example... Figure 4C As depicted, the barrier layer 416 can be formed via a third additive manufacturing process, such as an electrochemical deposition process using electrochemical deposition equipment 478. The barrier layer 416 can also be formed by other methods, such as sputtering a thin film of barrier metal followed by masking and etching. The barrier layer 416 is an assembly of the pillar 410.

[0054] refer to Figure 4D On the head 414, an insulating layer 480 is formed adjacent to the barrier layer 416. The insulating layer 480 prevents unintended electrical contact with the head 414. The insulating layer 480 may comprise, for example, an organic polymer material, a silicone polymer material, an inorganic material, or a combination thereof. The insulating layer 480 may be formed by a third additive process, such as a photopolymerization extrusion process using a photopolymerization extrusion apparatus 482 having a monomer source 482a and an ultraviolet laser 482b. The insulating layer 480 is an assembly of the pillar 410.

[0055] refer to Figure 4EA solder layer 418 can be formed on the barrier layer 416. The solder layer 418 can be formed by a fourth additive manufacturing process, such as a material extrusion process using material extrusion equipment 466 to place solder paste 464 on the barrier layer 416. See reference... Figure 3E Disclosed, the solder layer 418 can be heated to remove volatile materials or reduce the resistance between the solder layer 418 and the barrier layer 416. The solder layer 418 is an assembly of the support 410.

[0056] refer to Figure 4F The microelectronic device 400 is assembled onto a circuit substrate 450. The circuit substrate 450 has an insulating layer 454 and conductive pads 452a, 452b, and 452c located on the insulating layer 454. The microelectronic device 400 is assembled onto the circuit substrate 450 by contacting a solder layer 418 with the pads 452a and 452c and heating the solder layer 418 to form solder connections between the pads 452a and 452c and the pillar 410 in a first contact region 474 and a second contact region 476, respectively. An insulating layer 480 prevents electrical contact between the pad 452b and the head 414. A dielectric layer 406 provides the microelectronic device 400 with a reference... Figure 2L The advantages disclosed are similar to those of providing support for the pillar 410 and protection for the die 402 during and after assembly to the circuit substrate 450 and during use of the assembled microelectronic device 400.

[0057] Figures 5A to 5G This is a cross-section of a microelectronic device depicted in a stage of another example fabrication method. (Reference) Figure 5A The microelectronic device 500 includes a die 502. The die 502 includes I / O terminals 504. A seed layer 584 is formed on the die 502. The seed layer 584 is conductive and electrically contacts the I / O terminals 504. The seed layer 584 may include an adhesive sublayer having titanium, tungsten, or nickel directly on the die 502. The seed layer 584 may include an electroplated surface sublayer having copper or nickel to provide a suitable surface for electroplating processes.

[0058] An electroplating mask 586 is formed on the seed layer 584. The electroplating mask 586 has pillar openings 588 of the seed layer 584 exposed over the I / O terminal 504. The pillar openings 588 may taper gradually, being narrower at one end near the I / O terminal 504 and wider at the opposite end far from the I / O terminal 504.

[0059] In one version of this example, the electroplating mask 586 may comprise an organic polymer and may be formed by forming a mask layer of the organic polymer on a seed layer 584. Pillar openings 588 may be formed in the mask layer using a laser ablation process employing a scanning laser ablation apparatus 590. After the formation of the pillar openings 588 is completed, the remaining mask layer provides the electroplating mask 586. Figure 5A The conical configuration of the columnar opening 588 can advantageously provide additional process tolerance for laser ablation processes.

[0060] In another version, the electroplating mask 586 may comprise a photoresist, a photosensitive polyimide, or a photosensitive silicone polymer, and may be formed by a photolithography operation. Forming pillar openings 588 with a tapered configuration can advantageously provide additional process tolerance for the photolithography operation. Alternatively, the electroplating mask 586 may be formed by an additive manufacturing process or a screen printing process.

[0061] refer to Figure 5B A pillar conductor 570 is formed in the pillar opening 588 by using an electroplating operation of a seed layer 584. The pillar conductor 570 may contain, for example, copper, nickel, gold, silver, palladium, platinum, or tungsten. Figure 5B The pillar conductor 570 is depicted as being halfway through the electroplating process.

[0062] refer to Figure 5C The electroplating operation continues to complete the pillar conductor 570. In this example, the pillar conductor 570 extends above and laterally beyond the pillar opening 588. A portion of the pillar conductor 570 in the pillar opening 588 provides the pillar 512 of the pillar 510 of the microelectronic device 500. A portion of the pillar conductor 570 above the electroplating mask 586 provides the head 514 of the pillar 510.

[0063] refer to Figure 5D A barrier layer 516 is formed on the head 514. The barrier layer 516 can be formed, for example, by using one or more electroplating processes, one or more electroless plating processes, by additive manufacturing, or by sputtering a thin film of barrier metal onto the seed layer 584, followed by masking and etching. Figure 1 The composition disclosed in the barrier layer 116. The barrier layer 516 is a component of the support column 510.

[0064] refer to Figure 5E Remove Figure 5DThe electroplating mask 586 is used. The electroplating mask 586 can be removed, for example, by using an oxygen ashing process, an ozone process, a wet cleaning process using organic solvents, or a combination thereof. After removing the electroplating mask 586, a seed layer 584 is removed from the area exposed by the pillar 512, leaving a seed layer 584 between the pillar 512 and the I / O terminal 504. The seed layer 584 can be removed, for example, by a plasma etching process, a wet etching process, an electrochemical etching process (sometimes referred to as a reverse electroplating process), or a combination thereof. The portion of the seed layer 584 between the pillar 512 and the I / O terminal 504 is an assembly of the pillar 510.

[0065] refer to Figure 5F A dielectric layer 506 is formed on die 502. Dielectric layer 506 may include a reference... Figure 1 The dielectric layer 506 may be any of the dielectric materials disclosed herein. The dielectric layer 506 extends from the die 502 to the head 514 and may optionally extend upwards to half of the side of the head 514. The dielectric layer 506 may provide the advantages disclosed herein with reference to dielectric layers 106, 206, 306, and 406 in other examples, namely, that it may provide support for the pillar 510 and protection for the die 502 during and after assembly, and during use of the assembled microelectronic device 500.

[0066] The dielectric layer 506 can be formed by a molding process, wherein dielectric material is disposed on a die 502 between pillars 510, and then molded into the desired configuration using a molding die 592. Other methods for forming the dielectric layer 506, such as spin coating and then etch-back processes, are also within the scope of this example.

[0067] refer to Figure 5G The microelectronic device 500 is assembled onto a circuit substrate 550. The circuit substrate 550 has an insulating layer 554 and pads 552. The pads 552 are conductive. Solder preforms 594 can be placed on the pads 552. Figure 5G As shown, the microelectronic device 500 is assembled by bringing the pillar 510 and the pad 552 into contact with the solder preform 594. The solder preform 594 is heated to reflow the solder preform 594, thereby forming solder joints between the pillar 510 and the pad 552.

[0068] The various features of the examples disclosed herein can be combined in other manifestations of the example integrated circuit. For example, this can be achieved by referring to... Figures 2A to 2L , Figures 3A to 3F , Figures 4A to 4F or Figures 5A to 5F Any method formed in the disclosed method Figure 1 Pillar 110. Similarly, it can be referenced... Figures 2A to 2L , Figures 3A to 3F , Figures 4A to 4F or Figures 5A to 5F Any method formed in the disclosed method Figure 1 The dielectric layer 106. The steps disclosed in the example methods for forming dielectric layers 206, 306, 406 or 506 herein may be combined with the steps disclosed in other instances herein for forming pillars 212, 312, 412 or 512, and may be further combined with the steps disclosed in further instances herein for forming heads 214, 314, 414 or 514.

[0069] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are possible.

Claims

1. A microelectronic device, comprising: a die; a first input / output (I / O) terminal and a second I / O terminal on the die; a dielectric layer on the die; a first post electrically coupled to the first I / O terminal and a second post electrically coupled to the second I / O terminal; and a head electrically coupled to both the first post and the second post at an end of each of the first post and the second post opposite the first I / O terminal and the second I / O terminal, the head extending through the dielectric layer, wherein the first I / O terminal and the second I / O terminal are on a same side of the die.

2. The microelectronic device of claim 1, wherein the head extends laterally through the first post in at least one lateral direction.

3. The microelectronic device of claim 1, further comprising a barrier layer on the head and a solder layer in contact with the barrier layer.

4. The microelectronic device of claim 3, wherein the barrier layer includes a metal selected from the group consisting of nickel, palladium, platinum, titanium, tantalum, cobalt, tungsten, molybdenum, and zinc.

5. The microelectronic device of claim 1, wherein: the first post and the second post include copper; and the head includes copper.

6. The microelectronic device of claim 1, wherein the first post and the second post include one of nickel, platinum, aluminum, tungsten, gold, graphene, or carbon nanotubes.

7. The microelectronic device of claim 1, wherein the dielectric layer includes a photosensitive polymer material.

8. The microelectronic device of claim 1, wherein the first post and the second post include a conductive post liner extending around lateral boundaries of the first post and the second post, and the head includes a conductive head liner extending around a lateral boundary of the head.

9. An interconnect structure, comprising: a dielectric layer; a first post electrically coupled to a first contact on a die and a second post electrically coupled to a second contact on the die, the first contact and the second contact on a same side of the die; and a head electrically coupled to both the first post and the second post at an end of each of the first post and the second post opposite the first contact and the second contact, the head extending through the dielectric layer, a portion of the head exposed from a surface of the dielectric layer.

10. The interconnect structure of claim 9, wherein the head extends laterally through the first post in at least one lateral direction.

11. The interconnect structure of claim 9, further comprising a barrier layer on the portion of the head and a solder layer in contact with the barrier layer.

12. The interconnect structure of claim 11, wherein the barrier layer includes a metal selected from the group consisting of nickel, palladium, platinum, titanium, tantalum, cobalt, tungsten, molybdenum, and zinc.

13. The interconnect structure of claim 9, wherein: the first and second posts comprise copper; and the head comprises copper.

14. The interconnect structure of claim 9, wherein the first and second posts comprise one of nickel, platinum, aluminum, tungsten, gold, graphene, or carbon nanotubes.

15. The interconnect structure of claim 9, wherein the dielectric layer comprises a photosensitive polymer material.

16. The interconnect structure of claim 9, wherein the first and second posts comprise an electrically conductive post liner extending around lateral boundaries of the first and second posts, and the head comprises an electrically conductive head liner extending around a lateral boundary of the head.

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