Address mapping method and device, terminal, base station, readable storage medium and program product

Abstract

The invention relates to an address mapping method and device, a terminal, a base station, a readable storage medium and a program product, relates to the technical field of computers, and can improve the utilization efficiency of a chip containing bad blocks. The method comprises the following steps: determining an address to be mapped; the address mapping bit of the to-be-mapped address has a target address mapping code; the target address mapping code comprises at least one of a plurality of continuous address mapping codes; the address mapping codes are used for corresponding to blocks in the storage chip; obtaining a physical address of the to-be-mapped address in a normal block corresponding to the storage chip based on the target address mapping code; different normal blocks included in the storage chip correspond to different address mapping codes; the storage chip comprises at least one abnormal block, and the address mapping code corresponding to the abnormal block corresponds to a normal block included in the storage chip.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an address mapping method, apparatus, terminal, base station, computer-readable storage medium, and computer program product. Background Technology

[0002] With the development of chip testing and repair technology, chips containing bad blocks can be recycled and reused with the help of relevant chip repair methods.

[0003] In related technologies, reuse is mainly achieved by redesigning chip hardware. For example, bad blocks in the chip can be avoided through hardware-level modifications and adaptations, allowing the chip to continue to be used.

[0004] However, this approach is highly targeted; each hardware modification scheme may only be applicable to chips with specific bad block distribution patterns, and the hardware modification is costly and time-consuming. Therefore, the relevant technologies suffer from low utilization efficiency when reusing chips containing bad blocks. Summary of the Invention

[0005] Therefore, it is necessary to provide an address mapping method, apparatus, terminal, base station, computer-readable storage medium, and computer program product to address the aforementioned technical problems.

[0006] Firstly, this application provides an address mapping method, including:

[0007] The address to be mapped is determined; the address mapping bits of the address to be mapped have a target address mapping code; the target address mapping code includes at least one of a plurality of consecutive address mapping codes; the address mapping code is used to correspond to a block in the memory chip;

[0008] Based on the target address mapping code, the physical address of the address to be mapped in the normal block corresponding to the memory chip is obtained; different normal blocks included in the memory chip correspond to different address mapping codes; the memory chip includes at least one abnormal block, and the address mapping code corresponding to the abnormal block is mapped to the normal block included in the memory chip.

[0009] In one embodiment, obtaining the physical address of the address to be mapped in the normal block corresponding to the memory chip based on the target address mapping code includes:

[0010] Based on the target address mapping code and mapping relationship configuration information, the physical address of the address to be mapped in the normal block corresponding to the memory chip is obtained; the mapping relationship configuration information includes the mapping relationship between the address identifier and the address mapping code of the normal block; the mapping relationship configuration information before the memory chip generates the abnormal block is different from the mapping relationship configuration information after the memory chip generates the abnormal block.

[0011] In one embodiment, obtaining the physical address of the address to be mapped in the normal block corresponding to the memory chip based on the target address mapping code and mapping relationship configuration information includes:

[0012] Based on the chip select flag, block flag, and mapping relationship configuration information of the target address mapping code, a target address identifier corresponding to the target normal block selected in the target memory chip is obtained; the target memory chip select includes at least one of a plurality of memory chip selects in the memory chip, and the target normal block includes at least one of the plurality of normal blocks selected in the target memory chip.

[0013] Based on the target address identifier, determine the physical address of the address to be mapped in the target normal block.

[0014] In one embodiment, at least one address mapping code to be processed in the mapping relationship configuration information is determined according to the address mapping code corresponding to the first abnormal block, and the at least one address mapping code to be processed is sequentially corresponding to the address identifier of at least one normal block following the first abnormal block.

[0015] In one embodiment, at least one normal block following the first abnormal block includes:

[0016] The normal block of the same memory chip select as the first abnormal block of the memory chip, and / or the normal block of a different memory chip select of the memory chip as the first abnormal block of the memory chip.

[0017] In one embodiment, the address mapping code corresponding to the abnormal block is mapped to the address identifier of the last normal block of the memory chip in the mapping relationship configuration information.

[0018] In one embodiment, after determining the address to be mapped, the method further includes:

[0019] Based on the values ​​of multiple target bits in the address to be mapped, the target address mapping code on the address mapping bits of the address to be mapped is determined; the number of target bits is related to the number of blocks in the memory chip.

[0020] Secondly, this application also provides an address mapping device, comprising:

[0021] The address acquisition module is used to determine the address to be mapped; the address to be mapped has a target address mapping code on the address mapping bits; the target address mapping code includes at least one of a plurality of consecutive address mapping codes; the address mapping code is used to correspond to a block in the memory chip;

[0022] The address mapping module is used to obtain the physical address of the address to be mapped in the normal block of the memory chip based on the target address mapping code; different normal blocks included in the memory chip correspond to different address mapping codes; the memory chip includes at least one abnormal block, and the address mapping code corresponding to the abnormal block is mapped to the normal block included in the memory chip.

[0023] Thirdly, this application also provides a terminal, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the address mapping method as described in any of the preceding claims.

[0024] Fourthly, this application also provides a base station, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the address mapping method as described in any of the preceding claims.

[0025] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the address mapping method as described in any of the preceding claims.

[0026] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the address mapping method as described in any of the preceding claims.

[0027] The aforementioned address mapping method, apparatus, terminal, base station, computer-readable storage medium, and computer program product can determine an address to be mapped, wherein the address mapping bits of the address to be mapped have a target address mapping code, the target address mapping code includes at least one of a plurality of consecutive address mapping codes, the address mapping code is used to correspond to a block in the memory chip, and then the physical address of the normal block corresponding to the address to be mapped in the memory chip can be obtained based on the target address mapping code, wherein different normal blocks included in the memory chip correspond to different address mapping codes, the memory chip includes at least one abnormal block, and the address mapping code corresponding to the abnormal block is mapped to the normal block included in the memory chip. In this embodiment, on the one hand, by constructing a correspondence between blocks and address mapping codes in the memory chip, the address to be mapped can be accurately mapped to the physical address of a specified normal block using the address mapping code, thus achieving physical address mapping within the specified block. On the other hand, by mapping the address mapping codes corresponding to abnormal blocks containing bad blocks in the memory chip to normal blocks in the memory chip, bad blocks can be excluded from address mapping in software, while other normal blocks in the memory chip are utilized effectively without redesigning the hardware, thus reducing chip design costs. Furthermore, this embodiment can accurately and flexibly map the address to be mapped to a specified normal block for abnormal blocks in different memory chips, exhibiting high flexibility and universality. Therefore, this embodiment can effectively improve utilization efficiency when reusing chips containing bad blocks. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart illustrating an address mapping method in one embodiment;

[0030] Figure 2 This is a diagram showing the storage space configuration of a storage chip in one embodiment;

[0031] Figure 3a This illustrates a correspondence between an address mapping code and a block in one embodiment;

[0032] Figure 3b This illustrates a correspondence between an address mapping code and a block in one embodiment;

[0033] Figure 4 This is a flowchart illustrating another address mapping method in one embodiment;

[0034] Figure 5 This is a structural block diagram of an address mapping device in one embodiment;

[0035] Figure 6 This is an internal structural diagram of a computer device in one embodiment;

[0036] Figure 7 This is an internal structural diagram of another computer device in one embodiment. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0038] It should be noted that the terms "comprising" and "having," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusion. The term "multiple" as used in this application refers to two or more. The term "and / or" as used in this application refers to one of the solutions, or any combination of multiple solutions.

[0039] In one embodiment, such as Figure 1 As shown, an address mapping method is provided. This embodiment illustrates the application of this method to an electronic device, where the electronic device can refer to any device including memory, such as a terminal, base station, server, or one or more other devices. The electronic device may have a chip deployed on it, and the method can be executed through the chip. Furthermore, this method can also be applied to chip modules, virtual devices, and storage media. For example, a virtual device may include a chip, and the various modules within the virtual device may include software and / or hardware.

[0040] In this embodiment, the method may include the following steps:

[0041] Step S101: Determine the address to be mapped; the address mapping bits of the address to be mapped have a target address mapping code; the target address mapping code includes at least one of a series of consecutive address mapping codes; the address mapping code is used to correspond to a block in the memory chip.

[0042] The address to be mapped can be understood as a logical address to be converted into a physical address of the memory chip. The address to be mapped can be generated by the processor or controller in the terminal device and can be used to indicate the storage and / or retrieval location of data. For example, in a computer system, the memory access address and system address provided by the Central Processing Unit (CPU) can be regarded as the address to be mapped.

[0043] In this context, the address mapping bits can be understood as specific bit segments on the address to be mapped used to identify the block to which the physical address belongs in the memory chip during the address mapping process. The number determined by the actual value carried by the address mapping bits can be called the address mapping code, and each address mapping code can uniquely correspond to a block in the memory chip. The target address mapping code can be an address mapping code determined based on the value of the address mapping bits of the address to be mapped.

[0044] In this context, "block" can be understood as being obtained by dividing the basic storage units of the memory chip. Each block can include a preset number of storage units (such as 256 megabytes (MB), 512 megabytes, etc.) to facilitate address management and data access.

[0045] In specific implementations, electronic devices may include memory. In some embodiments, the memory may include one or more of the following: Dynamic Random Access Memory (DRAM) and Random Access Memory (RAM).

[0046] The memory includes memory chips, which can be composed of a large number of independent memory cells. Each memory cell can store data. In some embodiments, the memory chip includes memory cells that can perform normal data read and write operations; it can also include memory cells that are difficult to use normally due to hardware failure, substandard performance, or other reasons. One or more such memory cells can form bad blocks in the memory chip. For example, multiple memory cells inside the memory chip can be arranged in rows and columns to form a memory array. When some rows in the memory array fail and cannot work normally, that is, when the memory chip contains a failed row (FAIL ROW) composed of multiple memory cells, such memory chips are also called B-rule materials.

[0047] For bad blocks contained in memory chips, memory reuse can be achieved in some ways by redesigning the chip hardware. For example, through hardware-level modifications and adaptations, bad blocks in the memory can be avoided or repaired, allowing the memory containing bad blocks to continue to be used. However, this approach is highly specific, meaning that each hardware modification scheme may only be applicable to memory with a specific bad block distribution pattern; moreover, it is costly and time-consuming, requiring a significant investment of human and material resources for hardware redesign.

[0048] To address this, this embodiment pre-divides the memory chip into multiple blocks. In some optional embodiments, the blocks can be divided according to one or more dimensions, such as row address, bank address, and column address. Corresponding address mapping codes can be assigned to each block in the memory chip, forming a continuous set of address mapping codes. For example, when using binary encoding for the address mapping codes, block 0 corresponds to address mapping code 000, block 1 to address mapping code 001, block 2 to address mapping code 010, and so on up to block 7 to address mapping code 111. These address mapping codes form a continuous set of address mapping codes (i.e., 000 to 111). By associating continuous address mapping codes with corresponding blocks in the memory chip, when an electronic device accesses different addresses to be mapped, the corresponding physical block in the memory chip can be located using the continuous mapping codes, preventing the address from becoming invalid due to one or more address mapping codes not corresponding to the appropriate block.

[0049] In this step, the address to be mapped can be obtained and parsed to obtain the target address mapping code on the address mapping bits of the address to be mapped.

[0050] Step S102: Based on the target address mapping code, obtain the physical address of the normal block corresponding to the address to be mapped in the memory chip; different normal blocks included in the memory chip correspond to different address mapping codes; the memory chip includes at least one abnormal block, and the address mapping code corresponding to the abnormal block is mapped to the normal block included in the memory chip.

[0051] Specifically, the multiple blocks obtained from dividing the memory chip can include at least one normal block and at least one abnormal block. A normal block is a block within the memory chip that can perform normal data read and write operations; that is, multiple memory cells within a normal block can be read and written normally. Different normal blocks correspond to different address mapping codes, thus allowing accurate identification of a specific normal block within the memory chip through the address mapping code. An abnormal block can be understood as a block in the memory chip where at least some memory cells are abnormal. In this embodiment, by remapping the address mapping codes corresponding to the abnormal blocks to normal blocks, the validity of address access can be guaranteed.

[0052] On the other hand, when expanding memory capacity, some methods involve adding more memory chips. However, after expansion, the total storage space of the multiple memory chips may not be an integer power of 2. For example... Figure 2The 3-megabyte (Gb), 6-megabyte, and 12-megabyte sizes shown, when constructing the relationship between blocks and address mapping codes in the memory chip, limit the tail storage space of the memory chip. This can result in a certain address mapping code not having a corresponding block, causing a non-existent physical address segment between multiple blocks. For example, ... Figure 3a As shown, the total storage space of memory chips CS0 and CS1 is 3Gb respectively. According to the integer power of 2, 4, there is 1Gb of space missing at the end of each chip. This can be addressed by configuring the blocks of CS1 to be concatenated to the end of the actual space of CS0 through continuous address mapping codes.

[0053] In this embodiment, abnormal blocks can be understood as non-existent tail space. When the memory chip contains abnormal blocks, the address mapping code corresponding to the original abnormal block can be remapped to a normal block in the memory chip. This allows the physical address contained in the abnormal block to be skipped during address mapping, and the connection is made through other normal blocks, thus achieving compatible use of abnormal blocks. For example, as... Figure 3b As shown, the address mapping code "2" originally corresponding to the bad block in the CS0 chip can be mapped to other normal blocks.

[0054] In some embodiments, blocks in the memory chip can be detected and identified at one or more stages, thereby promptly mapping the address mapping codes corresponding to abnormal blocks to normal blocks. For example, during the production or factory delivery stage, each block in the memory chip can be tested for abnormality, and the test results can be recorded. Blocks whose test results meet preset conditions are identified as abnormal blocks, and the address mapping codes corresponding to these abnormal blocks are mapped to normal blocks in the memory chip. Alternatively, after delivery, the usage of the memory chip can be monitored during actual use, and abnormal blocks can be identified among multiple blocks based on their actual read / write performance. In some embodiments, when a block includes multiple memory cells, the block can be identified as an abnormal block when the number of abnormal memory cells exceeds a threshold (where the threshold value can be greater than or equal to 1).

[0055] In this step, based on the determined target address mapping code and the mapping relationship between each normal block and the address mapping code, the normal block corresponding to the address to be mapped in the memory chip and the physical address of the address to be mapped in that normal block can be determined. The physical address can be the actual address in the memory chip used to uniquely identify a memory cell. In some embodiments, an offset bit within the block can be determined based on the address to be mapped. This offset bit can indicate the position within the block, and then the physical address of the address to be mapped in the normal block corresponding to the memory chip can be determined based on the target address mapping code and the offset bit within the block.

[0056] In the above address mapping method, the address to be mapped can be determined, wherein the address mapping bits of the address to be mapped have a target address mapping code. The target address mapping code includes at least one of a series of consecutive address mapping codes. The address mapping code is used to correspond to a block in the memory chip. Then, based on the target address mapping code, the physical address of the normal block corresponding to the address to be mapped in the memory chip can be obtained. Different normal blocks included in the memory chip correspond to different address mapping codes. The memory chip includes at least one abnormal block, and the address mapping code corresponding to the abnormal block is mapped to the normal block included in the memory chip. In this embodiment, on the one hand, by constructing a correspondence between blocks and address mapping codes in the memory chip, the address to be mapped can be accurately mapped to the physical address of a specified normal block using the address mapping code, thus achieving physical address mapping within the specified block. On the other hand, by mapping the address mapping codes corresponding to abnormal blocks containing bad blocks in the memory chip to normal blocks in the memory chip, bad blocks can be excluded from address mapping in software, while other normal blocks in the memory chip are utilized effectively without redesigning the hardware, thus reducing chip design costs. Furthermore, this embodiment can accurately and flexibly map the address to be mapped to a specified normal block for abnormal blocks in different memory chips, exhibiting high flexibility and universality. Therefore, this embodiment can effectively improve utilization efficiency when reusing chips containing bad blocks.

[0057] In one embodiment, in step S102, obtaining the physical address of the address to be mapped in the normal block corresponding to the storage chip based on the target address mapping code may include the following steps:

[0058] Based on the target address mapping code and mapping relationship configuration information, the physical address of the normal block corresponding to the address to be mapped in the memory chip is obtained; the mapping relationship configuration information includes the mapping relationship between the address identifier of the normal block and the address mapping code; the mapping relationship configuration information before the memory chip generates abnormal blocks is different from the mapping relationship configuration information after the memory chip generates abnormal blocks.

[0059] In practical applications, memory chips can be divided into multiple contiguous groups of memory cells, each group being called a block. Each block can include multiple memory cells. Blocks can be categorized into normal blocks and abnormal blocks. Normal blocks include blocks capable of performing normal data read and write operations; abnormal blocks refer to blocks containing bad blocks where the number of bad blocks meets a certain threshold.

[0060] The address identifier of a normal block can be an identifier used to uniquely identify each normal block in the memory chip. For example, the address identifier can be a block number or the starting physical address of the normal block in the memory chip. For example, the lowest access address space of the corresponding block can be determined based on the starting physical address.

[0061] The mapping configuration information can be configurable and used to set the mapping relationship between the address identifiers and address mapping codes of the blocks. In some embodiments, the mapping configuration information can be stored in the controller of the memory chip or the associated memory cell in the form of a table, array, or database. For example, if the mapping configuration information is recorded in a table, it can be as shown in Table 1 below.

[0062] Table 1

[0063]

[0064] In this embodiment, the target address mapping code in the address to be mapped can be obtained, and the mapping relationship configuration information contained in the memory chip can be read. This mapping relationship configuration information can differ before and after the memory chip generates abnormal blocks. In some embodiments, the adjustment of the mapping relationship configuration information can be performed during the memory chip's power-on initialization, or dynamically after abnormal blocks are detected in real time during the memory chip's operation. The specific timing of the adjustment can be set according to the actual application scenario.

[0065] Specifically, when no abnormal blocks are generated in the memory chip, the mapping relationship configuration information can include the mapping relationship between the address identifiers and address mapping codes of all blocks. At this time, each block in the memory chip can be considered a normal block, thus obtaining the mapping relationship between the address identifiers and address mapping codes of each block. When the memory chip contains abnormal blocks, the mapping relationship between the address identifiers and address mapping codes originally recorded in the mapping relationship configuration information can be adjusted so that the address mapping codes originally corresponding to the address identifiers of abnormal blocks are changed to correspond to the address identifiers of normal blocks. In other words, when the memory chip contains abnormal blocks, the address identifiers of abnormal blocks can be removed from the mapping relationship configuration information, and the mapping relationship between the address identifiers and address mapping codes of the remaining normal blocks can be reconfigured to ensure that multiple consecutive address mapping codes can correspond to each normal block.

[0066] Furthermore, based on the target address mapping code and the mapping relationship recorded in the mapping relationship configuration information, the physical address of the address to be mapped in the corresponding normal block of the memory chip can be determined. In specific implementation, the address identifier of each normal block can correspond to a unique physical address range. In this embodiment, the address identifier of the normal block where the address to be mapped is located can be determined based on the target address mapping code and the mapping relationship configuration information, and then the physical address of the address to be mapped in that normal block can be determined based on the physical address range corresponding to that address identifier.

[0067] In this embodiment, the physical address of a normal block is determined based on the target address mapping code and mapping relationship configuration information. The mapping relationship configuration information is adjusted according to the occurrence of abnormal blocks, which ensures that each address to be mapped can always be correctly mapped to the physical address of a normal block in the memory chip. This avoids data read / write errors caused by abnormal blocks and improves the data storage reliability of the memory chip. At the same time, by flexibly adjusting the mapping relationship configuration information, abnormal blocks can be avoided without modifying the hardware structure of the memory chip, thus reducing the maintenance cost of the memory chip.

[0068] In one embodiment, obtaining the physical address of the address to be mapped in the corresponding normal block of the memory chip based on the target address mapping code and mapping relationship configuration information may include the following steps:

[0069] Based on the chip select flag, block flag, and mapping relationship configuration information of the target address mapping code, the target address identifier corresponding to the target normal block selected by the target memory chip is obtained; the target memory chip select includes at least one of multiple memory chip selects in the memory chip, and the target normal block includes at least one of multiple normal blocks selected by the target memory chip; according to the target address identifier, the physical address of the address to be mapped in the target normal block is determined.

[0070] The memory chip may include multiple memory chip selects. Each memory chip integrates a memory cell array for storing data. A memory chip select can be understood as a memory module within the memory chip, with each memory chip select containing a corresponding memory cell array. A target memory chip select is determined from the multiple memory chip selects and is used to store the data corresponding to the address to be mapped. There may be one or more target memory chip selects. A target normal block is determined from the multiple normal blocks of the target memory chip select and is specifically used to store the data corresponding to the address to be mapped. There may be one or more target normal blocks.

[0071] In practical applications, the target address mapping code may include a chip select flag indicating the target memory chip select and a block flag indicating the target normal block. In this step, the chip select flag and block flag can be extracted from the target address mapping code, and combined with the mapping relationship configuration information, the target memory chip select corresponding to the value on the chip select flag and the target normal block corresponding to the value on the block flag in the target memory chip select can be determined. Thus, the target address identifier can be obtained based on the address identifier code corresponding to the target normal block.

[0072] Then, the physical address of the address to be mapped within the target normal block can be determined based on the target address identifier. In some embodiments, the physical start address of the target normal block can be determined based on the target address identifier, and then the address offset relative to the physical start address can be determined based on the block offset bits in the address to be mapped. For example, the address offset can be determined based on the value of the last M bits (M is a positive integer) of the address to be mapped. After obtaining the address offset within the block, the physical address corresponding to the address to be mapped can be determined based on the address offset and the physical start address of the target normal block. For example, if the physical start address of the target normal block is 0x200000 and the address offset is 0x100, then the physical address corresponding to the address to be mapped is 0x200000 + 0x100 = 0x200100.

[0073] In some embodiments, after obtaining the address to be mapped, it can be pre-converted to a target format (such as binary format). Then, the address offset contained in the address to be mapped is determined according to the address to be mapped in the target format and the address mapping relationship. The address mapping relationship can indicate the memory chip select, row address, bank address, column address, channel, and data queue (DQ) corresponding to multiple bits in the target format, thereby identifying the address offset. For example, when the memory chip includes 15 rows, the address mapping relationship can indicate that bits 30 to 15 of the address to be mapped in the target format correspond to these 15 rows respectively. In some optional embodiments, the address mapping relationship can include an RBC (Row-Bank-Column) mapping relationship.

[0074] In this embodiment, by combining the chip select flag and block flag in the target address mapping code with the mapping relationship configuration information, the target memory chip select and target normal block in the memory can be accurately identified, effectively avoiding the impact of abnormal blocks on address mapping and improving the reliability of the memory chip during chip reuse. At the same time, by using the target address flag, it is ensured that the address to be mapped can be accurately mapped to the physical location of the target normal block, realizing efficient address management in scenarios with multiple memory chip selects and multiple blocks, which helps to reduce the risk of address conflicts and improve the read and write efficiency of the memory chip.

[0075] In one embodiment, at least one address mapping code to be processed in the mapping relationship configuration information is determined based on the address mapping code corresponding to the first abnormal block, and at least one address mapping code to be processed is sequentially corresponding to the address identifier of at least one normal block following the first abnormal block.

[0076] Specifically, the mapping configuration information may include multiple address mapping codes arranged sequentially according to address order. When the memory chip includes a faulty chip, the mapping configuration information includes at least one address mapping code to be processed. This at least one address mapping code to be processed is determined based on the address mapping code corresponding to the first faulty block, which can be the address mapping code in the mapping configuration information that corresponds to the faulty block and is listed first in the order.

[0077] In one exemplary embodiment, the address mapping code to be processed may be the address mapping code corresponding to the first abnormal block itself. In another exemplary embodiment, the address mapping code to be processed may include the address mapping code corresponding to the first abnormal block and one or more subsequent address mapping codes. The number of address mapping codes to be processed can be determined based on the difference between the total number of address mapping codes from the first abnormal block to the last address mapping code in the mapping relationship configuration information and the number of abnormal blocks. For example, there are a total of Q (Q is a positive integer) address mapping codes from the first abnormal block to the last address mapping code in the mapping relationship configuration information. These Q mapping codes contain X (X is a positive integer) abnormal blocks. Since the relationship between the address identifiers of the X abnormal blocks and their address mapping codes can be eliminated when constructing the mapping relationship, the number of address mapping codes to be processed can be determined based on the difference between Q and X. Based on this number and the address mapping code corresponding to the first abnormal block, at least one address mapping code to be processed can be determined.

[0078] After determining at least one address mapping code to be processed, the at least one address mapping code to be processed can be sequentially mapped to the address identifiers of at least one normal block following the first abnormal block. Specifically, in this embodiment, after determining the address mapping code to be processed, each address mapping code to be processed can be sequentially mapped to the address identifiers of at least one normal block following the first abnormal block. Sequential mapping can be understood as matching the order of the address mapping codes to be processed with the order of the address identifiers of the normal blocks (e.g., they are consistent). That is, the first address mapping code to be processed corresponds to the address identifier of the first normal block following the first abnormal block, the second address mapping code to be processed corresponds to the address identifier of the second normal block following the first abnormal block, and so on.

[0079] For example, if the address mapping code to be processed is M3, and the normal blocks after the first abnormal block A3 include A4 and A5, then the address identifiers of M3 and A4 can be mapped sequentially; or if the address mapping code to be processed includes M3, M4, and M5, and the normal blocks after the first abnormal block A3 include A4, A5, and A6, then M3 can be mapped to A4, M4 to A5, and M5 to A6 in sequence to achieve sequential mapping.

[0080] In this embodiment, by determining the address mapping code to be processed based on the address mapping code of the first abnormal block and sequentially mapping it to the address identifiers of subsequent normal blocks, a valid address mapping relationship can be accurately and smoothly re-established when the memory chip includes abnormal blocks. This enables rapid and accurate adjustment of the mapping relationship configuration information, ensuring accurate access and processing of subsequent normal blocks, avoiding the impact of abnormal blocks on data reading of subsequent normal blocks, and improving the reliability and continuity of data processing.

[0081] In one embodiment, at least one normal block following the first abnormal block may include a normal block in the same memory chip select as the first abnormal block in the memory chip, or a normal block in a different memory chip select than the first abnormal block in the memory chip. For example, when the address mapping code to be processed includes the address mapping code corresponding to the last block of memory chip select A of the memory chip, the address identifier corresponding to the first normal block in the next memory chip select of memory chip select A, i.e., memory chip select B, can be mapped to the address mapping code according to the address order.

[0082] In this embodiment, when mapping the address code to be processed to a normal block, the corresponding subsequent normal block can be located in the same memory chip select or in different memory chip selects. This can more comprehensively cover the possible normal data distribution in the storage system and help improve the utilization rate of normal blocks in each memory chip select. For example, if there are no subsequent normal blocks in the memory chip select where the first abnormal block is located, mapping to normal blocks in other subsequent memory chip selects can improve the mapping continuity of the address to be mapped in each memory chip select in the same memory.

[0083] In one embodiment, the address mapping code corresponding to the abnormal block can be directly mapped to the address identifier of the last normal block of the memory chip in the mapping relationship configuration information. Specifically, when the number of abnormal blocks meets the quantity condition and the address mapping code originally corresponding to the abnormal block meets the position condition, the address mapping code corresponding to the abnormal block can be mapped to the address identifier of the last normal block.

[0084] For example, if there is an abnormal block in a memory chip, and all other blocks are normal blocks, and the address mapping code corresponding to the abnormal block is located in the middle of multiple address mapping codes, the address identifier corresponding to the last normal block of the memory chip can be determined according to the mapping relationship configuration information, and the address mapping code of the abnormal block can be mapped to the address identifier corresponding to the last normal block.

[0085] In this embodiment, by starting from the address identifier of the last normal block and mapping it to the address mapping code of the abnormal block, the mapping relationship between the address identifier code and the normal block in the memory chip can be re-established, improving the continuity of the address to be mapped. At the same time, this embodiment can effectively reduce the mapping relationship extension caused by rebuilding the mapping relationship, reduce the number of times the original normal block address identifier is re-mapped to the new address mapping code, and improve the configuration efficiency of the mapping relationship configuration information.

[0086] In one embodiment, after step S101, the method may further include the following steps:

[0087] The target address mapping code on the address mapping bits of the address to be mapped is determined based on the values ​​of multiple target bits in the address to be mapped; the number of target bits is related to the number of blocks in the memory chip.

[0088] The target bit can refer to a specific bit selected from all bits of the address to be mapped, used to determine the address mapping code. The position of the target bit can be continuous or discrete.

[0089] In a specific implementation, the number of blocks in the memory chip can be determined, thereby determining the number of target bits used to represent that number of blocks. In some embodiments, the number N of blocks contained in the memory chip select in the memory chip can be determined. After determining the number of blocks N, the number of target bits used to represent N different blocks can be determined, where N is a positive integer.

[0090] In some embodiments, the number of target bits can be determined based on the number of blocks and the number system of the symbols, such as binary, decimal, hexadecimal, etc. Specifically, for example, when divided into 2^k blocks (k is a positive integer) and using binary, k bits can represent 2^k different combinations, which can cover the identification requirements of 2^k blocks. For example, if the number of blocks is 8, i.e., N=8=2^3, then the number of target bits can be 3, which can be distinguished by 8 identifiers: 000, 001, 010, 011, 100, 101, 110, and 111.

[0091] Furthermore, after obtaining the address to be mapped, the target address mapping code can be determined based on the values ​​of multiple target bits in the address to be mapped.

[0092] In some optional embodiments, a specific number of bits starting from the most significant bit in the address to be mapped can be selected as the target bits, or a number of bits starting from the least significant bit in the address to be mapped can be selected as the target bits, or a number of non-contiguous bits in the address to be mapped can be selected as the target bits. For example, as shown in Table 2 below, after determining the number of target bits, multiple target bit selection modes can be provided to set which bits in the address to be mapped participate in the mapping, including mode 0, mode 1, and mode 2. Taking mode 0 and mode 1 as examples, the target bits in mode 0 are bits 31 to 28 of the address to be mapped, and the target bits in mode 1 are bits 32 to 29 of the address to be mapped.

[0093] Table 2

[0094]

[0095] After determining multiple target bits, the values ​​of the target bits can be read and processed to obtain the target address mapping code. Processing methods can include directly combining the values ​​of the target bits in sequence, or calculating the values ​​of the target bits using preset logical operations (such as XOR, AND, OR, etc.). For example, when the target bits are the 3rd bit (value 1) and the 5th bit (value 0), if a direct combination method is used, the target address mapping code is 10; if an XOR operation is used, the result of XORing 1 and 0 is 1, so the target address mapping code is "1" (binary). In this case, leading zeros can be added to make the number of bits consistent with the number of target bits, i.e., "01".

[0096] In this embodiment, by determining the number of target bits in the address to be mapped based on the number of blocks in the memory chip, the value of the corresponding bit can be extracted from the address to be mapped to determine the target address mapping code pointing to a specific block. This reduces addressing redundancy while fully distinguishing each block, and improves the address translation efficiency during data reading and writing. Especially in multi-block parallel storage or complex storage architecture, it can optimize the accuracy and speed of data location.

[0097] To enable those skilled in the art to better understand the above steps, the present application is illustrated by an embodiment below, but it should be understood that the present application is not limited thereto.

[0098] like Figure 4 As shown, this embodiment may include the following steps:

[0099] Step S401: Determine the address to be mapped.

[0100] Step S402: Determine the target address mapping code on the address mapping bit of the address to be mapped based on the values ​​of multiple target bits in the address to be mapped; the target address mapping code includes at least one of multiple consecutive address mapping codes; the address mapping code is used to correspond to the block in the memory chip.

[0101] Step S403: Based on the chip select flag, block flag, and mapping relationship configuration information of the target address mapping code, obtain the target address identifier corresponding to the target normal block selected in the target storage chip.

[0102] The mapping configuration information of the memory chip before abnormal block partitioning is different from that after abnormal block partitioning is generated.

[0103] In one embodiment, at least one address mapping code to be processed in the mapping relationship configuration information is determined based on the address mapping code corresponding to the first abnormal block. At least one address mapping code to be processed is sequentially corresponding to the address identifiers of at least one normal block following the first abnormal block. The at least one normal block following the first abnormal block may be in the same memory chip select as the first abnormal block or in a different memory chip select.

[0104] In another embodiment, the address mapping code corresponding to the abnormal block can be mapped to the address identifier of the last normal block of the memory chip in the mapping relationship configuration information.

[0105] In one embodiment, the memory chip includes one or more memory chip selects. Each memory chip select can be divided into blocks by rows. Taking a 4Gb memory chip select as an example, the memory chip select can include multiple memory banks. Each memory bank is a two-dimensional memory cell array composed of n rows and m columns. The memory banks, rows, and columns together form the three-dimensional memory space corresponding to the memory chip select. When dividing into blocks, it can be divided by rows, with each block consisting of 8191 rows, resulting in a total of 8 blocks. The block identifier can be the 3 target bits in the address to be mapped, used to indicate the row address. For example, the highest 3 bits among the multiple bits used to indicate the row address. Correspondingly, the format of the target address mapping code can be [cs,r,r,r], where cs is the chip select identifier and the three r are the block identifier bits.

[0106] In one embodiment, when mapping the address code corresponding to an abnormal block to the address identifier of a normal block, the rows contained in the abnormal block can be regarded as non-existent and skipped during address mapping. For example, if one or more rows from row0 to row8191 of memory bank 1 are corrupted, the blocks corresponding to row0 to row8191 will be identified as abnormal blocks, and row0-row8191 of multiple memory banks can be skipped during address mapping.

[0107] Step S404: Determine the physical address of the address to be mapped in the target normal block based on the target address identifier.

[0108] It should be emphasized that the address mapping method provided in one or more embodiments of this application can also be executed by one or more of the following devices: a chip, a chip module, or an address mapping device, wherein the address mapping device may be, for example, a chip or a chip module. Regarding the various module units included in the devices and products described in the above embodiments, they may be software module units, hardware module units, or a combination of both. For example, for devices and products applied to or integrated into a chip, all included module units may be implemented using hardware methods such as circuits, or at least some module units may be implemented using software programs running on a processor integrated within the chip, while the remaining (if any) module units may be implemented using hardware methods such as circuits; for devices and products applied to or integrated into a chip module, all included module units may be implemented using hardware methods such as circuits, and different module units may be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some module units may be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) component units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each component can be implemented using hardware methods such as circuits. Different component units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some component units can be implemented using software programs that run on the processor integrated within the terminal. The remaining (if any) component units can be implemented using hardware methods such as circuits.

[0109] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0110] Based on the same inventive concept, this application also provides an address mapping apparatus for implementing the address mapping method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more address mapping apparatus embodiments provided below can be found in the limitations of the address mapping method described above, and will not be repeated here.

[0111] In one exemplary embodiment, an address mapping device is provided. This device may be a virtual device, such as a chip, and the various modules in the virtual device may be software and / or hardware.

[0112] In one exemplary embodiment, such as Figure 5 As shown, the address mapping device may include:

[0113] Address acquisition module 501 is used to determine the address to be mapped; the address to be mapped has a target address mapping code on the address mapping bits; the target address mapping code includes at least one of a plurality of consecutive address mapping codes; the address mapping code is used to correspond to a block in the memory chip;

[0114] Address mapping module 502 is used to obtain the physical address of the address to be mapped in the normal block corresponding to the memory chip based on the target address mapping code; different normal blocks included in the memory chip correspond to different address mapping codes; the memory chip includes at least one abnormal block, and the address mapping code corresponding to the abnormal block is mapped to the normal block included in the memory chip.

[0115] In one embodiment, the address mapping module 502 is used for:

[0116] Based on the target address mapping code and mapping relationship configuration information, the physical address of the address to be mapped in the normal block corresponding to the memory chip is obtained; the mapping relationship configuration information includes the mapping relationship between the address identifier and the address mapping code of the normal block; the mapping relationship configuration information before the memory chip generates the abnormal block is different from the mapping relationship configuration information after the memory chip generates the abnormal block.

[0117] In one embodiment, the address mapping module 502 is used for:

[0118] Based on the chip select flag, block flag, and mapping relationship configuration information of the target address mapping code, a target address identifier corresponding to the target normal block selected in the target memory chip is obtained; the target memory chip select includes at least one of a plurality of memory chip selects in the memory chip, and the target normal block includes at least one of the plurality of normal blocks selected in the target memory chip.

[0119] Based on the target address identifier, determine the physical address of the address to be mapped in the target normal block.

[0120] In one embodiment, at least one address mapping code to be processed in the mapping relationship configuration information is determined based on the address mapping code corresponding to the first abnormal block, and the at least one address mapping code to be processed is sequentially corresponding to the address identifiers of at least one normal block following the first abnormal block.

[0121] In one embodiment, at least one normal block following the first abnormal block includes:

[0122] The normal block of the same memory chip select as the first abnormal block of the memory chip, and / or the normal block of a different memory chip select of the memory chip as the first abnormal block of the memory chip.

[0123] In one embodiment, the address mapping code corresponding to the abnormal block is mapped to the address identifier of the last normal block of the memory chip in the mapping relationship configuration information.

[0124] In one embodiment, the address acquisition module 501 is further configured to:

[0125] Based on the values ​​of multiple target bits in the address to be mapped, the target address mapping code on the address mapping bits of the address to be mapped is determined; the number of target bits is related to the number of blocks in the memory chip.

[0126] Each module in the aforementioned address mapping device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0127] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory may include non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores mapping configuration information. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements an address mapping method.

[0128] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements an address mapping method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0129] Those skilled in the art will understand that Figure 6 and Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0130] In one embodiment, a terminal is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0131] In one embodiment, a base station is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps in the above method embodiments.

[0132] In one embodiment, a server is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0133] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0134] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0135] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0136] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0138] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An address mapping method, characterized in that, The method includes: The address to be mapped is determined; the address mapping bits of the address to be mapped have a target address mapping code; the target address mapping code includes at least one of a plurality of consecutive address mapping codes; the address mapping code is used to correspond to a block in the memory chip; Based on the target address mapping code, the physical address of the address to be mapped in the normal block corresponding to the memory chip is obtained; different normal blocks included in the memory chip correspond to different address mapping codes; the memory chip includes at least one abnormal block, and the address mapping code corresponding to the abnormal block is mapped to the normal block included in the memory chip.

2. The method according to claim 1, characterized in that, The step of obtaining the physical address of the address to be mapped in the normal block corresponding to the memory chip based on the target address mapping code includes: Based on the target address mapping code and mapping relationship configuration information, the physical address of the address to be mapped in the normal block corresponding to the memory chip is obtained; the mapping relationship configuration information includes the mapping relationship between the address identifier and the address mapping code of the normal block; the mapping relationship configuration information before the memory chip generates the abnormal block is different from the mapping relationship configuration information after the memory chip generates the abnormal block.

3. The method according to claim 2, characterized in that, The step of obtaining the physical address of the address to be mapped in the normal block corresponding to the memory chip based on the target address mapping code and mapping relationship configuration information includes: Based on the chip select flag, block flag, and mapping relationship configuration information of the target address mapping code, a target address identifier corresponding to the target normal block selected in the target memory chip is obtained; the target memory chip select includes at least one of a plurality of memory chip selects in the memory chip, and the target normal block includes at least one of the plurality of normal blocks selected in the target memory chip. Based on the target address identifier, determine the physical address of the address to be mapped in the target normal block.

4. The method according to claim 2, characterized in that, At least one address mapping code to be processed in the mapping relationship configuration information is determined according to the address mapping code corresponding to the first abnormal block, and the at least one address mapping code to be processed is sequentially corresponding to the address identifier of at least one normal block following the first abnormal block.

5. The method according to claim 4, characterized in that, At least one normal block following the first abnormal block includes: The normal block of the same memory chip select as the first abnormal block of the memory chip, and / or the normal block of a different memory chip select of the memory chip as the first abnormal block of the memory chip.

6. The method according to claim 2, characterized in that, The address mapping code corresponding to the abnormal block is mapped to the address identifier of the last normal block of the memory chip in the mapping relationship configuration information.

7. The method according to any one of claims 1 to 6, characterized in that, After determining the address to be mapped, the process also includes: Based on the values ​​of multiple target bits in the address to be mapped, the target address mapping code on the address mapping bits of the address to be mapped is determined; the number of target bits is related to the number of blocks in the memory chip.

8. An address mapping device, characterized in that, The device includes: The address acquisition module is used to determine the address to be mapped; the address to be mapped has a target address mapping code on the address mapping bits; the target address mapping code includes at least one of a plurality of consecutive address mapping codes; the address mapping code is used to correspond to a block in the memory chip; The address mapping module is used to obtain the physical address of the address to be mapped in the normal block of the memory chip based on the target address mapping code; different normal blocks included in the memory chip correspond to different address mapping codes; the memory chip includes at least one abnormal block, and the address mapping code corresponding to the abnormal block is mapped to the normal block included in the memory chip.

9. A terminal comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A base station, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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