A method and apparatus for protecting instruction stream and parameters.

Abstract

This invention discloses a method and apparatus for protecting instruction streams and parameters, belonging to the field of computer technology. The method includes: a reconfigurable cryptographic coprocessor in a chip initiates a DMA module via a control module to read secure data from a FLASH memory; a verification module verifies the secure data; a decryption module decrypts the secure data to obtain plaintext data; the plaintext data is stored in a data storage module via a data configuration and clearing module; and the reconfigurable processor in the reconfigurable cryptographic coprocessor obtains instruction streams and parameters as needed and participates in the execution of the cryptographic algorithm. This solution ensures the security and integrity of the instruction streams and parameters obtained by the reconfigurable processor, thereby guaranteeing the security of the algorithm implemented by the reconfigurable cryptographic coprocessor.

Description

Technical Field

[0001] This invention relates to a method and apparatus for protecting instruction streams and parameters, belonging to the field of computer technology. Background Technology

[0002] There are many types of symmetric algorithms currently available, and different application scenarios require different grouping algorithms. Some applications even modify and update existing grouping algorithms. Traditional symmetric algorithm implementations are insufficient to meet the current demands for algorithm flexibility. Therefore, reconfigurable cryptographic coprocessors are often used to implement applications requiring various algorithms. When implementing different algorithm requirements, the reconfigurable coprocessor executes specific operations. This execution requires the participation of instruction streams and configuration parameters of internal algorithm units. In current technology, these instruction streams and configuration parameters are stored in plaintext on the chip. If these parameters are stolen or tampered with, it will pose a significant threat to the security of the reconfigurable cryptographic coprocessor implementing different algorithms. Therefore, protecting these crucial data—the instruction streams and configuration parameters—is a pressing issue that needs to be addressed. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a method and apparatus for protecting instruction streams and parameters.

[0004] According to a first aspect of the present invention, a method for protecting instruction streams and parameters is provided, the method comprising the following steps:

[0005] Step S1: After the chip is powered on, the reconfigurable cryptographic coprocessor in the chip starts the DMA module through the control module to read the control field in the security data from the FLASH memory, writes the key in the control field into the decryption module, writes the check code in the control field into the verification module, and writes the length of the instructions and parameters in the control field into the control module.

[0006] Step S2: The reconfigurable cryptographic coprocessor reads the data field from the security data in the FLASH memory through the DMA module and stores the data field in the FIFO module;

[0007] Step S3: The reconfigurable cryptographic coprocessor obtains the data field from the FIFO module through the decryption module, decrypts the data field using the key to obtain plaintext data, and outputs the plaintext data to the data configuration and clearing module. The data configuration and clearing module stores the plaintext data in the data storage module according to the length of the instructions and parameters in the control module.

[0008] Step S4: The reconfigurable cryptographic coprocessor obtains the data field from the FIFO module through the verification module, performs calculations on the data field to obtain the processing result, and compares the processing result with the verification code. If the comparison matches, proceed to step S5; otherwise, proceed to step S6.

[0009] Step S5: The reconfigurable cryptographic coprocessor sends a verification success notification to the control module through the verification module;

[0010] Step S6: The reconfigurable cryptographic coprocessor sends a verification failure notification to the control module through the verification module and outputs a second signal to the data configuration and clearing module. The data configuration and clearing module clears the plaintext data in the data storage module according to the length of the instructions and parameters input by the control module.

[0011] According to a second aspect of the present invention, a protection device for instruction streams and parameters is provided, the device being applied to a chip including a reconfigurable cryptographic coprocessor, the device comprising: a control module, a DMA module, a FIFO module, a decryption module, a verification module, a data configuration and clearing module, and a data storage module;

[0012] The control module is connected to the DMA module, the verification module, and the data configuration and clearing module. It is used to start the DMA module, receive the instructions and parameter lengths sent by the DMA module, and receive verification success or verification failure notifications output by the verification module. It also outputs the lengths of the instructions and parameters to the data configuration and clearing module.

[0013] The DMA module is connected to the control module, the decryption module, the verification module, and the FIFO module. It is used to obtain secure data from the FLASH memory of the chip, transmit the key in the secure data to the decryption module, transmit the checksum in the secure data to the verification module, transmit the length of the instructions and parameters in the secure data to the control module, transmit the data fields in the secure data to the FIFO module for storage, and also to notify the control module after the data transmission is completed.

[0014] The decryption module is connected to the DMA module, the FIFO module, and the data configuration and clearing module. It is used to read data fields from the FIFO module, decrypt the data fields using the key passed from the DMA module, output a decryption completion signal to the data configuration and clearing module, and output the decrypted plaintext data to the data configuration and clearing module.

[0015] The verification module is connected to the DMA module, the FIFO module, the control module, and the data configuration and clearing module. It is used to read data fields from the FIFO module, perform calculations on the data fields to obtain processing results, verify the processing results according to the verification code passed from the DMA module, send a verification success notification to the control module when the verification is successful, send a verification failure notification to the control module when the verification fails, output a second signal to the data configuration and clearing module, and output a first signal to the data configuration and clearing module.

[0016] The data configuration and clearing module is connected to the decryption module, the verification module, the control module, and the data storage module. It is used to receive plaintext data output by the decryption module, receive the instruction length output by the control module, receive the first signal output by the verification module, write plaintext data into the data storage module, and also to receive the second signal output by the verification module and clear the plaintext data in the data storage module according to the second signal.

[0017] The data storage module and the data configuration and clearing module are used to store plaintext data.

[0018] According to a third aspect of the present invention, a reconfigurable cryptographic coprocessor is provided, the reconfigurable cryptographic coprocessor including the means described above, the reconfigurable cryptographic coprocessor implementing different cryptographic algorithms through the means.

[0019] According to a fourth aspect of the present invention, a chip is provided, the chip comprising the aforementioned reconfigurable cryptographic coprocessor, the chip implementing algorithmic applications through the reconfigurable cryptographic coprocessor.

[0020] The beneficial effects of the technical solution provided by this invention include at least the following:

[0021] This invention provides a method and apparatus for protecting instruction streams and parameters. When a reconfigurable cryptographic coprocessor implements a cryptographic algorithm, it performs secure loading processing on the ciphertext data of the instruction stream and parameters, which are encrypted by the host computer and written to the FLASH memory. The data after secure loading is stored in a designated data storage module, and the reconfigurable processor within the reconfigurable cryptographic coprocessor retrieves it as needed and participates in the execution process of the cryptographic algorithm implementation. This ensures the security and integrity of the instruction stream and parameters obtained by the reconfigurable processor, thereby guaranteeing the security of various algorithms implemented by the reconfigurable cryptographic coprocessor. Attached Figure Description

[0022] To illustrate more clearly, the embodiments of the present invention or the prior art will be briefly described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic flowchart of the data encryption process in a method for protecting instruction streams and parameters provided in Embodiment 1 of the present invention.

[0024] Figure 2 This is a flowchart illustrating the data security loading process in a method for protecting instruction streams and parameters provided in Embodiment 1 of the present invention.

[0025] Figure 3 This is a schematic diagram of a protection device for instruction streams and parameters provided in Embodiment 2 of the present invention;

[0026] Figure 4 This is a schematic diagram of the data configuration and clearing module in a protection device for instruction streams and parameters provided in Embodiment 2 of the present invention;

[0027] Figure 5 This is a circuit diagram of the data configuration and clearing module in a protection device for instruction streams and parameters provided in Embodiment 2 of the present invention;

[0028] Figure 6 This is a schematic diagram of the structure of a protection device for instruction stream and parameters provided in Embodiment 2 of the present invention, applied to a chip including a reconfigurable cryptographic coprocessor. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0030] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of devices and methods consistent with some aspects of the invention as detailed in the appended claims.

[0031] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Example 1

[0032] Before describing the method for protecting instruction streams and parameters provided in this application, we will first explain the relevant background information of the embodiments of this application.

[0033] In existing technologies, reconfigurable cryptographic coprocessors are typically used to implement applications with different algorithm requirements. The reconfigurable cryptographic coprocessor works in conjunction with the CPU module in the chip to complete the specific implementation. After receiving the execution instructions from the CPU, the reconfigurable cryptographic coprocessor processes a specific operation in the algorithm implementation. During processing, the reconfigurable processor needs to obtain the instruction stream and the configuration parameters of the internal algorithm unit to participate in the specific execution process. Currently, the instruction stream and the configuration parameters of the internal algorithm unit are stored in plaintext in the reconfigurable cryptographic coprocessor or chip. If the instruction stream and the configuration parameters of the internal algorithm unit are stolen or tampered with, it will pose a huge threat to the security of the reconfigurable cryptographic coprocessor in implementing different algorithms.

[0034] Based on this, embodiments of this application provide a method for protecting instruction streams and parameters. The method for protecting instruction streams and parameters provided by this application ensures the security and integrity of the instruction streams and parameters obtained by the reconfigurable processor.

[0035] The method for protecting instruction streams and parameters provided in this application will be described in detail below.

[0036] This invention provides a method for protecting instruction streams and parameters. The method is applicable to a system including a host computer and a chip. The chip specifically includes a CPU module, a reconfigurable cryptographic coprocessor, a download interface, and a FLASH memory. The method specifically includes: an encryption process for the instruction stream and parameters by the host computer and a process for the chip to securely load the instruction stream and parameters.

[0037] On the one hand, such as Figure 1 As shown, the encryption process of the host computer for the instruction stream and parameters includes:

[0038] Step 101: The host computer generates a set of symmetric keys;

[0039] In this embodiment, the host computer specifically generates the symmetric key using a random number generator;

[0040] Specifically, the generated key length is preferably 128 bits;

[0041] For example, the key is 0x33A8DD1F 0x31C70788 0x591012B1 0x5FEC8027.

[0042] Step 102: The host computer obtains the instruction stream and parameters as the data to be protected, and encrypts the data to be protected using a symmetric key to obtain the first ciphertext;

[0043] In this embodiment, the host computer specifically uses the symmetric key generated in step 101 to encrypt the data to be protected through an encryption program, and the encryption algorithm is SM4.

[0044] In this embodiment, the instruction stream is specifically hexadecimal machine code written by the user according to the syntax of the instruction set and compiled by the compiler, and stored in a specified storage location in the host computer;

[0045] For example, an 8-in-8-out lookup table instruction is: FLUT DR1,C0R1,C0R4,SEL8L, which, after being compiled by the compiler, yields a 32-bit instruction data 0x1437E060;

[0046] Specifically, a collection of several instruction data sets together constitutes a complete instruction stream. The reconfigurable processor in the reconfigurable cryptographic coprocessor needs to parse these instruction streams to complete the corresponding functional operations. Parameters are also data similar to instruction streams, and the instruction stream needs to complete the operation with the cooperation of parameters.

[0047] For example, for an 8-in-8-out lookup table, the 256 bytes of data pre-written in the lookup table are the parameters that need to be configured, which correspond to 256 bytes of parameters.

[0048] In this embodiment, the host computer obtains the instruction stream and parameters by reading the instruction stream and parameters from a file stored in a specified storage location through a program.

[0049] Step 103: The host computer calculates the checksum of the first ciphertext using a preset algorithm;

[0050] In this embodiment, the host computer calculates the first ciphertext using a preset algorithm through a predetermined program to obtain the check code of the first ciphertext;

[0051] Specifically, the preset algorithm is the national cryptographic SM3 algorithm. Step 103 is as follows: the host computer iterates continuously in groups of 64 bytes to obtain a 256-bit hash value, and uses the hash value as the check code.

[0052] For example, the checksum is: 0x4D3BE0A0 0xB0F52AAE 0x3CBBEBC8 0x61995383 0x7E042B17 0x26D677BA 0x631469E1 0x7D0C2155.

[0053] Step 104: The host computer uses the key, verification code, and length of the data to be protected as the control field, and the first ciphertext as the data field. The control field and the data field are organized into secure data, and the secure data is stored in the chip's FLASH memory through the chip's download interface.

[0054] In this embodiment, the download interface is specifically an external interface of the chip, such as SWD, USB, SPI, etc. The host computer downloads secure data to the chip's FLASH memory through the chip's external interface.

[0055] Specifically, the control fields are as follows: a 4-word key, an 8-word checksum, a 1-word instruction stream length, and a 1-word parameter length;

[0056] For example, the key is 0x33A8DD1F, 0x31C70788, 0x591012B1, 0x5FEC8027, the checksum is 0x4D3BE0A0, 0xB0F52AAE0x3CBBEBC8, 0x61995383, 0x7E042B17, 0x26D677BA, 0x631469E1, 0x7D0C2155, the instruction stream length is 0x1000, representing 4KB of instruction data, and the parameter length is 0x400, representing 1KB of parameter data;

[0057] In this embodiment, the chip needs to be powered on when step 104 is executed.

[0058] In this embodiment, the host computer generates and uses a symmetric key to encrypt the instruction stream and parameters. It is easy to imagine that the host computer can also generate an asymmetric key and use the asymmetric key to encrypt and decrypt the instruction stream and parameters, using corresponding algorithms for encryption and decryption.

[0059] On the other hand, such as Figure 2 As shown, the process of securely loading the instruction stream and parameters into a chip includes:

[0060] Step 201: Power on the chip;

[0061] Step 202: The reconfigurable cryptographic coprocessor in the chip starts the DMA module through the control module to read the control field from the security data in the FLASH memory, writes the key in the control field into the decryption module, writes the check code in the control field into the verification module, and writes the length of the instructions and parameters in the control field into the control module.

[0062] Step 203: The reconfigurable cryptographic coprocessor reads the data field from the security data from the FLASH memory through the DMA module and stores the data field into the FIFO module;

[0063] Step 204: The reconfigurable cryptographic coprocessor obtains the data field from the FIFO module through the decryption module, decrypts the data field using the key to obtain plaintext data, and outputs the plaintext data to the data configuration and clearing module. The data configuration and clearing module stores the plaintext data in the data storage module according to the length of the instructions and parameters output by the control module.

[0064] Step 205: The reconfigurable cryptographic coprocessor obtains the data field from the FIFO module through the verification module, performs calculations on the data field to obtain the processing result, and compares the processing result with the verification code. If the comparison matches, proceed to step 206; otherwise, proceed to step 207.

[0065] In this embodiment, steps 204 and 205 can be executed simultaneously;

[0066] Step 206: The reconfigurable cryptographic coprocessor sends a verification success notification to the control module through the verification module;

[0067] Step 207: The reconfigurable cryptographic coprocessor sends a verification failure notification to the control module through the verification module and outputs a second signal to the data configuration and clearing module. The data configuration and clearing module clears the plaintext data in the data storage module according to the length of the instructions and parameters output by the control module.

[0068] In this embodiment, when the CPU module in the chip receives a cryptographic algorithm processing request, it sends an execution instruction to the reconfigurable cryptographic coprocessor in the chip. The reconfigurable cryptographic coprocessor in the chip obtains plaintext data from the data storage module through the reconfigurable processor and performs the corresponding operation.

[0069] In this embodiment, the chip automatically clears the plaintext data in the data storage module every time power is lost, thereby eliminating the risk of data leakage.

[0070] In this embodiment, the chip executes a secure loading instruction stream and parameters process every time it is powered on, storing the instruction stream and parameters required by the reconfigurable cryptographic coprocessor to implement different algorithm requirements into the data storage module for the reconfigurable processor in the reconfigurable cryptographic coprocessor to obtain;

[0071] In this embodiment, the reconfigurable cryptographic coprocessor is implemented by a reconfigurable processor when different algorithm requirements are met. During the implementation process, the reconfigurable processor obtains the instruction stream and parameters stored in the data storage module.

[0072] This invention provides a method for protecting instruction streams and parameters. The method involves encrypting the instruction streams and parameters using a host computer and writing the encrypted data into the chip's FLASH memory. The encrypted data stored in the FLASH memory is then securely loaded into the chip. The plaintext data of the securely loaded instruction streams and parameters is stored in a designated data storage area of ​​a reconfigurable cryptographic coprocessor within the chip. The reconfigurable processor within the reconfigurable cryptographic coprocessor then retrieves the data as needed and participates in the execution process of the reconfigurable processor, thereby ensuring the security and integrity of the instruction streams and parameters obtained by the reconfigurable processor. Example 2

[0073] This invention provides a protection device for instruction stream and parameters, which is applied to a chip including a reconfigurable cryptographic coprocessor;

[0074] like Figure 3 As shown, the device includes: a control module, a DMA module, a FIFO module, a decryption module, a verification module, a data configuration and clearing module, and a data storage module;

[0075] The control module is connected to the DMA module, the verification module, and the data configuration and clearing module. It is used to start the DMA module, receive the instructions and parameter lengths sent by the DMA module, receive the verification success notification output by the verification module, control the data configuration and clearing module to store the plaintext data decrypted by the decryption module into the data storage module according to the instructions and parameter lengths, receive the verification failure notification output by the verification module, and control the data configuration and clearing module to clear the data in the data storage module according to the instructions and parameter lengths.

[0076] The DMA module is connected to the control module, decryption module, verification module, and FIFO module. It is used to obtain secure data from the chip's FLASH memory, transmit the key in the secure data to the decryption module, transmit the checksum in the secure data to the verification module, transmit the length of the instructions and parameters in the secure data to the control module, transmit the data fields in the secure data to the FIFO module for storage, and also to notify the control module after the data transmission is completed.

[0077] The decryption module is connected to the DMA module, FIFO module, and data configuration and clearing module. It is used to read data fields from the FIFO module, decrypt the data fields using the key passed from the DMA module, output a decryption completion signal to the data configuration and clearing module, and output the decrypted plaintext data to the data configuration and clearing module.

[0078] The verification module is connected to the DMA module, FIFO module, control module, and data configuration and clear module. It is used to read data fields from the FIFO module, perform calculations on the data fields to obtain the processing results, verify the processing results according to the verification code passed from the DMA module, send a verification success notification to the control module when the verification is successful, send a verification failure notification to the control module when the verification fails, output a second signal to the data configuration and clear module, and also output a first signal to the data configuration and clear module.

[0079] The data configuration and clearing module is connected to the decryption module, verification module, control module, and data storage module. It is used to receive plaintext data output by the decryption module, receive the instruction length input by the control module, receive the first signal output by the verification module, write plaintext data into the data storage module, and also to receive the second signal output by the verification module to clear the plaintext data in the data storage module.

[0080] The data storage module and the data configuration and clearing module are used to store plaintext data;

[0081] The data storage module is also connected to the reconfigurable processor, allowing the reconfigurable processor to access plaintext data.

[0082] like Figure 4 The diagram shown is a structural schematic of the data configuration and clearing module. Figure 5 The diagram shown is a circuit diagram of the data configuration and clearing module.

[0083] The data configuration and clearing module is used to write and clear data in the data storage module;

[0084] In this embodiment, clearing data means writing all zeros to the data storage module. The written data includes instruction streams and parameters.

[0085] like Figure 4 As shown, the data configuration and clearing module includes: a trigger, an OR gate, a first AND gate, a second AND gate, a NOT gate, a first comparator, a second comparator, a first selector, a second selector, a first address counter, and a second address counter;

[0086] The trigger is connected to an OR gate, a first selector, a second comparator, a second selector, and a verification module. It is used to receive the signal output by the verification module, output a signal to the OR gate, output a signal to the first selector, and receive the signal output by the second comparator.

[0087] Specifically, Figure 5 In this circuit, D0 is a trigger, OR0 is an OR gate, MUX0 is the first selector, CMP1 is the second comparator, and SM3_ERR is the output of the verification module. Specifically, trigger D0 receives the signal output by the verification module through the output SM3_ERR.

[0088] Specifically, the signals output by the trigger include a first signal or a second signal, wherein the first signal indicates that plaintext data is written to the data storage module, for example, the first signal is 0, and the second signal indicates that the plaintext data in the data storage module is cleared, for example, the second signal is 1;

[0089] The OR gate is connected to the trigger, the first AND gate, the second AND gate and the decryption module to receive the decryption completion signal output by the decryption module, receive the signal output by the trigger, and output signals to the first AND gate and the second AND gate;

[0090] Specifically, Figure 5 In this code, OR0 is an OR gate, AND0 is the first AND gate, AND1 is the second AND gate, and SM4_DONE is the output of the decryption module. Specifically, OR0 receives the decryption completion signal output by the decryption module through the output of the decryption module SM4_DONE.

[0091] The first AND gate, the first OR gate, the first comparator, and the data storage module are connected to output a write enable signal for the instruction stream to the data storage module.

[0092] The second AND gate, OR gate, NOT gate, and data storage module are connected to the data storage module to output the write enable signal of the parameters to the data storage module;

[0093] The NOT gate is connected to the second AND gate and the first comparator, and is used to perform a NOT operation on the signal output by the first comparator and output the signal to the second AND gate.

[0094] Specifically, Figure 5 In this configuration, AND0 is the first AND gate, AND1 is the second AND gate, CMP0 is the first comparator, and IO is the NOT gate.

[0095] Specifically, the write enable signal of the instruction stream is valid when it is 1, and the write enable signal of the parameters is valid when it is 1.

[0096] The first comparator is connected to the first selector, the first address counter, and the first AND gate and NOT gate. It is used to receive the signal output by the first selector, compare it with the value of the first address counter, and output the comparison result signal to the first AND gate and NOT gate.

[0097] Specifically, Figure 5 WADDR0 is the first address counter, which increments from 0 when data is written.

[0098] Specifically, the first comparator compares the signal output by the first selector with the value of the first address counter. If the comparison is the same, it outputs the third signal; if the comparison is different, it outputs the fourth signal. For example, the third signal is 0 and the fourth signal is 1.

[0099] The first selector is connected to the trigger, the first comparator and the control module. It is used to receive the signal output by the trigger, receive the instruction length output by the control module, determine the signal to be output to the first comparator based on the signal output by the trigger, and the signal output to the first comparator is the instruction length or fixed data.

[0100] Specifically, Figure 5INS_LEN is the output terminal of the control module. The first selector MUX0 specifically receives the length of the instruction output by the control module through the output terminal INS_LEN of the control module.

[0101] Specifically, the fixed data is 128 bits of 0 data;

[0102] Specifically, determining the signal to be output to the first comparator based on the signal output by the trigger is as follows: if the signal output by the trigger is the first signal, then the signal to be output to the first comparator is determined to be the instruction length; if the signal output by the trigger is the second signal, then the signal to be output to the first comparator is determined to be fixed data.

[0103] The second comparator is connected to the second address counter and the flip-flop. It is used to obtain the value of the second address counter and compare it with fixed data. When the value of the second address counter is the same as the fixed data, the clear state of the flip-flop is reset.

[0104] Specifically, Figure 5 CMP1 is the second comparator. Resetting the clear state of the flip-flop specifically involves changing the clear state of the flip-flop from valid to invalid. After the clear state of the flip-flop is reset, the signal output by the flip-flop to the OR gate OR0 is the first signal. WADDR1 is the second address counter. The second address counter decrements from the data address value when clearing data.

[0105] The second selector is connected to the trigger, the decryption module and the data storage module. It is used to receive the signal output by the trigger and the data output by the decryption module, and output the data output by the decryption module to the data storage module according to the received signal.

[0106] Specifically, the data output by the decryption module based on the received signal is as follows: the second selector determines the output data based on the signal output by the trigger. If the signal output by the trigger is the first signal, the output data is determined to be the data output by the decryption module; if the signal output by the trigger is the second signal, the output data is determined to be fixed data.

[0107] Specifically, Figure 5 In the middle, MUX1 is the second selector, and SM4_DOUT is the output terminal of the decryption module. Specifically, the second selector MUX1 receives the data output by the decryption module through the output terminal SM4_DOUT.

[0108] The first address counter is connected to the first comparator and the data storage module, and the second address counter is connected to the second comparator and the data storage module. The first address counter and the second address counter count according to the write enable signal of the instruction stream and parameters. The counting starts when the write enable signal is valid and increments the count value according to the number of writes.

[0109] Figure 5 WEN0 and WEN1 are the output terminals of the write enable signal for the instruction stream and the write enable signal for the parameter, respectively. WADDR0 and WADDR1 are address counters, which are the output terminals of the address signal for the instruction stream and the address signal for the parameter, respectively. WDATA0 and WDATA1 are the output terminals of the data signal for the instruction stream and the data signal for the parameter, respectively. SM3_ERR is the output terminal of the verification module. SM4_DONE is the decryption completion signal output terminal of the decryption module. SM4_DOUT is the plaintext data output terminal of the decryption module.

[0110] This invention also provides a reconfigurable cryptographic coprocessor, which includes the aforementioned protection device for instruction streams and parameters, and implements different cryptographic algorithms through the device.

[0111] This invention also provides a chip that includes the reconfigurable cryptographic coprocessor described above, which implements algorithm applications through the reconfigurable cryptographic coprocessor.

[0112] like Figure 6 The diagram shows a schematic of the device applied to a chip containing a reconfigurable cryptographic coprocessor.

[0113] The chip includes a download interface, a FLASH memory, a CPU module, and a reconfigurable cryptographic coprocessor that includes the device. The chip receives security data sent by the host computer through the download interface and stores it in the FLASH memory. The chip receives instructions from the host computer to implement cryptographic algorithms through the CPU module. The reconfigurable cryptographic coprocessor that includes the device completes the specific implementation of the cryptographic algorithms.

[0114] It should be noted that the above embodiments of the instruction stream and parameter protection device are only illustrated by the division of the above functional modules when executing the instruction stream and parameter protection method. In practical applications, the above functions can be allocated and performed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the instruction stream and parameter protection device and the instruction stream and parameter protection method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0115] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0116] In this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or order; the term "multiple" refers to two or more unless otherwise explicitly defined. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. The terms "install," "connect," "link," "fix," etc., should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0117] In the description of this invention, it should be understood that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0118] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, equivalent variations made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for protecting instruction streams and parameters, characterized in that, The method includes the following steps: Step S1: After the chip is powered on, the reconfigurable cryptographic coprocessor in the chip starts the DMA module through the control module to read the control field in the security data from the FLASH memory, writes the key in the control field into the decryption module, writes the check code in the control field into the verification module, and writes the length of the instructions and parameters in the control field into the control module. Step S2: The reconfigurable cryptographic coprocessor reads the data field from the security data in the FLASH memory through the DMA module and stores the data field in the FIFO module; Step S3: The reconfigurable cryptographic coprocessor obtains the data field from the FIFO module through the decryption module, decrypts the data field using the key to obtain plaintext data, and outputs the plaintext data to the data configuration and clearing module. The data configuration and clearing module stores the plaintext data in the data storage module according to the length of the instructions and parameters in the control module. Step S4: The reconfigurable cryptographic coprocessor obtains the data field from the FIFO module through the verification module, performs calculations on the data field to obtain the processing result, and compares the processing result with the verification code. If the comparison matches, proceed to step S5; otherwise, proceed to step S6. Step S5: The reconfigurable cryptographic coprocessor sends a verification success notification to the control module through the verification module; Step S6: The reconfigurable cryptographic coprocessor sends a verification failure notification to the control module through the verification module and outputs a second signal to the data configuration and clearing module. The data configuration and clearing module clears the plaintext data in the data storage module according to the length of the instructions and parameters input by the control module.

2. The method for protecting instruction streams and parameters according to claim 1, characterized in that, Also includes: Step A1: The host computer generates a key; Step A2: The host computer obtains the instruction stream and parameters as data to be protected, and encrypts the data to be protected using the key to obtain the first ciphertext; Step A3: The host computer calculates the checksum of the first ciphertext using a preset algorithm; Step A4: The host computer uses the key, the verification code, and the length of the data to be protected as a control field, and the first ciphertext as a data field. It organizes the control field and the data field to obtain secure data, and stores the secure data in the FLASH memory through the chip's download interface.

3. The method for protecting instruction streams and parameters according to claim 1, characterized in that, The method further includes: Step P1: When the CPU module in the chip receives a cryptographic algorithm processing request, it sends an execution instruction to the reconfigurable cryptographic coprocessor. Step P2: The reconfigurable cryptographic coprocessor obtains plaintext data from the data storage module through the reconfigurable processor in the chip, and performs corresponding operations according to the execution instructions.

4. A protection device for instruction stream and parameters, characterized in that, The device is applied to a chip including a reconfigurable cryptographic coprocessor, and the device includes: a control module, a DMA module, a FIFO module, a decryption module, a verification module, a data configuration and clearing module, and a data storage module; The control module is connected to the DMA module, the verification module, and the data configuration and clearing module. It is used to start the DMA module, receive the instructions and parameter lengths sent by the DMA module, and receive verification success or verification failure notifications output by the verification module. It also outputs the lengths of the instructions and parameters to the data configuration and clearing module. The DMA module is connected to the control module, the decryption module, the verification module, and the FIFO module. It is used to obtain secure data from the FLASH memory of the chip, transmit the key in the secure data to the decryption module, transmit the checksum in the secure data to the verification module, transmit the length of the instructions and parameters in the secure data to the control module, transmit the data fields in the secure data to the FIFO module for storage, and also to notify the control module after the data transmission is completed. The decryption module is connected to the DMA module, the FIFO module, and the data configuration and clearing module. It is used to read data fields from the FIFO module, decrypt the data fields using the key passed from the DMA module, output a decryption completion signal to the data configuration and clearing module, and output the decrypted plaintext data to the data configuration and clearing module. The verification module is connected to the DMA module, the FIFO module, the control module, and the data configuration and clearing module. It is used to read data fields from the FIFO module, perform calculations on the data fields to obtain processing results, verify the processing results according to the verification code passed from the DMA module, send a verification success notification to the control module when the verification is successful, send a verification failure notification to the control module when the verification fails, output a second signal to the data configuration and clearing module, and output a first signal to the data configuration and clearing module. The data configuration and clearing module is connected to the decryption module, the verification module, the control module, and the data storage module. It is used to receive plaintext data output by the decryption module, receive the instruction length output by the control module, receive the first signal output by the verification module, write plaintext data into the data storage module, and also to receive the second signal output by the verification module and clear the plaintext data in the data storage module according to the second signal. The data storage module and the data configuration and clearing module are used to store plaintext data.

5. The protection device for command stream and parameters according to claim 4, characterized in that, The data configuration and clearing module includes: a trigger, an OR gate, a first AND gate, a second AND gate, a NOT gate, a first comparator, a second comparator, a first selector, a second selector, a first address counter, and a second address counter; The trigger is connected to the OR gate, the first selector, the second comparator, the verification module, and the second selector; The OR gate is connected to the trigger, the first AND gate, the second AND gate, and the decryption module; The first AND gate is connected to the OR gate, the first comparator, and the data storage module; The second AND gate is connected to the OR gate, the NOT gate, and the data storage module; The NOT gate is connected to the second AND gate and the first comparator; The first comparator is connected to the first selector, the first address counter, the first AND gate, and the NOT gate; The first selector is connected to the trigger, the first comparator, and the control module; The second comparator is connected to the second address counter and the flip-flop; The second selector is connected to the trigger, the decryption module, and the data storage module; The first address counter is connected to the first comparator and the data storage module, and the second address counter is connected to the second comparator and the data storage module.

6. A reconfigurable cryptographic coprocessor, characterized in that, The reconfigurable cryptographic coprocessor includes the means of any one of claims 4-5, and the reconfigurable cryptographic coprocessor implements different cryptographic algorithms through the means.

7. A chip, characterized in that, The chip includes the reconfigurable cryptographic coprocessor as described in claim 6, and the chip implements algorithm applications through the reconfigurable cryptographic coprocessor.

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