HBM PHY test chip circuit and method based on zero-delay FIFO control

Abstract

The invention aims to provide an HBM PHY test chip circuit and method based on zero-delay FIFO control. The circuit comprises a command control channel module, a writing channel module and a reading channel module. The command control channel module is connected with the HBM PHY through a command control channel interface and is used for storing control information; the write channel module is connected with the HBM PHY through a write channel interface and is used for detecting write data enabling, and if the write data enabling exists, the control logic reads data in the write channel module and sends the data to the write channel interface; and the read channel module is connected with the HBM PHY through a read channel interface, and is used for detecting read effective data, comparing the read effective data with correct data, and writing the read effective data into the read data if the read effective data is inconsistent with the correct data. The small storage controller capable of sending any data and instruction is matched with the corresponding automatic comparison function, the data storage function and the like.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to an HBM PHY test chip circuit and method based on zero-delay FIFO control. Background Technology

[0002] Due to advancements in manufacturing technology, memory systems have developed rapidly in recent years. High-bandwidth memory (HBM) is an example of a recent type of memory system, supporting low power consumption, ultra-wide communication channels, and stacked configurations. HBM subsystems involve different types of memory controllers (full-speed, half-speed, quarter-speed), HBM PHYs, and HBM DRAM. HBM subsystems are suitable for applications involving high-performance graphics and computing, high-end networking and communication devices, and processors requiring large amounts of memory. Due to their critical role in the end-application, validating all components involved in the HBM subsystem is essential. The HBM PHY is a key element of the entire HBM system solution. The HBM PHY typically receives HBM DRAM row-col commands, data, parity, etc., from the memory controller interface via the DFI interface and passes them together to the HBM memory. Ideally, the HBM PHY needs to support all HBM memory functions, such as frequency ratio, data rate, memory size, pseudo-channel mode, DBI, etc. HBM PHYs can be simulated and verified at the subsystem or system level. Such high-speed interface PHY IPs require thorough post-silicon verification before mass commercialization.

[0003] However, currently, various IP vendors typically offer two test chip solutions for designing HBM PHY IP: Solution 1: This test system includes a memory controller (commercial controller), PHY, and HBMDRAM. Solution 2: This solution is relatively simpler, not integrating the memory controller into the test chip, but utilizing the internal functions of the HBM PHY to complete silicon testing. While Solution 1 can fully verify the functionality, performance, and power consumption of the HBM PHY, it also has significant disadvantages. Integrating a commercial controller requires purchase, significantly increasing the cost of the test chip. Furthermore, the controller requires substantial logic resources; for example, a major IP vendor's controller on a certain Samsung process has over 8M standard logic cells. This lengthens the development cycle and increases the complexity of the test chip, significantly increasing its area and further incurring time and economic costs. Summary of the Invention

[0004] The purpose of this invention is to provide an HBM PHY test chip circuit and method based on zero-latency FIFO control. This method utilizes a small storage controller capable of issuing arbitrary data and instructions, along with corresponding automatic comparison and data storage functions. This design fully meets the requirements for testing HBM PHYs, enabling the issuance of arbitrary data and instructions as needed. Compared to integrating commercial controllers, this testing solution offers more controllable HBM PHY interfaces and easier backend physical implementation, thereby shortening the overall R&D cycle and saving development costs.

[0005] An HBM PHY test chip circuit based on zero-delay FIFO control includes: a command control channel module, a write channel module, and a read channel module; The command control channel module is connected to the HBM PHY via the command control channel interface and is used to store control information; The write channel module is connected to the HBM PHY through the write channel interface. It is used to detect write data enable. If write data is enabled, the control logic reads the data in the write channel module and sends it to the write channel interface. The read channel module is connected to the HBM PHY through the read channel interface. It is used to detect valid read data, compare the valid read data with the correct data, and if the valid read data and the correct data are inconsistent, the valid read data will be written to the read data.

[0006] Preferably, the command control channel module includes: an AC command zero-latency FIFO controller and a control logic module; The AC command zero-latency FIFO controller is used to store domain information and send it to the control interface of the HBM PHY. The domain information includes: DFI interface control information, read latency control counter, refresh counter, and refresh flag; The DFI interface control information is used to send commands to the control interface of the HBM PHY, including read enable, write enable, row commands, and column commands; The read delay control counter is used to control the execution time interval between two consecutive entries to meet the protocol requirements of HBMDRAM; The refresh counter is used to calculate the number of cycles and perform the refresh operation; The refresh flag is used to determine whether an entry is a refresh command.

[0007] Preferably, the write channel module includes: a write data module and a control logic module; The write channel module checks whether write data is enabled based on the data read from the AC FIFO; If write data is enabled, the control logic module will read the data in the write data module and transmit it to the AW interface. The write data module stores the data to be written to HBM DRAM.

[0008] Preferably, the read channel module includes: a read data module and a correct data module; The read channel module compares the valid read data transmitted from the DFI interface with the data in the correct data module accordingly. If the valid data read is inconsistent with the correct data, the valid data will be written to the read data module. The read data module stores the erroneous data read from the HBM DRAM, while the correct data module stores the expected data.

[0009] A method for testing HBM PHY chips based on shared zero-delay FIFO control, applied to an HBM PHY chip circuit based on zero-delay FIFO control, includes: Configure control commands for the AC command zero-latency FIFO controller, write channel module, and read channel module; The AC command zero-latency FIFO controller outputs instructions to the HBM DRAM through the DIF interface; HBM DRAM reads and writes data according to the instructions of the AC command zero-latency FIFO controller; The performance of the HBM PHY can be determined based on the data read and written.

[0010] Preferably, the control commands for configuring the AC command zero-latency FIFO controller, write channel module, and read channel module include: Configure the control instructions for the AC command zero-latency FIFO controller, setting AC_FIFO.Entry_0 as the activation instruction, AC_FIFO.Entry_1 as the write instruction, AC_FIFO.Entry_2 as the read instruction, AC_FIFO.Entry_3 as the write instruction, AC_FIFO.Entry_4 as the null instruction, AC_FIFO.Entry_5 as the pre-instruction, and AC_FIFO.Entry_6 as the refresh instruction. Configure the control instructions for the write channel module, setting the write data for Entry_0 of the write channel module to DATA0, and the write data for Entry_n of the write channel module to DATAn. The control instructions for configuring the correct data module will set the correct data for Entry_0 of the correct data module to DATA0, and the correct data for Entry_n of the correct data module to DATAn.

[0011] Preferably, the HBM DRAM reads and writes data according to the instructions of the AC command zero-latency FIFO controller, including: When the AC command zero-delay FIFO controller issues an activation command, the HBM DRAM performs the activation operation, and the value of the configuration counter is greater than or equal to the delay from the activation command to the write command. When the AC command zero-latency FIFO controller issues a write command, the HBM DRAM performs a write operation, reads the corresponding write data from the write channel module, sends it to the DFI interface, writes it to the address of the HBM DRAM, and configures the counter value to be greater than or equal to the internal write command to read command delay. When the AC command zero-delay FIFO controller issues a read command, the HBM DRAM performs a read operation, reads the address of the HBM DRAM, and the read data is returned from the HBM DRAM to the comparator of the test module. The correct data is read from the correct data module and sent to the comparator. The comparator compares the data. If the read data is inconsistent with the correct data, the erroneous data is written to the read channel module. The value of the configuration counter is greater than or equal to the delay between the read command and the write command. When the AC command zero-delay FIFO controller issues a null instruction, the HBM DRAM performs a null operation, and the value of the configuration counter meets the interval requirement; When the AC command zero-delay FIFO controller issues a precharge command, the HBM DRAM performs a precharge operation, configuring the counter value to be greater than or equal to; When the AC command zero-latency FIFO controller issues a refresh command, the HBM DRAM performs a refresh operation, configuring the counter value to be greater than or equal to...

[0012] Preferably, after the HBM DRAM performs its first read operation, a second write operation is also performed, specifically: When the AC command zero-latency FIFO controller issues a write command for the second time, the HBM DRAM performs a write operation, reads the corresponding write data from the write channel module, sends it to the DFI interface, writes it to the address of the HBM DRAM, and configures the counter value to be greater than or equal to the delay between the read command and the write command.

[0013] Preferably, it also includes replacing the Refresh instruction with the NOP instruction during the refresh phase.

[0014] Preferably, replacing the Refresh instruction with a NOP instruction during the refresh phase includes: When the refresh flag is configured to be valid in the AC command zero-delay FIFO controller, the refresh counter value is compared with the configuration waterline each time the value of the entry is read from the AC command zero-delay FIFO controller. If the requirements are met, the refresh instruction will be executed; otherwise, the refresh instruction will be replaced with an empty instruction.

[0015] The beneficial effects of this invention are as follows: 1. By configuring the required command sequence into the AC FIFO and then executing it sequentially, this test scheme can send arbitrary data and commands to the HBM DRAM, and can also automatically check and compare with golden data, and store erroneous data for debugging and analysis. Because it can precisely control each time slot and supports cyclic execution, it can effectively perform stress testing and test the corresponding power consumption; 2. The logic resources of the module of this invention are drastically reduced compared with the commercial version of the controller, which greatly reduces the implementation time of the backend and the investment cost of HBM PHY; 3. Compared with the non-integrated controller, this invention can send arbitrary data and commands from the DFI interface, so power consumption data in various scenarios can be tested according to different needs. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the PHY test module structure of the present invention; Figure 2 This is a schematic diagram of the HBM PHY test chip structure of the present invention; Figure 3 This is a schematic diagram of the operation of the PHY test module of the present invention; Figure 4 This is a schematic diagram of the token mechanism of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0021] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0022] Currently, various IP vendors typically offer two test chip solutions for designing HBM PHY IP: Solution 1: This test system includes a memory controller (commercial controller), PHY, and HBM DRAM. Solution 2: This simpler solution does not integrate the memory controller into the test chip but utilizes the internal functions of the HBM PHY to perform silicon testing. While Solution 1 can effectively verify the functionality, performance, and power consumption of the HBM PHY, it also has significant disadvantages. Integrating a commercial controller requires purchase, significantly increasing the cost of the test chip. Furthermore, the controller requires substantial logic resources; for example, a major IP vendor's controller on a certain Samsung process has over 8M standard logic cells. This lengthens the development cycle and increases the complexity of the test chip, significantly increasing its area and further incurring time and economic costs.

[0023] This invention configures the required command sequence into the AC FIFO and executes them sequentially. This test scheme can send arbitrary data and commands to the HBM DRAM, and can also automatically check and compare with golden data, storing erroneous data for debugging and analysis. Because it can precisely control each time slot and supports cyclic execution, it can effectively perform stress testing and test the corresponding power consumption. Compared with the logic resources of commercial controllers, the logic resources of this invention module are drastically reduced, which greatly reduces the implementation time and investment cost of the backend and HBM PHY. Compared with non-integrated controllers, this invention can send arbitrary data and commands from the DFI interface, allowing for the testing of power consumption data in various scenarios according to different needs.

[0024] Example 1 An HBM PHY test chip circuit based on zero-delay FIFO control, reference Figure 1 and Figure 2 It includes: a command control channel module, a write channel module, and a read channel module; The command and control channel module connects to the HBM PHY via the command and control channel interface and is used to store control information; The write channel module connects to the HBM PHY through the write channel interface to detect write data enable. If write data is enabled, the control logic reads the data from the write channel module and sends it to the write channel interface. The read channel module connects to the HBM PHY via the read channel interface to detect valid read data. It compares the valid read data with the correct data. If the valid read data and the correct data are inconsistent, the valid read data will be written to the read data.

[0025] In this embodiment of the invention, the HBM3 PHY design is used as an example. Because the HBM3 DRAM has a total of 16 channels, and each channel is independent of the others, Figure 1 A total of 16 block diagrams are instantiated. The AR interface represents the read channel interface between the PHY test module and the HBM PHY, the AW interface represents the write channel interface between the PHY test module and the HBM PHY, and the AC interface represents the command and control channel interface between the PHY test module and the HBM PHY.

[0026] Preferably, the command control channel module includes: an AC command zero-delay FIFO controller and a control logic module; The AC command zero-latency FIFO controller is used as the control interface for storing domain information and sending it to the HBM PHY. Domain information includes: DFI interface control information, read latency control counter, refresh counter, and refresh flag; DFI interface control information is used to send commands to the control interface of HBM PHY, including read enable, write enable, row commands, and column commands; The read delay control counter is used to control the execution time interval between two consecutive entries to meet the protocol requirements of HBM DRAM; Read latency control counter. Since a zero-latency FIFO stores multiple entries, and due to the FIFO's FIFO-first-out mechanism, the execution time interval between two consecutive entries must meet the HBM DRAM protocol requirements. Therefore, a counter is needed to determine the execution time between two entries. Without this counter, data is read continuously from the FIFO; for example, if it's an ACTIVE (activation command) and a Write (write command), the two commands will be sent to the HBM DRAM chip consecutively. This cannot meet the tRCDWR time interval requirement between ACTIVE and Write specified in the HBM DRAM protocol. The Samsung HBM3 DRAM manual specifies a minimum latency of MAX (12ns, 3nCK) for tRCDWR.

[0027] The refresh counter is used to calculate the number of loops and perform the refresh operation; A refresh counter is used because this FIFO supports a loop mechanism to allow the system to run for extended periods, meaning data read from the FIFO is written back to it. Therefore, the FIFO is not very deep; the execution time of one loop will not exceed the refresh cycle (maximum refresh cycle is 3.9µs). One loop takes 390ns, so the FIFO only needs to be refreshed on the 10th iteration. Therefore, this refresh counter is used.

[0028] The refresh flag is used to determine whether an entry is a refresh command.

[0029] Command and control channel module. This includes an AC (address / command) zero-latency FIFO controller (with SRAM storage) and control logic. A zero-latency FIFO is a specially designed first-in, first-out buffer designed to minimize the latency between data writing and reading, allowing data to be read immediately after writing; theoretically, the latency is zero cycles. The zero-latency FIFO stores key field information as shown in Table 1.

[0030] Table 1: Domain Information Preferably, the write channel module includes: a write data module and a control logic module; The write channel module checks whether write data is enabled based on the data read from the AC FIFO; If write data is enabled, the control logic module will read the data in the write data module and transmit it to the AW interface. The write data module stores the data to be written to HBM DRAM.

[0031] In this embodiment of the invention, the write channel module includes a WDM (write data memory) and related control logic. This module checks whether write data is enabled based on the data read from the AC FIFO. If write data is enabled, the related control logic reads the data from the WDM and transmits it to the AW interface. The WDM stores the data to be written to the HBM DRAM.

[0032] Preferably, the read channel module includes: a read data module and a correct data module; The read channel module compares the valid read data transmitted from the DFI interface with the data in the correct data module accordingly. If the valid data read is inconsistent with the correct data, the valid data will be written to the read data module. The read data module stores the erroneous data read from the HBM DRAM, while the correct data module stores the expected data.

[0033] In this embodiment of the invention, the read channel module includes an RDM (read data memory) and a GDM (correct data memory, also known as Golden data memory) and related control logic. This module compares valid read data received from the DFI interface with the data in the GDM. If the data is inconsistent, the incorrect data is written to the RDM for system analysis. The RDM stores erroneous data read from the HBM DRAM, while the GDM stores expected data.

[0034] Example 2 A method for testing HBM PHY chips based on shared zero-latency FIFO control, referenced Figure 3 It is applied to an HBM PHY test chip circuit based on zero-delay FIFO control, including: S100, configures control commands for the AC command zero-latency FIFO controller, write channel module and read channel module; The S200 AC command zero-latency FIFO controller outputs instructions to the HBM DRAM via the DIF interface; S300, HBM DRAM reads and writes data according to the instructions of the AC command zero-latency FIFO controller; S400 determines the performance of the HBM PHY based on the data read and written.

[0035] This invention enables the test chip solution to issue arbitrary data and commands with minimal logic resources, facilitating functional debugging and power consumption testing. Based on a zero-latency FIFO control method, it can predict the execution delay between the current and next instruction, improving testing efficiency. Supporting a refresh token mechanism, it reduces execution time during loop execution, more closely resembling real-world application scenarios. Furthermore, it effectively supports loop mechanisms, enabling long-term stress testing during silicon testing.

[0036] Preferably, in step S100, the control instructions for configuring the AC command zero-latency FIFO controller, the write channel module, and the read channel module include: Configure the control instructions for the AC command zero-latency FIFO controller, setting AC_FIFO.Entry_0 as the activation instruction, AC_FIFO.Entry_1 as the write instruction, AC_FIFO.Entry_2 as the read instruction, AC_FIFO.Entry_3 as the write instruction, AC_FIFO.Entry_4 as the null instruction, AC_FIFO.Entry_5 as the pre-instruction, and AC_FIFO.Entry_6 as the refresh instruction. Configure the control instructions for the write channel module, setting the write data for Entry_0 of the write channel module to DATA0, and the write data for Entry_n of the write channel module to DATAn. The control instructions for configuring the correct data module will set the correct data for Entry_0 of the correct data module to DATA0, and the correct data for Entry_n of the correct data module to DATAn.

[0037] The AC FIFO is configured as follows: Configure Entry_0 to Entry_y in AC_FIFO as shown above. That is, configure AC_FIFO.Entry_0 with the ACTIVE instruction, AC_FIFO.Entry_1 with the WRITE instruction, AC_FIFO.Entry_2 with the READ instruction, and so on. Figure 3 The WDM configuration is as follows: Configure Entry_0 to Entry_x in WDM as described above. That is, the write data configured for Entry_0 in WDM is DATA0, the write data configured for Entry_1 in WDM is DATA1, and so on. The GDM configuration is the same as the WDM configuration, and no configuration is made for RDM.

[0038] Preferably, S300, the HBM DRAM reads and writes data according to the instructions of the AC command zero-latency FIFO controller, including: When the AC command zero-delay FIFO controller issues an activation command, the HBM DRAM performs the activation operation, and the value of the configuration counter is greater than or equal to the delay from the activation command to the write command. The value in AC_FIFO.entry0 is read and sent to the DFI interface, and the HBM DRAM executes the Active instruction. The corresponding value for this entry is configured to meet the HBM DRAM Active instruction format. For the value of cmd_cnt in this entry, it must be greater than or equal to tRCDWR (the delay between the Active instruction and the Write instruction). To meet the requirement in the HBM DRAM protocol that the time interval between the ACTIVE instruction and the WRITE instruction must be greater than or equal to tRCDWR, after reading the value of this entry, wait for cmd_cnt clock cycles before proceeding to the next step.

[0039] When the AC command zero-latency FIFO controller issues a write command, the HBM DRAM performs a write operation, reads the corresponding write data from the write channel module, sends it to the DFI interface, writes it to the address of the HBM DRAM, and configures the counter value to be greater than or equal to the internal write command to read command delay. The system reads AC_FIFO.entry1 and simultaneously reads the corresponding write data DATA0 from the WDM, sending it to the DFI interface. The HBM DRAM executes the Write instruction, writing to address X in the HBM DRAM. The corresponding configuration data is then set; this entry data must satisfy the HBM DRAM write instruction format. The value of cmd_cnt in this entry must be greater than or equal to WL+2+tWTRL (internal write-to-read command delay) to meet the HBM DRAM protocol requirement that the time interval between the Write and Read instructions must be greater than or equal to WL+2+tWTRL. After reading the value of this entry, the system waits for cmd_cnt clock cycles before proceeding to the next step.

[0040] When the AC command zero-delay FIFO controller issues a read command, the HBM DRAM performs a read operation, reads the address of the HBM DRAM, and the read data is returned from the HBM DRAM to the comparator of the test module. The correct data is read from the correct data module and sent to the comparator. The comparator compares the data. If the read data is inconsistent with the correct data, the erroneous data is written to the read channel module. The value of the configuration counter is greater than or equal to the delay between the read command and the write command. The AC_FIFO.entry2 is read and sent to the DFI interface. The HBM DRAM executes a Read instruction, reading data from address X in the HBM DRAM. The read data is returned from the HBM DRAM to the comparator in the test module. Simultaneously, DATA0 is read from the GDM and sent to the comparator. The comparator compares the two data; if they are inconsistent, the erroneous data is written to the RDM for system analysis. The corresponding value for this entry is configured to meet the HBM DRAM read instruction format. The value of cmd_cnt in this entry must be greater than or equal to tRTW (read-to-write delay) to meet the HBM DRAM protocol requirement that the time interval between the Read and Write instructions must be greater than or equal to tRTW. After reading the value of this entry, wait for cmd_cnt clock cycles before proceeding to the next step.

[0041] When the AC command zero-delay FIFO controller issues a null instruction, the HBM DRAM performs a null operation, and the value of the configuration counter meets the interval requirement; Read AC_FIFO.entry4 and send it to the DFI interface. The HBM DRAM executes the NOP instruction. Configure the corresponding value for this entry to meet the HBM DRAM's NOP instruction format. Configure the cmd_cnt value in this entry to meet the interval requirements during testing. After reading the value of this entry, wait for cmd_cnt clock cycles before proceeding to the next step.

[0042] When the AC command zero-delay FIFO controller issues a precharge command, the HBM DRAM performs a precharge operation, configuring the counter value to be greater than or equal to; Read AC_FIFO.entry5 and send it to the DFI interface. HBM DRAM executes the Pre-charge instruction. Configure the corresponding data; this entry data must meet the HBM DRAM pre-charge instruction format. The value of cmd_cnt must be greater than or equal to tRP to meet the HBM DRAM protocol requirement that the time interval between the Pre-charge instruction and the Refresh instruction must be greater than or equal to tRP. After reading the value of this entry, wait for cmd_cnt clock cycles before proceeding to the next step.

[0043] When the AC command zero-latency FIFO controller issues a refresh command, the HBM DRAM performs a refresh operation, configuring the counter value to be greater than or equal to...

[0044] AC_FIFO.entry6 is read and sent to the DFI interface, triggering the HBM DRAM to execute a Refresh instruction. The corresponding data is configured, ensuring the entry data meets the HBM DRAM refresh instruction format. The value of cmd_cnt in this entry must be greater than or equal to tREFI to meet the refresh instruction timing requirements specified in the HBM DRAM protocol. After reading the value of this entry, the system waits for cmd_cnt clock cycles before executing the next entry. It's important to note that during prolonged stress testing, data read from the AC FIFO will be rewritten to the AC FIFO, with the instruction looping until the maximum configured loop value is reached.

[0045] Preferably, after the HBM DRAM performs its first read operation, a second write operation is also performed, specifically: When the AC command zero-latency FIFO controller issues a write command for the second time, the HBM DRAM performs a write operation, reads the corresponding write data from the write channel module, sends it to the DFI interface, writes it to the address of the HBM DRAM, and configures the counter value to be greater than or equal to the delay between the read command and the write command.

[0046] Read AC_FIFO.entry3 and simultaneously read the corresponding write data DATA1 from WDM, sending it to the DFI interface. HBM DRAM executes the Write instruction, writing to address Y in HBM DRAM. Configure the corresponding value for this entry, ensuring the entry data meets the HBM DRAM Write instruction format. The value of cmd_cnt in this entry must be greater than or equal to WL+2+RU(tWR / tCK) to meet the requirement in the HBM DRAM protocol that the time interval between the Write instruction and the NOP instruction must be greater than or equal to WL+2+RU(tWR / tCK). After reading the value of this entry, wait for cmd_cnt clock cycles before proceeding to the next step.

[0047] Preferably, it also includes replacing the Refresh instruction with the NOP instruction during the refresh phase.

[0048] Since Refresh only needs to be executed once every tREFI (3.9us) time interval to meet the requirements of the HBM DRAM protocol, this invention specifically designs a token mechanism that replaces the Refresh instruction with the NOP instruction to improve execution efficiency. Specifically, when the refresh flag is valid in the AC FIFO, after each entry value is read from the FIFO, the refresh counter value is compared with the configuration threshold. If the requirements are met, the refresh instruction is executed; otherwise, the refresh instruction is replaced with the NOP instruction.

[0049] Preferably, refer to Figure 4 During the refresh phase, replacing refresh instructions with NOP instructions includes: When the refresh flag is configured to be valid in the AC command zero-delay FIFO controller, the refresh counter value is compared with the configuration waterline each time the value of the entry is read from the AC command zero-delay FIFO controller. If the requirements are met, the refresh instruction will be executed; otherwise, the refresh instruction will be replaced with an empty instruction.

[0050] like Figure 4 As shown, the token represents the remaining time before the refresh operation needs to be performed. Figure 4 The dark rectangular entry represents a refresh command. Initially, a raw value is configured for the refresh counter. After the entry is read, it is compared with the configured threshold. If the requirements are not met, the refresh command is not executed, and it is replaced by a NOP command. The current refresh counter is then refreshed and written back to the FIFO. This process continues until a refresh command read from the FIFO meets the requirements, at which point the current refresh command is executed.

[0051] This invention configures the required command sequence into the AC FIFO and executes them sequentially. This test scheme can send arbitrary data and commands to the HBM DRAM, and can also automatically check and compare with golden data, storing erroneous data for debugging and analysis. Because it can precisely control each time slot and supports cyclic execution, it can effectively perform stress testing and test the corresponding power consumption. Compared with the logic resources of commercial controllers, the logic resources of this invention module are drastically reduced, which greatly reduces the implementation time and investment cost of the backend and HBM PHY. Compared with non-integrated controllers, this invention can send arbitrary data and commands from the DFI interface, allowing for the testing of power consumption data in various scenarios according to different needs.

[0052] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. An HBM PHY test chip circuit based on zero-delay FIFO control, characterized in that, include: Command control channel module, write channel module, and read channel module; The command control channel module is connected to the HBM PHY via the command control channel interface and is used to store control information; The write channel module is connected to the HBM PHY through the write channel interface. It is used to detect write data enable. If write data is enabled, the control logic reads the data in the write channel module and sends it to the write channel interface. The read channel module is connected to the HBM PHY through the read channel interface. It is used to detect valid read data, compare the valid read data with the correct data, and if the valid read data and the correct data are inconsistent, the valid read data will be written to the read data.

2. The HBM PHY test chip circuit based on zero-delay FIFO control according to claim 1, characterized in that, The command control channel module includes: an AC command zero-latency FIFO controller and a control logic module; The AC command zero-latency FIFO controller is used to store domain information and send it to the control interface of the HBM PHY. The domain information includes: DFI interface control information, read latency control counter, refresh counter, and refresh flag; The DFI interface control information is used to send commands to the control interface of the HBM PHY, including read enable, write enable, row commands, and column commands; The read delay control counter is used to control the execution time interval between two consecutive entries to meet the protocol requirements of HBM DRAM; The refresh counter is used to calculate the number of cycles and perform the refresh operation; The refresh flag is used to determine whether an entry is a refresh command.

3. The HBM PHY test chip circuit based on zero-delay FIFO control according to claim 1, characterized in that, The write channel module includes: a write data module and a control logic module; The write channel module checks whether write data is enabled based on the data read from the AC FIFO; If write data is enabled, the control logic module will read the data in the write data module and transmit it to the AW interface. The write data module stores the data to be written to HBM DRAM.

4. The HBM PHY test chip circuit based on zero-delay FIFO control according to claim 1, characterized in that, The read channel module includes: a read data module and a correct data module; The read channel module compares the valid read data transmitted from the DFI interface with the data in the correct data module accordingly. If the valid data read is inconsistent with the correct data, the valid data will be written to the read data module. The read data module stores the erroneous data read from the HBM DRAM, while the correct data module stores the expected data.

5. A method for testing an HBM PHY chip based on shared zero-delay FIFO control, applied to an HBM PHY test chip circuit based on zero-delay FIFO control as described in any one of claims 1-4, characterized in that, include: Configure control commands for the AC command zero-latency FIFO controller, write channel module, and read channel module; The AC command zero-latency FIFO controller outputs instructions to the HBM DRAM through the DIF interface; HBM DRAM reads and writes data according to the instructions of the AC command zero-latency FIFO controller; The performance of the HBM PHY can be determined based on the data read and written.

6. The method for testing HBM PHY chips based on shared zero-latency FIFO control according to claim 5, characterized in that, The control commands for configuring the AC command zero-latency FIFO controller, write channel module, and read channel module include: Configure the control instructions for the AC command zero-latency FIFO controller, setting AC_FIFO.Entry_0 as the activation instruction, AC_FIFO.Entry_1 as the write instruction, AC_FIFO.Entry_2 as the read instruction, AC_FIFO.Entry_3 as the write instruction, AC_FIFO.Entry_4 as the null instruction, AC_FIFO.Entry_5 as the pre-instruction, and AC_FIFO.Entry_6 as the refresh instruction. Configure the control instructions for the write channel module, setting the write data for Entry_0 of the write channel module to DATA0, and the write data for Entry_n of the write channel module to DATAn. The control instructions for configuring the correct data module will set the correct data for Entry_0 of the correct data module to DATA0, and the correct data for Entry_n of the correct data module to DATAn.

7. The method for testing HBM PHY chips based on shared zero-latency FIFO control according to claim 5, characterized in that, The HBM DRAM reads and writes data according to the instructions of the AC command zero-latency FIFO controller, including: When the AC command zero-delay FIFO controller issues an activation command, the HBM DRAM performs the activation operation, and the value of the configuration counter is greater than or equal to the delay from the activation command to the write command. When the AC command zero-latency FIFO controller issues a write command, the HBM DRAM performs a write operation, reads the corresponding write data from the write channel module, sends it to the DFI interface, writes it to the address of the HBM DRAM, and configures the counter value to be greater than or equal to the internal write command to read command delay. When the AC command zero-delay FIFO controller issues a read command, the HBM DRAM performs a read operation, reads the address of the HBM DRAM, and the read data is returned from the HBM DRAM to the comparator of the test module. The correct data is read from the correct data module and sent to the comparator. The comparator compares the data. If the read data is inconsistent with the correct data, the erroneous data is written to the read channel module. The value of the configuration counter is greater than or equal to the delay between the read command and the write command. When the AC command zero-delay FIFO controller issues a null instruction, the HBM DRAM performs a null operation, and the value of the configuration counter meets the interval requirement; When the AC command zero-delay FIFO controller issues a precharge command, the HBM DRAM performs a precharge operation, configuring the counter value to be greater than or equal to; When the AC command zero-latency FIFO controller issues a refresh command, the HBM DRAM performs a refresh operation, configuring the counter value to be greater than or equal to...

8. The method for testing HBM PHY chips based on shared zero-latency FIFO control according to claim 7, characterized in that, After the HBM DRAM performs its first read operation, a second write operation is also performed, specifically: When the AC command zero-latency FIFO controller issues a write command for the second time, the HBM DRAM performs a write operation, reads the corresponding write data from the write channel module, sends it to the DFI interface, writes it to the address of the HBM DRAM, and configures the counter value to be greater than or equal to the delay between the read command and the write command.

9. The method for testing HBM PHY chips based on shared zero-latency FIFO control according to claim 7, characterized in that, Also includes: During the refresh phase, the NOP instruction is used instead of the Refresh instruction.

10. The method for testing HBM PHY chips based on shared zero-latency FIFO control according to claim 9, characterized in that, The replacement of the Refresh instruction with the NOP instruction during the refresh phase includes: When the refresh flag is configured to be valid in the AC command zero-delay FIFO controller, the refresh counter value is compared with the configuration waterline each time the value of the entry is read from the AC command zero-delay FIFO controller. If the requirements are met, the refresh instruction will be executed; otherwise, the refresh instruction will be replaced with an empty instruction.

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