Pluggable storage device, storage equipment and computing system comprising storage equipment

Abstract

The invention relates to a pluggable storage device, storage equipment and a computing system comprising the storage equipment. A pluggable storage device includes a plurality of memory sockets, a slot, and a master controller. And the slot is connected with external equipment. The master controller may be communicatively coupled to the plurality of memory sockets and slots, and has an error correction function. The main controller sets at least one data processing mode from among a plurality of data processing modes based on error rates of a plurality of memory modules mounted in a plurality of memory sockets, and remaps input / output data according to the at least one data processing mode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 63 / 669,902, filed July 11, 2024; Korean Patent Application No. 10-2025-0001638, filed January 6, 2025; and U.S. Patent Application No. 19 / 072,908, filed March 6, 2025, all of which are incorporated herein by reference in their entirety. Technical Field

[0003] Various embodiments generally relate to a semiconductor device, and more specifically, to a pluggable storage device, a storage apparatus, and a computing system including the storage apparatus. Background Technology

[0004] Many cloud service providers, such as Microsoft and Google, require significant storage capacity to build their servers and use multiple storage devices to provide the necessary storage space.

[0005] In order to effectively manage multiple storage devices, storage tiering technology is essential, which separates storage devices according to their uses and stores data according to access frequency.

[0006] However, with time and increased usage conditions, the performance of storage devices inevitably degrades. When the performance of a storage device fails to meet predetermined standards, it must be discarded. This leads to increased costs when replacing degraded storage devices.

[0007] Therefore, there is a need to develop technologies that can improve the performance of storage devices or reuse degraded storage devices instead of discarding them. Summary of the Invention

[0008] In one embodiment, a pluggable storage device may include a plurality of memory sockets, slots, and a main controller. Slots may be configured to connect to external devices. The main controller may be communicatively coupled to the plurality of memory sockets and slots and may have error correction capabilities. The main controller may be configured to set at least one data processing mode from a plurality of data processing modes based on the error rates of a plurality of memory modules mounted in the plurality of memory sockets, and may be configured to remap input / output data according to at least one data processing mode.

[0009] In an embodiment, a pluggable storage device can include a plurality of memory modules, a slot, and a main controller. The plurality of memory modules can be installed in a plurality of memory sockets. The slot can be configured to be connected with an external device. The main controller can be communicably coupled to the plurality of memory sockets and the slot, and can have an error correction function. The main controller can include at least one memory controller configured to perform training on the plurality of memory modules to detect an error rate, configured to output memory management information including the error rate, and configured to generate an error correction code for input / output data; a host interface communicably coupled to at least one host through the slot; a data remapping circuit configured to remap the input / output data and the error correction code according to at least one predetermined data processing mode; and a board management controller configured to set at least one data processing mode from among a plurality of data processing modes for the plurality of memory modules based on the memory management information, and configured to transmit and receive the memory management information to and from the host interface.

[0010] In an embodiment, a storage apparatus can include a plurality of pluggable storage devices and a communication path manager. The plurality of pluggable storage devices can be configured to perform training on a plurality of memory modules to detect an error rate, can be configured to set at least one data processing mode from among a plurality of data processing modes to perform a data remapping operation including error correction based on the error rate, and can be configured to output memory management information including the error rate and the set data processing mode. The communication path manager can be configured to selectively couple at least one of the plurality of pluggable storage devices with at least one external device according to the memory management information.

[0011] In an embodiment, a computing system can include a plurality of hosts and a storage apparatus. The plurality of hosts can be configured to output external device information including storage capacities and bandwidths of the plurality of hosts. The storage apparatus can include a plurality of pluggable storage devices, can be configured to perform a data remapping operation including error correction by setting at least one data processing mode from among a plurality of data processing modes based on an error rate of each of the plurality of pluggable storage devices, and can be configured to allocate at least one of the plurality of pluggable storage devices to each of the plurality of hosts based on the external device information. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 and Figure 2 is a diagram illustrating a configuration of a pluggable storage device according to an embodiment of the disclosure.

[0013] Figure 3 is a diagram illustrating a configuration of a main controller according to an embodiment of the disclosure.

[0014] Figure 4 This is a diagram illustrating the characteristic differences of data processing modes according to embodiments of the present disclosure.

[0015] Figure 5 This is a diagram illustrating the configuration of a pluggable storage device operating in a first data processing mode according to an embodiment of the present disclosure.

[0016] Figure 6 This is a diagram illustrating a data remapping method based on a first data processing mode.

[0017] Figure 7 This is a diagram illustrating the configuration of a pluggable storage device operating in a second data processing mode according to an embodiment of the present disclosure.

[0018] Figure 8 This is a diagram illustrating a data remapping method based on a second data processing mode.

[0019] Figure 9 This is a diagram illustrating the configuration of a pluggable storage device operating in a third data processing mode according to an embodiment of the present disclosure.

[0020] Figure 10 This is a diagram illustrating a data remapping method under a third data processing mode according to an embodiment of the present disclosure.

[0021] Figure 11 and Figure 12 This is a diagram illustrating the detailed operation of the data remapping method based on the third data processing mode.

[0022] Figure 13 This is a diagram illustrating the configuration of a main controller according to an embodiment of the present disclosure.

[0023] Figure 14 This is a diagram illustrating a data remapping method associated with a fourth data processing mode according to an embodiment of the present disclosure.

[0024] Figures 15 to 18 This is a diagram illustrating an example of a data processing mode using a pluggable storage device according to an embodiment of the present disclosure.

[0025] Figure 19 This is a diagram illustrating the configuration of a storage device according to an embodiment of the present disclosure.

[0026] Figure 20 This is a diagram illustrating the configuration of a storage device according to an embodiment of the present disclosure.

[0027] Figure 21 This is a diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0028] Figure 22is a diagram illustrating an example of a storage device allocation method in a computing system according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0029] Various embodiments can improve the performance of storage devices, improve the performance of used storage devices by adjusting their operation-related patterns so that they can be reused to reduce costs, and automatically allocate storage devices to match the operation characteristics of a host, thereby enabling efficient system construction.

[0030] Embodiments of the disclosure will be described in greater detail below with reference to the accompanying drawings.

[0031] Figure 1 and Figure 2 is a diagram illustrating a configuration of a pluggable storage device according to an embodiment of the disclosure.

[0032] Referring to Figure 1 , the pluggable storage device 10 can include a substrate 11, a plurality of memory sockets 12, a slot 13, and a main controller 100.

[0033] The plurality of memory sockets 12, the slot 13, and the main controller 100 can be mounted on the substrate 11.

[0034] Referring to Figure 2 , the plurality of memory sockets 12 can be equipped with a plurality of memory modules 14. The plurality of memory modules 14 can each be a dual in-line memory module (DIMM).

[0035] The slot 13 allows the pluggable storage device 10 to be indirectly or directly connected to a host.

[0036] The slot 13 and the main controller 100 can be configured to support a communication method, such as Compute Express Link (CXL).

[0037] The main controller 100 can be communicatively coupled to the plurality of memory sockets 12 and the slot 13, and can include an error correction function. The main controller 100 can perform training on the plurality of memory modules 14 to detect an error rate, and operate the plurality of memory modules 14 in at least one data processing mode among a plurality of data processing modes having different error correction capabilities, storage capacities, and bandwidths based on the error rate. The training can be performed periodically or aperiodically depending on an internal setting or an external request. Each time the training is performed, the error rate can change, and the data processing mode can also change accordingly.

[0038] The main controller 100 can set at least one data processing mode from among a plurality of different data processing modes based on the error rate of the plurality of memory modules 14, and remap input / output data according to the at least one data processing mode.

[0039] The plurality of data processing modes can include a first data processing mode, a second data processing mode, and a third data processing mode. The first data processing mode can have a higher weight of storage capacity and bandwidth relative to error correction capability. The second data processing mode can have a higher weight of error correction capability relative to storage capacity and bandwidth. The third data processing mode can be set such that the weight of error correction capability and the weight of storage capacity and bandwidth have intermediate values between the values in the first data processing mode and the second data processing mode. While three data processing modes are described, in other embodiments, more than three data processing modes with different weights of device characteristics and capabilities can be implemented.

[0040] The host controller 100 can divide the plurality of memory modules 14 into a plurality of groups according to the first data processing mode, and can assign a different channel to each of the plurality of groups. The host controller 100 can divide the plurality of memory modules 14 into a plurality of groups according to the second data processing mode, assign one channel to two different groups of the plurality of groups, use one of the two different groups for storing normal data (hereinafter referred to as data), and use the other of the two different groups for error correction. This same assignment method can be applied to the remaining groups in the second data processing mode. In the third data processing mode, the host controller 100 can divide the plurality of memory modules 14 into a plurality of groups, assign one channel to a first group and a second group of the plurality of groups, use at least one of the memory modules of the first group for correction performed on the second group, and use the remaining memory modules for storing data of the first group. At least one of the memory modules of the second group is used for error correction performed on the first group, and the remaining memory modules are used for storing data of the second group. This same assignment method can be applied to groups other than the first group and the second group.

[0041] The pluggable storage device 10 can reuse memory modules that have been used in other systems and degraded by installing them into the plurality of memory sockets 12. The pluggable storage device 10 can apply an appropriate data processing mode to the plurality of memory modules 14 based on an error rate. Specifically, if the error rate exceeds a predetermined threshold, a data processing mode with relatively enhanced error correction functionality can be applied to the memory module to prevent deterioration in operational reliability. The word "predetermined" used herein with respect to a parameter (e.g., a predetermined timing, time, or voltage level) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0042] Figure 3 FIG. 1 is a diagram illustrating a configuration of a pluggable storage device according to an embodiment of the disclosure. FIG. 2 is a diagram illustrating a configuration of a host controller according to an embodiment of the disclosure.

[0043] See Figure 3 The main controller 100 may include a first memory controller 110A, a second memory controller 110B, a host interface 120, a data remapping circuit 130, and a board management controller 140.

[0044] The first memory controller 110A can perform training on multiple memory modules coupled thereto to detect error rates, and output memory management information INF-MM including the error rates, as well as error correction codes for generating input / output data. The memory management information INF-MM may include at least one of error rate-related information, data processing mode setting-related information, storage capacity-related information, and bandwidth-related information.

[0045] The first memory controller 110A can classify multiple memory modules coupled thereto into multiple groups, and can allocate channels to multiple groups according to a first data processing mode, a second data processing mode, and a third data processing mode. The first memory controller 110A can selectively utilize multiple memory modules for data storage or error correction code storage for each of the first, second, and third data processing modes.

[0046] The first memory controller 110A may include multiple memory interface blocks PHYA1, PHYA2, error correction block ECCA, and multiple memory control blocks MCTRLA1, MCTRLA2.

[0047] Multiple memory interface blocks PHYA1 and PHYA2 can be coupled to multiple memory modules divided into multiple groups, based on each group. (See reference...) Figure 1 and Figure 2 The multiple memory interface blocks PHYA1 and PHYA2 can be coupled to multiple memory sockets 12.

[0048] The error correction block ECCA can include multiple error correction circuits ECCA1 and ECCA2. The multiple error correction circuits ECCA1 and ECCA2 can be connected one-to-one or jointly with multiple memory interface blocks PHYA1 and PHYA2 to generate error correction codes for data transmitted through multiple memory interface blocks PHYA1 and PHYA2.

[0049] For example, in the first data processing mode, multiple error correction circuits ECCA1 and ECCA2 can be connected one-to-one with multiple memory interface blocks PHYA1 and PHYA2 to generate error correction codes for data transmitted through the multiple memory interface blocks PHYA1 and PHYA2 respectively. In the second data processing mode, multiple error correction circuits ECCA1 and ECCA2 can be connected together with only one of the multiple memory interface blocks PHYA1 and PHYA2, and can generate error correction codes for data transmitted through only one of the multiple memory interface blocks PHYA1 and PHYA2.

[0050] Multiple memory control blocks MCTRLA1 and MCTRLA2 can be coupled to multiple error correction circuits ECCA1 and ECCA2, and can perform training on multiple memory modules to detect error rates and generate memory management information INF-MM including the error rates. Multiple memory control blocks MCTRLA1 and MCTRLA2 can control the data input / output of multiple memory modules and the operation of multiple error correction circuits ECCA1 and ECCA2. Multiple memory control blocks MCTRLA1 and MCTRLA2 can divide multiple memory modules into multiple groups and allocate channels to multiple groups for a first data processing mode, a second data processing mode, and a third data processing mode. Multiple memory control blocks MCTRLA1 and MCTRLA2 can selectively utilize multiple memory modules for data storage or error correction code storage for each of the first, second, and third data processing modes.

[0051] The second memory controller 110B may include multiple memory interface blocks PHYB1, PHYB2, an error correction block ECCB, and multiple memory control blocks MCTRLB1, MCTRLB2. The second memory controller 110B can be configured to perform functions similar to those of the first memory controller 110A, therefore a detailed description of its configuration will be omitted.

[0052] Figure 3 An example configuration with two memory controllers is shown, but the number of memory controllers can vary depending on the number of memory modules.

[0053] Host interface 120 can be configured to support compute fast links and can communicate with at least one host via compute fast links.

[0054] The data remapping circuit 130 can remap input / output data and error correction codes to match at least one predetermined data processing mode.

[0055] The board management controller 140 can set at least one data processing mode from a first data processing mode, a second data processing mode, and a third data processing mode based on the memory management information INF-MM. The board management controller 140 can send data DTA and memory management information INF-MM to the host via the host interface 120, and receive data DTA and memory management information INF-MM from the host. The board management controller 140 can set at least one data processing mode from the first data processing mode, the second data processing mode, and the third data processing mode based on the error rate included in the memory management information INF-MM.

[0056] Figure 4 A diagram illustrating the characteristic differences of data processing modes according to embodiments of the present disclosure. Figures 4 to 12 An example of a pluggable storage device 10 is shown, comprising 12 memory modules divided into four groups of three memory modules each, with each memory module having a capacity of 16-64 GB. However, the number of memory modules, the number of groups, the storage capacity, the bandwidth, and the error correction capability may vary depending on the design schemes of other embodiments and examples contemplated in this disclosure.

[0057] The first data processing mode (Mode 1), the second data processing mode (Mode 2), and the third data processing mode (Mode 3) of this disclosure can be determined based on the error rate. For example, the error rate can be divided into three ranges: a first range with a low error rate, a second range with a medium or intermediate error rate, and a third range with a high error rate. The first range has the lowest requirement for error correction capability, the second range has a medium requirement for error correction capability, and the third range has the highest requirement for error correction capability.

[0058] The first data processing mode (Mode 1) has a higher weighting for storage capacity and bandwidth relative to error correction capability; that is, within the total storage capacity, the storage capacity and bandwidth used for data storage are higher than the storage capacity used for error correction capability. In the first data processing mode (Mode 1), a portion of the total storage capacity of each of the multiple memory modules can be used for error correction, while the remaining storage capacity can be used for data storage.

[0059] The second data processing mode (Mode 2) has a higher weighting for error correction capabilities relative to storage capacity and bandwidth; that is, the storage capacity used for error correction is set higher compared to the first data processing mode (Mode 1). In the second data processing mode (Mode 2), multiple memory modules are divided into multiple groups, and the same channel is allocated to two different groups within the multiple groups. One group uses the same channel to store data, while the other group is used for error correction.

[0060] By altering the ratio of the weights of error correction capability to those of storage capacity and bandwidth, a third data processing mode (Mode 3) is configured with values ​​between the first data processing mode (Mode 1) and the second data processing mode (Mode 2). Specifically, the storage capacity and bandwidth used for data storage, and the storage capacity used for error correction capability, relative to the total storage capacity, have values ​​intermediate between the first and second data processing modes (Mode 1 and Mode 2). In the third data processing mode (Mode 3), multiple memory modules can be divided into multiple groups. The same channels can be allocated to the first and second groups. At least one memory module in the first group can be used for error correction of the second group, while the remaining memory modules in the first group can be used for data storage of the first group. Similarly, at least one memory module in the second group can be used for error correction of the first group, while the remaining memory modules in the second group can be used for data storage of the second group.

[0061] Therefore, when the error rate corresponds to a first range with the lowest error rate, this disclosure can be set to a first data processing mode (mode 1); when the error rate corresponds to a third range with the highest error rate, this disclosure can be set to a second data processing mode (mode 2); and when the error rate corresponds to a second range with a medium error rate, this disclosure can be set to a third data processing mode (mode 3).

[0062] For example, see Figure 4 In the first data processing mode (Mode 1), the memory module can be controlled according to four channels 4CH and six memory selection signals 6CS:CS<5:0>. The storage capacity DST for storing data can be 192-768GB, the bandwidth BW can be 51.2GB / s, and the error correction circuit ECC can correct 5.6% of the storage capacity errors, meaning that the pluggable storage device 10 has the highest performance in terms of storage capacity DST and bandwidth BW.

[0063] In the second data processing mode (Mode 2), the memory module can be controlled according to two channels 2CH and six memory selection signals 6CS:CS<5:0>. The storage capacity DST used to store data can be 96-384GB, the bandwidth BW can be 25.6GB / s, and the error correction circuit ECC can correct 27.8% of the errors in the storage capacity, meaning that the pluggable storage device 10 has the highest performance in error correction.

[0064] In the third data processing mode (mode 3), the memory module can be controlled according to two channels 2CH and eight memory selection signals 8CS:CS<7:0>. The storage capacity DST for storing data can be 128-512GB, the bandwidth BW can be 38.4GB / s, and the error correction circuit ECC can correct 20.4% of the errors in the storage capacity, that is, the pluggable storage device 10 has the performance of a trade-off between storage capacity DST and bandwidth BW and error correction performance.

[0065] Figure 5 This is a diagram illustrating the configuration of a pluggable storage device operating in a first data processing mode according to an embodiment of the present disclosure. Figure 6 This is a diagram illustrating a data remapping method based on a first data processing mode.

[0066] The following is for reference. Figure 5 and Figure 6 , will describe Figure 1 and Figure 2 The configuration of the pluggable storage device 10 and the data remapping method according to the first data processing mode.

[0067] See Figure 5 Multiple memory modules 14 (see Figure 2 The memory modules can be divided into four groups: Group 14A to Group 14D. Each group can include multiple memory modules, such as three memory modules. Group 14A can include memory modules 14A1-14A3, Group 14B can include memory modules 14B1-14B3, Group 14C can include memory modules 14C1-14C3, and Group 14D can include memory modules 14D1-14D3. In the following description, for ease of description, modules 14A1-14A3, 14B1-14B3, 14C1-14C3, and 14D1-14D3 will be referred to as the first to twelfth memory modules. Each memory module can include multiple memory chips, for example, 18 memory chips per memory module. The number of memory chips included in each memory module is not limited and can vary depending on the type and capacity of the memory module.

[0068] The first group 14A can be coupled to the main controller via the first channel CH0; the second group 14B can be coupled to the main controller via the third channel CH2; the third group 14C can be coupled to the main controller via the second channel CH1; and the fourth group 14D can be coupled to the main controller via the fourth channel CH3. The main controller can be referenced above. Figure 3 The main controller 100.

[0069] The first group 14A to the fourth group 14D can be selectively controlled by the first to sixth memory selection signals CS<5:0>, respectively. For example, the first memory module 14A1 can have a front memory chip and a rear memory chip selectively controlled by the first and second memory selection signals CS0 / 1, the second memory module 14A2 can have a front memory chip and a rear memory chip selectively controlled by the third and fourth memory selection signals CS2 / 3, and the third memory module 14A3 can have a front memory chip and a rear memory chip selectively controlled by the fifth and sixth memory selection signals CS4 / 5. The second group 14B to the fourth group 14D can also be selectively controlled by the first to sixth memory selection signals CS<5:0> in a similar manner to the first group 14A.

[0070] See Figure 6 The data remapping circuit 130 of the pluggable storage device 10 can perform a remapping of data output from the first group 14A to the fourth group 14D with data provided by the host to be written to the first group 14A to the fourth group 14D, according to a first data processing mode (mode 1). In the first data processing mode (mode 1), 64 symbols S0-S63 can be used as data symbols, and 8 symbols S64-S71 can be used as error correction code (ECC) symbols, thus enabling remapping using a total of 72 symbols S0-S71. For example, reference symbols S0-S3, each symbol can be input and output through I / O pads DQ0-DQ3 in 8-burst length BL mode. The remaining symbols can be input and output through I / O pads in a similar manner. Therefore, the storage capacity and bandwidth of the pluggable storage device 10 can be maximized.

[0071] Figure 7 This is a diagram illustrating the configuration of a pluggable storage device operating in a second data processing mode according to an embodiment of the present disclosure. Figure 8 This is a diagram illustrating a data remapping method based on a second data processing mode.

[0072] The following will refer to Figure 7 and Figure 8 To describe the above reference Figure 1 and Figure 2 The configuration of the pluggable storage device 10 and the data remapping method according to the second data processing mode.

[0073] See Figure 7 In the second data processing mode (Mode 2), the memory modules of the first group 14A and the second group 14B can be coupled to the main controller via the first channel CH0, while the memory modules of the third group 14C and the fourth group 14D can be coupled to the main controller via the second channel CH1. The main controller can be as described above. Figure 3The main controller 100. The first group 14A to the fourth group 14D can all be selectively controlled via the first to sixth memory selection signals CS<5:0>. In the second data processing mode (mode 2), the first group 14A to the fourth group 14D are selectively controlled via the first to sixth memory selection signals CS<5:0> in the same manner as described above. Figure 5 The first data processing mode (mode 1) is similar, so a detailed description will be omitted here.

[0074] The first group 14A can be used for data storage, while the second group 14B can be used for error correction of the first group 14A. In some embodiments, the first group 14A is used only for data storage, while the second group 14B is used only for error correction of the first group 14A. The first group 14A and the second group 14B can be used for data storage and error correction in a one-to-one correspondence between memory modules receiving the same sequence of memory select signals. That is, the first memory module 14A1 receiving the memory select signal CS0 / 1 can be used for data storage, while the fourth memory module 14B1 receiving the memory select signal CS0 / 1 can be used for error correction of the first memory module 14A1. The second memory module 14A2 receiving the memory select signal CS2 / 3 can be used for data storage, while the fifth memory module 14B2 receiving the memory select signal CS2 / 3 can be used for error correction of the second memory module 14A2. The third memory module 14A3 receiving the memory select signal CS4 / 5 can be used for data storage, while the sixth memory module 14B3 receiving the memory select signal CS4 / 5 can be used for error correction of the third memory module 14A3.

[0075] The third group 14C can be used for data storage, while the fourth group 14D can be used for error correction of the third group 14C. The usage method is similar to that of the first group 14A and the second group 14B mentioned above, so a detailed description will be omitted here.

[0076] See Figure 8 The data remapping circuit 130 of the pluggable storage device 10 can perform a remapping of the data output from the first group 14A to the fourth group 14D with the data provided by the host to be written to the first group 14A to the fourth group 14D, according to a second data processing mode (mode 2). For example, in the second data processing mode (mode 2) using the first group 14A and the second group 14B, 64 symbols S0-S63 can be used as data symbols, and 80 symbols S64-S143 can be used as error correction code (ECC) symbols, thus remapping can be achieved using a total of 144 symbols S0-S143. Therefore, the error correction capability of the pluggable storage device 10 can be maximized.

[0077] Figure 9This is a diagram illustrating the configuration of a pluggable storage device operating in a third data processing mode according to an embodiment of the present disclosure. Figure 10 This is a diagram illustrating a data remapping method based on a third data processing mode.

[0078] The following will refer to Figure 9 and Figure 10 To describe the above reference Figure 1 and Figure 2 The configuration of the pluggable storage device 10 and the data remapping method according to the third data processing mode.

[0079] See Figure 9 In the third data processing mode (Mode 3), the first group 14A and the second group 14B can be coupled to the main controller via the first channel CH0, while the third group 14C and the fourth group 14D can be coupled to the main controller via the second channel CH1. The main controller can be as described above. Figure 3 The main controller 100. The first group 14A to the fourth group 14D can be selectively controlled via the first to eighth memory selection signals CS<7:0>. The first memory module 14A1 can be controlled via the first and second memory selection signals CS0 / 1, the second memory module 14A2 can be controlled via the third and fourth memory selection signals CS2 / 3, and the third memory module 14A3 can be controlled via the fifth to eighth memory selection signals CS4 / 5 / 6 / 7. The fourth memory module 14B1 can be controlled via the fifth and sixth memory selection signals CS4 / 5, the fifth memory module 14B2 can be controlled via the seventh and eighth memory selection signals CS6 / 7, and the sixth memory module 14B3 can be controlled via the first to fourth memory selection signals CS0 / 1 / 2 / 3. The third group 14C can be selectively controlled via the first to eighth memory selection signals CS<7:0> in a manner similar to the first group 14A, and the fourth group 14D can be selectively controlled via the first to eighth memory selection signals CS<7:0> in a manner similar to the second group 14B.

[0080] One memory module in the first group 14A can be used for error correction in the second group 14B, while the remaining memory modules can be used for data storage in the first group 14A. That is, the first memory module 14A1 and the second memory module 14A2 in the first group 14A can be used for data storage, while the third memory module 14A3 can be used for error correction in the fourth memory module 14B1 and the fifth memory module 14B2 in the second group 14B.

[0081] One memory module in the second group 14B can be used for error correction in the first group 14A, while the remaining memory modules can be used for data storage in the second group 14B. Specifically, the fourth memory module 14B1 and the fifth memory module 14B2 in the second group 14B can be used for data storage, while the sixth memory module 14B3 can be used for error correction in the first memory module 14A1 and the second memory module 14A2 in the first group 14A.

[0082] One memory module from the third group 14C can be used for error correction in the fourth group 14D, while the remaining memory modules can be used for data storage in the third group 14C. Similarly, one memory module from the fourth group 14D can be used for error correction in the third group 14C, while the remaining memory modules can be used for data storage in the fourth group 14D. Since the use of the memory modules in the third group 14C and the fourth group 14D is similar to that of the first group 14A and the second group 14B described above, a detailed description is omitted here.

[0083] See Figure 10 The data remapping circuit 130 of the pluggable storage device 10 can perform a remapping of the data output from the first group 14A to the fourth group 14D with the data provided by the host to be written to the first group 14A to the fourth group 14D, according to the third data processing mode (mode 3). In the third data processing mode (mode 3), 64 symbols S0-S63 can be used as data symbols, and 44 symbols S64-S107 can be used as error correction code (ECC) symbols, so that a total of 108 symbols S0-S107 can be used for remapping. Therefore, when compared with the second data processing mode, the error correction capability of the pluggable storage device 10 can be balanced for storage capacity and bandwidth.

[0084] Figure 11 and Figure 12 This is a diagram illustrating the detailed operation of a data remapping method under a third data processing mode according to an embodiment of the present disclosure.

[0085] For reference Figure 9 and Figure 10 In the third data processing mode (mode 3) of this disclosure, one memory module is allocated for error correction of two memory modules used for data storage. Therefore, data writing / reading is performed according to the burst segmentation processing mode, i.e., burst truncation 4 (BC4) mode, instead of the reference mode. Figure 6 The aforementioned burst length 8 mode. In the third data processing mode (mode 3), remapping is performed by entering BC4 mode, and then using address signals (e.g., A2) to split the 8 bits of data per memory module into the first 4 bits and the last 4 bits for processing according to BC4 mode.

[0086] First, see Figure 11 When the address signal A2 is '0', during a write operation, the data corresponding to the serial numbers 0-3 of the data input / output pads DQ is stored in the memory cell area corresponding to the burst length serial numbers 0-3 in the memory module. During a read operation, the data output from the memory cell area of ​​the burst length serial numbers 0-3 is output to the data input / output pads DQ of serial numbers 0-3.

[0087] When the address signal A2 is '0', according to the memory selection signal CS0, data output from the memory chip on the front side of one of the two memory modules used for data storage in the first group of three memory modules coupled to the second channel CH1 is stored in the memory cell region corresponding to the burst length 0-3 of the memory chip on the front side of the memory module, and used for error correction by the modules in the second group coupled to the second channel CH1. And according to the memory selection signal CS1 (not shown), data output from the memory chip on the back side of one of the two memory modules used for data storage in the first group of three memory modules coupled to the second channel CH1 is stored in the memory cell region corresponding to the burst length 0-3 of the memory chip on the back side of the memory module, and used for error correction by the modules in the second group coupled to the second channel CH1. Furthermore, data output corresponding to burst lengths 4-7 is blocked, i.e., terminated. As described above, the main controller can use a total of 108 symbols S0-S107 to remap the data in the memory modules.

[0088] Next, see Figure 12 When the address signal A2 is '1', according to the memory selection signal CS2, data output from the memory chip on the front side of the other memory module (one of the two memory modules used for data storage in the first group coupled to the second channel CH1) is stored in the memory cell region corresponding to the burst length 4-7 of the memory chip on the front side of the memory module, and used for error correction by the modules in the second group coupled to the second channel CH1. Then, according to the memory selection signal CS3 (not shown), data output from the memory chip on the back side of the other memory module (one of the two memory modules used for data storage in the first group coupled to the second channel CH1) is stored in the memory cell region corresponding to the burst length 4-7 of the memory chip on the back side of the memory module, and used for error correction by the modules in the second group coupled to the second channel CH1. Furthermore, data output corresponding to burst length 0-3 is blocked, i.e., terminated. As described above, the main controller can use a total of 108 symbols S0-S107 to remap the data in the memory modules.

[0089] Figure 13 This is a diagram illustrating the configuration of a main controller according to an embodiment of the present disclosure.

[0090] The main controller 200 can support a first data processing mode, a second data processing mode, and a third data processing mode, and can also support a fourth data processing mode. The fourth data processing mode has increased storage capacity for error correction functions by compressing data according to each of the first, second, and third data processing modes.

[0091] See Figure 13 The main controller 200 may include a first memory controller 210A, a second memory controller 210B, a host interface 220, a data remapping circuit 230, a board management controller 240, and a data compression circuit 250.

[0092] The first memory controller 210A can perform training on multiple memory modules coupled to itself to detect error rates, output memory management information INF-MM including the error rates, and generate error correction codes for input / output data. The memory management information INF-MM may include at least one of error rate, data processing mode, storage capacity, and bandwidth.

[0093] The first memory controller 210A can classify multiple memory modules coupled to itself into multiple groups, and can allocate channels to multiple groups for a first data processing mode, a second data processing mode, a third data processing mode, and a fourth data processing mode. The first memory controller 210A can selectively utilize multiple memory modules for data storage or error correction code storage for the first data processing mode, the second data processing mode, the third data processing mode, and the fourth data processing mode.

[0094] The second memory controller 210B can be configured to perform functions similar to those performed by the first memory controller 210A, therefore a detailed configuration description will be omitted here.

[0095] Figure 13 An example configuration with two memory controllers is shown, but the number of memory controllers can vary depending on the number of memory modules.

[0096] Host interface 220 can be configured to support compute fast links and can communicate with at least one host via compute fast links.

[0097] The first memory controller 210A, the second memory controller 210B, and the host interface 220 can be referenced as above. Figure 3The first memory controller 110A, the second memory controller 110B, and the host interface 120 are configured in a similar manner, so detailed descriptions will be omitted here.

[0098] The data remapping circuit 230 can remap input / output data and error correction codes to match at least one predetermined data processing pattern.

[0099] The data compression circuit 250 can compress the data provided by the data remapping circuit 230 to generate compressed data, and can provide the compressed data to the data remapping circuit 230.

[0100] The board management controller 240 can set at least one data processing mode from a first data processing mode, a second data processing mode, a third data processing mode, and a fourth data processing mode based on the memory management information INF-MM. The board management controller 240 can send data DTA and memory management information INF-MM to the host via the host interface 220, and receive data DTA and memory management information INF-MM from the host. The board management controller 240 can set at least one data processing mode from the first data processing mode, the second data processing mode, and the third data processing mode based on the error rate included in the memory management information INF-MM. The board management controller 240 can set a fourth data processing mode based on internal settings or external requests using the memory management information INF-MM.

[0101] Figure 14 This is a diagram illustrating a data remapping method associated with a fourth data processing mode according to an embodiment of the present disclosure.

[0102] The fourth data processing mode is a mode for compressing data based on each of the first, second, and third data processing modes. It can be implemented simultaneously as an additional option within the operation methods of the first, second, and third data processing modes.

[0103] See Figure 14 When the first data processing mode is set and the fourth data processing mode is requested, data remapping can be performed using compressed data generated by compressing data according to the first data processing mode.

[0104] When a fourth data processing mode is added to the first data processing mode, the number of data symbols can be reduced to 56 (e.g., S0-S55) compared to the first data processing mode, while the number of error correction code symbols can be increased to 16 (e.g., S56-S71), while the total number of symbols remains 72 (e.g., S0-S71), the same as in the first data processing mode. Therefore, the number of error correction code symbols can be increased, and the error correction capability is improved.

[0105] Figures 15 to 18 This is a diagram illustrating an example of a data processing mode using a pluggable storage device according to an embodiment of the present disclosure.

[0106] See Figure 15 The main controller controls groups one through four (see...). Figure 5 The memory module included in the training performs the training. As a result, when the error rates of the first to fourth groups are within the first range, increasing storage capacity and bandwidth is crucial. Therefore, the main controller can set a first data processing mode (mode 1) for the first to fourth groups. The main controller can be as described above. Figure 3 The main controller 100 described above or as referenced above Figure 13 One of the main controllers 200 described.

[0107] See Figure 16 The main controller can perform training on the memory modules included in the first to fourth groups. If the error rates of the first and second groups are within the first range, while the error rates of the third and fourth groups are within the third range, it is beneficial to increase the storage capacity and bandwidth of the first and second groups, and to improve operational reliability by enhancing the error correction capabilities of the third and fourth groups. Therefore, the main controller can set a first data processing mode (mode 1) for the first and second groups and allocate different channels CH0 and CH2 to them, and set a second data processing mode (mode 2) for the third and fourth groups and allocate the same channel CH1 to them. The main controller can be a reference... Figure 3 The main controller 100 or reference described Figure 13 One of the main controllers 200 described.

[0108] See Figure 17 The main controller can perform training on the memory modules included in the first through fourth groups. If the error rates of the first and second groups are within the third range, but the error rates of the third and fourth groups are within the second range, it is advantageous to improve operational reliability by enhancing the error correction capabilities of the first and second groups. Furthermore, it is desirable to strike a trade-off between error correction capabilities and storage capacity and bandwidth for the third and fourth groups. Therefore, the main controller can set a second data processing mode (mode 2) for the first and second groups and allocate the same channel CH0, and set a third data processing mode (mode 3) for the third and fourth groups and allocate the same channel CH1. The main controller can be a reference... Figure 3 The main controller 100 described or referenced Figure 13 One of the main controllers 200 described.

[0109] See Figure 18The main controller can set a fourth data processing mode (mode 4) for the first to fourth groups based on internal settings or external requests. In this case, the fourth data processing mode (mode 4) operates in parallel with one of the first data processing modes (mode 1), the second data processing mode (mode 2), and the third data processing mode (mode 3). Figure 18 An example of parallel operation of the fourth data processing mode (Mode 4) and the first data processing mode (Mode 1) is shown. The main controller can be a reference... Figure 13 The main controller 200 is described.

[0110] The main controller can perform training on the memory modules included in the first through fourth groups. If the detected error rates of the first through fourth groups fall within a first range, the main controller can apply the data remapping method according to the first data processing mode (mode 1) to the first through fourth groups and allocate different channels CH0-CH3. In this state, when a request for the fourth data processing mode (mode 4) occurs, the main controller can set the fourth data processing mode (mode 4), in which the data processed according to the first data processing mode (mode 1) is compressed to improve error correction capability.

[0111] Figure 19 This is a diagram illustrating the configuration of a storage device according to an embodiment of the present disclosure.

[0112] See Figure 19 Storage device 300A may include multiple pluggable storage devices PMD 310A-1 to 310A-n and a communication path manager 320A. Storage device 300A can perform internal and external communication via compute-fast links.

[0113] Multiple pluggable storage devices 310A-1 to 310A-n can be similar to those described above. Figures 1 to 18 The described pluggable storage device 10 is configured to be used.

[0114] Multiple pluggable storage devices 310A-1 to 310A-n can each perform training on the memory module coupled to them to detect the error rate. Based on the detected error rate, one or more of a first data processing mode, a second data processing mode, a third data processing mode, and a fourth data processing mode can be set to perform a data remapping operation.

[0115] Multiple pluggable storage devices 310A-1 to 310A-n can receive and output memory management information INF-MM and data DTA. The memory management information INF-MM may include at least one of error rate-related information, data processing mode setting-related information, storage capacity-related information, and bandwidth-related information. The data processing mode setting-related information may also include a fourth data processing mode request. The memory management information INF-MM may also include external device information. External device information is information provided to the storage device 300A by an external device (i.e., the host), and may include storage capacity, bandwidth, and latency information required by the host.

[0116] The communication path manager 320A can selectively couple multiple pluggable storage devices 310A-1 to 310A-n to at least one host based on memory management information INF-MM. The communication path manager 320A may include a fabric manager or a compute fast link switch.

[0117] The communication path manager 320A can store the storage capacity and bandwidth of multiple pluggable storage devices 310A-1 to 310A-n, as well as the storage capacity and bandwidth required by each host, according to the memory management information INF-MM. The communication path manager 320A can selectively connect to at least one pluggable storage device, which is configured with a data processing mode corresponding to at least one host, according to the memory management information INF-MM.

[0118] Figure 20 This is a diagram illustrating the configuration of a storage device according to an embodiment of the present disclosure.

[0119] See Figure 20 The storage device 300B may include multiple pluggable storage devices PMD 310B-1 to 310B-n, a communication path manager 320B, and a board management controller 330. The storage device 300B can perform internal and external communication via compute-fast links.

[0120] As per the above reference Figures 1 to 18 The described pluggable storage device 10 is an example of a configuration including a board management controller. According to... Figure 20 The multiple pluggable storage devices 310B-1 to 310B-n are shown as sharing a single board management controller 330, rather than each having an embedded board management controller.

[0121] Except for the absence of a board management controller, multiple pluggable storage devices 310B-1 to 310B-n can also be configured as described above. Figures 1 to 18 The described pluggable storage device 10.

[0122] Multiple pluggable storage devices 310B-1 to 310B-n can each perform training on the memory modules coupled to them to detect error rates and output memory management information INF-MM including the detected error rates. Each of the multiple pluggable storage devices 310B-1 to 310B-n can remap data DTA according to the set data processing mode.

[0123] The communication path manager 320B can selectively couple multiple pluggable storage devices 310B-1 to 310B-n to at least one host based on memory management information INF-MM. The communication path manager 320B may include a structure manager or a compute fast link switch. The memory management information INF-MM may include at least one of error rate-related information, data processing mode setting-related information, storage capacity-related information, and bandwidth-related information. The memory management information INF-MM may also include external device information.

[0124] Based on the memory management information INF-MM, the communication path manager 320B can know the storage capacity and bandwidth of multiple pluggable storage devices 310B-1 to 310B-n, as well as the storage capacity and bandwidth required by each host. The communication path manager 320B can selectively connect to at least one pluggable storage device corresponding to at least one host, based on the memory management information INF-MM.

[0125] The board management controller 330 can set the data processing mode of each of the plurality of pluggable storage devices 310B-1 to 310B-n to at least one or more of a first data processing mode, a second data processing mode, a third data processing mode, and a fourth data processing mode based on memory management information INF-MM provided by each of the plurality of pluggable storage devices 310B-1 to 310B-n. The board management controller 330 can send the memory management information INF-MM to the host and receive the memory management information INF-MM from the host through the communication path manager 320B.

[0126] Figure 21 This is a diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Figure 22 This is a diagram illustrating an example of a storage device allocation method in a computing system according to an embodiment of the present disclosure.

[0127] Below, for reference Figure 21 and Figure 22 The following describes a method for configuring and allocating storage devices in a computing system 400 according to embodiments of the present disclosure.

[0128] See Figure 21The computing system 400 may include a storage device 500 and multiple hosts HTS1-HTSn.

[0129] Storage device 500 can be compared with the above reference. Figure 19 The storage device described is 300A or as referenced above. Figure 20 The storage device 300B described is similarly configured, and its configuration will not be repeated here.

[0130] Multiple hosts HTS1-HTSn can provide storage management information to storage device 500, and in response, storage device 500 stores storage capacity, bandwidth and latency information suitable for multiple hosts.

[0131] As described above, storage device 500 can set at least one data processing mode or one or more data processing modes based on the error rate of each of the plurality of pluggable storage devices, and can store storage capacity and bandwidth according to the set data processing mode and the storage capacity, bandwidth and latency information required by the host. Therefore, storage device 500 can allocate at least one pluggable storage device to each of the plurality of hosts HTS1-HTSn to realize data communication.

[0132] Figure 22 An example is shown of assigning and connecting a first pluggable storage device PWD1 and a second pluggable storage device PWD2 to a first host HST1 and a second host HST2 among a plurality of hosts HTS1-HTSn.

[0133] See Figure 22 Assume that the first pluggable storage device PWD 1 has a first data processing mode (mode 1) configured for all memory modules, the second pluggable storage device PWD 2 has a first data processing mode (mode 1) configured for memory modules corresponding to the first and second groups, and a second data processing mode (mode 2) configured for memory modules corresponding to the third and fourth groups. It is also assumed that the first host HST1 is a host suitable for high-capacity and high-bandwidth memory types, while the second host HST2 is a host suitable for relatively low-capacity and low-bandwidth memory types.

[0134] Based on the stored memory management information, the communication path manager of storage device 500 can assign all memory modules of the first pluggable storage device PWD1, as well as the memory modules corresponding to the first and second groups of the second pluggable storage device PWD2, to the first host HST1 and connect them to the first host HST1; and assign the memory modules corresponding to the third and fourth groups of the second pluggable storage device PWD2 to the second host HST2 and connect them to the second host HST2. In other words, storage device 500 can assign one pluggable storage device to multiple hosts, or assign multiple pluggable storage devices to a single host, based on memory management information including external device information, by assigning memory modules of different groups to different hosts.

[0135] although Figure 22 Although not directly shown, the first pluggable storage device PWD1 can be assigned to and connected to the first host HST1 in a one-to-one relationship, and the second pluggable storage device PWD2 can be assigned to and connected to the second host HST2.

[0136] In another example, if any one of the multiple hosts HTS1-HTSn performs a latency-insensitive role, the storage device 500 can be requested to use memory management information to implement a fourth data processing mode.

[0137] In response to the setting of the fourth data processing mode, the storage device 500 may set some or all of the memory modules of at least one of a plurality of pluggable storage devices to the fourth data processing mode, and may assign the corresponding pluggable storage device to the host that requests the setting of the fourth data processing mode and connect to the host.

[0138] Furthermore, even if multiple hosts HTS1-HTSn do not request the setting of the fourth data processing mode, the storage device 500 itself can determine the host's operation type based on the latency information included in the memory management information and set at least one of the multiple pluggable storage devices to the fourth data processing mode.

[0139] By assigning at least one of the multiple pluggable storage devices to the multiple hosts HTS1-HTSn as described above, this disclosure can improve performance by enabling the computing system 400 to operate in an optimal operating environment.

[0140] The concept has been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions can be made without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to the description provided. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A pluggable storage device, comprising: Multiple memory sockets; A slot for connecting to external devices; as well as The main controller, communicatively coupled to the plurality of memory sockets and the slots, and having error correction capabilities, The main controller: sets at least one data processing mode from multiple data processing modes based on the error rate of multiple memory modules installed in the multiple memory sockets, and remaps input / output data according to the at least one data processing mode.

2. The pluggable storage device according to claim 1, wherein, The plurality of memory modules include DIMMs, where DIMM stands for Dual In-line Memory Module.

3. The pluggable storage device according to claim 1, wherein, The main controller supports fast link CXL, where CXL stands for compute fast link.

4. The pluggable storage device according to claim 1, wherein, The main controller detects the error rate by performing training on the plurality of memory modules.

5. The pluggable storage device according to claim 1, wherein, In the multiple data processing modes, the memory capacity, bandwidth, and error correction capability of the error correction function are set differently.

6. The pluggable storage device according to claim 5, wherein, The plurality of data processing modes include a first data processing mode and a second data processing mode, wherein the first data processing mode has the memory capacity and the bandwidth having a higher weight relative to the error correction capability, and the second data processing mode has the error correction capability having a higher weight relative to the memory capacity and the bandwidth.

7. The pluggable storage device according to claim 6, wherein, The plurality of data processing modes further includes a third data processing mode in which the weights of the error correction capability, the storage capacity, and the bandwidth are set to an intermediate value between the first data processing mode and the second data processing mode. The plurality of data processing modes further includes a fourth data processing mode in which the weights of the error correction capability are increased by compressing data according to each of the first, second, and third data processing modes.

8. The pluggable storage device according to claim 6, wherein, The main controller: divides the plurality of memory modules into multiple groups according to the first data processing mode; and assigns different channels to each of the multiple groups.

9. The pluggable storage device according to claim 6, wherein, The main controller: The plurality of memory modules are divided into multiple groups according to the second data processing mode; The same channel is assigned to two different groups among the plurality of groups; as well as One of the two different groups is used for data storage, while the other group is used for error correction.

10. The pluggable storage device according to claim 7, wherein, The main controller: The plurality of memory modules are divided into multiple groups according to the third data processing mode; Assign the same channel to the first and second groups of the plurality of groups; At least one memory module from the first group is used for error correction in the second group, while the remaining memory modules are used for data storage in the first group. as well as At least one memory module from the second group is used for error correction in the first group, while the remaining memory modules are used for data storage in the second group.

11. The pluggable storage device according to claim 7, wherein, The main controller: when the fourth data processing mode is selected in response to an external request, compresses data according to the currently set data processing mode from the first data processing mode, the second data processing mode, and the third data processing mode.

12. A pluggable storage device, comprising: Multiple memory modules are installed in multiple memory sockets; A slot for connecting to external devices; as well as The main controller is communicatively coupled to the plurality of memory sockets and the slots, and has error correction capabilities. The main controller includes: At least one memory controller, which: performs training on the plurality of memory modules to detect an error rate; outputs memory management information including the error rate; and generates error correction codes for input / output data; A host interface, which is communicatively coupled to at least one host via the slot; A data remapping circuit, comprising: remapping the input / output data and the error correction code according to at least one predetermined data processing mode; and A board management controller, which: sets at least one data processing mode for the plurality of memory modules from a plurality of data processing modes based on the memory management information; and sends the memory management information to the host interface and receives the memory management information from the host interface.

13. The pluggable storage device according to claim 12, wherein, The multiple data processing modes include: The first data processing mode has storage capacity and bandwidth that have a higher weighting than the error correction capability of the error correction function; A second data processing mode, which has the error correction capability with a higher weight relative to the storage capacity and the bandwidth; and In the third data processing mode, the weights of the error correction capability, storage capacity, and bandwidth are set to intermediate values ​​between the corresponding values ​​in the first and second data processing modes.

14. The pluggable storage device of claim 12 further includes a data compression circuit that compresses the input / output data to generate compressed data.

15. The pluggable storage device according to claim 14, wherein, The multiple data processing modes include: The first data processing mode has storage capacity and bandwidth that have a higher weighting than the error correction capability of the error correction function; The second data processing mode has the error correction capability with a higher weight relative to the storage capacity and the bandwidth; A third data processing mode, in which the weights of the error correction capability, storage capacity, and bandwidth are set to values ​​between those of the first and second data processing modes; and A fourth data processing mode, in which the storage capacity for the error correction function is increased by compressing data according to each of the first, second and third data processing modes.

16. The pluggable storage device according to claim 12, wherein, The main controller supports fast computation links.

17. The pluggable storage device according to claim 15, wherein, The main controller: divides the plurality of memory modules into multiple groups according to the first data processing mode; and assigns different channels to each of the multiple groups.

18. The pluggable storage device according to claim 15, wherein, The main controller: The plurality of memory modules are divided into multiple groups according to the second data processing mode; The same channel is assigned to two different groups among the plurality of groups; as well as One of the two different groups is used for data storage, while the other is used for error correction.

19. The pluggable storage device according to claim 15, wherein, The main controller: The plurality of memory modules are divided into multiple groups according to the third data processing mode; Assign the same channel to the first and second groups of the plurality of groups; At least one memory module from the first group is used for error correction in the second group, while the remaining memory modules are used for data storage in the first group. as well as At least one memory module from the second group is used for error correction in the first group, while the remaining memory modules are used for data storage in the second group.

20. The pluggable storage device according to claim 15, wherein, The main controller: when the fourth data processing mode is selected in response to an external request, compresses data according to the currently set data processing mode from the first data processing mode, the second data processing mode, and the third data processing mode.

21. The pluggable storage device according to claim 12, wherein, The at least one memory controller includes: Multiple memory interface blocks, each coupled to the multiple memory modules divided into multiple groups based on a group; Multiple error correction circuits, which: are coupled to the multiple memory interface blocks; and generate error correction codes for data transmitted through the multiple memory interface blocks; and Multiple memory control blocks coupled to the multiple error correction circuits; training the multiple memory modules to detect the error rate; and generating memory management information including the error rate.

22. The pluggable storage device according to claim 13, wherein, The at least one memory controller includes: Multiple memory interface blocks, each coupled to the multiple memory modules divided into multiple groups based on a group; Multiple error correction circuits, wherein: in a first data processing mode, they are connected one-to-one with the multiple memory interface blocks, generating error correction codes for data transmitted through each of the multiple memory interface blocks; and in a second data processing mode, they are connected to one of the multiple memory interface blocks, generating error correction codes for data transmitted through said one memory interface block; and Multiple memory control blocks coupled to the multiple error correction circuits; training the multiple memory modules to detect the error rate; and generating memory management information including the error rate.

23. The pluggable storage device according to claim 12, wherein, The host interface: Based on the memory management information, changes the number of signal lines to be used according to the currently set data processing mode.

24. A storage device, comprising: Multiple pluggable storage devices, wherein: training multiple memory modules to detect an error rate; setting at least one data processing mode from multiple data processing modes based on the error rate to perform a data remapping operation including error correction; and outputting memory management information including the error rate and the set data processing mode; and A communication path manager that selectively couples at least one of the plurality of pluggable storage devices to at least one external device based on the memory management information.

25. The storage device according to claim 24, wherein, The multiple data processing modes include: The first data processing mode has storage capacity and bandwidth that are given a higher weight than the error correction capability of the error correction. A second data processing mode, which has the error correction capability with a higher weight relative to the storage capacity and the bandwidth; and In the third data processing mode, the weights of the error correction capability, storage capacity, and bandwidth are set to values ​​that are intermediate between the first and second data processing modes.

26. The memory device of claim 25, wherein, The plurality of pluggable storage devices: divide the plurality of memory modules into a plurality of groups according to the first data processing mode; and assign a different channel to each of the plurality of groups.

27. The storage device according to claim 25, wherein, The plurality of pluggable storage devices: The plurality of memory modules are divided into multiple groups according to the second data processing mode; The same channel is assigned to two different groups among the plurality of groups; as well as One of the two different groups is used for data storage, while the other group is used for error correction.

28. The storage device according to claim 25, wherein, The plurality of pluggable storage devices: The plurality of memory modules are divided into multiple groups according to the third data processing mode; Assign the same channel to the first and second groups of the plurality of groups; At least one memory module of the first group is used for error correction of the second group, while the remaining memory modules of the first group are used for data storage of the first group. as well as At least one memory module of the second group is used for the error correction of the first group, while the remaining memory modules of the second group are used for data storage of the second group.

29. The storage device according to claim 25, wherein, The plurality of data processing modes further includes a fourth data processing mode in which the storage capacity for error correction is increased by compressing data according to each of the first, second and third data processing modes.

30. The storage device according to claim 29, wherein, The plurality of pluggable storage devices: when the fourth data processing mode is selected, compress data according to the data processing mode currently set from the first data processing mode, the second data processing mode, and the third data processing mode.

31. The storage device according to claim 24, wherein, The communication path manager includes a structure manager or a compute fast link switch.

32. A computing system, comprising: Multiple hosts, which: output external device information, the external device information including the storage capacity and bandwidth of the multiple hosts; and A storage device comprising a plurality of pluggable storage devices, the storage device: performing a data remapping operation including error correction by setting at least one data processing mode from a plurality of data processing modes based on the error rate of each of the plurality of pluggable storage devices; and allocating at least one of the plurality of pluggable storage devices to each of the plurality of hosts based on the external device information.

33. The computing system according to claim 32, wherein, The multiple data processing modes include: The first data processing mode has storage capacity and bandwidth that are given a higher weight than the error correction capability of the error correction. A second data processing mode, which has the error correction capability with a higher weight relative to the storage capacity and the bandwidth; and In the third data processing mode, the weights of the error correction capability, storage capacity, and bandwidth are set to values ​​that are intermediate between the first and second data processing modes.

34. The computing system according to claim 33, wherein, The plurality of pluggable storage devices: divide the plurality of memory modules into a plurality of groups according to the first data processing mode; and assign a different channel to each of the plurality of groups.

35. The computing system according to claim 33, wherein, The plurality of pluggable storage devices: The installed memory modules are divided into multiple groups according to the second data processing mode; The same channel is assigned to two different groups among the plurality of groups; as well as One of the two different groups is used for data storage, while the other group is used for error correction.

36. The computing system according to claim 33, wherein, The plurality of pluggable storage devices: The installed memory modules are divided into multiple groups according to the third data processing mode; Assign the same channel to the first and second groups of the plurality of groups; At least one memory module from the first group is used for the error correction of the second group, while the remaining memory modules from the first group are used for data storage of the first group. as well as At least one memory module from the second group is used for the error correction of the first group, while the remaining memory modules of the second group are used for data storage of the second group.

37. The computing system according to claim 33, wherein, The plurality of data processing modes further includes a fourth data processing mode in which the storage capacity for error correction is increased by compressing data according to each of the first, second and third data processing modes.

38. The computing system according to claim 37, wherein, The plurality of pluggable storage devices: when the fourth data processing mode is selected, compress data according to the data processing mode currently set from the first data processing mode, the second data processing mode, and the third data processing mode.

39. The computing system according to claim 32, wherein, The storage device: Based on the external device information, two of the plurality of pluggable storage devices are assigned to one of the plurality of hosts.

40. The computing system according to claim 32, wherein, The storage device: Based on the external device information, one of the plurality of pluggable storage devices is assigned to two of the plurality of hosts.

Images