A prefetch address acquisition method and device

Abstract

This specification relates to the field of computer technology, and in particular to a method and apparatus for obtaining a prefetch address. The method includes: obtaining an access address; updating an Active Generation Table (AGT) based on the access address, wherein the updated AGT includes a first spatial access pattern and a first valid access count corresponding to region information in the access address; determining whether the first valid access count in the AGT exceeds a preset threshold; if it exceeds the preset threshold, obtaining a prefetch address based on the offset address corresponding to a second spatial access pattern similar to the first spatial access pattern in a Pattern History Table (PHT) and the region information of the access address, wherein the second spatial access pattern in the PHT is the first spatial access pattern that has been kicked out of the AGT. Using the embodiments of this specification, the versatility and reusability of learning patterns are effectively improved, and the prefetch coverage of the prefetcher is increased.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a method and apparatus for obtaining prefetch addresses. Background Technology

[0002] With the widespread deployment of multi-core processors in data-intensive applications such as servers and databases, memory system performance has become a bottleneck restricting overall performance. In workloads such as commercial database systems and transaction processing (OLTP / DSS), memory-related pause times account for more than half of the total execution time. Although modern servers offer significant memory bandwidth, the large number of data dependencies in the access chain leads to a severe deficiency in memory-level parallelism (MLP), causing the memory system to fail to fully utilize bandwidth. To alleviate this bottleneck, various data prefetching techniques have been proposed to preload data into the cache before it is actually accessed, thus hiding high latency. For example, in database systems, cache misses are a key factor affecting query performance; therefore, hardware prefetchers are considered one of the important means to improve data access performance on multi-core servers.

[0003] Spatial Memory Streaming (SMS) data prefetching is a program counter-based (PC-based) hardware data prefetching technique that addresses spatial locality. Its core is to predict and prefetch cache blocks that may be accessed in the future by dynamically learning the spatial correlation patterns of program access to memory.

[0004] Spatial-locality data prefetchers (DP) focus on the patterns of access addresses within a region. They observe and record the relative addresses of access addresses within that region, and this address range, divided into the smallest learning unit, is called a "region". Within a region, each access address relative to the region's base address, with the smallest granularity being a cache line, is recorded as an "offset address". All offset addresses form the offset pattern within this region.

[0005] SMS binds spatial pattern indexes to the PC at the time of triggering, ensuring that each spatial pattern training and prediction is only effective within the same PC path. This locality dependency makes it difficult to migrate and use trained patterns when the data access path changes (e.g., triggered by different threads, functions, or conditional branches), resulting in severe cold start problems, longer training times, and limited prefetch coverage. It performs particularly poorly in one-time access scenarios such as database scans and complex intermediate query operations.

[0006] The lack of versatility and low prefetch coverage of PC-based SMS prefetching solutions is an urgent problem that needs to be solved. Summary of the Invention

[0007] To address the problems in the prior art, embodiments of this specification provide a prefetch address acquisition method and apparatus, which solves the problem of PC-based learning and prediction in the prior art, and instead uses relevant information of the access address region for learning and prediction, thereby enhancing globality and improving the prefetch hit rate and generalization ability of untrained paths.

[0008] This specification provides an embodiment of a prefetch address acquisition method, including,

[0009] Get the access address;

[0010] The Active Generation Table (AGT) is updated according to the access address, wherein the updated AGT includes a first spatial access pattern and a first valid access count corresponding to the region information in the access address;

[0011] Determine whether the first valid access count in the AGT exceeds a preset threshold;

[0012] If the preset threshold is exceeded, the prefetch address is obtained based on the offset address of the second spatial access mode that is similar to the first spatial access mode in the mode history table PHT and the region information of the access address, wherein the second spatial access mode in the PHT is the first spatial access mode that was kicked out in the AGT.

[0013] As a further aspect of this specification, updating the Active Generation Table (AGT) based on the access address further includes,

[0014] Determine whether the region information in the access address matches in the AGT;

[0015] If no match is found, a first spatial access mode and a first valid access count corresponding to the region information are created in the AGT according to the access address;

[0016] If a match is found, determine whether the access address in the AGT is a new first space access mode;

[0017] If it is a new first spatial access mode, then update the first spatial access mode and the first valid access count corresponding to the region information in the AGT according to the access address.

[0018] As a further aspect of this specification, if a match is not found, the process of creating a first spatial access mode and a first valid access count in the AGT corresponding to the region information based on the access address further includes:

[0019] Determine whether the AGT is full;

[0020] If the AGT is not full, a first spatial access mode and a first valid access count corresponding to the region information are created in the AGT;

[0021] If the AGT is full, a first space access mode is kicked out from the AGT and transferred to the PHT as the second space access mode according to preset rules.

[0022] As a further aspect of this specification, kicking out a first spatial access mode from the AGT to the PHT as a second spatial access mode according to preset rules further includes,

[0023] After the first valid access count corresponding to the first space access mode that has been kicked out is removed from the PHT and used as the second valid access count,

[0024] In the AGT, a first spatial access mode and a first valid access count corresponding to the region information are created.

[0025] As a further aspect of this specification, based on the offset address corresponding to the second spatial access mode in the PHT that is similar to the first spatial access mode and the region information of the access address, the prefetch address further includes,

[0026] The first spatial access pattern is used to traverse the second spatial access pattern in the PHT.

[0027] Perform a bitwise AND operation between the first space access pattern and each of the second space access patterns, and count the number of 1s after the AND operation.

[0028] When the number of 1s exceeds a preset threshold, the second space access mode is determined to be similar to the first space access mode.

[0029] As a further aspect of this specification, after performing a bitwise AND operation between the first space access mode and each of the second space access modes, and calculating the number of 1s after the AND operation, the method further includes...

[0030] Calculate the ratio of the number of 1s to the second valid access count;

[0031] When the ratio exceeds a preset ratio threshold, it is determined that the second space access mode is similar to the first space access mode.

[0032] As a further aspect of this specification, if a match is found, determining whether the access address in the AGT is a new first space access mode further includes,

[0033] If the bit corresponding to the offset address of the access address in the first spatial access mode is 0, then the access address is a new first spatial access mode in the AGT.

[0034] As a further aspect of this specification, if it is a new first spatial access mode, then updating the first spatial access mode and the first valid access count corresponding to the region information in the AGT according to the access address further includes,

[0035] Set the position corresponding to the offset address of the access address in the first space access mode to 1, and increment the first valid access count by 1.

[0036] As a further aspect of this specification, after obtaining the prefetch address, it also includes,

[0037] The second spatial access pattern that occurs during prefetching is recorded as a historical prefetching pattern corresponding to the area information;

[0038] When a prefetch occurs again, filter out offset addresses that are duplicates of the second space access pattern during the current prefetch and the historical prefetch pattern.

[0039] As a further aspect of this specification, the second spatial access pattern in which prefetching occurs is recorded as a historical prefetch pattern corresponding to the said region information, further including...

[0040] And mark the flag bits of the region information;

[0041] When a prefetch occurs again, filtering out offset addresses where the second space access pattern of the current prefetch overlaps with the historical prefetch pattern further includes...

[0042] If the flag bit of the region information has been marked, the second space access mode at the current prefetching time is masked using the historical prefetching mode. Based on the offset address of the masked second space access mode and the region information of the access address, the prefetch address for the next prefetch is obtained.

[0043] As a further aspect of this specification, after obtaining the prefetch address for the next prefetch, it also includes,

[0044] The masked second space access pattern is bitwise ANDed with the historical prefetch pattern to obtain the historical prefetch pattern corresponding to the region information.

[0045] As a further aspect of this specification, the historical prefetching pattern and flag corresponding to the region information are stored in the AGT.

[0046] This specification also provides a prefetch address acquisition device, which includes,

[0047] The acquisition unit is used to obtain the access address;

[0048] An update unit is configured to update the Active Generation Table (AGT) based on the access address, wherein the AGT includes a first spatial access pattern and a first valid access count corresponding to the region information in the access address;

[0049] The judgment unit is used to determine whether the first valid access count in the AGT exceeds a preset threshold;

[0050] If the prefetch unit exceeds the preset threshold, it is used to obtain the prefetch address based on the offset address corresponding to the second spatial access mode similar to the first spatial access mode in the mode history table PHT and the region information of the access address, wherein the second spatial access mode in the PHT is the first spatial access mode that has been kicked out in the AGT.

[0051] This specification also provides a processor, including a prefetcher that performs the above-described methods.

[0052] This specification also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described above.

[0053] This specification also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the above-described method.

[0054] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0055] Using the embodiments in this specification, learning and prefetching based on access patterns within a specific region can effectively learn the access patterns of data stored in that region. Furthermore, the conditions for generating prefetches do not depend on any specific PC. This effectively compensates for the lack of versatility and fragmentation inherent in PC-based prefetching, significantly improving the versatility and reusability of the learned patterns and increasing the prefetch coverage of the prefetcher. Moreover, with the internal prefetch throttling mechanism, excessive duplicate prefetching is avoided, thereby improving processor performance. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 The diagram shown is a schematic representation of GSMS (Global SMS) prefetching in an embodiment of this specification.

[0058] Figure 2 The diagram shown is a flowchart of a prefetch address acquisition method according to an embodiment of this specification.

[0059] Figure 3 The diagram shown is a flowchart of an embodiment of GSMS in this specification;

[0060] Figure 4 This is a schematic diagram illustrating the address prefetching method in an embodiment of this specification;

[0061] Figure 5 The diagram shown is a schematic of the record entries added to AGT in this embodiment of the specification;

[0062] Figure 6 The diagram shown illustrates how an AGT record entry is pushed into the PHT according to an embodiment of this specification.

[0063] Figure 7 The diagram shown is a schematic diagram illustrating how the access address is determined to be a new offset address in an embodiment of this specification.

[0064] Figure 8 The diagram shown is a schematic diagram of an embodiment of this specification where the access address is a new offset address;

[0065] Figure 9 The diagram shown is a schematic representation of pattern matching in an embodiment of this specification.

[0066] Figure 10a The diagram shown is a schematic diagram of how a prefetch address is generated according to an embodiment of this specification;

[0067] Figure 10b The diagram shown is a schematic diagram of the prefetching throttling mechanism in an embodiment of this specification;

[0068] Figure 10c The diagram shown is a schematic diagram of the prefetching throttling mechanism in an embodiment of this specification;

[0069] Figure 11 The diagram shown is a structural schematic of a prefetch address acquisition device according to an embodiment of this specification.

[0070] Figure 12 The diagram shown is a schematic representation of a computer device provided in an embodiment of this specification.

[0071] [Explanation of Labels in the Attached Image]

[0072] 1101. Acquisition Unit;

[0073] 1102. Update Unit;

[0074] 1103, Judgment Unit;

[0075] 1104. Prefetching unit;

[0076] 1202. Computer equipment;

[0077] 1204, Processor;

[0078] 1206. Memory;

[0079] 1208. Drive mechanism;

[0080] 1210. Input / output module;

[0081] 1212. Input devices;

[0082] 1214. Output devices;

[0083] 1216. Presentation equipment;

[0084] 1218. Graphical User Interface;

[0085] 1220. Network interface;

[0086] 1222. Communication link;

[0087] 1224. Communication bus. Detailed Implementation

[0088] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0089] In modern processor architectures, the data prefetcher is typically deployed between the L2 cache and main memory, or between the L1 cache and L2 cache. It exists as an independent microarchitectural module, collaborating with multiple core subsystems to pre-schedule data and alleviate memory access bottlenecks. The prefetcher captures potential access patterns by listening to access requests (load / store instructions) or cache miss events in the processor core or cache system. When a new access behavior occurs, the prefetcher accumulates access characteristics using its internal training structures (such as history tables, window buffers, and active record tables). In the future, once a triggering event matching the historical characteristics is detected, the prefetcher generates a prefetch request. These prefetch requests are typically inserted into the structure that sends load requests in a similar form to normal load requests and are coordinated and issued by the cache controller. If system resources permit, the prefetcher will load the predicted data from the next-level cache or main memory into the current-level cache in a non-blocking manner. After predicting the data that needs to be loaded, the prefetcher actively sends a load request to the next-level cache or main memory. The entire loading process occurs in the background and does not block the normal execution of the CPU. For example, if the L2 cache prefetcher predicts that the next possible access address X, it will send a request to load X to the L3 cache (or main memory). At this time, the CPU can still continue to execute other instructions (such as operations or accessing cached data). After the data is transferred from the next level to the current-level cache (such as L2), if the CPU does access X later, it can directly hit the current-level cache, avoiding blocking and waiting.

[0090] SMS primarily consists of two parts: the Active Generation Table (AGT) and the Pattern History Table (PHT). The AGT is responsible for detecting and learning Region Access Patterns, while the PHT stores the learned patterns and initiates prefetching at appropriate times. An AGT entry needs to record information including a region tag, indicating which region the access address belongs to, or the region to which a newly assigned entry for this access belongs. The AGT event refers to a specific record in the AGT table, containing detailed information about the entry (such as identifier, attributes, status, associated data, etc.). This region tag is used for subsequent access address mapping. Existing SMS methods also include a "PC / offset" in the AGT, which records the PC value (program counter) and offset value of the first allocation of the AGT entry. PC information is used for indexing the AGT entry when it is subsequently replaced in the PHT, while offset information is used to merge the AGT pattern (spatial access pattern) with the PHT entry after indexing. Spatial-locality DP, also known as the offset pattern mentioned earlier, records the offset address accessed within the region.

[0091] When the AGT record entries are full and new areas are about to be accessed, requiring space to allocate new record entries, an AGT record entry is evicted into the PHT according to the replacement principle, forming a persistent space access pattern entry in the PHT, which is directly used for future prefetching. The AGT entry evicted into the PHT is first indexed based on the PC value or its hash value. If a PHT entry with the same PC or PC hash value exists, the corresponding entry is evicted, allowing that PHT entry to obtain and store the space access pattern learned from the AGT.

[0092] After obtaining a PHT entry, when the processor detects during runtime that the currently accessed PC and offset match an entry in the PHT, the spatial pattern of that entry is "activated". The PHT predicts the address to be accessed next based on the pattern, loads the corresponding cache line data from the L2 cache into L1, adds the offset address corresponding to the cache line to the region base address of the region accessed by this PC, and generates a series of prefetch address access flows for that region.

[0093] However, the prefetcher's ability to generalize learned patterns is insufficient. SMS prefetching relies on PC information corresponding to triggered accesses for learning and prediction. As a PC-based prefetcher, its prefetch entries are built based on PC triggers recorded in historical accesses. If a new execution path or access pattern appears that has not yet seen its corresponding trigger PC, the current SMS mechanism cannot immediately generate an accurate prediction. This results in SMS's limited generalization ability when encountering untrained code paths or highly dynamically changing access patterns, potentially failing to capture new spatial access patterns in a timely manner.

[0094] In a typical SMS implementation, spatial pattern training is bound to triggering conditions one-to-one. This means that even if multiple triggering paths access similar data structures, their spatial patterns must be recorded separately, resulting in redundant storage and pollution of training record entries, thus affecting efficient coverage. During multi-threaded or multi-stage queries, data structure accesses occur in interleaved patterns. SMS cannot uniformly abstract these accesses, making it difficult to fully utilize the learned access patterns.

[0095] The training and matching process of SMS relies solely on PC value indexes. The system cannot summarize and reuse frequently occurring access patterns across paths, resulting in high-value patterns failing to fully play their predictive role and reducing the system's training efficiency and prefetch coverage.

[0096] like Figure 1The diagram illustrates a GSMS (Global SMS) prefetching scheme according to an embodiment of this specification. This embodiment proposes a GSMS technique that utilizes access addresses for training and access pattern correlation for matching. During the training phase, after indexing / updating the Access Gateway (AGT), the AGT records learn spatial access patterns and update the matching PHT (Physical Access Detector) entries with these learned patterns. When the replacement policy is met, the AGT's spatial access patterns are kicked into (equivalent to storing and updating) the PHT. During the prediction phase, the AGT record entries are first indexed using access addresses, and the updated AGT spatial access patterns are used to match the most relevant spatial access patterns in the PHT before generating prefetch addresses. The scheme in this embodiment considers the inherent commonality of spatial patterns, meaning that similar or overlapping accesses can represent accesses to the same or similar data structures. This allows similar access patterns under multiple access paths to be effectively utilized, improving the utilization rate of record entries and increasing the number of prefetches, thus improving the prefetcher's coverage.

[0097] like Figure 2 The diagram shows a flowchart of a prefetch address acquisition method according to an embodiment of this specification. The diagram illustrates triggering the prefetch process by adding a first valid access count to the AGT. When the prefetch process is triggered, the loading prediction of the next data item is made based on the similarity of spatial access patterns. This fully reflects the common expressive ability inherent in spatial access patterns, meaning that similar or overlapping accesses can represent accesses to the same or similar data structures. In other words, the training phase in this embodiment adds training and learning of valid accesses, and then adds a judgment on the number of valid accesses, thereby triggering the prediction process. The prediction phase adds an extension to the similarity of spatial access patterns. Specifically, this method includes:

[0098] Step 201, obtain the access address;

[0099] Step 202: Update the Active Generation Table (AGT) according to the access address, wherein the updated AGT includes a first spatial access pattern and a first valid access count corresponding to the region information in the access address;

[0100] Step 203: Determine whether the first valid access count in the AGT exceeds a preset threshold;

[0101] Step 204: If the preset threshold is exceeded, the prefetch address is obtained based on the offset address of the second spatial access mode similar to the first spatial access mode in the Pattern History Table (PHT) and the region information of the access address, wherein the second spatial access mode in the PHT is the first spatial access mode that was kicked out in the AGT.

[0102] The method described in this specification records the spatial access patterns of historical access offset addresses in the AGT and stores the learned spatial access patterns in the PHT. This effectively learns the spatial access patterns of data accessed within a certain region. In the prediction phase, after accessing the AGT record entries based on the access addresses and updating the relevant AGT record entries, it is determined whether to search for the most relevant spatial access pattern in the PHT based on the number of valid accesses before generating a prefetch. This fully utilizes the common expressive ability of the spatial access patterns themselves, that is, similar or overlapping accesses can represent accesses to the same or similar data structures, thus having high versatility and global integration characteristics. This effectively improves the versatility and utilization of spatial access patterns and enhances the prefetch coverage of the prefetcher.

[0103] As an embodiment of this description, updating the Active Generation Table (AGT) based on the access address further includes,

[0104] Determine whether the region information in the access address matches in the AGT;

[0105] If no match is found, a first spatial access mode and a first valid access count corresponding to the region information are created in the AGT according to the access address;

[0106] If a match is found, determine whether the access address in the AGT is a new first space access mode;

[0107] If it is a new first spatial access mode, then update the first spatial access mode and the first valid access count corresponding to the region information in the AGT according to the access address.

[0108] In this embodiment, the access address is divided into three parts: region, offset address, and cache line. The least significant bit is the byte offset address within a cache line, the number of bits determined by the cache line size. The second part, from least significant to most significant, is the offset address of the cache lines within the region. A region contains several cache lines, and this is represented in the address by the bits above the cache line byte level down to the bits below the region level. This segment of bits can represent the address at the granularity of each cache line. For example, if a cache line in a cache is 64 bytes, then the byte address of a cache line is the lower 6 bits of the address. Assuming a 1KB region has a total of 10 bits in binary address, with the lower 6 bits representing the cache line, then bits 7 through 10 correspond to 16 cache lines and can also represent the addresses of these 16 cache lines. The higher bits of the first cache line address are represented as 0001, the second as 0010, and so on, up to 1111 for the 16th. The third part is the offset address of the cache lines within the region. The bits from the highest bit to the lowest bit of the line range represent the total number of regions and their corresponding addresses within the monitored cache range. The offset address of a cache line within a region is the offset address of the cache line relative to the region's base address 0000, which is 0, 1...15, i.e., the decimal representation converted from the "high-order" binary bits. One way to record these offset addresses within a region in the processor is to use a vector of size equal to the number of cache lines within the region. For example, a 16-bit vector, with bits 0 to 15 representing the 16 cache lines. When we want to indicate that a cache line exists in a region, the corresponding vector bit is set to 1; otherwise, it is set to 0. The learned space access pattern within a region is recorded by updating the vector.

[0109] To determine whether the region information in the access address matches in the AGT, the region number corresponding to the highest bit of the access address is matched and indexed in the AGT. If there is an entry for that region number in the AGT, it means a match; otherwise, it means a miss.

[0110] When there is a miss, it means that there is no record entry related to the region at the access address in the AGT. In other words, the region corresponding to the access address has not been accessed before, so it is necessary to enter the process of creating a new entry. When there is a hit, it means that there is a record entry related to the region at the access address in the AGT. In other words, the region corresponding to the access address has been accessed before, so it is necessary to enter the process of updating the entry.

[0111] The method described in this specification allows for updating (including creating and updating) record entries in the AGT based on the region in the access address, effectively learning the spatial access patterns of data stored in a certain region.

[0112] As an embodiment of this description, if a miss occurs, the process further includes creating a first spatial access mode and a first valid access count in the AGT corresponding to the region information based on the access address.

[0113] Determine whether the AGT is full;

[0114] If the AGT is not full, a first spatial access mode and a first valid access count corresponding to the region information are created in the AGT;

[0115] If the AGT is full, a first space access mode is kicked out from the AGT and transferred to the PHT as the second space access mode according to preset rules.

[0116] In this step, if there is still space in the AGT to create a new record entry, a new AGT record entry is created based on the region and offset address in the access address. This AGT record entry includes at least a region, a first spatial access pattern (region_access_bits), and a first valid access count (count). When creating a new AGT record entry, the first spatial access pattern can be the same as the offset address in the access address. Subsequently, the first spatial access pattern can be updated based on the offset addresses of other access addresses with the same region information, that is, a certain bit in the vector is set to 1. The first valid access count records how many bits in the first spatial access pattern are set to 1, that is, indicating which cache lines in the region have been accessed so far.

[0117] If there is no space in the AGT to create a new record entry, a record entry needs to be evicted from the current AGT to the PHT. The evict record entry includes the aforementioned region, first spatial access pattern (region_access_bits), and first effective access count (count). The first spatial access pattern records which cache lines in the region have been accessed so far. When the first spatial access pattern is migrated to the second spatial access pattern of the corresponding record entry in the PHT, it is equivalent to storing the spatial access pattern learned by prefetching for use in the next prefetch. In this step, other information besides the aforementioned region, first spatial access pattern (region_access_bits), and first effective access count (count) can also be discarded to reduce the storage space occupied by the PHT.

[0118] Then, a first spatial access mode and a first valid access count are created in the AGT that correspond to the region information in the access address.

[0119] As an embodiment of this description, the prefetch address is further obtained based on the offset address corresponding to a second spatial access pattern similar to the first spatial access pattern in the Pattern History Table (PHT) and the region information of the access address.

[0120] The first spatial access pattern is used to traverse the second spatial access pattern in the PHT.

[0121] Perform a bitwise AND operation between the first space access pattern and each of the second space access patterns, and count the number of 1s after the AND operation.

[0122] When the number of 1s exceeds a preset threshold, the second space access mode is determined to be similar to the first space access mode.

[0123] In this step, after the AGT record entries are kicked out to the PHT, the PHT contains record entries for spatial access patterns for different regions. When a new access address is hit in the AGT, if the offset address of the access address is different from the first spatial access pattern of the record entry in the AGT, and the first valid access count exceeds a preset threshold, it is necessary to traverse similar second spatial access patterns in the PHT table according to the first spatial access pattern to prefetch subsequent access addresses.

[0124] Since the offset address of the new access address may update the first space access mode, the first space access mode and the second space access mode may be different. Therefore, the first space access mode is bitwise ANDed with each of the second space access modes, and the number of 1s after the AND is calculated. When the number of 1s exceeds the preset threshold, it is determined that the second space access mode is similar to the first space access mode, and address prefetching is performed according to the second space access mode.

[0125] As one embodiment of this description, after performing a bitwise AND operation between the first space access pattern and each of the second space access patterns, and calculating the number of 1s after the AND operation, the method further includes...

[0126] Calculate the ratio of the number of 1s to the second valid access count;

[0127] When the ratio exceeds a preset ratio threshold, it is determined that the second space access mode is similar to the first space access mode.

[0128] In this step, following the previous embodiment, the first spatial access mode is further bitwise ANDed with each of the second spatial access modes, and the number of 1s after the AND is calculated. When the number of 1s accounts for the ratio of the second valid access count, and the ratio exceeds a preset ratio threshold, it is determined that the second spatial access mode is similar to the first spatial access mode.

[0129] The steps in this embodiment can be used as a further processing of the previous embodiment, or the determination of spatial access pattern similarity can be completed using only the previous embodiment.

[0130] As an embodiment of this description, if a match is found, determining whether the access address in the AGT is a new first space access mode further includes,

[0131] If the bit corresponding to the offset address of the access address in the first spatial access mode is 0, then the access address is a new first spatial access mode in the AGT.

[0132] In this step, if the first space access mode in the AGT record entry does not record the offset address of the current access address, it means that the cache line at the current access address has not been accessed before and needs to be loaded from the lower-level cache or main memory. Therefore, the subsequent AGT update process is required. If the first space access mode in the AGT record entry records the offset address of the current access address (i.e., the corresponding vector bit is 1), it means that the cache line at the current access address has been accessed before, and this access only needs to read the data from the cache line at this level.

[0133] In another embodiment, when the first spatial access mode record in the AGT record entry contains the offset address in the current access address, the first valid access count in the record entry corresponding to that region in the AGT can be incremented by 1. This indicates that the region has been accessed multiple times and may be a relatively "hot" region. When kicking the AGT record entry to the PHT, this first valid access count can be used as a reference to avoid kicking relatively "hot" record entries to the PHT. Alternatively, the first valid access count can be used to determine whether to start the prefetch process in the PHT, obtain the prefetch address of the offset address corresponding to the second spatial access mode in the PHT, and use other offset addresses related to the current access address space as the next possible load data.

[0134] In other embodiments, other replacement strategies may also be adopted, such as Least Recently Used (LRU), Most Recently Used (MRU), Static Re-Reference Interval Prediction (SRRIP), Dynamic Re-Reference Interval Prediction (DRRIP), etc.

[0135] As an embodiment of this description, if it is a new first spatial access mode, then updating the first spatial access mode and the first valid access count corresponding to the region information in the AGT according to the access address further includes,

[0136] Set the position corresponding to the offset address of the access address in the first space access mode to 1, and increment the first valid access count by 1.

[0137] In this step, if the offset address of the current access address has not been accessed in previous accesses, that is, the first space access mode corresponding to this region in the AGT does not record the bit corresponding to the offset address of the current access address, the bit corresponding to the first space access mode will be set to 1, representing which cache lines have been accessed so far, and the first valid access count will be incremented by 1, representing the number of times this region has been accessed.

[0138] As one embodiment of this description, after obtaining the prefetch address, the following steps are also included:

[0139] The second spatial access pattern that occurs during prefetching is recorded as a historical prefetching pattern corresponding to the area information;

[0140] When a prefetch occurs again, filter out offset addresses that are duplicates of the second space access pattern during the current prefetch and the historical prefetch pattern.

[0141] In this step, because GSMS performs large-scale batch prefetching and has relatively lenient matching conditions, if every region access generates a prefetch of the entire region, a large number of useless duplicate prefetches will occur. Therefore, after a prefetch is generated, the spatial access pattern of this prefetch can be recorded as a historical prefetch pattern. In the next prefetch, the offset address that is the same as the historical prefetch pattern can be filtered out, thereby reducing duplicate prefetches.

[0142] As an embodiment of this description, the second spatial access pattern in which prefetching occurs is further included in the historical prefetch pattern corresponding to the region information.

[0143] And mark the flag bits of the region information;

[0144] When a prefetch occurs again, filtering out offset addresses where the second space access pattern of the current prefetch overlaps with the historical prefetch pattern further includes...

[0145] If the flag bit of the region information has been marked, the second space access mode at the current prefetching time is masked using the historical prefetching mode. Based on the offset address of the masked second space access mode and the region information of the access address, the prefetch address for the next prefetch is obtained.

[0146] In this step, historical prefetch patterns can be used to mask the current second space access pattern, thereby filtering out duplicate offset addresses. For example, a flag is added to a region to indicate whether the space access pattern corresponding to that region in the access address has been prefetched. If the space access pattern of that region has been prefetched, the flag is set, indicating that the region has been prefetched, and the space access pattern corresponding to the offset address generated this time is recorded as a historical prefetch pattern. In the vctor bit of the historical prefetch pattern, "1" can represent that a certain cache line has been prefetched, and "0" can represent that the cache line has not been prefetched. When prefetching is needed again in the future, the flag is used to determine whether the region has been prefetched. If it has been prefetched, it means that the historical prefetch pattern should be used to filter out the new offset address that the current PHT will generate. The bits of the historical prefetch pattern vector and the second space access pattern vector can be XORed to filter out the prefetched cache line offset address. At the same time, cache lines prefetched through GSMS are marked in the flag. When a cache line replaced by GSMS is replaced in the future cache, the vector bit corresponding to the offset address in that historical prefetch mode will be reset to "0", indicating that the cache line is no longer in the cache and can be prefetched by GSMS again in the future.

[0147] As one embodiment of this description, after obtaining the prefetch address for the next prefetch, the method further includes:

[0148] The masked second space access pattern is bitwise ANDed with the historical prefetch pattern to obtain the historical prefetch pattern corresponding to the region information.

[0149] In this step, after the address is prefetched again, the historical prefetch pattern is updated according to the prefetched offset address so that more duplicate offset addresses can be filtered out in the next prefetch.

[0150] As one embodiment of this description, the historical prefetching pattern and flag corresponding to the region information are stored in the AGT.

[0151] In this step, flags and historical prefetch patterns can also be included in the AGT record entries, so that the historical prefetch patterns and flags can be updated simultaneously with the AGT updates.

[0152] The methods described in the various embodiments of this specification can effectively learn the spatial access patterns of data stored in a certain region. During prefetching, prefetching is performed within the region where the accessed address is located. If a spatial access pattern is found to be highly similar to a previously learned spatial access pattern, that spatial access pattern can be used to generate prefetches. This prefetching effectively improves generality and globality, enhancing the generality and utilization of the learned spatial access patterns and increasing the prefetch coverage of the prefetcher. Furthermore, with the assistance of internal prefetch filtering mechanisms, excessive duplicate prefetching is avoided, thereby improving processor performance.

[0153] like Figure 3 The diagram shows a flowchart of the GSMS embodiment of this specification. The flowchart describes the overall process steps of GSMS. The order of the steps is not limited to the order of description in the figures and text. There are other execution orders that can also achieve the purpose of this embodiment, which will not be described in detail here. Figure 4 This diagram illustrates a prefetching address method according to an embodiment of this specification. It depicts the process of obtaining a prefetched address by performing a similarity match between a first spatial access pattern recorded in the AGT's record entries and a second spatial access pattern in the PHT's record entries. This can be combined with... Figure 4 ,right Figure 3 To understand and compare the described methods, Figure 3 The methods shown include:

[0154] Step 301: Receive the access address.

[0155] In this embodiment, assuming there is a request to access the L2 cache, the binary representation of the access address is: 000 001 000 010 010 000, in bytes. The high six bits "000 001" represent the region, which is 1, indicating that the cache line is located in "region 1". The next six bits "000 010" represent the relative offset address, which is 2, indicating that the cache line is the 3rd position in region 1. The next six bits "010000" represent the position of the data within this cache line. Typically, the L2 cache line length is 64 bytes, and the data prefetcher operates on a line-by-line basis; therefore, these 6 bits are usually masked and can also be interpreted as "000 000". In summary, the access address requests access to the cache line with region information of region 1 and offset address of 2.

[0156] Step 302: Check if AGT is hit. If it is hit, proceed to step 309. If it is not hit, proceed to step 303.

[0157] In this embodiment, determining whether the access address is hit in the AGT depends on whether there is already a record entry in the AGT with the "region" tag also set to "region 1". If so, it means a hit; otherwise, it means a miss.

[0158] Furthermore, each record entry in the AGT is accessed, and the "region" of each record entry is queried in turn to see if there is a record entry that matches the region information in the access address. If region 1 is found, it is a hit; if region 1 is not found, it is a miss.

[0159] Step 303: Assign AGT record entries.

[0160] In this embodiment, when a miss occurs, the information of this access address needs to be recorded, and a new record entry needs to be added to the AGT.

[0161] Step 304: Determine if AGT is full. If not, proceed to step 305; if full, proceed to step 306.

[0162] Step 305: Add a new AGT record entry.

[0163] In this embodiment, an idle AGT record entry can be directly allocated, and information can be recorded into the record entry, such as... Figure 5 The diagram shown illustrates a newly added record entry in the AGT of this embodiment. This newly added AGT record entry includes the following information:

[0164] ① Region: Record the region information "1" in the access address, representing region1;

[0165] ② First Space Access Mode (region_access_bits): Records the third offset address corresponding to region 1 that has been accessed. Set the third bit of the 64-bit vector corresponding to region_access_bits to 1. Since this is the first access to region 1, only the current third offset address is 1, and the other bits are 0, indicating that it has not yet been accessed.

[0166] ③ First valid access count (count): Records how many bits in the "region_access_bits" of the current entry are set to "1", which indicates the number of offset addresses that have been accessed in the current region 1. As described in this embodiment, only 1 offset address has been accessed so far, so the count is "1".

[0167] ④ Flag bit (gen): Indicates whether the record entry has been prefetched. In this embodiment, it is a newly added record entry that has not yet been indexed and prefetched, so the flag bit is set to "0".

[0168] ⑤ History Prefetch Pattern (gen_history): Records the offset addresses where the current region has been prefetched. In this embodiment, since no prefetch has been generated yet, every bit in the 64-bit vector of the history prefetch pattern corresponding to this region is 0.

[0169] The flag bits and history prefetch patterns mentioned above are not content that the AGT must record and store.

[0170] Step 306: Determine if the PHT is full. If not, proceed to step 308; if full, proceed to step 307.

[0171] Step 307: Remove a record entry from PHT.

[0172] In this embodiment, a record entry of PHT can be kicked out of PHT to the lower-level cache according to a preset strategy. For example, preset strategies such as Least Recently Used (LRU) and Least Frequently Used (LFU) can be used. Alternatively, PHT record entries that have not been prefetched within a predetermined time can be cleared, thereby allowing PHT to free up space to receive record entries kicked out by AGT.

[0173] Step 308: Kick the AGT record entry into PHT.

[0174] In this embodiment, as Figure 6 The diagram illustrates how an AGT record entry is moved to the PHT according to an embodiment of this specification. Based on the AGT table replacement strategy (which can be the preset strategy described in the preceding steps), an AGT record entry is selected, and its "region_access_bits" is recorded in the PHT. For example, assuming a "region 12" record entry is selected based on the replacement strategy, the first spatial access pattern ("pattern") and "count" obtained during the training period recorded in the "region_access_bits" of this record entry are recorded in a PHT record entry. Other information can be discarded. Then, the newly added record entry completely updates and overwrites the record entry corresponding to region 12. For example, the above... Figure 5 In the illustrated embodiment, the access address information is stored in the record entry corresponding to region 12, forming a structure as shown below. Figure 6 The AGT record entries are shown in the attached diagram below.

[0175] At this point, a new record entry has been inserted into the AGT.

[0176] Step 309: If a match is found, check if the offset address in the access address is a new offset address. If so, proceed to step 310. If the same offset address already exists in the record entry of the AGT, proceed to step 314 to end.

[0177] In this embodiment, as Figure 7 The diagram illustrates how an access address is determined to be a new offset address in an embodiment of this specification. In this embodiment, assuming that the region information is accessed during AGT access and found to be 1, it means that the information for that region is recorded in the current AGT, indicating a hit. Further access to the first spatial access mode (region_access_bits) information is performed to determine if the offset address of the current access address is a new offset address. It is found that the third cache line corresponding to the offset address of the current access address already has the third bit set to 1 in the first spatial access mode (region_access_bits marked in red in the diagram), indicating that the same region and the same offset access address have previously accessed this cache line, and are exactly the same as the current access address. In this case, the AGT record entry is not updated, and the process proceeds to step 314 to end.

[0178] Step 310: If it is a new offset address, update the AGT record entry.

[0179] In this embodiment, as Figure 8 The diagram illustrates an embodiment of this specification where the access address is a new offset address. Assuming that during access to the AGT, the region information is accessed and found to be 1, indicating that the AGT has recorded information about that region, a hit. Further access to the first spatial access mode (region_access_bits) information reveals that in the third cache line corresponding to the offset address of the current access address, the third bit of the first spatial access mode is set to 0, indicating that this offset address within that region has not been accessed. Therefore, the record entry corresponding to region 1 in the AGT is updated, setting the third bit of the region_access_bits of the third cache line corresponding to offset address 2 to 1, and the first valid access count increases from 5 to 6.

[0180] Step 311: Determine whether count exceeds a preset threshold. If it exceeds the preset threshold, proceed to step 312; otherwise, proceed to step 314 to end.

[0181] In this embodiment, when an access address hits the AGT and the offset address in that access address is the new offset address, the count in the corresponding record entry for that region will be incremented. Each time the AGT record entry is updated, region_access_bits and count can be updated, and the relationship between count and a preset threshold can be determined. For example, if the preset threshold is set to 5, the count before the update is 5, which does not exceed the preset threshold, so over-prefetching will not occur. After updating the AGT record entry, training ends; as described above. Figure 8 As shown, after updating the AGT record entries, the count in region 1 is 6, which is equal to the preset threshold of 6. Therefore, it exceeds the preset threshold, and prefetching is required to proceed to step 312. Of course, the statement that the count exceeds the preset threshold in this step is just a way of comparing the count with the preset threshold. Exceeding the threshold could mean greater than or equal to, or greater than, and this is not limited here.

[0182] In another embodiment, step 311 may not be sequential with step 310, which updates AGT record entries. Instead, it may monitor the count of each AGT record entry in real time and determine its relationship with a preset threshold. When the count does not exceed the preset threshold, the process can proceed to step 314 to end.

[0183] Step 312: Match similar second-space access patterns.

[0184] In this embodiment, when the count of a certain record entry in the AGT is monitored and found to be greater than a preset threshold, it indicates that the first spatial access pattern in the region can be matched with the second spatial access pattern in the PHT to find a similar second spatial access pattern.

[0185] As described in step 311 above, if the number of accesses within the region corresponding to the access address is sufficient to meet the conditions for PHT pattern matching, then pattern matching will be performed.

[0186] like Figure 9 The diagram shown is a schematic of pattern matching in an embodiment of this specification. Pattern matching is to determine the similarity between the first spatial access pattern (region_access_bits) of the current AGT record entry and the second spatial access pattern (region_access_bits) of each PHT record entry. For example, the overlap rate between the first spatial access pattern and the second spatial access pattern is calculated. If the similarity is high, it means that the region of the current access address is more likely to access the offset address of the spatial access pattern again in the future prefetch.

[0187] As an embodiment of this application, the similarity comparison can be performed as follows: First, calculate the number of bits that AND with the first spatial access pattern (region_access_bits) and the second spatial access pattern (region_access_bits) to be 1, which is taken as the "overlap count". The higher the overlap count, the higher the overlap rate and the stronger the similarity. The second spatial access pattern with the highest overlap count can be selected as the corresponding spatial access pattern for prefetching. Figure 9 As shown, for example, performing an AND operation between the first space access pattern 11101…110 and the second space access pattern 11111…101 of the AGT (where all ellipses are 0) yields an overlap pattern 11101…100 (where all ellipses are 0), with a overlap count of 5.

[0188] As another embodiment of this application, the similarity comparison can be performed as follows: First, calculate the number of bits that AND with the first spatial access pattern (region_access_bits) and the second spatial access pattern (region_access_bits) to produce a value of 1, which is taken as the "overlap count". Then, calculate the ratio of this overlap count to the second valid access count in the PHT record entry. This ratio represents the similarity between the first and second spatial access patterns. The second spatial access pattern with the highest similarity (largest ratio) can be selected as the corresponding spatial access pattern for prefetching. Here, the second valid access count represents the number of valid bits in the current second spatial access pattern. Figure 9 As shown, for example, if the number of overlaps is 5, then the second valid access count of PHT is 7, and the ratio of the two is 5 / 7 = 0.714.

[0189] Step 313: Generate the prefetch address.

[0190] In this embodiment, the prefetch address is obtained based on the second spatial access mode obtained in the above steps, the corresponding offset address, and the region information of the access address.

[0191] In one embodiment, such as Figure 10a The diagram illustrates the generation of prefetch addresses in an embodiment of this specification. This embodiment describes directly adding the region information from the access address to the offset address corresponding to the second spatial access pattern to obtain multiple prefetch address streams. Specifically, after obtaining the matching second spatial access pattern, the final prefetch address stream is obtained by adding the high-order region address (region 1 in the example) to its recorded pattern (i.e., the offset address set to 1 in region_access_bits in the PHT), thus generating a series of prefetch addresses.

[0192] In another embodiment, since there may be duplicate prefetches in the aforementioned prefetching, a throttling mechanism can be added. The throttling mechanism mainly uses the set bits in the history prefetch pattern (gen_history) to generate a mask, filtering out some offset addresses in the second space access pattern, and generating offset addresses that do not overlap with the history prefetch pattern (gen_history).

[0193] like Figure 10bThe diagram illustrates the prefetch throttling mechanism in an embodiment of this specification. It describes how, after a prefetch occurs, the historical prefetch pattern (gen_history) and flag (gen) corresponding to the region that generated the prefetch are updated. The flag (gen), originally 0, is set to 1. The offset address in the historical prefetch pattern is updated according to the offset address in the second space access pattern, representing the recording of prefetch addresses that have already been prefetched in the historical prefetch pattern. Figure 10a The second space access mode in the PHT shown is 11111…101 (where all ellipses are 0), as follows: Figure 10b The historical prefetch pattern in the AGT shown is 11111…101 (where all ellipses are 0), and the flag is set from 0 to 1.

[0194] like Figure 10c The diagram illustrates the prefetch throttling mechanism of this embodiment, describing the process of filtering duplicate offset addresses using historical prefetch patterns during prefetching. When prefetching occurs, the second spatial access pattern (11111…101 in this example) is obtained by performing a similarity match between the first spatial access pattern (00000…100 in this example) and all second spatial access patterns in the PHT. At this time, the flag bit corresponding to the region is obtained; if this flag bit (gen) is 1, it indicates that the region has previously undergone prefetching. The historical prefetch patterns (00000…101 in this example) are used to mask the second spatial access patterns, for example, by performing an XOR operation between the historical prefetch patterns and the second spatial access patterns. Figure 10c As described above, the generated pattern 11111…000 after the XOR operation is obtained, and the prefetch address stream is obtained by superimposing the region address and the masked generated pattern.

[0195] After prefetching is complete, the historical prefetch pattern needs to be updated based on the masked second space access pattern. For example, the masked second space access pattern can be bitwise ANDed with the historical prefetch pattern to obtain the new historical prefetch pattern corresponding to the region. Figure 10c In the embodiment shown, the historical prefetch pattern is updated from the original 00000…101 to 11111…101.

[0196] When a record entry in the AGT is replaced in the future, it is also necessary to look up the AGT and reset the historical prefetch pattern existing in that AGT to "0" (see Appendix). Figure 6 This means that the record is no longer in the cache and can be prefetched by GSMS in the future.

[0197] In other embodiments, the flag bits and history prefetch patterns can be located in the AGT or in other cache spaces such as the PHT, without limitation.

[0198] like Figure 11 The diagram shown is a schematic representation of a prefetch address acquisition device according to an embodiment of this specification. The diagram illustrates the structure of a device implementing the above method using logic circuits, software, or general-purpose processing chips, interfaces, etc. The device includes:

[0199] Acquisition unit 1101 is used to acquire the access address;

[0200] The update unit 1102 is used to update the Active Generation Table (AGT) according to the access address, wherein the AGT includes a first spatial access mode and a first valid access count corresponding to the region information in the access address;

[0201] The judgment unit 1103 is used to determine whether the first valid access count in the AGT exceeds a preset threshold;

[0202] If the preset threshold is exceeded, the prefetch unit 1104 is used to obtain the prefetch address based on the offset address corresponding to the second spatial access mode similar to the first spatial access mode in the Pattern History Table (PHT) and the region information of the access address, wherein the second spatial access mode in the PHT is the first spatial access mode that has been kicked out in the AGT.

[0203] The apparatus described in the embodiments of this specification records the spatial access patterns of historical access offset addresses in the AGT and stores the learned spatial access patterns in the PHT. This effectively learns the spatial access patterns of data accessed in a certain region. In the prediction phase, after accessing the AGT record entries according to the access addresses and updating the relevant AGT record entries, it is determined whether to search for the most relevant spatial access pattern in the PHT based on the number of valid accesses before generating a prefetch. This fully utilizes the common expressive ability of the spatial access patterns themselves, that is, similar or overlapping accesses can represent accesses to the same or similar data structures. This results in high versatility and global integration, effectively improving the versatility and utilization of spatial access patterns and increasing the prefetch coverage of the prefetcher.

[0204] like Figure 12The diagram illustrates a computer device according to an embodiment of this specification. The prefetch address acquisition device of this embodiment can be located in the computer device of this embodiment, and the above-described method can also be run on the computer device of this embodiment to execute the method described in this specification. The computer device 1202 may include one or more processors 1204, such as one or more central processing units (CPUs), each processing unit can implement one or more hardware threads. The computer device 1202 may also include any memory 1206 for storing any kind of information such as code, settings, data, etc. Non-limitingly, for example, the memory 1206 may include any type of RAM, any type of ROM, flash memory device, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory can represent a fixed or removable component of the computer device 1202. In one case, when the processor 1204 executes associated instructions stored in any memory or combination of memories, the computer device 1202 can perform any operation of the associated instructions. The computer device 1202 also includes one or more drive mechanisms 1208 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0205] Computer device 1202 may also include an input / output module 1210 (I / O) for receiving various inputs (via input device 1212) and providing various outputs (via output device 1214). A specific output mechanism may include a presentation device 1216 and an associated graphical user interface (GUI) 1218. In other embodiments, the input / output module 1210 (I / O), input device 1212, and output device 1214 may be omitted, and the device may function solely as a computer device within a network. Computer device 1202 may also include one or more network interfaces 1220 for exchanging data with other devices via one or more communication links 1222. One or more communication buses 1224 couple the components described above together.

[0206] Communication link 1222 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 1222 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0207] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the methods described above.

[0208] This specification also provides a processor, including a prefetcher that performs the methods described above. The processor may be a single-core or multi-core microprocessor, a system-on-a-chip (SoC), a graphics processing unit (GPU), or any integrated circuit that includes at least one computing core and has a hierarchical cache memory.

[0209] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the methods described above.

[0210] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0211] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0212] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0213] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0214] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0215] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0216] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0217] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0218] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0219] This specification uses specific embodiments to illustrate the principles and implementation methods of this specification. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this specification. Therefore, the content of this specification should not be construed as a limitation of this specification.

Claims

1. A method for obtaining a prefetch address, characterized in that, include, Get the access address; The Active Generation Table (AGT) is updated according to the access address, wherein the updated AGT includes a first spatial access pattern and a first valid access count corresponding to the region information in the access address; Determine whether the first valid access count in the AGT exceeds a preset threshold; If the preset threshold is exceeded, the prefetch address is obtained based on the offset address of the second spatial access mode that is similar to the first spatial access mode in the mode history table PHT and the region information of the access address, wherein the second spatial access mode in the PHT is the first spatial access mode that was kicked out in the AGT.

2. The method according to claim 1, characterized in that, Updating the Active Generation Table (AGT) based on the access address further includes... Determine whether the region information in the access address matches in the AGT; If no match is found, a first spatial access mode and a first valid access count corresponding to the region information are created in the AGT according to the access address; If a match is found, determine whether the access address in the AGT is a new first space access mode; If it is a new first spatial access mode, then update the first spatial access mode and the first valid access count corresponding to the region information in the AGT according to the access address.

3. The method according to claim 2, characterized in that, If no match is found, a first spatial access mode and a first valid access count corresponding to the region information are created in the AGT based on the access address, further including: Determine whether the AGT is full; If the AGT is not full, a first spatial access mode and a first valid access count corresponding to the region information are created in the AGT; If the AGT is full, a first space access mode is kicked out from the AGT and transferred to the PHT as the second space access mode according to preset rules.

4. The method according to claim 3, characterized in that, Further, according to preset rules, a first spatial access mode is kicked out from the AGT and transferred to the PHT as a second spatial access mode. After the first valid access count corresponding to the first space access mode that has been kicked out is removed from the PHT and used as the second valid access count, In the AGT, a first spatial access mode and a first valid access count corresponding to the region information are created.

5. The method according to claim 4, characterized in that, Based on the offset address corresponding to the second spatial access mode in the PHT that is similar to the first spatial access mode, and the region information of the access address, the prefetch address is further obtained, including: The first spatial access pattern is used to traverse the second spatial access pattern in the PHT. Perform a bitwise AND operation between the first space access pattern and each of the second space access patterns, and count the number of 1s after the AND operation. When the number of 1s exceeds a preset threshold, the second space access mode is determined to be similar to the first space access mode.

6. The method according to claim 5, characterized in that, After performing a bitwise AND operation between the first space access pattern and each of the second space access patterns, and counting the number of 1s after the AND operation, the process also includes... Calculate the ratio of the number of 1s to the second valid access count; When the ratio exceeds a preset ratio threshold, it is determined that the second space access mode is similar to the first space access mode.

7. The method according to claim 2, characterized in that, If a match is found, determining whether the access address in the AGT is a new first space access mode further includes... If the bit corresponding to the offset address of the access address in the first spatial access mode is 0, then the access address is a new first spatial access mode in the AGT.

8. The method according to claim 7, characterized in that, If it is a new first spatial access mode, then updating the first spatial access mode and the first valid access count corresponding to the region information in the AGT according to the access address further includes, Set the position corresponding to the offset address of the access address in the first space access mode to 1, and increment the first valid access count by 1.

9. The method according to claim 1, characterized in that, After obtaining the prefetch address, it also includes, The second spatial access pattern that occurs during prefetching is recorded as a historical prefetching pattern corresponding to the area information; When a prefetch occurs again, filter out offset addresses that are duplicates of the second space access pattern during the current prefetch and the historical prefetch pattern.

10. The method according to claim 9, characterized in that, The second spatial access pattern that occurs during prefetching is further included in the historical prefetching pattern corresponding to the region information. And mark the flag bits of the region information; When a prefetch occurs again, filtering out offset addresses where the second space access pattern of the current prefetch overlaps with the historical prefetch pattern further includes... If the flag bit of the region information has been marked, the second space access mode at the current prefetching time is masked using the historical prefetching mode. Based on the offset address of the masked second space access mode and the region information of the access address, the prefetch address for the next prefetch is obtained.

11. The method according to claim 10, characterized in that, After obtaining the prefetch address for the next prefetch, it also includes, The masked second space access pattern is bitwise ANDed with the historical prefetch pattern to obtain the historical prefetch pattern corresponding to the region information.

12. The method according to claim 10, characterized in that, The historical prefetching pattern and flag corresponding to the region information are stored in the AGT.

13. A prefetch address acquisition device, characterized in that, The device includes, The acquisition unit is used to obtain the access address; An update unit is configured to update the Active Generation Table (AGT) based on the access address, wherein the AGT includes a first spatial access pattern and a first valid access count corresponding to the region information in the access address; The judgment unit is used to determine whether the first valid access count in the AGT exceeds a preset threshold; If the prefetch unit exceeds the preset threshold, it is used to obtain the prefetch address based on the offset address corresponding to the second spatial access mode similar to the first spatial access mode in the mode history table PHT and the region information of the access address, wherein the second spatial access mode in the PHT is the first spatial access mode that has been kicked out in the AGT.

14. A processor, characterized in that... Includes a prefetcher that performs the method as described in any one of claims 1-12.

15. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1-12.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the method of any one of claims 1-12.

17. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-12.

Images