Method and device for evaluating subsequent process interconnection heat effect and electronic equipment

Abstract

The invention discloses a subsequent process interconnection heat effect evaluation method and device and electronic equipment. And based on the basic information of each through hole / metal wire, constructing an equivalent three-dimensional thermal resistance network of the subsequent process interconnection BEOL, and obtaining a BEOL equivalent thermal resistance netlist output by the network. On the basis of reserving the space structure information of the BEOL, complex physical field simulation and high-precision simulation with high cost do not need to be carried out, the simulation efficiency is improved, the simulation cost is reduced, and meanwhile the simulation precision and the space resolution are guaranteed. And then circuit simulation is carried out based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain a steady-state temperature value of each node. A static equivalent thermal resistance modeling process is converted into a dynamic process cooperating with simulation, and the accuracy of a circuit-level simulation result is improved. Thermal effect evaluation is carried out based on the steady-state temperature value, the BEOL equivalent thermal resistance net list and the through hole density of each metal layer, and data support is conveniently provided for device performance evaluation and circuit layout optimization.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method, apparatus and electronic device for evaluating the thermal effects of back-end process interconnects. Background Technology

[0002] With the development of integrated circuits, the density of devices in circuits is constantly increasing and the size of devices is constantly shrinking, which increases the difficulty of heat dissipation. Back-end of line (BEOL) interconnects, as heat dissipation channels in circuits, directly affect heat dissipation efficiency, thereby impacting the performance of individual devices and the reliability of the circuit. Evaluating the thermal effects of BEOLs can enable device performance assessment and circuit layout optimization.

[0003] In existing technologies, there are methods that simplify the BEOL (Boundary Thermal Resistance) to account for its heat dissipation effect and thus evaluate its thermal effects. However, this method cannot accurately obtain evaluation results because it ignores the size and structural information of the BEOL. On the other hand, the method of using high-precision finite element simulation to obtain comprehensive and accurate evaluation results is difficult to meet the needs of rapid iterative optimization of circuit layout design due to its high computational cost and low efficiency. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a method, apparatus, and electronic device for evaluating the thermal effects of back-end interconnects, which balances the accuracy, cost, and efficiency of the evaluation results when assessing the thermal effects of BEOLs, thereby facilitating data support for device performance evaluation and circuit layout optimization.

[0005] This application discloses a method for evaluating the interconnection thermal effects of downstream processes, the method comprising:

[0006] Based on the basic information of each via / metal line in the circuit, the via density of each metal layer is obtained, and the equivalent three-dimensional thermal resistance network of the interconnection BEOL of the subsequent process is constructed; the basic information includes the circuit netlist, as well as the number, size and material of each via / metal line;

[0007] Obtain the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network;

[0008] Circuit simulation is performed based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain the steady-state temperature values ​​of each node in the circuit.

[0009] Thermal effects are evaluated based on the steady-state temperature, the BEOL equivalent thermal resistance grid, and the through-hole density.

[0010] Optionally, the step of obtaining the via density of each metal layer based on the basic information of each via / metal line in the circuit, and constructing the equivalent three-dimensional thermal resistance network of the interconnect BEOL for subsequent processes, includes:

[0011] Calculate the through-hole density based on the quantity and the size;

[0012] Based on the aforementioned basic information, calculate the thermal resistance value corresponding to each through hole / metal line;

[0013] The equivalent three-dimensional thermal resistance network is constructed based on the thermal resistance value and the connection relationship.

[0014] Optionally, the step of calculating the thermal resistance value corresponding to each via / metal wire based on the basic information includes:

[0015] Obtain the product of the thermal conductivity of the material of each through-hole / metal wire and the heat transfer cross-sectional area of ​​each through-hole / metal wire; the heat transfer cross-sectional area is included in the dimensions;

[0016] The thermal resistance value is obtained by taking the ratio of the size of each through hole / metal wire in each heat conduction direction to the product of the two dimensions.

[0017] Optionally, obtaining the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network includes:

[0018] The equivalent three-dimensional thermal resistance network is obtained based on the thermal resistance value and the series and parallel connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network, and the total equivalent thermal resistance value of BEOL is output.

[0019] The equivalent three-dimensional thermal resistance network is obtained by outputting the BEOL equivalent thermal resistance netlist based on the thermal resistance value and the connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network.

[0020] Optionally, the step of performing circuit simulation based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain the steady-state temperature values ​​of each node in the circuit includes:

[0021] Circuit simulation is performed based on the circuit netlist, the BEOL equivalent thermal resistance netlist, and the device compact model to calculate the temperature value of each node in the circuit.

[0022] The BEOL equivalent thermal resistance grid table is updated based on the temperature value.

[0023] The temperature values ​​of each node in the circuit are recalculated based on the updated BEOL equivalent thermal resistance netlist.

[0024] The iterative operation continues until the temperature fluctuation is within a preset range, thus obtaining the steady-state temperature value.

[0025] Optionally, the thermal effect assessment based on the steady-state temperature value, the BEOL equivalent thermal resistance network, and the via density includes:

[0026] The steady-state temperature value is mapped to a three-dimensional space to generate a temperature distribution cloud map;

[0027] The thermal effect is evaluated by combining the temperature distribution cloud map, the BEOL equivalent thermal resistance grid, and the through-hole density.

[0028] Optionally, before constructing the equivalent three-dimensional thermal resistance network for interconnecting subsequent process BEOLs, the method further includes:

[0029] The layout data file of the first circuit is parsed to obtain the first basic information; the first circuit has not been used to construct the equivalent three-dimensional thermal resistance network, and the first basic information is used to construct the equivalent three-dimensional thermal resistance network of the first circuit.

[0030] The updated portion of the layout data file of the second circuit is identified, and the updated portion is parsed to obtain the second basic information; the second circuit has been constructed using the equivalent three-dimensional thermal resistance network, and the second basic information is used to update the equivalent three-dimensional thermal resistance network of the second circuit.

[0031] Optionally, after performing a thermal effect assessment, the method further includes:

[0032] The layout data file of the circuit is optimized based on the thermal effect evaluation results to obtain a new layout data file;

[0033] Identify and parse the updated portion of the new map data file to obtain new basic information;

[0034] Based on the new basic information, the equivalent three-dimensional thermal resistance network is reconstructed to evaluate the thermal effects.

[0035] Based on the above-mentioned method for evaluating the thermal effects of interconnected downstream processes, this application also discloses an apparatus for evaluating the thermal effects of interconnected downstream processes, comprising: a construction unit, an output unit, a simulation unit, and an evaluation unit.

[0036] The building unit is used to obtain the via density of each metal layer based on the basic information of each via / metal line in the circuit, and to build an equivalent three-dimensional thermal resistance network for the interconnection BEOL of the subsequent process; the basic information includes the circuit netlist, as well as the number, size and material of each via / metal line;

[0037] The output unit is used to obtain the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network.

[0038] The simulation unit is used to perform circuit simulation based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain the steady-state temperature value of each node in the circuit.

[0039] The evaluation unit is used to evaluate the thermal effect based on the steady-state temperature value, the BEOL equivalent thermal resistance grid, and the through-hole density.

[0040] Optionally, the building unit includes:

[0041] A density calculation subunit is used to calculate the through-hole density based on the quantity and the size;

[0042] The thermal resistance calculation subunit is used to calculate the thermal resistance value corresponding to each through hole / metal wire based on the basic information.

[0043] Construct sub-units to build the equivalent three-dimensional thermal resistance network based on the thermal resistance value and the connection relationship.

[0044] Optionally, the thermal resistance calculation subunit includes:

[0045] The multiplication sub-unit is used to obtain the product of the thermal conductivity of the material of each through-hole / metal wire and the heat transfer cross-sectional area of ​​each through-hole / metal wire; the heat transfer cross-sectional area is included in the dimension;

[0046] Compared to the sub-unit, the ratio of the size of each through-hole / metal wire in each heat conduction direction to the product is used to obtain the thermal resistance value.

[0047] Optionally, the output unit includes:

[0048] The equivalent thermal resistance value acquisition subunit is used to acquire the total equivalent thermal resistance value of BEOL output by the equivalent three-dimensional thermal resistance network based on the thermal resistance value and the series and parallel connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network.

[0049] The thermal resistance netlist acquisition subunit is used to acquire the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network based on the thermal resistance value and the connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network.

[0050] Optionally, the simulation unit includes:

[0051] The simulation subunit is used to perform circuit simulation based on the circuit netlist, the BEOL equivalent thermal resistance netlist, and the device compact model, and to calculate the temperature value of each node in the circuit.

[0052] The update sub-unit is used to update the BEOL equivalent thermal resistance netlist based on the temperature value;

[0053] The sub-unit is recalculated to recalculate the temperature values ​​of each node in the circuit based on the updated BEOL equivalent thermal resistance netlist.

[0054] An iterative subunit is used for iterative operation until the fluctuation of the temperature value is within a preset range, thereby obtaining the steady-state temperature value.

[0055] Optionally, the evaluation unit includes:

[0056] A sub-unit is generated to map the steady-state temperature value to a three-dimensional space and generate a temperature distribution cloud map;

[0057] The evaluation subunit is used to evaluate the thermal effect by combining the temperature distribution cloud map, the BEOL equivalent thermal resistance grid, and the through-hole density.

[0058] Optionally, the device further includes:

[0059] The parsing unit is used to parse the layout data file of the first circuit to obtain the first basic information; the first circuit has not been constructed with the equivalent three-dimensional thermal resistance network, and the first basic information is used to construct the equivalent three-dimensional thermal resistance network of the first circuit.

[0060] The identification unit is used to identify the updated portion in the layout data file of the second circuit, and parse the updated portion to obtain the second basic information; the second circuit has been constructed with the equivalent three-dimensional thermal resistance network, and the second basic information is used to update the equivalent three-dimensional thermal resistance network of the second circuit.

[0061] Optionally, the device further includes:

[0062] An optimization unit is used to optimize the layout data file of the circuit based on the thermal effect evaluation results to obtain a new layout data file;

[0063] The re-identification unit is used to identify and parse the updated portion of the new map data file to obtain new basic information;

[0064] The reconstruction unit is used to reconstruct the equivalent three-dimensional thermal resistance network based on the new basic information for thermal effect evaluation.

[0065] Based on the above-described method for evaluating the interconnection thermal effects of downstream processes, this application also discloses an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of any of the above-described methods when executing the program.

[0066] This application discloses a method, apparatus, and electronic device for evaluating the thermal effects of back-end interconnects. An equivalent three-dimensional thermal resistance network (TDR network) for the back-end interconnect BEOL is constructed based on the basic information of each via / metal line in the circuit. The circuit netlist, the via density of each metal layer, and the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network are obtained. While preserving the spatial structure information of the BEOL, complex physical field simulations and costly high-precision simulations are eliminated, improving simulation efficiency, reducing simulation costs, and ensuring simulation accuracy and spatial resolution. Subsequently, circuit simulation is performed based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain the steady-state temperature values ​​of each node in the circuit. The static equivalent thermal resistance modeling process is transformed into a dynamic process coordinated with simulation, improving the accuracy of circuit-level simulation results. Thermal effect evaluation is performed based on the steady-state temperature values, the BEOL equivalent thermal resistance netlist, and the via density, facilitating data support for device performance evaluation and circuit layout optimization. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0068] Figure 1a This is a flowchart illustrating a method for evaluating the interconnect thermal effects of downstream processes disclosed in an embodiment of this application.

[0069] Figure 1b This is a schematic diagram of constructing an equivalent three-dimensional thermal resistance network as disclosed in the embodiments of this application;

[0070] Figure 2 This is a flowchart illustrating another method for evaluating the interconnect thermal effects of downstream processes disclosed in an embodiment of this application.

[0071] Figure 3 This is a schematic diagram of the structure of an apparatus for evaluating the interconnected thermal effects of downstream processes, as disclosed in an embodiment of this application. Detailed Implementation

[0072] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0073] Example 1: This application discloses a method for evaluating the interconnection thermal effect of downstream processes.

[0074] For details, please refer to Figure 1a The method for evaluating the interconnection thermal effect of downstream processes disclosed in this embodiment includes the following steps:

[0075] Step 101: Based on the basic information of each via / metal line in the circuit, obtain the via density of each metal layer, and construct the equivalent three-dimensional thermal resistance network of the interconnect BEOL for subsequent processes.

[0076] In this embodiment, the method reads circuit-related technical documents, physical verification rule documents, and layout data files. Each via / metal line in the circuit is numbered in ascending order from lower to higher layers, and the circuit netlist and basic information of each via / metal line are parsed out. The circuit netlist describes the interconnections of circuit components (such as transistors, resistors, and capacitors). The basic information includes the number of cross-sections, geometric dimensions, vertex coordinates in the layout, connection relationships of each via / metal line, and the names of the metal and dielectric materials used. Memory can then be allocated for this basic information, and it can be stored hierarchically. The via density of each layer can also be calculated based on the number and size of vias in each metal layer.

[0077] In the method of this embodiment, two modes are supported during the acquisition of basic information: comprehensive analysis and differential analysis. The comprehensive analysis mode is suitable for entirely new layout designs or layout designs requiring a complete update. As an feasible solution, taking a completely new first circuit layout design that has not yet had its equivalent three-dimensional thermal resistance network constructed as an example, the first basic information can be obtained by comprehensively analyzing the layout data file of the first circuit. This first basic information is used to construct the equivalent three-dimensional thermal resistance network of the first circuit for the first time.

[0078] In contrast, the differentiated parsing mode is suitable for the iterative optimization process of layout design. As a feasible solution, this mode, after reading the layout data file, can automatically identify the changes made to the layout data file compared to previous layout data files. In practice, these changes are typically the coordinate values ​​of vias / metal lines in the layout. These changes are used to update the previous layout data file, while the unchanged parts of the previous layout data file remain unchanged, avoiding repeated parsing and improving parsing efficiency. Specifically, taking a second circuit that requires layout design optimization and has previously had an equivalent three-dimensional thermal resistance network constructed as an example, the updated parts in the second circuit's layout data file are identified, and these updated parts are parsed to obtain second basic information. This second basic information is used to update the equivalent three-dimensional thermal resistance network of the second circuit.

[0079] In the method of this embodiment, the thermal resistance value corresponding to each through-hole / metal wire can be calculated based on basic information. Specifically, this can be achieved by multiplying the thermal conductivity of the material of each through-hole / metal wire by the heat transfer cross-sectional area (which is a dimension) of each through-hole / metal wire. Then, the ratio of the dimension of each through-hole / metal wire in each heat conduction direction to the product is obtained to obtain the thermal resistance value. The formula can be: Thermal resistance value = through-hole / metal wire dimension in heat conduction direction ÷ (material thermal conductivity × heat transfer cross-sectional area). In actual operation, the through-hole dimension usually only requires attention to the through-hole length, while the metal wire needs to have two lengths in the two heat conduction directions, namely the horizontal and vertical directions.

[0080] In the method of this embodiment, since the metal wire involves heat conduction in both the vertical and horizontal directions, relevant empirical parameters can be set to segment the metal wire for calculating the thermal resistance values ​​in the vertical and horizontal directions, respectively. For example, a scaling factor 'a' (a>1) can be defined, and the metal wire segmentation position is located at a distance of "a×through-hole width" from the edge. The value of 'a' can be determined based on small-scale temperature field simulation and thermal resistance extraction results to ensure that the calculated thermal resistance value is close to the accurately extracted thermal resistance value.

[0081] In the method of this embodiment, considering the thermal conductivity of the dielectric layer, each thermal resistance can be further refined into a series-parallel network of via / metal wire thermal resistance and dielectric thermal resistance. That is, the equivalent series-parallel network will also be different depending on the thermal resistance modeling strategy. The material thermal conductivity is calculated by an approximate formula considering secondary temperature dependence and size effect, and the initial temperature can be set to 300K. For materials with anisotropic thermal conductivity, the thermal conductivity tensor matrix is ​​used to describe its thermal conductivity.

[0082] As a feasible approach, the relationship between the intrinsic thermal conductivity of a material and temperature can be described as follows:

[0083] k0=α+β·T+γ·T 2 (1)

[0084] In the formula, k0 is the thermal conductivity, T is the temperature, and α, β, and γ are fitting coefficients, which vary for different materials.

[0085] As another feasible approach, the relationship between the thermal conductivity of a thin-film material and its thickness can be described as follows:

[0086] k film =k0·F(d / Λ) (2)

[0087] (3)

[0088] In the formula, k filmLet be the thermal conductivity, d be the material thickness, Λ be the phonon mean free path, and e be the Euler number. t is the integral variable, which can be integrated over t from 1 to ∞, and the result of the integration does not include t.

[0089] In the method of this embodiment, an equivalent three-dimensional thermal resistance network is constructed based on the thermal resistance value and the connection relationship. For example... Figure 1b As shown, the vias and metal wires are equivalent to thermal resistances Rth in a series-parallel network, and the thermal resistance values ​​of each thermal resistance are calculated.

[0090] Step 102: Obtain the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network.

[0091] In the method of this embodiment, the equivalent three-dimensional thermal resistance network can calculate the total equivalent thermal resistance value of BEOL based on the aforementioned thermal resistance values ​​and the series-parallel connections of the thermal resistance elements in the equivalent three-dimensional thermal resistance network. The total equivalent thermal resistance value of BEOL can also be used to set the initial boundary thermal resistance for device thermal simulation. Simultaneously, the equivalent three-dimensional thermal resistance network outputs the BEOL equivalent thermal resistance netlist based on the aforementioned thermal resistance values ​​and the connection relationships of the thermal resistance elements in the equivalent three-dimensional thermal resistance network.

[0092] Step 103: Perform circuit simulation based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain the steady-state temperature value of each node in the circuit.

[0093] In the method of this embodiment, a circuit simulator can be used to read the circuit netlist, the BEOL equivalent thermal resistance netlist, and the device compact model to perform circuit (level) simulation and calculate the temperature values ​​of each node in the circuit. The device compact model is a pre-defined simplified mathematical model used to describe the behavior of semiconductor devices.

[0094] The specific temperature values ​​of each node are calculated based on the BEOL equivalent thermal resistance netlist and the simulated input power consumption of each node, using the linear superposition theory of heat and the thermal resistance matrix theory. Since an increase in temperature changes the thermal conductivity, which in turn affects the equivalent thermal resistance, the temperature values ​​of each node require multiple iterative calculations to obtain a steady-state temperature. One feasible approach is to read the temperature values ​​of each node, recalculate the material's thermal conductivity, update the BEOL equivalent thermal resistance netlist, and then recalculate the temperature values ​​of each node in the circuit based on the updated BEOL equivalent thermal resistance netlist. This iterative operation continues until the temperature fluctuations are within a preset range, ultimately yielding the steady-state temperature value.

[0095] Step 104: Based on the steady-state temperature value, the BEOL equivalent thermal resistance grid, and the through-hole density, perform a thermal effect assessment.

[0096] In the method of this embodiment, the steady-state temperature values ​​of each node are mapped to three-dimensional space to generate a temperature distribution cloud map. By combining the temperature distribution cloud map, the BEOL equivalent thermal resistance netlist, and the total equivalent thermal resistance and via density of the BEOL, thermal effect assessment can be performed.

[0097] Furthermore, based on the thermal effect evaluation results, the circuit layout data file can be optimized to obtain a new layout data file. After identifying and parsing the updated portions of the new layout data file to obtain new basic information, differentiated analysis can be used based on this new basic information to reconstruct the equivalent three-dimensional thermal resistance network for thermal effect evaluation. This process is repeated multiple times to generate the equivalent three-dimensional thermal resistance network and perform circuit-level simulation, achieving iterative optimization of the layout design.

[0098] The method described in this embodiment parses and stores basic information such as the geometric parameters and connection relationships of each via / metal wire, which not only improves the efficiency of thermal resistance calculation and layout design iterative optimization, but also provides key data support for the subsequent construction of an equivalent three-dimensional thermal resistance network. Secondly, based on the analyzed geometric parameters and connection relationships, an equivalent three-dimensional thermal resistance network (BEOL) is constructed, avoiding complex physical field simulations and significantly improving simulation efficiency. Simultaneously, it maximizes the preservation of spatial structure information of subsequent interconnects, thereby improving the model's accuracy and spatial resolution. Furthermore, considering the temperature dependence of material thermal conductivity, the temperature and equivalent thermal resistance netlist are iteratively updated during circuit-level simulation and equivalent three-dimensional thermal resistance network node temperature value calculation, transforming the static equivalent thermal resistance modeling process into a dynamic process coordinated with simulation. This dynamic modeling method fully considers material properties and effectively improves the accuracy of circuit-level simulation results. Finally, while generating the equivalent three-dimensional thermal resistance network, the total equivalent thermal resistance value and the via density of each layer are calculated and output. After simulation, a temperature distribution cloud map can be generated based on the spatial structure information of the back-end interconnection, providing multi-level convenient information for thermal effect analysis and layout design optimization.

[0099] Example 2: This application discloses another method for evaluating the interconnection heat effect of downstream processes. Please refer to [link / reference]. Figure 2 This embodiment describes the entire process of evaluating the interconnected thermal effects of downstream processes.

[0100] Step 201: Parse the layout data file corresponding to the target circuit to obtain the circuit netlist of the target circuit and the basic information of each via / metal line in the target circuit.

[0101] Step 202: Based on the number, size, and material information of each via / metal line in the basic information, calculate the via density in each metal layer and the corresponding thermal resistance value of each via / metal line.

[0102] Step 203: Construct an equivalent three-dimensional thermal resistance network based on the thermal resistance value and the connection relationship of each through hole / metal wire.

[0103] Step 204: Output the BEOL equivalent thermal resistance netlist based on the thermal resistance value and the connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network.

[0104] Step 205: Read the BEOL equivalent thermal resistance netlist and the target circuit netlist using a circuit simulator, perform circuit simulation, and obtain the temperature values ​​of each node in the target circuit.

[0105] Step 206: Update the BEOL equivalent thermal resistance netlist based on the temperature value, and recalculate the temperature value of each node until the temperature value stabilizes within the preset range to obtain the steady-state temperature value.

[0106] Step 207: Map the steady-state temperature value to three-dimensional space to generate a temperature distribution cloud map.

[0107] Step 208: Combine the temperature distribution cloud map, BEOL equivalent thermal resistance grid, and through-hole density to evaluate the thermal effect.

[0108] Based on the method for evaluating the interconnection thermal effects of downstream processes disclosed in the above embodiments, this embodiment correspondingly discloses an apparatus for evaluating the interconnection thermal effects of downstream processes. Please refer to... Figure 3 The device for evaluating the interconnected thermal effects of downstream processes includes: a construction unit 301, an output unit 302, a simulation unit 303, and an evaluation unit 304.

[0109] The construction unit 301 is used to obtain the via density of each metal layer based on the basic information of each via / metal line in the circuit, and to construct the equivalent three-dimensional thermal resistance network of the interconnect BEOL of the subsequent process; the basic information includes the circuit netlist, as well as the number, size and material of each via / metal line;

[0110] The output unit 302 is used to obtain the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network.

[0111] The simulation unit 303 is used to perform circuit simulation based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain the steady-state temperature value of each node in the circuit.

[0112] The evaluation unit 304 is used to evaluate the thermal effect based on the steady-state temperature value, the BEOL equivalent thermal resistance grid, and the through-hole density.

[0113] Optionally, the building unit 301 includes:

[0114] A density calculation subunit is used to calculate the through-hole density based on the quantity and the size;

[0115] The thermal resistance calculation subunit is used to calculate the thermal resistance value corresponding to each through hole / metal wire based on the basic information.

[0116] Construct sub-units to build the equivalent three-dimensional thermal resistance network based on the thermal resistance value and the connection relationship.

[0117] Optionally, the thermal resistance calculation subunit includes:

[0118] The multiplication sub-unit is used to obtain the product of the thermal conductivity of the material of each through-hole / metal wire and the heat transfer cross-sectional area of ​​each through-hole / metal wire; the heat transfer cross-sectional area is included in the dimension;

[0119] Compared to the sub-unit, the ratio of the size of each through-hole / metal wire in each heat conduction direction to the product is used to obtain the thermal resistance value.

[0120] Optionally, the output unit 302 includes:

[0121] The equivalent thermal resistance value acquisition subunit is used to acquire the total equivalent thermal resistance value of BEOL output by the equivalent three-dimensional thermal resistance network based on the thermal resistance value and the series and parallel connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network.

[0122] The thermal resistance netlist acquisition subunit is used to acquire the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network based on the thermal resistance value and the connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network.

[0123] Optionally, the simulation unit 303 includes:

[0124] The simulation subunit is used to perform circuit simulation based on the circuit netlist, the BEOL equivalent thermal resistance netlist, and the device compact model, and to calculate the temperature value of each node in the circuit.

[0125] The update sub-unit is used to update the BEOL equivalent thermal resistance netlist based on the temperature value;

[0126] The sub-unit is recalculated to recalculate the temperature values ​​of each node in the circuit based on the updated BEOL equivalent thermal resistance netlist.

[0127] An iterative subunit is used for iterative operation until the fluctuation of the temperature value is within a preset range, thereby obtaining the steady-state temperature value.

[0128] Optionally, the evaluation unit 304 includes:

[0129] A sub-unit is generated to map the steady-state temperature value to a three-dimensional space and generate a temperature distribution cloud map;

[0130] The evaluation subunit is used to evaluate the thermal effect by combining the temperature distribution cloud map, the BEOL equivalent thermal resistance grid, and the through-hole density.

[0131] Optionally, the device further includes:

[0132] The parsing unit is used to parse the layout data file of the first circuit to obtain the first basic information; the first circuit has not been constructed with the equivalent three-dimensional thermal resistance network, and the first basic information is used to construct the equivalent three-dimensional thermal resistance network of the first circuit.

[0133] The identification unit is used to identify the updated portion in the layout data file of the second circuit, and parse the updated portion to obtain the second basic information; the second circuit has been constructed with the equivalent three-dimensional thermal resistance network, and the second basic information is used to update the equivalent three-dimensional thermal resistance network of the second circuit.

[0134] Optionally, the device further includes:

[0135] An optimization unit is used to optimize the layout data file of the circuit based on the thermal effect evaluation results to obtain a new layout data file;

[0136] The re-identification unit is used to identify and parse the updated portion of the new map data file to obtain new basic information;

[0137] The reconstruction unit is used to reconstruct the equivalent three-dimensional thermal resistance network based on the new basic information for thermal effect evaluation.

[0138] Based on the above-described method for evaluating the interconnection thermal effects of downstream processes, this application also discloses an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of any of the above-described methods when executing the program.

[0139] The embodiments in this specification are described in a progressive manner. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant details can be found in the method section.

[0140] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0141] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0142] The features described in the embodiments of this specification can be substituted for or combined with each other, so that those skilled in the art can implement or use this application.

[0143] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for evaluating the interconnected thermal effects of downstream processes, characterized in that, include: Based on the basic information of each via / metal line in the circuit, the via density of each metal layer is obtained, and the equivalent three-dimensional thermal resistance network of the interconnection BEOL of the subsequent process is constructed; the basic information includes the circuit netlist, as well as the number, size and material of each via / metal line; Obtain the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network; Circuit simulation is performed based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain the steady-state temperature values ​​of each node in the circuit. Thermal effects are evaluated based on the steady-state temperature, the BEOL equivalent thermal resistance grid, and the through-hole density.

2. The method according to claim 1, characterized in that, The process of obtaining the via density of each metal layer based on the basic information of each via / metal line in the circuit, and constructing the equivalent three-dimensional thermal resistance network for interconnecting the BEOL in subsequent processes, includes: Calculate the through-hole density based on the quantity and the size; Based on the aforementioned basic information, calculate the thermal resistance value corresponding to each through hole / metal line; The equivalent three-dimensional thermal resistance network is constructed based on the thermal resistance value and the connection relationship.

3. The method according to claim 2, characterized in that, The calculation of the thermal resistance value corresponding to each through-hole / metal line based on the basic information includes: Obtain the product of the thermal conductivity of the material of each through-hole / metal wire and the heat transfer cross-sectional area of ​​each through-hole / metal wire; the heat transfer cross-sectional area is included in the dimensions; The thermal resistance value is obtained by taking the ratio of the size of each through hole / metal wire in each heat conduction direction to the product of the two dimensions.

4. The method according to claim 2, characterized in that, The process of obtaining the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network includes: The equivalent three-dimensional thermal resistance network is obtained based on the thermal resistance value and the series and parallel connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network, and the total equivalent thermal resistance value of BEOL is output. The equivalent three-dimensional thermal resistance network is obtained by outputting the BEOL equivalent thermal resistance netlist based on the thermal resistance value and the connection relationship of the thermal resistance elements in the equivalent three-dimensional thermal resistance network.

5. The method according to claim 1, characterized in that, The circuit simulation based on the circuit netlist and the BEOL equivalent thermal resistance netlist, to obtain the steady-state temperature values ​​of each node in the circuit, includes: Circuit simulation is performed based on the circuit netlist, the BEOL equivalent thermal resistance netlist, and the device compact model to calculate the temperature value of each node in the circuit. The BEOL equivalent thermal resistance grid table is updated based on the temperature value. The temperature values ​​of each node in the circuit are recalculated based on the updated BEOL equivalent thermal resistance netlist. The iterative operation continues until the temperature fluctuation is within a preset range, thus obtaining the steady-state temperature value.

6. The method according to claim 1, characterized in that, The thermal effect assessment based on the steady-state temperature value, the BEOL equivalent thermal resistance mesh, and the via density includes: The steady-state temperature value is mapped to a three-dimensional space to generate a temperature distribution cloud map; The thermal effect is evaluated by combining the temperature distribution cloud map, the BEOL equivalent thermal resistance grid, and the through-hole density.

7. The method according to any one of claims 1-6, characterized in that, Before constructing the equivalent three-dimensional thermal resistance network for the interconnected BEOL of subsequent processes, the method further includes: The layout data file of the first circuit is parsed to obtain the first basic information; the first circuit has not been used to construct the equivalent three-dimensional thermal resistance network, and the first basic information is used to construct the equivalent three-dimensional thermal resistance network of the first circuit. The updated portion of the layout data file of the second circuit is identified, and the updated portion is parsed to obtain the second basic information; the second circuit has been constructed using the equivalent three-dimensional thermal resistance network, and the second basic information is used to update the equivalent three-dimensional thermal resistance network of the second circuit.

8. The method according to claim 7, characterized in that, After assessing the thermal effects, the method further includes: The layout data file of the circuit is optimized based on the thermal effect evaluation results to obtain a new layout data file; Identify and parse the updated portion of the new map data file to obtain new basic information; Based on the new basic information, the equivalent three-dimensional thermal resistance network is reconstructed to evaluate the thermal effects.

9. An apparatus for evaluating the interconnected thermal effects of downstream processes, characterized in that, include: The system comprises a construction unit, an output unit, a simulation unit, and an evaluation unit. The building unit is used to obtain the via density of each metal layer based on the basic information of each via / metal line in the circuit, and to build an equivalent three-dimensional thermal resistance network for the interconnection BEOL of the subsequent process; the basic information includes the circuit netlist, as well as the number, size and material of each via / metal line; The output unit is used to obtain the BEOL equivalent thermal resistance netlist output by the equivalent three-dimensional thermal resistance network. The simulation unit is used to perform circuit simulation based on the circuit netlist and the BEOL equivalent thermal resistance netlist to obtain the steady-state temperature value of each node in the circuit. The evaluation unit is used to evaluate the thermal effect based on the steady-state temperature value, the BEOL equivalent thermal resistance grid, and the through-hole density.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method as described in any one of claims 1-8.

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