Power amplifier structure

Abstract

The invention relates to the technical field of wireless communication, and provides a power amplifier structure. The power amplifier structure comprises an input matching circuit, a plurality of first driving stage amplifiers, a second driving stage amplifier, an inter-stage matching circuit, a plurality of first power stage amplifiers, a plurality of second power stage amplifiers, an output matching circuit, a first biasing circuit, a second biasing circuit and a third biasing circuit. When the output power of the input matching circuit is greater than or equal to the preset working power, the first biasing circuit and the second biasing circuit respectively control the first driving stage amplifier and the first power stage amplifier to be switched on to work, and the third biasing circuit respectively controls the second driving stage amplifier and the second power stage amplifier to be switched off; and when the output power of the input matching circuit is smaller than the preset working power, the first driving stage amplifier and the first power stage amplifier are closed, and the second driving stage amplifier and the second power stage amplifier are conducted to work. According to the invention, the power consumption during low-power work can be reduced.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a power amplifier structure. Background Technology

[0002] With the advancement of the information age, wireless communication technology has developed rapidly, with mobile phones, wireless LANs, and Bluetooth becoming an indispensable part of its development. The progress of wireless communication technology is inseparable from the development of radio frequency circuits and microwave technology.

[0003] The power amplifier (PA) structure of the related technology includes an input matching circuit, a power amplifier, and an output matching circuit connected in sequence. The input matching circuit receives the radio frequency signal and performs impedance matching, then the signal is amplified by the power amplifier, and finally output after matching by the output matching circuit, thus realizing the power amplification output process. Currently, this power amplifier structure is widely used in radio frequency power amplifiers.

[0004] However, the power amplifier structure described above typically uses a shared high-power and low-power channel. At low power, power consumption is reduced by decreasing the bias current of the transistors. However, because many transistors are still working at low power, the power consumption cannot be reduced to a low level, affecting the battery life of mobile devices. Summary of the Invention

[0005] To address the shortcomings of the existing technologies, this invention proposes a power amplifier structure to solve the problem of high power consumption when the existing power amplifier structure operates at low power.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: This invention provides a power amplifier structure, which includes an input matching circuit, multiple first driver stage amplifiers, second driver stage amplifiers, an interstage matching circuit, multiple first power stage amplifiers, multiple second power stage amplifiers, an output matching circuit, a first bias circuit, a second bias circuit, and a third bias circuit. The input terminal of the input matching circuit is used to receive radio frequency signals, and the output terminal of the input matching circuit is connected to the input terminals of the first driver stage amplifier and the second driver stage amplifier, respectively. The output terminals of the first driver stage amplifier and the second driver stage amplifier are both connected to the input terminal of the interstage matching circuit, and the output terminal of the interstage matching circuit is connected to the input terminals of the first power stage amplifier and the second power stage amplifier, respectively. The output terminals of the first power stage amplifier and the second power stage amplifier are both connected to the output matching circuit. The first bias circuit is used to provide a bias voltage for the first driver stage amplifier, the second bias circuit is used to provide a bias voltage for the first power stage amplifier, and the third bias circuit is used to provide bias voltages for the second driver stage amplifier and the second power stage amplifier, respectively. The preset operating power is such that when the output power of the input matching circuit is greater than or equal to the preset operating power, the first bias circuit and the second bias circuit respectively control the first driver stage amplifier and the first power stage amplifier to turn on, and the third bias circuit respectively controls the second driver stage amplifier and the second power stage amplifier to turn off. When the output power of the input matching circuit is less than the preset operating power, the first bias circuit and the second bias circuit respectively control the first driver stage amplifier and the first power stage amplifier to turn off, and the third bias circuit respectively controls the second driver stage amplifier and the second power stage amplifier to turn on.

[0007] Preferably, the first driver stage amplifier comprises M units, and the first power stage amplifier comprises N units, where M and N are positive integers.

[0008] Preferably, a plurality of the first driver stage amplifiers are connected in parallel, and a plurality of the first power stage amplifiers are connected in parallel.

[0009] Preferably, the second power stage amplifier comprises K units, where K is a positive integer.

[0010] Preferably, multiple second power stage amplifiers are connected in parallel.

[0011] Preferably, the output matching circuit includes a first capacitor, a second capacitor, a first inductor, and a second inductor; The first end of the first inductor serves as the input end of the output matching circuit. The second end of the first inductor is connected to the first end of the first capacitor and the first end of the second inductor. The second end of the first capacitor is grounded. The second end of the second inductor is connected to the first end of the second capacitor and serves as the output end of the output matching circuit. The second end of the second capacitor is grounded.

[0012] Compared with related technologies, in the embodiments of the present invention, the input terminal of the input matching circuit is used to receive radio frequency signals, and the output terminal of the input matching circuit is connected to the input terminals of the first driver stage amplifier and the second driver stage amplifier, respectively; the output terminal of the first driver stage amplifier is connected to the output terminal of the second driver stage amplifier, and the output terminal of the first driver stage amplifier is also connected to the input terminal of the interstage matching circuit, the output terminal of the interstage matching circuit is connected to the input terminals of the first power stage amplifier and the second power stage amplifier, and the output terminal of the first power stage amplifier is connected to the output terminal of the second power stage amplifier; a preset operating power is used, and when the output power of the input matching circuit is greater than or equal to the preset operating power, the first bias circuit and the second bias circuit respectively control the first driver stage amplifier and the first power stage amplifier to conduct. The third bias circuit controls the second driver stage amplifier and the second power stage amplifier to turn off respectively. When the output power of the input matching circuit is less than the preset operating power, the first bias circuit and the second bias circuit control the first driver stage amplifier and the first power stage amplifier to turn off respectively, and the third bias circuit controls the second driver stage amplifier and the second power stage amplifier to turn on respectively. In this way, the driver stage and the power stage are controlled in two parts. When operating in the high-power state of the first threshold power, the first driver stage amplifier and the first power stage amplifier are driven to work. When operating in the low-power state of the second threshold power, the second driver stage amplifier and the second power stage amplifier are driven to work. This ensures both high-power performance and low-power power consumption, further reducing the low-power power consumption of the power amplifier. Attached Figure Description

[0013] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 A block diagram of a power amplifier structure provided in an embodiment of the present invention; Figure 2 A circuit diagram of the output matching circuit of the power amplifier structure provided in an embodiment of the present invention.

[0014] Among them, 100 is the power amplifier structure, 1 is the input matching circuit, 2 is the first driver stage amplifier, 3 is the second driver stage amplifier, 4 is the interstage matching circuit, 5 is the first power stage amplifier, 6 is the second power stage amplifier, 7 is the output matching circuit, 8 is the first bias circuit, 9 is the second bias circuit, and 10 is the third bias circuit. Detailed Implementation

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0016] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Please see Figures 1-2 As shown, this embodiment of the invention provides a power amplifier structure 100, which includes an input matching circuit 1, multiple first driver stage amplifiers 2, second driver stage amplifiers 3, interstage matching circuit 4, multiple first power stage amplifiers 5, multiple second power stage amplifiers 6, an output matching circuit 7, a first bias circuit 8, a second bias circuit 9, and a third bias circuit 10.

[0019] The input terminal of the input matching circuit 1 is used to receive radio frequency signals. The output terminal of the input matching circuit 1 is connected to the input terminals of the first driver stage amplifier 2 and the second driver stage amplifier 3, respectively. The output terminal of the first driver stage amplifier 2 is connected to the output terminal of the second driver stage amplifier 3, and the output terminal of the first driver stage amplifier 2 is also connected to the input terminal of the interstage matching circuit 4. The output terminal of the interstage matching circuit 4 is connected to the input terminals of the first power stage amplifier 5 and the second power stage amplifier 6, respectively. The output terminal of the first power stage amplifier 5 is connected to the output terminal of the second power stage amplifier 6, and the output terminal of the first power stage amplifier 5 is also connected to the output matching circuit 7. The first bias circuit 8 is used to provide a bias voltage for the first driver stage amplifier 2, the second bias circuit 9 is used to provide a bias voltage for the first power stage amplifier 5, and the third bias circuit 10 is used to provide bias voltages for the second driver stage amplifier 3 and the second power stage amplifier 6, respectively.

[0020] When the output power of the input matching circuit 1 is greater than or equal to the preset operating power, the first bias circuit 8 and the second bias circuit 9 respectively control the first driver stage amplifier 2 and the first power stage amplifier 5 to operate, and the third bias circuit 10 respectively controls the second driver stage amplifier 3 and the second power stage amplifier 6 to turn off.

[0021] When the output power of the input matching circuit 1 is less than the preset operating power, the first bias circuit 8 and the second bias circuit 9 respectively control the first driver stage amplifier 2 and the first power stage amplifier 5 to turn off, and the third bias circuit 10 respectively controls the second driver stage amplifier 3 and the second power stage amplifier 6 to turn on. The preset operating power is a set output power value; when the output power of the input matching circuit 1 is less than the preset operating power, it is in a low-power operating state. Optionally, the first driver stage amplifier 2 and the first power stage amplifier 5 operate as high-power circuits, and the second driver stage amplifier 3 and the second power stage amplifier 6 operate as low-power circuits. This divides the driver stage and power stage into two parts for control. When operating in the high-power state with the first threshold power, the first driver stage amplifier 2 and the first power stage amplifier 5 are driven; when operating in the low-power state with the second threshold power, the second driver stage amplifier 3 and the second power stage amplifier 6 are driven, thus ensuring both high-power performance and low-power power consumption, further reducing the low-power power consumption of the power amplifier.

[0022] Specifically, during high-power operation, both the first bias circuit 8 and the second bias circuit 9 operate simultaneously, while during low-power operation, only the third bias circuit 10 operates. During low-power operation, if the number of transistors is large, the quiescent current is high to keep the transistors on, resulting in high power consumption. Therefore, this invention significantly reduces power consumption by turning off most transistors and turning on only a small number during low-power operation. If the number of transistors in the first driver stage is already small during high-power operation, the transistors in the second driver stage amplifier 3 can be replaced by those in the first driver stage amplifier 2.

[0023] In particular, the power amplifier structure 100 allows the transistors to operate completely independently in both high-power and low-power modes. The high and low power modes can be designed using independent transistor parameters and matching parameters, which can better optimize the performance of low-power modes.

[0024] In this embodiment, the first driver stage amplifier 2 comprises M transistors, and the first power stage amplifier 5 comprises N transistors, where M and N are positive integers. The maximum output current of a single transistor has a physical upper limit, which cannot meet the demands of high-power loads. When multiple transistors are connected in parallel, the total output current is approximately n times the current of a single transistor (n is the number of transistors in parallel). Combined with the load voltage, this significantly increases the maximum output power of the circuit. Preferably, as follows... Figure 1 As shown, the first driver stage amplifier 2 includes two units, and the first power stage amplifier 5 includes four units. Of course, there can also be multiple units.

[0025] In this embodiment, multiple first driver stage amplifiers 2 are connected in parallel, and multiple first power stage amplifiers 5 are connected in parallel.

[0026] In this embodiment, the second power stage amplifier 6 comprises K units, where K is a positive integer. Preferably, there is one second driver stage amplifier 3 and two second power stage amplifiers 6. Of course, there can also be multiple units.

[0027] In this embodiment, multiple second power stage amplifiers 6 are connected in parallel. When multiple second power stage amplifiers 6 are connected in parallel, the total output current is approximately n times the current of a single transistor (where n is the number of transistors connected in parallel). Combined with the load voltage, this significantly increases the maximum output power of the circuit.

[0028] In this embodiment, the output matching circuit 7 includes a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2. The first terminal of the first inductor L1 serves as the input terminal of the output matching circuit 7. The second terminal of the first inductor L1 is connected to both the first terminal of the first capacitor C1 and the first terminal of the second inductor L2. The second terminal of the first capacitor C1 is grounded. The second terminal of the second inductor L2 is connected to the first terminal of the second capacitor C2 and serves as the output terminal of the output matching circuit 7. The second terminal of the second capacitor C2 is grounded. The output matching circuit 7 acts as a bridge connecting the power amplifier and the load. It achieves maximum power transmission through impedance matching and transformation, suppresses harmonics and purifies the signal through filtering and frequency selection, ultimately ensuring the efficient and stable operation of the entire system. Its parameters (L and C values) need to be determined based on the operating frequency, amplifier output impedance, and load impedance. It can achieve impedance transformation to adapt to different impedance requirements, further suppress filtering and harmonics, and facilitate stable signal transmission.

[0029] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A power amplifier structure, characterized in that, The power amplifier structure includes an input matching circuit, multiple first driver stage amplifiers, a second driver stage amplifier, an interstage matching circuit, multiple first power stage amplifiers, multiple second power stage amplifiers, an output matching circuit, a first bias circuit, a second bias circuit, and a third bias circuit. The input terminal of the input matching circuit is used to receive radio frequency signals, and the output terminal of the input matching circuit is connected to the input terminal of the first driver stage amplifier and the input terminal of the second driver stage amplifier, respectively. The output terminals of the first driver stage amplifier and the second driver stage amplifier are both connected to the input terminal of the interstage matching circuit, and the output terminal of the interstage matching circuit is connected to the input terminal of the first power stage amplifier and the input terminal of the second power stage amplifier, respectively. The output terminals of the first power stage amplifier and the second power stage amplifier are both connected to the output matching circuit. The first bias circuit is used to provide a bias voltage for the first driver stage amplifier, the second bias circuit is used to provide a bias voltage for the first power stage amplifier, and the third bias circuit is used to provide bias voltages for the second driver stage amplifier and the second power stage amplifier, respectively. The preset operating power is such that when the output power of the input matching circuit is greater than or equal to the preset operating power, the first bias circuit and the second bias circuit respectively control the first driver stage amplifier and the first power stage amplifier to turn on, and the third bias circuit respectively controls the second driver stage amplifier and the second power stage amplifier to turn off. When the output power of the input matching circuit is less than the preset operating power, the first bias circuit and the second bias circuit respectively control the first driver stage amplifier and the first power stage amplifier to turn off, and the third bias circuit respectively controls the second driver stage amplifier and the second power stage amplifier to turn on.

2. The power amplifier structure according to claim 1, characterized in that, The first driver stage amplifier comprises M units, and the first power stage amplifier comprises N units, where M and N are positive integers.

3. The power amplifier structure according to claim 2, characterized in that, Multiple first driver stage amplifiers are connected in parallel, and multiple first power stage amplifiers are connected in parallel.

4. The power amplifier structure according to claim 2, characterized in that, The second power stage amplifier comprises K units, where K is a positive integer.

5. The power amplifier structure according to claim 4, characterized in that, Multiple second power stage amplifiers are connected in parallel.

6. The power amplifier structure according to claim 1, characterized in that, The output matching circuit includes a first capacitor, a second capacitor, a first inductor, and a second inductor; The first end of the first inductor serves as the input end of the output matching circuit. The second end of the first inductor is connected to the first end of the first capacitor and the first end of the second inductor. The second end of the first capacitor is grounded. The second end of the second inductor is connected to the first end of the second capacitor and serves as the output end of the output matching circuit. The second end of the second capacitor is grounded.

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