Cascode switching circuit and method for driving cascode device

Abstract

The invention discloses a cascode switch circuit and a method for driving a cascode device. The cascode switch circuit comprises a cascode device, and the cascode device comprises a JFET (Junction Field Effect Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) which are coupled in a cascode topology. The cascode switching circuit also includes a gate driver having a gate driver input configured to receive a switching input signal and a gate driver output coupled to a gate of the MOSFET and configured to switch the MOSFET between a MOSFET on state and a MOSFET off state based on the switching input signal. In addition to this, the cascode switching circuit includes a current source coupled between the gate driver output and a gate of the JFET and configured to forward bias a gate-source junction of the JFET when the cascode device is in an on state.

Description

[0001] This application claims the benefit of provisional patent application No. 63 / 669,729, filed on July 11, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] The technology disclosed herein relates generally to power electronic devices, and more particularly to cascode switching circuits and gate driving methods for driving switches in a cascode configuration. Background Technology

[0003] Power electronics can be used to control the conversion and distribution of electrical power. For example, a switching power converter can be used to generate a direct current ("DC") voltage from an alternating current ("AC") voltage by switching the current flowing through a magnetic element, such as an inductor. Conversely, an inverter can be used to convert a DC voltage to an AC voltage. In these and other forms of power electronics, power switches can be used to control the conversion and flow of power through a power conversion system and to the electronic circuitry powered by the device. Specifically, power conversion can be performed by switching a power converter or inverter that operates by switching one or more corresponding switches between an on state (also known as a closed state or conductive state) and an off state (also known as an open state or non-conductive state). Power switches can also be used in a variety of solid-state protection applications to quickly isolate and protect circuits and systems from faults such as overcurrent conditions, overvoltage conditions, and / or short-circuit conditions.

[0004] Common-source cascode switches can be used as power switches in power conversion systems and / or solid-state protection applications to drive high currents and withstand large voltages. When used in such power applications, it may be desirable for one or more common-source cascode switches to have low on-state resistance, thereby limiting unwanted power losses and heat generation. The inventors of the embodiments of this disclosure have recognized that reducing the on-state resistance of a common-source cascode switch for a given application typically comes at the cost of a larger die size and increased cost. The inventors of the embodiments of this disclosure have also recognized that providing a higher saturation current (and therefore a higher surge current capability) for a given application typically also comes at the cost of a larger die size and increased cost. The embodiments of this disclosure can address one or more of these challenges. Summary of the Invention

[0005] The aspects disclosed in the specific embodiments relate to a power switching device that is operable to reduce on-state resistance and increase saturation current (and thus increase surge current capability).

[0006] According to one example, a cascode switching circuit includes: a cascode device comprising a JFET and a MOSFET coupled in a cascode topology; a gate driver having a gate driver input configured to receive a switch input signal and a gate driver output coupled to the gate of the MOSFET and configured to switch the MOSFET between an on-state and an off-state based on the switch input signal; and a current source coupled between the gate driver output and the gate of the JFET and configured to forward bias the gate-source junction of the JFET when the cascode device is in an on-state. In some examples, the cascode switching circuit further includes a voltage clamp coupled to the gate of the JFET and configured to prevent the gate voltage of the JFET from exceeding a clamping threshold. In some examples, the voltage clamp includes a Zener diode. In the same or different examples, the cascode switching circuit further includes a resistor coupled in series between the gate driver output and the gate of the MOSFET. In the same or different examples, the cascode switching circuit also includes a capacitor coupled in parallel to the current source. In the same or different examples, the cascode switching circuit also includes a junction resistor coupled between the current source and the gate of the JFET. In the same or different examples, the current source includes a resistor. In the same or different examples, the MOSFET is an NMOS transistor. In the same or different examples, the MOSFET is a silicon MOSFET, and the JFET is a silicon carbide JFET. In the same or different examples, the cascode switching circuit also includes a junction temperature sensor coupled across the gate and source of the JFET and configured to output a sensor voltage signal based on a temperature change of the JFET.

[0007] According to another example, the cascode switching circuit includes: a cascode device comprising a JFET and a MOSFET coupled in a cascode topology; a gate driver having a gate driver input configured to receive a switching input signal and a gate driver output coupled to the gate of the MOSFET and configured to switch the MOSFET between an on-state and an off-state based on the switching input signal; and a current source coupled between the power source and the gate of the JFET and configured to forward bias the gate-source junction of the JFET when the cascode device is in the on-state. In some examples, the cascode switching circuit further includes a voltage clamp coupled to the gate of the JFET and configured to prevent the gate voltage of the JFET from exceeding a clamping threshold. In some examples, the voltage clamp includes a Zener diode. In the same or different examples, the cascode switching circuit further includes a resistor coupled in series between the gate driver output and the gate of the MOSFET. In the same or different examples, the current source includes a resistor. In the same or different examples, the MOSFET is an NMOS transistor. In the same or different examples, the MOSFET is a silicon MOSFET, and the JFET is a silicon carbide JFET. In the same or different examples, the cascode switching circuit also includes a junction temperature sensor coupled across the gate and source of the JFET and configured to output a sensor voltage signal based on the temperature change of the JFET.

[0008] Another example provides a method for operating a cascode device including a JFET and a MOSFET coupled in a cascode topology, the method comprising: receiving a switching input signal; switching the MOSFET between an on-state and an off-state based on the switching input signal; and forward biasing the gate-source junction of the JFET with a current source when the cascode device is in the on-state. In some examples, the method further includes providing a pulsed current to the gate of the JFET with a capacitor coupled in parallel to the current source and in response to the switching input signal. In the same or different examples, the method further includes controlling the charging and discharging times of the JFET's gate with a resistor coupled in series between the capacitor and the gate of the JFET. In the same or different examples, the method further includes monitoring the junction temperature of the JFET based on the gate-source voltage of the JFET. In the same or different examples, the MOSFET is a silicon MOSFET and the JFET is a silicon carbide JFET.

[0009] After reading the following detailed description in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement its additional aspects. Attached Figure Description

[0010] A more complete understanding of this embodiment can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0011] Figure 1 A schematic diagram of a gate drive circuit for a common-source cascode device according to an embodiment of the present disclosure is illustrated.

[0012] Figure 2 A schematic diagram of a common-source cascode switching circuit according to an embodiment of the present disclosure is illustrated.

[0013] Figure 3 A schematic diagram of a common-source cascode switching circuit according to an embodiment of the present disclosure is illustrated.

[0014] Figure 4 A schematic diagram of a common-source cascode switching circuit according to an embodiment of the present disclosure is illustrated.

[0015] Figure 5 A schematic diagram of a common-source cascode switching circuit according to an embodiment of the present disclosure is illustrated.

[0016] Figure 6 A schematic diagram of a common-source cascode switching circuit according to an embodiment of the present disclosure is illustrated.

[0017] Figure 7 A schematic diagram of a junction temperature sensor according to an embodiment of the present disclosure is shown.

[0018] Figure 8 A graph illustrating the relationship between gate-source voltage and junction temperature for a JFET is shown according to an embodiment of the present disclosure.

[0019] Figure 9 Examples of embodiments according to this disclosure are shown at different junction temperatures (T). J The graph shows the on-state current-voltage characteristics of the cascode device under different JFET gate biases.

[0020] Figure 10 Examples of embodiments according to this disclosure are shown at different junction temperatures (T). J The graph shows the measured on-state resistance of the cascode device under different JFET gate biases.

[0021] Figure 11 Examples of embodiments according to this disclosure are provided. Figure 4 The waveform curve of the common source cascode switching circuit.

[0022] Figure 12A block diagram of an interconnection system for components of an electric vehicle is illustrated, in which an embodiment of the common-source cascode switching circuit of this disclosure can be deployed.

[0023] Figure 13 An embodiment of the present disclosure illustrates a method for operating a cascode device, the cascode device comprising a JFET and a MOSFET coupled in a cascode topology. Detailed Implementation

[0024] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the description, the drawings, and the claims. The disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended to be an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0025] Various terms are used to refer to specific system components. Different companies may use different names to refer to a component, and this disclosure is not intended to distinguish between components with different names but the same form and function. In the following description and in the claims, the terms "comprising" and "including" are used in an open form, and therefore, these terms should be interpreted as meaning "including but not limited to". Additionally, the term "coupled" is intended to indicate either an indirect connection or a direct connection. Thus, if a first device is coupled to or is coupled to a second device, the connection between the first device and the second device can be achieved through a direct connection or through an indirect connection via other elements and connectors.

[0026] Furthermore, although terms such as “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. Terms such as “first” and “second” may be used only to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element, without departing from the scope of this disclosure. Moreover, the identification of a “first” element does not necessarily require the presence of a “second” element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated entries listed.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein are to be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be construed as having an idealized or overly formal meaning unless expressly defined herein.

[0028] Figure 1 A schematic diagram of a gate drive circuit 10 for a cascode device 12 according to an embodiment of the present disclosure is shown. For example... Figure 1 As shown, the cascode device 12 may include a junction field-effect transistor (JFET) 14 and a metal-oxide-semiconductor field-effect transistor (MOSFET) 16 coupled in a cascode topology.

[0029] JFET 14 may be, for example, a silicon carbide JFET formed on a silicon carbide substrate. JFET 14 may also be formed of any other semiconductor material such as silicon (Si) or gallium nitride (GaN), which is suitable for use in power electronic devices, for example. Furthermore, JFET 14 may be a normally-on JFET. For the purposes of this disclosure, a normally-on transistor (such as JFET 14) may also be referred to as a depletion-type transistor. In some embodiments, JFET 14 may have a DC voltage rating, for example, from 200 volts to 10,000 volts.

[0030] In some embodiments, MOSFET 16 may be an n-channel MOSFET (NMOS or NMOS transistor). Furthermore, in some embodiments, MOSFET 16 may be, for example, a silicon MOSFET formed on a silicon substrate. MOSFET 16 may also be formed of any other semiconductor material such as silicon carbide (SiC) or gallium nitride (GaN), which is suitable for use in power electronic devices, for example. Additionally, MOSFET 16 may be a normally-off transistor. For the purposes of this disclosure, a normally-off transistor (such as MOSFET 16) may also be referred to as an enhancement-mode transistor. MOSFET 16 may have a lower DC voltage rating than JFET 14. In some embodiments, MOSFET 16 may have a DC voltage rating of, for example, from 10 volts to 70 volts.

[0031] like Figure 1 As shown, the source terminal 18 of JFET 14 can be coupled to the drain terminal 20 of MOSFET 16 at the internal node SD of the cascode device 12. Furthermore, the source terminal 22 of MOSFET 16 can be coupled to a fixed voltage node 24, which... Figure 1The source terminal 22 of MOSFET 16 is depicted as grounded. For the purposes of this disclosure, the source terminal 22 of MOSFET 16 may also be generally referred to as the source terminal of cascode device 12. In addition, the drain terminal 26 of JFET 14 may be coupled to load terminal 28, to which an external load (not shown) may be coupled. For the purposes of this disclosure, the drain terminal 26 of JFET 14 may also be generally referred to as the drain terminal of cascode device 12. The gate terminal 30 of JFET 14 and the gate terminal 32 of MOSFET 16 may be externally connected to cascode device 12. As described in further detail below, the gate terminal 30 of JFET 14 may be driven separately from the gate terminal 32 of MOSFET 16 by gate drive circuitry 10.

[0032] like Figure 1 As shown, the gate terminal 30 of JFET 14 can be coupled to a fixed voltage node 24 via a resistor 34. The resistance value of resistor 34 can be, for example, in the range of 0 ohms to 100 ohms. Furthermore, gate driver 36 may have a gate driver output 38, which can be coupled to the gate terminal 32 of MOSFET 16 via a resistor 40 to control the cascode device 12. Gate driver 36 may have a power supply terminal 42 configured to receive a supply voltage VCC at a level that supplies power to gate driver 36 (e.g., 5V, 8V, 10V, 12V, 15V, 20V, or higher). Gate driver 36 may also have a ground terminal 44, which can be coupled to the fixed voltage node 24.

[0033] Gate driver 36 may have a gate driver input 46 configured to receive a switching input signal that alternates between an on signal (such as a logic high signal) and an off signal (such as a logic low signal). Gate driver 36 may be configured to respond to an on signal by generating an on-state voltage level at gate driver output 38 to turn on MOSFET 16, thereby effectively coupling load terminal 28 to fixed voltage node 24. Gate driver 36 may also be configured to respond to an off signal by generating an off-state voltage level at gate driver output 38 to turn off MOSFET 16, thereby effectively decoupling load terminal 28 from fixed voltage node 24.

[0034] When the cascode device 12 is in the ON state, both JFET 14 and MOSFET 16 will be ON. The drain voltage (VSD_S) of MOSFET 16 is positive and equal to the product of the current flowing through the cascode device 12 and the ON-state resistance of MOSFET 16. Due to the relatively small ON-state resistance of MOSFET 16 (e.g., 10 mΩ, 5 mΩ, 2 mΩ or less), the drain voltage VSD_S can be relatively small. The JFET gate voltage VJG_S between the gate terminal 30 of JFET 14 and the source terminal 22 of MOSFET 16 can be close to zero because no current flows through resistor 34 during the ON state. Therefore, the JFET gate bias (VJG_SD) between the gate terminal 30 of JFET 14 and the source terminal 18 of JFET is VJG_SD = VJG_S - VSD_S = -VSD_S, which indicates that the gate-source junction of JFET 14 can be slightly reverse biased in the on state.

[0035] Figure 2 A schematic diagram of a common-source cascode switching circuit 48 according to an embodiment of the present disclosure is shown. For example... Figure 2 As shown, the cascode switching circuit 48 may include a cascode device 12, which includes a JFET 14 and a MOSFET 16 coupled in a cascode topology. The cascode switching circuit 48 may also include a gate driver 36, a resistor 40, a current source 50, and a voltage clamp 52, as described in further detail below, which may be configured to jointly drive the JFET 14 and the MOSFET 16.

[0036] As referenced above Figure 1 As described, the gate driver 36 may have a gate driver input 46 configured to receive a switch input signal and a gate driver output 38 coupled to the gate of the MOSFET 16 and configured to switch the MOSFET 16 between a MOSFET on state and a MOSFET off state based on the switch input signal. Furthermore, as... Figure 2 As shown, the common-source cascode switching circuit 48 may further include a resistor 40 connected in series between the gate driver output 38 and the gate of the MOSFET 16. Therefore, the resistance value of the resistor 40 can be selected to control the switching speed of the MOSFET 16 during the transition from the MOSFET on state to the MOSFET off state, or vice versa during the transition from the MOSFET off state to the MOSFET on state.

[0037] Current source 50 may be coupled between gate driver output 38 and gate of JFET 14, and is configured to forward bias gate-source junction of JFET 14 when cascode device 12 is in the ON state. Specifically, current source 50 may be coupled in series between gate driver output 38 of gate driver 36 and gate terminal 30 of JFET 14.

[0038] The current source 50 may have a current source input terminal 54 and a current source output terminal 56. During normal operation, the voltage drop between the current source input terminal 54 and the current source output terminal 56 may be, for example, in the range of 0.5 volts to 40 volts. The output current of the current source 50 can typically be constant and may be, for example, in the range of 0.01 mA to 100 mA. In some embodiments, the current source 50 may be implemented using a resistor, a current regulator, or a combination thereof.

[0039] Voltage clamp 52 may be coupled to the gate of JFET 14 and configured to prevent the gate voltage of JFET 14 from exceeding a clamping threshold. For example, voltage clamp 52 may be coupled between the gate terminal 30 of JFET 14 and the source terminal 22 of MOSFET 16. In some embodiments, voltage clamp 52 may have electrical characteristics similar to those of a Zener diode, wherein the first clamping terminal 58 operates similarly to the cathode of a Zener diode, and the second clamping terminal 60 operates similarly to the anode of a Zener diode. Therefore, the clamping voltage across voltage clamp 52 may be similar to the reverse breakdown voltage of a Zener diode. The clamping voltage of voltage clamp 52 may be greater than the normal operating JFET gate voltage VJG_S between the gate terminal 30 of JFET 14 and the source terminal 22 of MOSFET 16. The value of the clamping voltage may be in the range of, for example, 3 volts to 10 volts. The voltage clamp 52 may be formed by a Zener diode, or an avalanche diode, or an avalanche-rated silicon MOSFET, or any other voltage clamping circuit suitable for clamping the voltage between the first clamping terminal 58 and the second clamping terminal 60.

[0040] To drive the cascode device 12 in the ON state, the gate driver 36 can output a high-level voltage, which can be in the range of, for example, +5V to +25V. The high-level voltage supplied to the gate terminal 32 of the MOSFET 16 drives the MOSFET 16 in the ON state. Furthermore, under such conditions, the current source 50 can provide sufficient current at the current source output terminal 56 to bias the gate terminal 30 of the JFET 14 at a positive voltage, thereby keeping the JFET 14 in the ON state. For example, the JFET gate voltage VJG_S between the gate terminal 30 of the JFET 14 and the source terminal 22 of the MOSFET 16 can be in the range of, for example, 1V to 3V, which can be less than the clamping voltage of the voltage clamp 52. Therefore, the voltage clamp 52 can operate normally in blocking mode with negligible leakage current during the ON state of the cascode device 12, and the output current of the current source 50 can flow into the gate terminal 30 of the JFET 14 to forward bias the gate-source junction of the JFET 14.

[0041] To drive the off-state cascode device 12, the gate driver 36 can output a low-level voltage, which can be, for example, in the range of 0 volts to -10 volts. This low-level voltage supplied to the gate terminal 32 of the MOSFET 16 can drive the off-state MOSFET 16. Furthermore, under such conditions, the gate-source junction of the JFET 14 can be reverse-biased (and therefore can conduct negligible leakage current). In an embodiment where the output voltage of the gate driver 36 is 0 volts, the JFET gate voltage VJG_S between the gate terminal 30 of the JFET 14 and the source terminal 22 of the MOSFET 16 can be approximately 0 volts because there may be no current flowing through the current source 50. In other embodiments where the output voltage of the gate driver 36 is negative (e.g., -10 volts), a small reverse current can flow from the second clamp terminal 60 through the voltage clamp 52 to the first clamp terminal 58, then from the current source output terminal 56 through the current source 50 to the current source input terminal 54, and to the gate driver output terminal 38 of the gate driver 36. The reverse current can be limited by the resistance of the current source 50 (e.g., in the mA range). Therefore, the JFET gate voltage VJG_S between the gate terminal 30 of JFET 14 and the source terminal 22 of MOSFET 16 can be equal to 0 volts minus VTAtoTC, where VTAtoTC is the forward voltage drop across voltage clamp 52. Typical values ​​for VTAtoTC can range, for example, from 0.5 volts to 2.0 volts. Therefore, the JFET gate voltage VJG_S between the gate terminal 30 of JFET 14 and the source terminal 18 of JFET 14 can range from 0 volts to -2 volts, depending on the output voltage level of gate driver 36 and the forward voltage drop of voltage clamp 52.

[0042] Figure 3 A schematic diagram of a common-source cascode switching circuit 348 according to an embodiment of the present disclosure is shown. For example... Figure 3 As shown, the common-source cascode switching circuit 348 may include the same circuit described above. Figure 2 Similar components to the described cascode switching circuit 48. For example, the cascode switching circuit 348 may include a gate driver 36, a resistor 40, a current source 50, a voltage clamp 52, and a cascode device 12, which may be similar to those described above. Figure 2 It operates in a similar manner to that described. In addition, the cascode switching circuit 348 may also include a capacitor 62 and a junction resistor 64. The capacitor 62 may be coupled in parallel to the current source 50. Furthermore, the junction resistor 64 may be coupled between the current source 50 and the gate of the JFET 14. Therefore, as described in further detail below, the capacitor 62 and the junction resistor 64 control the switching transition time of the cascode device 12.

[0043] When the cascode device 12 is switched from the off state to the on state, or vice versa, from the on state to the off state, a large pulse current can be provided by capacitor 62 to quickly charge or discharge the gate input capacitance of JFET 14. For example, when the cascode device 12 is a module consisting of multiple JFET chips connected in parallel, the large pulse current can be as high as or greater than 20 amps. As described above, current source 50 can be configured such that the output current of current source 50 is small (e.g., in the mA range). Therefore, current source 50 can have a small effect on charging and discharging the gate input capacitance of JFET 14, and thus a small effect on the switching speed of cascode device 12. Without capacitor 62, the large pulse current would have to flow through voltage clamp 52, thus requiring voltage clamp 52 to have a high surge current capability. To reduce the required surge current capability of voltage clamp 52, capacitor 62 can be coupled in parallel with current source 50. Therefore, when the gate driver output 38 of the gate driver 36 transitions from low to high (to turn on the cascode device 12) or from high to low (to turn off the cascode device 12), the capacitor 62 can provide an AC coupling that provides a large charging current or discharging current to the gate of the JFET 14.

[0044] In some embodiments, the switching speed of the cascode device 12 can also be controlled by a junction resistor 64, which can be connected in series between the gate terminal 30 of the JFET 14 and the current source output terminal 56. In some embodiments (such as...) Figure 3In the illustrated embodiment, junction resistor 64 may be implemented by a single resistor. In other embodiments, junction resistor 64 may be formed by a resistor circuit, which may include, for example, a network of resistors and / or diodes. The resistance of junction resistor 64 may provide an RC delay together with the gate capacitance of JFET 14, which may be tuned to achieve the desired rise and fall times of the gate voltage of JFET 14 during the transition from the off state to the on state and conversely, during the transition from the on state to the off state.

[0045] Figure 4 A schematic diagram of a common-source cascode switching circuit 348 according to an embodiment of the present disclosure is shown. For example... Figure 4 As shown, in some embodiments, current source 50 can be implemented using resistor 51. Resistor 51 may have a resistance value, for example, in the range of kΩ. Therefore, as described above, current source 50 can provide an output current in the range of mA, for example, in the range of 0.01mA to 100mA depending on the voltage at the gate driver output 38 of gate driver 36. Furthermore, in some embodiments, voltage clamp 52 can be implemented using Zener diode 53. As described above, voltage clamp 52 can be configured with a clamping voltage in the range of, for example, 3V to 10V. Therefore, Zener diode 53 can be configured with a reverse breakdown voltage equal to the desired clamping voltage (e.g., in the range of 3V to 10V).

[0046] Figure 5 A schematic diagram of a common-source cascode switching circuit 548 according to an embodiment of this disclosure is shown. For example... Figure 5 As shown, the common-source cascode switching circuit 548 may include the same circuit described above. Figure 2 Similar components to the described cascode switching circuit 48. For example, the cascode switching circuit 548 may include a gate driver 36, a resistor 40, a current source 50, a voltage clamp 52, and a cascode device 12, which may be similar to those described above. Figure 2 Operate in a similar manner as described below, unless otherwise stated below.

[0047] like Figure 5As shown, current source 50 may be coupled between power source 66 and the gate of JFET 14, and may be configured to forward bias the gate-source junction of JFET 14 when cascode device 12 is in the ON state. For example, current source input terminal 54 of current source 50 may be coupled to power source 66 having a voltage VDD sufficient to drive current to gate terminal 30 of JFET 14. In some embodiments, VDD may be, for example, 3 volts, 5 volts, 10 volts, 20 volts, or higher. When MOSFET 16 (and cascode device 12 as a whole) is driven in the ON state, output current from current source 50 may flow into gate terminal 30 of JFET 14 to forward bias the JFET gate-source junction. When MOSFET 16 (and cascode device 12 as a whole) is driven to the off state, the gate-source junction of JFET 14 can be reverse biased with negligible leakage current, allowing the output current of current source 50 to flow into voltage clamp 52 and drive voltage clamp 52 into voltage clamping mode. Therefore, during the off state of MOSFET 16 (and cascode device 12 as a whole), the JFET gate voltage VJG_S can be equal to the clamping voltage of voltage clamp 52.

[0048] The gate-source junction of JFET 14 is a PN junction. Therefore, the gate-source junction of JFET 14 can be forward biased by the output current of current source 50 during the on-state. Typically, the output current of current source 50 is constant or nearly constant during operation. Therefore, refer to the following... Figure 6 As described in further detail, the gate-source voltage of the JFET 14 can be used as a temperature sensing parameter to measure the junction temperature of the JFET 14 during the on-state.

[0049] Figure 6 A schematic diagram of a common-source cascode switching circuit 648 according to an embodiment of the present disclosure is shown. For example... Figure 6 As shown, the common-source cascode switching circuit 648 may include the same circuit described above. Figure 3 Similar components to the described cascode switching circuit 348. For example, the cascode switching circuit 648 may include a gate driver 36, a resistor 40, a current source 50, a voltage clamp 52, a capacitor 62, a junction resistor 64, and a cascode device 12, which may be similar to those described above. Figure 3 (and reference) Figure 2 Operate in a similar manner as described below, unless otherwise described below.

[0050] like Figure 6As shown, the cascode switching circuit 648 may also include a junction temperature sensor 68. In some embodiments, the junction temperature sensor 68 may be coupled across the gate and source of the JFET 14 and configured to output a sensor voltage signal based on temperature changes of the JFET 14. For example, the junction temperature sensor 68 may have a gate voltage input terminal 70 coupled to the gate terminal 30 of the JFET 14 and a source voltage input terminal 72 coupled to the source terminal 18 of the JFET 14. The junction temperature sensor 68 can thus measure the gate-source voltage of the JFET 14 during the on-state of the cascode device 12. The gate-source voltage of a JFET (such as JFET 14) typically varies with temperature in increments of approximately -2 mV / °C. The junction temperature sensor 68 can thus convert the gate-source voltage of the JFET 14 into a sensor voltage signal that is substantially proportional (or inversely proportional) to the junction temperature of the JFET 14. Temperature sensor output terminal 74 can be provided from outside the junction temperature sensor 68 to output a sensor voltage signal to an external protection circuit (not shown), which can shut down the common-source cascode device 12 in response to the sensor voltage signal under over-temperature conditions.

[0051] Although the junction temperature sensor 68 is in Figure 6 The junction is depicted as part of a cascode switch circuit 648, but the junction temperature sensor 68 can also be coupled across the gate and source of the JFET 14 to monitor the cascode switch circuit 48. Figure 2 ), Common source common gate switch circuit 348 ( Figure 3 and Figure 4 ) and common source cascode switching circuit 548 ( Figure 5 The temperature of JFET 14 in either of the following.

[0052] Figure 7 A schematic diagram of a junction temperature sensor 68 according to an embodiment of the present disclosure is shown. Although for illustrative purposes... Figure 7 A specific circuit configuration is shown, but the junction temperature sensor 68 can be implemented with any circuit configuration suitable for providing a sensor voltage signal that is proportional (or inversely proportional) to the temperature.

[0053] like Figure 7As shown, the junction temperature sensor 68 may have an operational amplifier 76 coupled between the power supply rail 78 and the fixed voltage node 24 to receive power during operation. The power supply rail 78 may be powered by the supply voltage VCC. The operational amplifier 76 may have a non-inverting input terminal 80 and an inverting input terminal 82. A first isolation diode 84 may have a cathode coupled to the gate voltage input terminal 70 and an anode coupled to the non-inverting input terminal 80 of the operational amplifier 76. A second isolation diode 86 may have a cathode coupled to the source voltage input terminal 72 and an anode coupled to the inverting input terminal 82 of the operational amplifier 76. When the cascode device 12 ( Figure 6 When in the off state (as shown in the diagram), the first isolation diode 84 and the second isolation diode 86 can provide high isolation impedance.

[0054] The junction temperature sensor 68 may further include a first protection voltage clamp 88, which may be coupled between the non-inverting input terminal 80 and the fixed voltage node 24. A second protection voltage clamp 90 may be coupled between the inverting input terminal 82 and the fixed voltage node 24. Figure 7 In an exemplary implementation, both the first protection voltage clamp 88 and the second protection voltage clamp 90 may be implemented by a Zener diode that clamps the non-inverting input terminal 80 and the inverting input terminal 82 to a safe voltage range (e.g., between 5 volts and 8 volts).

[0055] A first sensor current source 92 can be coupled between the power supply rail 78 and the non-inverting input terminal 80. Furthermore, a second sensor current source 94 can be coupled between the power supply rail 78 and the inverting input terminal 82. The first sensor current source 92 and the second sensor current source 94 can be configured to measure the relationship between the gate terminal 30 and the source terminal 18 of the JFET 14 (e.g., ...). Figure 6 The voltage between the first sensor current source 92 and the second sensor current source 94 is shown in the figure. In some embodiments, the current values ​​for the first sensor current source 92 and the second sensor current source 94 can be in the range of, for example, 0.1mA to 10mA. Operational amplifier 76 can be configured to connect the gate terminal 30 of JFET 14 to the source terminal 18 of JFET 14. Figure 6 The voltage between (shown in the figure) is converted into a ground reference temperature-dependent sensor output voltage that can be provided to an external circuit (not shown) coupled to the temperature sensor output terminal 74.

[0056] As described above, the gate-source voltage of a JFET (such as JFET 14) can typically be around -2mV / °C. However, to most accurately correlate the sensor voltage signal at the output of the junction temperature sensor 68 with the JFET junction temperature, the precise gate-source voltage of a specific JFET design can be measured experimentally using an example of a design for JFET 14. For example, it can be done as follows: Figure 8 The measurements shown are accurate gate-source voltages for a specific JFET design (such as the design for JFET14) as a function of junction temperature.

[0057] Figure 9 Examples of embodiments according to this disclosure are shown at different junction temperatures (T). J The graphs show the on-state current-voltage characteristics of cascode devices under different JFET gate biases. Specifically, Figure 9 The on-state current-voltage characteristics of a cascode device (such as cascode device 12) are illustrated, wherein a MOSFET (such as MOSFET 16) uses a gate-source voltage of 15 volts (V0). GS Driven by ) pulse settling time (t) p The current is 60 μs, and the gate (JG)(i) of the JFET is forward biased with a current (I) of 1 mA. JG (i) Forward biased, or (ii) coupled to the source terminal (S) of a cascode device. Figure 9 As shown, the gate (JG) of a forward-biased JFET can be adjusted for a given drain-source voltage (V) of a cascode device. DS ) provides increased drain current (I D In some examples, a forward bias current of 1mA (I0) is used. JG The gate (JG) of a forward-biased JFET can provide, for example, a given drain-source voltage (V) in a cascode device. DS Lower drain current (I) D () increased by 20%.

[0058] Figure 10 Examples of embodiments according to this disclosure are shown at different junction temperatures (T). J The graph shows the measured on-state resistance of the cascode device under different JFET gate biases. Specifically, Figure 10 The on-state resistance (R) of a cascode device (such as cascode device 12) is illustrated. DSON ), where MOSFETs (such as MOSFET 16) use a 15-volt gate-source voltage (V). GS Driven by ) pulse settling time (t) pThe current is 60 μs, and the gate (JG)(i) of the JFET is forward biased with a current (I) of 1 mA. JG (ii) Forward bias, or coupled to the source terminal (S) of a cascode device. In some examples, a forward bias current (I0) of 1mA is used. JG The gate (JG) of a forward-biased JFET can provide, for example, when the drain current (I) D The on-state resistance (R) is approximately 250 amperes. DSON A 10% decrease in drain current (I) D The on-state resistance (R) is approximately 1000 amperes. DSON The 14% decrease in drain current (I) and the decrease in drain current (I) D Further increasing by more than 1000 amperes, the on-state resistance (R) DSON The percentage decrease is higher.

[0059] Figure 11 Examples of embodiments according to this disclosure are provided. Figure 4 The waveform curve of a common-source cascode switching circuit. (Example:) Figure 11 As shown, the JFET gate voltage can transition from 0 volts during the off-state of the cascode device 12 to approximately +2.55 volts during the on-state of the cascode device 12. Therefore, the JFET gate-source junction can be forward biased during the on-state, thereby reducing the on-state resistance of the JFET 14 (and the cascode device 12 as a whole).

[0060] The various examples of common-source cascode switching circuits disclosed herein (such as common-source cascode switching circuits 48, 348, 548 and 648) can be used in a variety of applications (including, for example, electric vehicle applications). Figure 12 A block diagram illustrating an interconnection system for components of an electric vehicle 96 is shown, in which various implementations of the common-source cascode switching circuit described herein can be deployed.

[0061] like Figure 12As shown, the electric propulsion subsystem 98 may include a motor control system 100. A smart motor controller 102 may be operatively coupled to a brake 104 and an accelerator 106 to receive inputs related to vehicle deceleration and acceleration, respectively. The smart motor controller 102 may process these inputs and regulate the flow of electrical energy to a three-phase inverter 108, which may include a cascode switching circuit (such as any of cascode switching circuits 48, 348, 548, and 648). The three-phase inverter 108 may modulate electrical power in response to signals from the smart motor controller 102 and supply that power to the motor 110. The cascode switching circuit 48 may be used during a fuse-breaking process to protect the motor 110 in the event of an electrical fault. The motor 110 may convert electrical energy into mechanical energy, which may then be transmitted to the wheels 112 of the electric vehicle 96 via a mechanical transmission 114.

[0062] like Figure 12 As shown, the energy source subsystem 116 may be adjacent to the electric propulsion subsystem 98. The energy source subsystem 116 may include an energy management unit 118 that oversees the distribution and storage of electrical energy within the electric vehicle 96. The energy management unit 118 may be coupled to an energy source 120, such as a rechargeable battery or fuel cell, which provides primary electrical power to the electric vehicle 96. Additionally, an energy replenishment unit 122 may be incorporated to replenish the energy source 120 when it is depleted.

[0063] Furthermore, auxiliary subsystem 124 can be used to manage non-propulsion-related functions. For example, auxiliary power source 126 can obtain energy from energy source 120 and direct that energy to various auxiliary components, including, for example, power steering unit 128 that receives power to assist in manipulating steering wheel 130, and temperature control unit 132 that maintains the thermal conditions of the vehicle system.

[0064] Figure 13 A method 1300 for operating a cascode device according to an embodiment of the present disclosure is illustrated, the cascode device comprising a JFET and a MOSFET coupled in a cascode topology. Method 1300 can be performed by any suitable mechanism, including, for example, cascode switching circuits 48, 348, 548, or 648, or any suitable combination thereof. Method 1300 can be used with... Figure 13 The steps shown in the diagram can be performed in fewer or more steps. Furthermore, the steps of method 1300 can be repeated, performed recursively, or combined with... Figure 13 The different execution sequences are shown in the diagram.

[0065] At step 1302, method 1300 may include receiving a switch input signal. And at step 1304, method 1300 may include switching the MOSFET between a MOSFET on state and a MOSFET off state based on the switch input signal. For example, as referenced above... Figure 2 As described, the gate driver 36 may have a gate driver input 46 configured to receive a switch input signal and a gate driver output 38 coupled to the gate of the MOSFET 16 and configured to switch the MOSFET 16 between a MOSFET on state and a MOSFET off state based on the switch input signal.

[0066] At step 1306, method 1300 may include forward biasing the gate-source junction of the JFET with a current source when the cascode device is in the ON state. For example, as referenced above. Figure 2 As described, current source 50 may be coupled between gate driver output 38 and the gate of JFET 14, and may be configured to provide current to the gate-source junction of JFET 14 when cascode device 12 is in the ON state. In another example, as referenced above... Figure 5 As described, current source 50 may be coupled between power source 66 and gate of JFET 14, and may be configured to provide current to the gate-source junction of JFET 14 when cascode device 12 is in the on state.

[0067] At step 1308, method 1300 may include providing a pulsed current to the gate of the JFET in response to a switching input signal, using a capacitor coupled in parallel to a current source. For example, as referenced above... Figure 3 As described, capacitor 62 can be connected in parallel to current source 50. When the voltage level at the gate driver output 38 is changed from the off state to the on state, or vice versa, capacitor 62 can provide a large pulse current to quickly charge or discharge the gate input capacitance of JFET 14.

[0068] At step 1310, method 1300 may include using a resistor connected in series between the capacitor and the gate of the JFET to control the charging and discharging times of the JFET's gate. For example, as referenced above... Figure 3As described, capacitor 62 may be coupled in parallel to current source 50, and junction resistor 64 may be coupled in series between current source 50 and gate of JFET 14. The resistance of junction resistor 64, together with gate capacitance of JFET 14, provides RC delay, which can be tuned to achieve desired rise and fall times of gate voltage of JFET 14 during the transition from off to on state of cascode device 12 and conversely during the transition from on to off state.

[0069] At step 1312, method 1300 may include monitoring the junction temperature of the JFET based on the gate-source voltage of the JFET. For example, as referenced above... Figure 6 As described, the gate-source voltage of a JFET (such as JFET 14) is typically variable with temperature. Therefore, a junction temperature sensor 68 can be coupled across the gate and source of JFET 14 and can be configured to output a sensor voltage signal that varies based on the gate-source voltage of JFET 14 (which is a function of temperature).

[0070] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The description of the various embodiments above exemplifies the principles of the invention. Based on the above disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A common-source cascode switching circuit, the common-source cascode switching circuit comprising: A common-source cascode device, the common-source cascode device comprising a JFET and a MOSFET coupled in a common-source cascode topology; A gate driver having a gate driver input configured to receive a switch input signal and a gate driver output coupled to the gate of the MOSFET and configured to switch the MOSFET between an on state and an off state based on the switch input signal; and A current source is coupled between the gate driver output and the gate of the JFET and is configured to forward bias the gate-source junction of the JFET when the cascode device is in the ON state.

2. The cascode switching circuit of claim 1, further comprising a voltage clamper coupled to the gate of the JFET and configured to prevent the gate voltage of the JFET from exceeding a clamping threshold.

3. The common-source cascode switching circuit according to claim 2, wherein the voltage clamper comprises a Zener diode.

4. The common-source common-gate switching circuit according to claim 1, wherein the common-source common-gate switching circuit further comprises a resistor, the resistor being connected in series between the gate driver output terminal and the gate of the MOSFET.

5. The common-source cascode switching circuit according to claim 1, wherein the common-source cascode switching circuit further includes a capacitor, the capacitor being connected in parallel to the current source.

6. The common-source cascode switching circuit according to claim 5, wherein the common-source cascode switching circuit further comprises a junction resistor coupled between the current source and the gate of the JFET.

7. The common-source cascode switching circuit according to claim 1, wherein the current source comprises a resistor.

8. The common-source cascode switching circuit according to claim 1, wherein the MOSFET is an NMOS transistor.

9. The common-source cascode switching circuit according to claim 1, wherein: The MOSFET is a silicon MOSFET; and The JFET is a silicon carbide JFET.

10. The common-source cascode switching circuit of claim 1, further comprising a junction temperature sensor coupled across the gate and source of the JFET and configured to output a sensor voltage signal based on a temperature change of the JFET.

11. A common-source cascode switching circuit, the common-source cascode switching circuit comprising: A common-source cascode device, the common-source cascode device comprising a JFET and a MOSFET coupled in a common-source cascode topology; A gate driver having a gate driver input configured to receive a switch input signal and a gate driver output coupled to the gate of the MOSFET and configured to switch the MOSFET between an on state and an off state based on the switch input signal; and A current source is coupled between a power source and the gate of the JFET and is configured to forward bias the gate-source junction of the JFET when the cascode device is in the ON state.

12. The cascode switching circuit of claim 11, further comprising a voltage clamp coupled to the gate of the JFET and configured to prevent the gate voltage of the JFET from exceeding a clamping threshold.

13. The common-source cascode switching circuit according to claim 11, wherein the current source comprises a resistor.

14. The common-source cascode switching circuit according to claim 11, wherein: The MOSFET is a silicon MOSFET; and The JFET is a silicon carbide JFET.

15. The common-source cascode switching circuit of claim 11, further comprising a junction temperature sensor coupled across the gate and source of the JFET and configured to output a sensor voltage signal based on a temperature change of the JFET.

16. A method for driving a cascode device, the cascode device comprising a JFET and a MOSFET coupled in a cascode topology, the method comprising: Receive switch input signal; The MOSFET is switched between the MOSFET on state and the MOSFET off state based on the switch input signal; as well as When the common-source cascode device is in the on state, the gate-source junction of the JFET is forward biased by a current source.

17. The method of claim 16, wherein a capacitor coupled in parallel to the current source is used to provide a pulsed current to the gate of the JFET in response to the switching input signal.

18. The method of claim 17, wherein the charging and discharging times of the gate of the JFET are controlled by a resistor connected in series between the capacitor and the gate of the JFET.

19. The method of claim 16, further comprising monitoring the junction temperature of the JFET based on the gate-source voltage of the JFET.

20. The method of claim 16, wherein: The MOSFET mentioned therein is a silicon MOSFET; and The JFET is a silicon carbide JFET.

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