Integrated circuit device, method of manufacturing same, and method of generating integrated circuit layout

Abstract

The IC device includes two isolation structures extending in parallel in a first direction in a front side of a semiconductor substrate, a stacked CFET circuit including a gate extending in the first direction between the isolation structures and a metal-like defined (MD) segment. Each gate extends along a first direction from a first position to a second position, and one of the MD segments is configured as a reference voltage connection of the circuit and extends from the first position to a third position that is further along the first direction than the second position. The front-side conductive line and the back-side conductive line extend in a second direction perpendicular to the first direction, and the conductive structure extends from the front-side conductive line to the back-side conductive line along a third direction perpendicular to each of the first direction and the second direction, and includes a portion of the MD segment located between a second position and a third position. Embodiments of the present disclosure also relate to an integrated circuit device, a method of manufacturing the same, and a method of generating an integrated circuit layout.

Description

Technical Field

[0001] Embodiments of this disclosure relate to integrated circuit devices and methods for manufacturing the same, as well as methods for generating integrated circuit layouts. Background Technology

[0002] The ongoing trend toward miniaturization of integrated circuits (ICs) has resulted in progressively smaller devices that consume less power but deliver more functionality at a higher speed than earlier technologies. This miniaturization has been achieved through design and manufacturing innovations associated with increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify designs for semiconductor devices while ensuring compliance with IC architecture design and manufacturing specifications. Summary of the Invention

[0003] Embodiments of this disclosure provide an integrated circuit device comprising: a first isolation structure and a second isolation structure extending parallel to each other in a first direction on the front side of a semiconductor substrate; a circuit including a plurality of stacked complementary field-effect transistors (CFETs), the plurality of stacked CFETs including a plurality of gates and a plurality of metallic defined (MD) segments extending in the first direction between the first isolation structure and the second isolation structure, wherein: each of the plurality of gates extends from the first location to the second location along the first direction, and the metallic defined segment of the plurality of metallic defined segments is configured as a reference voltage connection of the circuit and extends from the first location to the third location, the third location being further along the first direction than the second location; a first conductor extending in a second direction perpendicular to the first direction on the front side of the semiconductor substrate; a second conductor extending in the second direction on the back side of the semiconductor substrate; and a conductive structure extending from the first conductor to the second conductor in a third direction perpendicular to each of the first and second directions, wherein the conductive structure includes a portion of the metallic defined segment located between the second location and the third location.

[0004] Another embodiment of this disclosure provides a method for manufacturing an integrated circuit (IC) device, the method comprising: constructing a first isolation structure and a second isolation structure and a plurality of stacked complementary field-effect transistors (CFETs) on the front side of a semiconductor substrate, the construction of the plurality of stacked complementary field-effect transistors comprising: forming a plurality of gates and a plurality of metallic defining segments extending in the first direction between the first isolation structure and the second isolation structure in a second direction perpendicular to the first direction; and forming an interconnect structure adjacent to the plurality of gates and aligned with the plurality of gates in the first direction, wherein a portion of one of the plurality of metallic defining segments is aligned with the interconnect structure in a third direction perpendicular to each of the first and second directions; forming a front via on the portion of the metallic defining segment or one of the interconnect structures; forming a front conductor on the front via and the front conductor extending in the second direction; forming a back via on the other of the metallic defining segment or the interconnect structure; and forming a back conductor on the back via and the back conductor extending in the second direction.

[0005] Another embodiment of this disclosure provides a method for generating an integrated circuit (IC) layout, the method comprising: extending an interconnect region across the width of a cell; overlapping the interconnect region with a metallic defined (MD) region; overlapping the interconnect region and the metallic defined region with a front via region and a back via region; overlapping the front via region with a front metallic region and overlapping the back via region with a back metallic region, each of the front metallic region and the back metallic region extending in the cell width direction; and storing the integrated circuit layout including the cell in a memory device.

[0006] Embodiments of this application provide embedded power pickup IC devices, layouts, and methods. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0008] Figures 1A to 1C These are plan views and cross-sectional views of IC devices and layouts according to some embodiments.

[0009] Figure 2 It is a plan view of IC devices and layout according to some embodiments.

[0010] Figure 3It is a plan view of IC devices and layout according to some embodiments.

[0011] Figure 4A and Figure 4B These are plan views and cross-sectional views of IC devices and layouts according to some embodiments.

[0012] Figure 5 This is a flowchart of a method for manufacturing an IC device according to some embodiments.

[0013] Figure 6 This is a flowchart of a method for generating an IC layout diagram according to some embodiments.

[0014] Figure 7 It is a block diagram of a system generated based on IC layout diagrams of some embodiments.

[0015] Figure 8 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the discussed embodiments and / or configurations.

[0017] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] In various embodiments, the integrated circuit (IC) device, layout, and manufacturing method are directed to a stacked complementary field-effect transistor (CFET), which includes a gate and a metallic defined (MD) segment disposed between isolation structures in a region corresponding to a cell. The MD segment includes one of several MD segments configured to be connected to a reference voltage of a front-side conductor and a back-side conductor via an adjacent conductive structure including an interconnect structure. The interconnect structure is aligned with some or all of the gates and is located in the region corresponding to the cell and / or in the region corresponding to adjacent cells, for example, in the region between additional isolation structures aligned with the cells. In some embodiments, the stacked CFET of the cell is configured as a clock circuit.

[0019] Adjacent conductive structures, including interconnect structures, can provide low-resistance reference voltage connections from the front and back conductors to the circuitry corresponding to the cell (e.g., clock circuitry), thereby reducing voltage drops based on current flow compared to other methods (e.g., those that do not include adjacent conductive structures), thus enabling higher current operation, such as in high-drive clock cell applications.

[0020] The following discussion, based on various embodiments, Figures 1A to 1C These are plan and cross-sectional views of the IC devices and layout diagram 100. Figure 2 and Figure 3 These are planar diagrams of the IC device and layout diagrams 200 and 300, respectively. Figure 4A and Figure 4B These are plan and cross-sectional views of the IC devices and layout diagram 400. Figure 5 It is a flowchart of method 500 for manufacturing ICs, and Figure 6 For example, using Figure 7 The depicted IC layout generation system 700 and / or based on Figure 8 The flowchart depicts the method 600 for generating IC layout diagrams in the IC manufacturing process 800.

[0021] For illustrative purposes, each figure in this article has been simplified, for example... Figures 1A to 4B These figures are views of the IC structure, devices, and layout, including and excluding various components to facilitate the discussion below. In various embodiments, except... Figures 1A to 4B In addition to the components depicted, the IC structure, device and / or layout diagram includes one or more components corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, source / drain (S / D) structures, active regions, body connections or other transistor elements, isolation structures, etc.

[0022] In each of the IC device / layout diagrams 100-400, a reference indicator indicates the process used in manufacturing (e.g., below regarding...). Figure 5 The methods discussed are 500 and / or the following about Figure 8 The IC manufacturing process (as discussed in relation to the IC manufacturing system 800) at least partially defines the IC device components and IC layout components of the corresponding IC device components. Therefore, each of the IC device / layout diagrams 100-400 represents a view of the IC layout diagrams 100-400 and the corresponding IC device 100-400.

[0023] Each of the IC layout diagrams / devices 100-400 and IC layout diagram-400 discussed below includes some or all of the following arrangements: semiconductor substrate, active region / area, S / D region / structure, MD region / segment, gate region / structure, metal region / segment, interconnect and / or other via region / structure and / or isolation region / structure, each of which is discussed below.

[0024] A semiconductor substrate (e.g., substrate SUB) is a portion (e.g., a silicon (Si) wafer) or a portion (e.g., a die) of an epitaxial Si layer suitable for forming one or more IC devices (e.g., IC devices 100-400). In each embodiment discussed below, the semiconductor substrate includes a front side and a back side. On the front side, a first subset of the components of the IC device is formed by a first set of manufacturing processes (such as front-end process (FEOL), middle-end process (MEOL), and back-end process (BEOL). On the back side, a second subset of the components of the IC device is formed by a second set of manufacturing processes (such as a back-side metallization process) performed after the first set of manufacturing processes.

[0025] An active region / area (e.g., active region / area AA) is a region in an IC layout diagram that includes, during the manufacturing process, portions of a semiconductor substrate that define active regions directly or within an n-well or p-well region / area, and in some embodiments are also referred to as oxide diffusion or definition (OD), where one or more IC device components, such as S / D structures, are formed. In some embodiments, the active region is an n-type or p-type active region of a stacked complementary field-effect transistor (CFET) or another transistor configuration including a gate region / structure.

[0026] In various embodiments, the active region (structure) includes one or more of a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.), a dopant material (e.g., boron (B), aluminum (Al), phosphorus (P), arsenic (As), gallium (Ga)), or another suitable material.

[0027] In some embodiments, the active region is a region in an IC layout included in the manufacturing process, as part of defining a nanosheet structure, for example, a continuous volume of one or more layers of one or more semiconductor materials having n-type or p-type doping. In various embodiments, individual nanosheet layers comprise a single monolayer or multiple monolayers of a given semiconductor material.

[0028] An S / D region / structure (e.g., an S / D region or structure SD) is a region in an IC layout included in a manufacturing process, defining a portion of the S / D structure, and in some embodiments also referred to as a semiconductor structure, configured to have a doping type opposite to that of a corresponding active region / region. In some embodiments, the S / D region / structure is configured to have a lower resistivity than a portion of the corresponding active region / region of an adjacent channel component (e.g., a portion of the corresponding active region / region of a CFET or other transistor). In some embodiments, the S / D region / structure includes one or more portions with a doping concentration greater than one or more doping concentrations present in the corresponding channel component. In some embodiments, the S / D region / structure includes one or more epitaxial regions of a semiconductor material (e.g., Si, SiGe, and / or silicon carbide SiC). Depending on the context, an S / D region / structure (also referred to as an S / D terminal in some embodiments) may individually or collectively refer to a source or drain.

[0029] A MD region / segment (e.g., MD region / segment MD) is a conductive region in an IC layout included in a manufacturing process, as part of an MD segment defining a semiconductor substrate and / or an area on it, also referred to as a conductive segment, MD wire, or trace. In some embodiments, the MD region overlaps with an active region at the location of the S / D region in the IC layout, and the corresponding MD segment contacts and is electrically connected to the S / D structure of the active region.

[0030] In some embodiments, the MD segment includes a portion of at least one metal layer (e.g., a contact layer) that is situated on and in contact with the substrate and has a sufficiently small thickness to form an insulating layer between the MD segment and the overlying metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing low-resistance electrical connections between IC structural elements, i.e., a resistance level below a predetermined threshold, which corresponds to one or more tolerance levels for the resistance-based impact on circuit performance.

[0031] In various embodiments, the MD segment includes a portion of a semiconductor substrate and / or an epitaxial layer with a doped level, such that, for example, based on an implantation process, the segment has a low resistance level. In various embodiments, the doped MD segment includes one or more dopant materials with a doping concentration of approximately 1*102 16 / cubic centimeter (cm) -3 (or higher).

[0032] In some embodiments, the manufacturing process includes two MD layers and MD regions / segments, such as MD regions / segments (MD), which refer to two MD layers in the manufacturing process. In some embodiments, the MD segment is configured to be electrically connected to a single S / D structure in the p-type or n-type FET of the CFET and electrically isolated from the S / D structure of the other p-type or n-type FET of the CFET. In some embodiments, the MD segment (also referred to in some embodiments as MD local interconnect (MDLI) or local interconnect (LI)) is configured to be electrically connected to the S / D structures of the p-type FET and the n-type FET of the CFET.

[0033] The cut MD region is a region in the IC layout diagram included in the manufacturing process, serving as a definition of a discontinuous part in a given MD structure, such as a part that is etched away after the MD structure is formed, thereby causing adjacent and aligned MD segments to be electrically isolated from each other.

[0034] A gate region / structure (e.g., gate region / structure G) (also referred to as gate G in some embodiments) is a region included in an IC layout diagram during the manufacturing process, serving as a part defining the gate structure. The gate structure is a volume comprising one or more conductive segments (e.g., gate electrodes), comprising one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, thereby configuring the one or more conductive segments to control the voltage supplied at adjacent gate dielectric layers.

[0035] The gate dielectric layer (e.g., the gate dielectric layer of the gate structure G) is a volume comprising one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as low-k materials with a k value less than 3.8 or high-k materials with a k value greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), suitable for providing high resistance, i.e., a resistance level above a predetermined threshold, which corresponds to one or more tolerance levels for the resistance-based effect on circuit performance.

[0036] In some embodiments, the gate region / structure corresponds to a dummy gate region / structure, such as an isolation region / structure ISO. In some embodiments, the dummy gate region / structure includes a gate electrode electrically connected (e.g., bound) to one or more components, such as a power rail or other metal segment or an adjacent instance of the S / D region / structure, such that the transistor corresponding to the dummy gate region / structure and the overlapping / underlying active region / region is turned off by design. In some embodiments, the dummy gate region / structure overlapping / located above the edge of the active region / region is referred to as a continuous polysilicon on oxide-defined edge (CPODE) region / structure.

[0037] In some embodiments, the isolation region / structure (e.g., isolation region / structure ISO) includes a gate dielectric layer and / or one or more other dielectric layers, and is thus configured as an insulating layer capable of electrically isolating adjacent S / D structures, MD segments or other conductive components from each other.

[0038] A diced gate region (e.g., diced gate region CPO), also referred to in some embodiments as a diced polysilicon region, is a region included in the IC layout diagram during the manufacturing process. It defines a discontinuous portion within a given gate structure, such as a portion etched away after the gate electrode is formed, resulting in electrical isolation between adjacent and aligned gate electrode segments. A diced gate region can also be a diced metal gate (CMG) isolation, which refers to forming the diced gate region after the metal gate is formed.

[0039] A metal line or region (e.g., front metal region / segment M0, back metal region / segment BMO, or power rail or line VDD or VSS) is a region in an IC layout diagram included in a manufacturing process, as part of defining a metal line or segment in a given front or back metal layer of the manufacturing process, comprising one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials.

[0040] In some embodiments, a metal region / segment (e.g., metal region / segment M0) corresponds to the first or lowest front metal layer of the manufacturing process (also referred to in some embodiments as metal zero layer or front metal zero layer), or a second or higher level front metal layer. In some embodiments, a second front metal layer is referred to as metal one layer or front metal one layer, and a second back metal region / segment (e.g., metal region / segment M1) is referred to as metal one region / segment.

[0041] In some embodiments, the back metal region / segment (e.g., metal region / segment BMO) corresponds to the first or lowest back metal layer of the manufacturing process (also referred to as the back metal zero layer in some embodiments), or the second or higher level back metal layer.

[0042] In some embodiments, metal regions / segments (e.g., power rails or lines VDD or VSS) correspond to components of a power distribution network configured to distribute one or both of a power supply voltage (e.g., power supply voltage VDD) and a reference or ground voltage (e.g., reference voltage VSS). The power distribution network components are electrically connected to one or more parts, such as additional metal regions / segments and / or via regions / structures, configured to distribute the corresponding power supply or reference voltage, and electrically isolated from IC components outside the power distribution network.

[0043] A via region / structure (e.g., via region or structure VD or BVD or interconnect region / structure VLI), also referred to in some embodiments as a via or interconnect, is a region in an IC layout diagram included in a manufacturing process that defines a via / interconnect structure comprising one or more conductive materials configured to provide an electrical connection between a first (e.g., upper) conductive structure (e.g., metal segment M0, back-side metal segment BMO, or power rail or line VDD or VSS) and a second (e.g., lower) conductive structure aligned in the Z direction with the first conductive structure (e.g., metal segment, gate electrode of gate structure G, instance of MD segment MD, interconnect structure VLI, or S / D structure SD).

[0044] In some embodiments, the via region / structure VD and / or the back via region / structure BVD correspond to the following conductive structures, namely the S / D region / structure SD, the MD region / segment MD, or the interconnect region / structure VLI.

[0045] In some embodiments, the interconnect region / structure VLI (also referred to in some embodiments as local interconnect region / structure VLI or vertical local interconnect region / structure VLI) corresponds to each of the conductive structures below or above (one or more instances of MD region / segment MD, front via region / structure VD, or back via region / structure BVD).

[0046] Figure 1A This includes IC layout diagrams / device 100, as well as planar and block diagrams in the X and Y directions, and Figure 1B and Figure 1C Including along Figure 1A IC layout diagram / cross-sectional view of device 100 along lines A-A' and B-B', Y direction and Z direction. Figure 2 and Figure 3 Each of these includes the corresponding IC layout diagram / device 200 or 300, as well as planar and block diagrams in the X and Y directions. Figure 4A This includes IC layout diagrams / device 400, as well as planar and block diagrams in the X and Y directions, and Figure 4B Including along Figure 4AThe layout diagram of IC / cross-sectional view of device 400 along line C-C' and in the Y and Z directions. In some cases, for clarity, Figures 1A to 4B Not all instances of each component, including IC layout diagrams / devices 100-400, are marked.

[0047] like Figure 1B , Figure 1C and Figure 4B The depicted IC layout / device 100-400 corresponds to an example of a stacked CFET TU / TL, which has a nanosheet configuration and includes an upper transistor TU and a lower transistor TL. The upper transistor TU is positioned further along the positive Z-direction than the lower transistor TL. In various embodiments, the upper transistor TU includes an n-type transistor and the lower transistor TL includes a p-type transistor, or the upper transistor TU includes a p-type transistor and the lower transistor TL includes an n-type transistor.

[0048] IC layout diagrams / devices, including those discussed below, corresponding to configurations of other transistor types (e.g., FinFETs or planar transistors), are within the scope of this disclosure.

[0049] like Figures 1A to 4B As shown, each of the IC layout diagrams / devices 100-400 includes one or more instances of cells C1-C6, as further discussed below. A given cell instance corresponds to an IC layout diagram configured to be stored in a storage device, such as a cell library, like cell library 707 discussed below with respect to the IC layout diagram generation system 700, which at least partially defines the IC structure or device within a corresponding area of ​​an IC manufactured based on that cell. In some embodiments, the IC structure or device corresponding to cells C1-C6 is referred to as circuits C1-C6.

[0050] In some embodiments, the cell includes opposing boundary segments, such as opposing segments of the cell boundaries CB of cells C1-C6, including instances of isolation regions ISO, and the IC device based on the cell includes regions between corresponding isolation structures ISO. Figures 1A to 4B The instances of the element boundaries CB (dashed lines) depicted for elements C1-C6 correspond to the element height CH and element width CW, which will be discussed further below.

[0051] The components within a given cell C1-C6 are configured according to one or more electrical functions of an IC device manufactured based on an IC layout diagram, such as active switching or logic functions, or passive connection or loading functions. For example... Figures 1A to 4BAs depicted, cell C1 includes an instance of a stacked CFET transistor TU / TL configured to perform an active electrical function; each of cells C2 and C3 includes a conductive structure including an instance of an interconnect region / structure VLI configured to provide an electrical connection between front-side and back-side vias VD / BVD and / or metal lines M0 / BM0; and each of cells C4-C6 includes one or more instances of a stacked CFET-TL configured to perform an active electrical function and one or more instances of a conductive structure including an interconnect region / structure VLI.

[0052] In some embodiments, one or more of units C1 or C4-C6 are clock units, which include instances of stacked CFET transistors TU / TL configured as corresponding clock circuits C1 or C4-C6. In some embodiments, clock units / circuits C1 or C4-C6 are included in clock distribution circuits, such as clock trees. In some embodiments, clock units / circuits C1 or C4-C6 are referred to as high-drive clock units / circuits.

[0053] The instances of stacked CFET transistors TU / TL included in each cell / circuit C1 and C4-C6 include corresponding instances of gate region / structure G and MD region / segment MD, which extend across instances of active region / region AA in the Y direction (cell height CH direction) and are located between instances of isolation region / structure ISO along the X direction (cell width CW direction).

[0054] Instances of interconnect regions / structures VLI included in cells / circuits C2-C6 are positioned adjacent to corresponding instances of stacked CFET transistors TU / TL in the Y direction, such that the corresponding gate region / structure G is aligned with the corresponding interconnect region or structure VLI in the Y direction. For example... Figure 1A and Figures 2 to 4A The depicted units C2-C6 include instances of diced gate CPO, the diced gate CPO surrounding corresponding instances of interconnect regions / structures VLI, and thus configured to electrically isolate the corresponding instances of interconnect regions / structures VLI from adjacent components including corresponding adjacent instances of gate regions / structures G.

[0055] In some embodiments, instances of interconnect regions / structures VLI extend across the width CW of the corresponding cells C2-C6, such that the entire corresponding instance of the gate region / structure G is aligned with the instance of the interconnect region / structure VLI in the Y direction. In some embodiments, instances of interconnect regions / structures VLI extend across the width CW of the corresponding cells C2-C6, such that fewer than all of the corresponding instances of the gate region / structure G are aligned with the instance of the interconnect region / structure VLI in the Y direction, for example, all instances except for one or two of the outermost instances of the corresponding instances of the gate region / structure G along the X direction.

[0056] Figures 1A to 4B The number and orientation of cells C1-C6, as well as the width and number of gate region structures G of cells C1-C6, depicted are non-limiting examples provided for illustrative purposes. Except... Figures 1A to 4B Beyond those depicted, the number and orientation of cells C1-C6, as well as the width and number of gate regions / structures G, are within the scope of this disclosure.

[0057] like Figures 1A to 1C The depicted IC layout diagram 100 includes instances of cell / circuit C1 adjacent to cell / circuit C2 in the Y direction and instances of cell or circuit C1 adjacent to cell / circuit C3 in the Y direction. In some embodiments, the IC layout diagram 100 does not include instances of cell / circuit C1 and adjacent cell / circuit C2, or instances of cell or circuit C1 and adjacent cell or circuit C3.

[0058] Each cell C1-C3 (referred to in some embodiments as a single cell height cell C1-C3) has a cell height CH corresponding to the pitch (unmarked) of each of the back-side power supply voltage line VDD and the front-side reference voltage line VSS.

[0059] like Figure 1B and Figure 1C The depicted cell / circuit C1 includes an example of stacked CFET TU / TL, which includes an example of an MD region / structure MD extending in the Y direction to the adjacent cell / circuit C2 or C3, and the adjacent cell / circuit C2 or C3 includes a corresponding example of an MD region / structure MD. Cell C1 and the adjacent cell C2 or C3 include corresponding examples of MD regions MD adjacent to each other, such that the MD segment MD of the corresponding circuit C2 or C3 is a continuous conductive structure.

[0060] In some embodiments, adjacent MD regions and continuous conductive structures are referred to as MD regions / segments MD, and instances of MD regions / segments MD in circuit C2 or C3 are referred to as portions of MD regions / segments MD.

[0061] In some embodiments, an instance of the gate region / structure G in cell / circuit C1 is considered to extend from a first position along the Y direction to a second position along the Y direction, and the MD region / segment MD is considered to extend from the first position to a third position further along the Y direction than the second position, with a portion of the MD region / segment MD in cell / circuit C2 or C3 located between the second and third positions.

[0062] Each of the units / circuits C2 and C3 includes an interconnection region / structure VLI extending in the Z direction and aligned in the Z direction with a portion of the MD region / segment MD, a front via region / structure VD, a front metal region / line VSS in the bottommost front layer M0, a back via region / structure BVD, and a back metal region / line VSS in the bottommost back metal layer BMO.

[0063] In some embodiments, one or more of the front via region / structure VD, front metal region / line VSS, back via region / structure BVD, or back metal region / line VSS are not included in the cell / circuit (e.g., cell / circuit C2 or C3), but are included in the metal interconnect structure (e.g., MEOL or BEOL structure).

[0064] A portion of the MD region / segment MD, interconnect region / structure VLI, front via region / structure VD, and back via region / structure BVD are configured to extend between and electrically connect to the front metal region / line VSS and the back metal region / line VSS, forming a conductive structure. In some embodiments, the conductive structure extends between and electrically connects to the front metal region / line VDD and the back metal region / line VDD. In some embodiments, the conductive structure is referred to as a power pickup or an embedded power pickup.

[0065] exist Figures 1A to 1C In the depicted embodiments, each conductive structure extends along the Z-direction such that the components included in the conductive structure are aligned in the Z-direction. In some embodiments, one or more components of a given conductive structure are not aligned with one or more other components of the conductive structure in the Z-direction; for example, the front via VD and metal wire VSS are not aligned with the back via BVD and metal wire VSS in the Z-direction.

[0066] exist Figures 1A to 1C In the depicted embodiments, an example of a stacked CFET TU / TL in cell / circuit C1 includes a transistor TU configured as an n-type transistor, the transistor TU including an MD region / segment MD configured as a reference voltage connection of cell / circuit C1, and the conductive structure including an MD segment MD located on an interconnect region / structure VLI, a front via region structure VD adjacent to the MD structure MD, and a back via region / structure BVD adjacent to the interconnect region / structure VLI.

[0067] In some embodiments, instances of stacked CFET TU / TL and adjacent conductive structures are configured in other ways, for example, by including the MD segment MD corresponding to the MD portion in the transistor TL instead of the transistor TU and / or configuring it as a power supply voltage VDD connection for the cell / circuit instead of a reference voltage connection. In some embodiments, the conductive structures include an interconnect region / structure VLI located on the MD segment MD, a front via region structure VD adjacent to the interconnect region / structure VLI, and a back via region / structure BVD adjacent to the MD structure MD.

[0068] like Figure 1A and Figure 1B In addition to instances of interconnect regions / structures VLI, the depicted cell / circuit C2 includes a CFET electrically isolated from adjacent components, also referred to in some embodiments as a pseudo-CFET. Instances of interconnect regions / structures VLI are located between cell / circuit C1 and the pseudo-CFET, and the combination of instances of interconnect regions / structures VLI and the pseudo-CFET extends across the cell height CH. In some embodiments, by including a pseudo-CFET in cell C2 adjacent to cell C1, the load uniformity of one or more manufacturing processes for fabricating one or more instances of stacked CFET transistors TU / TL (e.g., included in circuit C1) is improved, resulting in improved uniformity of the corresponding CFET components compared to embodiments that do not include a pseudo-CFET (e.g., cell C3 discussed below).

[0069] like Figure 1A and Figure 1C As depicted, cell / circuit C3 does not include a pseudo-CFET, and instances of interconnect regions / structures VLI extend across the cell height CH. In some embodiments, by including interconnect regions / structures VLI extending across the cell length CH, cell C3 is capable of including interconnect regions / structures VLI with lower resistance compared to embodiments where interconnect regions / structures VLI do not extend across the cell width CH (e.g., cell C2 discussed above).

[0070] In addition to the electrical connections provided by unit / circuit C2 or C3, unit / circuit C1 includes one or more instances of front via region / structure VD (e.g., a corresponding instance electrically connected to MD region / segment MD and additional front metal line VSS) and one or more instances of back via region / structure BVD (e.g., additional instances electrically connected to MD region / segment MD and back metal line VDD).

[0071] As discussed above, the IC layout / device 100 includes cells / circuits C1 / C2 and / or C1 / C3, which are configured to include stacked CFET TU / TL, which includes gate regions / structures G and MD regions / segments MD disposed between isolation regions / structures ISO, and includes MD regions / segments MD, which include portions configured to be connected to reference voltages of front-side and back-side conductors VSS via adjacent conductive structures including interconnect regions / structures VLI. Interconnect regions / structures VLI are aligned with some or all of the gate regions / structures G of cell / circuit C1 and are located in one of the cells C2 or C3 adjacent to cell / circuit C1, and in some embodiments are configured as clock cells / circuits.

[0072] The adjacent conductive structure, including the interconnect region / structure VLI, can provide a low-resistance reference voltage connection from the front and back conductors VSS to the cell / circuit C1, thereby reducing the voltage drop based on current flow compared to other methods (such as those that do not include adjacent conductive structures), thus enabling higher current operation, such as high-drive clock cell applications.

[0073] like Figures 2 to 4B The depicted IC layout diagrams / devices 200-400 each include the information described above. Figures 1A to 1C The components discussed in the arrangement, except for the circuitry including the stacked CFET TU / TL and the adjacent conductive structures including the interconnect region / structure VLI, are all included in a single corresponding cell / circuit C4-C6, rather than in separate cells / circuits C1 / C2 or C1 / C3.

[0074] exist Figure 2 In the depicted embodiments, the IC layout / device 200 includes a cell / circuit C4, the cell height of which is twice the cell height CH of the cells / circuits C1-C3 discussed above. In some embodiments, the cell / circuit C4, referred to as a double-height cell, includes an instance of an interconnect region / structure VLI and an instance of a stacked CFET TU / TL located between two instances of an isolation region / structure ISO.

[0075] exist Figure 3 In the depicted embodiments, the IC layout / device 300 includes one or more instances of cell / circuit C5, whose cell height CH5 is equal to 1.5 times the cell height CH of cells / circuits C1-C3 discussed above. Cell / circuit C5 includes instances of interconnect regions / structures VLI and instances of stacked CFET TU / TL located between two instances of isolation regions / structures ISO. In some embodiments, instances of cell / circuit C5 are positioned adjacent to each other in the Y direction such that the sum of the two cell heights CH5 is equal to three times the cell height CH.

[0076] In some embodiments, such as Figure 3 As depicted, adjacent instances of cell / circuit C5 have opposite orientations relative to the Y direction, such that instances of interconnect region VLI are adjacent at a shared cell boundary, thereby defining a single interconnect structure VLI shared by instances of stacked CFET TU / TL in adjacent instances of cell / circuit R5.

[0077] exist Figure 4A and Figure 4B In the depicted embodiment, the IC layout / device 400 includes a cell / circuit C6 with a cell height equal to three times the cell height CH of the cells / circuits C1-C3 discussed above. Cell / circuit C6 (referred to in some embodiments as a triple-height cell) includes a single instance of a stacked CFET TU / TL located between two instances of the interconnect region / structure VLI, an instance of the stacked CFET TU / TL, and two instances of the interconnect region / structure VLI located between two instances of the isolation region / structure ISO.

[0078] like Figure 4A and Figure 4B The depicted MD region / segment MD is thus configured to be included in two adjacent conductive structures (including instances of interconnect regions / structures VLI).

[0079] As discussed above, each of the IC layouts / devices 200-400 is thus configured to include a corresponding cell / circuit C4-C6, which includes one or more instances of a stacked CFET TU / TL, the stacked CFET TU / TL including a gate region / structure G and an MD region / segment MD arranged between isolation regions / structures ISO, and including an MD region / segment MD including portions configured to be connected to a reference voltage of a front-side conductor and a back-side conductor VSS via one or more adjacent conductive structures (including instances of interconnect regions / structures VLI). One or more instances of interconnect regions / structures VLI are aligned with some or all of the adjacent instances of gate regions / structures G, such that each of the IC layouts / devices 200-400 including one or more instances of the corresponding cell / circuit C4-C6 can achieve the benefits discussed above regarding IC layouts / devices 100.

[0080] Figure 5 This is a flowchart of a method 500 for manufacturing an IC device according to some embodiments. Method 500 is operable to form the above-described... Figures 1A to 4B Some or all of one or more of the IC devices 100-400 discussed.

[0081] In some embodiments, some or all of the operations of performing method 500 are portions of constructing multiple IC devices (e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices) by performing a number of manufacturing operations (e.g., photolithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for constructing multiple IC devices in a semiconductor substrate).

[0082] In some embodiments, the operation of method 500 is as follows: Figure 5 The described sequence of execution. In some embodiments, the operation of method 500 is in accordance with... Figure 5 The order of execution differs from that described herein. In some embodiments, one or more additional operations are performed before, during, and / or after the operation of method 500. In some embodiments, performing some or all of the operations of method 500 includes performing the following descriptions of the IC manufacturing system 800 and... Figure 8 One or more operations are being discussed.

[0083] At operation 502, in some embodiments, a plurality of stacked CFETs are constructed by forming a gate structure and an MD segment between a first isolation structure and a second isolation structure, the MD segment being aligned with an interconnect structure and configured for a reference voltage connection. Forming the gate includes forming a gate extending in a first direction, as well as the first and second isolation structures, and the gate being located between the first and second isolation structures in a second direction perpendicular to the first direction. Forming the MD segment aligned with the interconnect structure includes forming an MD segment aligned with the interconnect structure in a third direction perpendicular to both the first and second directions.

[0084] In some embodiments, constructing multiple stacked CFETs includes constructing instances of stacked CFET TU / TL by forming gate structures G and MD segments MD between instances of isolation structures ISO, and including MD segments MD configured to be connected to a reference voltage, and including those described above regarding IC layout devices 100-400 and Figures 1A to 4B The discussed interconnect structure VLI instance is aligned to the part.

[0085] Building multiple stacked CFETs involves configuring multiple stacked CFETs according to one or more electrical functions, for example, corresponding to the above regarding... Figures 1A to 4B The discussed cells / circuits are C1 and / or C4-C6. In some embodiments, constructing multiple stacked CFETs includes configuring the multiple stacked CFETs as a clock circuit.

[0086] Forming MD segments aligned with the interconnect structure includes forming the interconnect structure. In some embodiments, forming the interconnect structure includes forming an interconnect structure between a first isolation structure and a second isolation structure.

[0087] In some embodiments, forming the first isolation structure and the second isolation structure includes forming a third isolation structure and a fourth isolation structure that extend parallel to each other in a first direction and are aligned with the first isolation structure and the second isolation structure in the front side of the semiconductor substrate, and forming an interconnect structure includes forming an interconnect structure between the third isolation structure and the fourth isolation structure.

[0088] Building multiple stacked CFETs by forming gate structures and MD segments involves performing one or more of multiple manufacturing processes, including photolithography, diffusion, implantation, deposition, plasma processing, etching, planarization, spin coating, soft baking, exposure, post-baking, development, rinsing, drying, or other suitable operations.

[0089] At operation 504, a front via is formed on one of the MD segments or interconnect structures, and a front conductor is formed on the front via. Forming the front conductor includes forming a front conductor extending in a second direction.

[0090] In some embodiments, forming the front via and the front conductor includes forming the IC layout devices 100-400 described above. Figures 1A to 4B The through-hole structure VD and the front metal line VSS are discussed.

[0091] In some embodiments, forming a front via includes forming a front via on an MD segment, the MD segment including the front MD segment of an n-type transistor of a plurality of stacked CFETs.

[0092] In some embodiments, forming a front through hole includes forming a plurality of front through holes, for example, including a front through hole on the MD segment; and forming a front guide includes forming a plurality of front guides on the plurality of front through holes.

[0093] Forming front-side vias and front-side conductors involves performing multiple manufacturing operations, including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, whereby one or more conductive materials are configured to form multiple consecutive low-resistance structures.

[0094] At operation 506, a back-side via is formed on another segment of the MD structure or interconnect, and a back-side conductor is formed on the back-side via. Forming the back-side conductor includes forming a back-side conductor extending in a second direction.

[0095] In some embodiments, forming a back-side via and a back-side conductor includes forming the above-mentioned IC layout devices 100-400 and Figures 1A to 4B The through-hole structure BVD and the back-side metal wire VSS are discussed.

[0096] In some embodiments, forming a back-side via includes forming a plurality of back-side vias, for example, including a back-side via on the MD segment; and forming a back-side conductor includes forming a plurality of back-side conductors on the plurality of back-side vias.

[0097] Forming back-side vias and back-side conductors involves performing multiple manufacturing operations, including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, whereby one or more conductive materials are configured to form multiple consecutive low-resistance structures.

[0098] By performing some or all of the operations of method 500, an IC device is manufactured in which the interconnect structure is aligned with the gate structure of an adjacent circuit, which includes stacked CFETs located in a region between isolation structures, thereby enabling the benefits discussed above regarding IC devices 100-400.

[0099] Figure 6 It is a generated IC layout diagram based on some embodiments (e.g., the above regarding Figures 1A to 4B The flowchart of method 600 (one or more of the IC layout diagrams 100-400 discussed) is shown.

[0100] In some embodiments, generating an IC layout includes generating and manufacturing an IC device based on the generated IC layout (e.g., as mentioned above). Figures 1A to 4B The IC layout diagrams corresponding to the IC devices (100-400) discussed.

[0101] In some embodiments, some or all of method 600 is executed by the computer's processor, for example, as described below. Figure 7 The processor 702 of the IC layout generation system 700 discussed.

[0102] Some or all of the operations of method 600 can be performed in the design room (e.g., as described below). Figure 8 The design process is carried out in part of the design process in the design room (820) under discussion.

[0103] In some embodiments, the operation of method 600 is as follows: Figure 6 The operations of method 600 are executed sequentially as described herein. In some embodiments, the operations of method 600 are performed simultaneously and / or in conjunction with... Figure 6 The order of execution differs from that depicted. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 600.

[0104] At operation 602, in some embodiments, the interconnect region is extended across the width of the cell. In some embodiments, extending the interconnect region across the width of the cell includes extending the interconnect region VLI across the width of the cell as described above. Figures 1A to 4BThe cell width CW of one or more cells C2-C6 is extended as discussed.

[0105] At operation 604, in some embodiments, the interconnect region overlaps with the MD region. In some embodiments, overlapping the interconnect region with the MD region includes making the interconnect region VLI overlap with the region described above. Figures 1A to 4B The MD regions under discussion partially overlap.

[0106] At operation 606, in some embodiments, the interconnect region and the MD region overlap with each of the front via region and the back via region. In some embodiments, overlapping the interconnect region and the MD region with each of the front via region and the back via region includes making the interconnect region VLI and the MD region MD overlap with the above-mentioned... Figures 1A to 4B The front via region VD and the back via region BVD overlap in the discussion.

[0107] At operation 608, in some embodiments, the cell is adjacent to a second cell in the IC layout diagram. In some embodiments, adjacenting the cell to the second cell includes making one or more instances of cell C2 or C3 similar to those described above. Figures 1A to 1C One or more instances of cell C1 in the IC layout diagram 100 discussed are adjacent.

[0108] In some embodiments, making a unit adjacent to a second unit includes making one or more instances of one or more of units C1-C6 related to the above-mentioned... Figures 1A to 4B One or more additional instances of cells C1-C6 in one or more of the IC layout diagrams 100-400 discussed are adjacent to each other.

[0109] At operation 610, in some embodiments, the front via region overlaps with the front metal region, and the back via region overlaps with the back metal region. In some embodiments, overlapping the front via region with the front metal region and overlapping the back via region with the back metal region includes overlapping the front via region VD with the front metal line VSS and overlapping the back via region BVD with the back metal line VSS, as described above regarding... Figures 1A to 4B The subject of discussion.

[0110] In some embodiments, overlapping the front via region with the front metal region and overlapping the back via region with the back metal region includes overlapping one or more additional front via regions with one or more additional front metal regions and / or overlapping one or more additional back via regions with one or more additional back metal regions, for example, as described above regarding Figures 1A to 4B The subject of discussion.

[0111] At operation 612, in some embodiments, an IC layout diagram including cells is stored in a memory device. In some embodiments, storing the IC layout diagram in the memory device includes storing the above-mentioned... Figures 1A to 4B The cells C1-C6 or one or more of the IC layouts in Figures 100-400 discussed are stored in a storage device.

[0112] In some embodiments, storing an IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile computer-readable storage medium or a database, and / or includes storing the IC layout diagram over a network. In some embodiments, storing an IC layout diagram in a storage device includes storing the IC layout diagram in a cell library 707 or a layout diagram 709 and / or via the following description... Figure 7 The network 714 storage of the IC layout generation system 700 is discussed.

[0113] At operation 614, in some embodiments, one or more manufacturing operations and one or more photolithographic exposures are performed based on the IC layout diagram. (The above is about...) Figure 5 And the following text about Figure 8 Non-limiting examples of performing one or more manufacturing operations (e.g., one or more photolithography exposures) based on an IC layout diagram are discussed.

[0114] By performing some or all of the operations of method 600, an IC layout diagram corresponding to the IC device is generated, wherein the interconnect structure is aligned with the gate structure of the adjacent circuit, which includes stacked CFETs in the region between the isolation structures, thereby enabling the benefits discussed above regarding IC devices 100-400 to be realized.

[0115] Figure 7 This is a block diagram of an IC layout generation system 700 according to some embodiments. The method for designing IC layouts described herein is implementable according to one or more embodiments, for example, using the IC layout generation system 700 according to some embodiments.

[0116] In some embodiments, the IC layout generation system 700 is a general-purpose computing device including a hardware processor 702 and a non-transitory computer-readable storage medium 704. Among other things, the storage medium 704 also encodes (i.e., stores) computer program code 706, which is a set of executable instructions. Execution of the instructions 706 by the hardware processor 702 represents (at least partially) an electronic design automation (EDA) tool that implements part or all of the method, such as those described above. Figure 6 The method 600 described for generating IC layout diagrams (hereinafter referred to as the process and / or method) is as follows.

[0117] Processor 702 is electrically coupled to computer-readable storage medium 704 via bus 708. Processor 702 is also electrically coupled to I / O interface 710 via bus 708. Network interface 712 is also electrically connected to processor 702 via bus 708. Network interface 712 is connected to network 714, enabling processor 702 and computer-readable storage medium 704 to be connected to external components via network 714. Processor 702 is configured to execute computer program code 706 encoded in computer-readable storage medium 704 so that IC layout generation system 700 can be used to perform some or all of the process and / or method. In one or more embodiments, processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0118] In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 704 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0119] In one or more embodiments, the computer-readable storage medium 704 stores computer program code 706 configured to enable an IC layout generation system 700 (where such an execution representation (at least partially) EDA tool) to perform part or all of the process and / or method. In one or more embodiments, the computer-readable storage medium 704 also stores information that facilitates the execution of part or all of the process and / or method.

[0120] In one or more embodiments, computer-readable storage medium 704 stores a unit library 707 that includes units of the type disclosed herein, such as those described above. Figures 1A to 4B The memory cell 112 in the IC layout diagram 200-400 is discussed.

[0121] In one or more embodiments, computer-readable storage medium 704 stores layout diagram 709, including the IC layout diagrams disclosed herein, such as those described above. Figures 1A to 4B The IC layout diagrams 100-400 are discussed.

[0122] IC layout generation system 700 includes an I / O interface 710. The I / O interface 710 is coupled to external circuitry. In one or more embodiments, the I / O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 702.

[0123] The IC layout generation system 700 also includes a network interface 712 coupled to a processor 702. The network interface 712 allows the system 700 to communicate with a network 714 to which one or more other computer systems are connected. The network interface 712 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the described process and / or method are implemented in two or more IC layout generation systems 700.

[0124] The IC layout generation system 700 is configured to receive information via I / O interface 710. The information received via I / O interface 710 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 702. This information is transmitted to processor 702 via bus 708. The IC layout generation system 700 is also configured to receive UI-related information via I / O interface 710. This information is stored as a user interface (UI) 742 on computer-readable medium 704.

[0125] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an IC layout generation system 700. In some embodiments, software applications such as those available from CADENCE DESIGN SYSTEMS are used. Use tools or another suitable layout generation tool to generate layout diagrams that include standard cells.

[0126] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), etc.

[0127] Figure 8 This is a block diagram of an IC manufacturing system 800 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on an IC layout diagram, the manufacturing system 800 manufactures at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0128] exist Figure 8 In this IC manufacturing system 800, entities such as design studio 820, mask room 830, and IC manufacturer / manufacturer (“manufacturer”) 850 interact in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 860. The entities in system 800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a series of separate networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 820, mask room 830, and IC manufacturer 850 are owned by a single, larger company. In some embodiments, two or more of the design studio 820, mask room 830, and IC manufacturer 850 coexist in a shared facility and use shared resources.

[0129] The design studio (or design team) 820 generates the IC design layout 822. The IC design layout 822 includes various geometric patterns, such as those mentioned above. Figures 1A to 4B One or more of the IC layout diagrams 100-400 discussed. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 860 to be manufactured. The individual layers combine to form various IC components. For example, a portion of the IC design layout diagram 822 includes various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design room 820 performs appropriate design processes to form the IC design layout diagram 822. Design processes include one or more of logic design, physical design, or placement and routing. The IC design layout diagram 822 is presented in the form of one or more data files containing information about the geometric patterns. For example, the IC design layout diagram 822 may be represented in GDSII or DFII file format.

[0130] Mask chamber 830 includes data preparation 832 and mask fabrication 844. Mask chamber 830 uses an IC design layout 822 to fabricate one or more masks 845 for fabricating various layers of an IC device 860 according to the IC design layout 822. Mask chamber 830 performs mask data preparation 832, in which the IC design layout 822 is converted into a representative data file (RDF). Mask data preparation 832 provides the RDF to mask fabrication 844. Mask fabrication 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 845 or a semiconductor wafer 853. The design layout 822 is manipulated by mask data preparation 832 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer 850. Figure 8 In this diagram, mask data preparation 832 and mask manufacturing 844 are shown as separate elements. In some embodiments, mask data preparation 832 and mask manufacturing 844 may be collectively referred to as mask data preparation.

[0131] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 822. In some embodiments, mask data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, treating OPC as an inverse imaging problem.

[0132] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks the IC design layout 822, which has been processed in the OPC, against a set of mask creation rules. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 822 to compensate for constraints during mask fabrication 844, which may undo some modifications performed by the OPC to satisfy the mask creation rules.

[0133] In some embodiments, mask data preparation 832 includes lithography process inspection (LPC), an LPC simulation performed by IC manufacturer 850 to manufacture IC device 860. The LPC simulates this process based on IC design layout 822 to create a simulated manufactured device, such as IC device 860. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, or combinations thereof. In some embodiments, after the LPC has created the simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 822.

[0134] It should be understood that, for clarity, the above description of mask data preparation 832 has been simplified. In some embodiments, data preparation 832 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 822 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 822 during data preparation 832 can be performed in various different sequences.

[0135] After mask data preparation 832 and during mask fabrication 844, a mask 845 or a set of masks 845 is fabricated based on a modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more photolithographic exposures based on the IC design layout 822. In some embodiments, a pattern is formed on the mask (photomask or intermediate mask) 845 using a mechanism of electron beams (e-beams) or multiple electron beams based on the modified IC design layout 822. The mask 845 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 845. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (such as ultraviolet (UV) or EUV beams) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 845. In the phase-shifting mask (PSM) version of mask 845, various components in the pattern formed on the phase-shifting mask are configured with appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 844 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 853, in etching processes to form various etched regions in semiconductor wafer 853, and / or in other suitable processes.

[0136] IC Manufacturer 850 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Manufacturer 850 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility for providing other services for foundry operations.

[0137] IC manufacturer 850 includes wafer fabrication tool 852 configured to perform various manufacturing operations on semiconductor wafer 853, such that IC device 860 is fabricated according to a mask (e.g., mask 845). In various embodiments, fabrication tool 852 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes discussed herein.

[0138] IC manufacturer 850 uses mask 845, manufactured by mask chamber 830, to manufacture IC device 860. Therefore, IC manufacturer 850 uses IC design layout 822 at least indirectly to manufacture IC device 860. In some embodiments, semiconductor wafer 853 is manufactured by IC manufacturer 850 using mask 845 to form IC device 860. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 853 also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed at subsequent manufacturing steps).

[0139] In some embodiments, the IC device includes: a first isolation structure and a second isolation structure extending parallel to each other in a first direction on the front side of a semiconductor substrate; a circuit including a plurality of stacked CFETs, each CFET including a plurality of gates and a plurality of MD segments extending in the first direction between the first and second isolation structures, wherein each of the plurality of gates extends from a first location along the first direction to a second location along the first direction, and the MD segments of the plurality of MD segments are configured as a reference voltage connection of the circuit and extend from the first location to a third location further along the first direction than the second location; a first conductor extending in a second direction perpendicular to the first direction on the front side of the semiconductor substrate; a second conductor extending in the second direction on the back side of the semiconductor substrate; and a conductive structure extending from the first conductor to the second conductor in a third direction perpendicular to each of the first and second directions, wherein the conductive structure includes a portion of the MD segment located between the second location and the third location. In some embodiments, the conductive structure includes: an interconnect structure partially adjacent to an MD segment along a third direction; a front via extending from a first conductor to one of the MD segment or the interconnect structure; and a back via extending from a second conductor to the other of the MD segment or the interconnect structure. In some embodiments, each of a plurality of gates is aligned with the interconnect structure along a first direction. In some embodiments, an MD segment among a plurality of MD segments includes a front MD segment of an n-type transistor of a corresponding stacked CFET in a plurality of stacked CFETs. In some embodiments, the IC device includes: a third conductor extending in a second direction on the front side of a semiconductor substrate; and a front via extending from the third conductor to the MD segment. In some embodiments, the IC device includes: a third isolation structure and a fourth isolation structure extending parallel in a first direction and aligned with a first isolation structure and a second isolation structure on the front side of a semiconductor substrate, wherein a conductive structure is located between the third isolation structure and the fourth isolation structure. In some embodiments, the IC device includes: a pseudo-stacked CFET located between the third isolation structure and the fourth isolation structure, wherein a conductive structure is located between the pseudo-stacked CFET and the stacked CFET including the MD segment. In some embodiments, the conductive structure is located between the first isolation structure and the second isolation structure.In some embodiments, the circuit is a first circuit including a plurality of stacked CFETs, the plurality of stacked CFETs being a first plurality of stacked CFETs, the first plurality of stacked CFETs including a plurality of gates and a plurality of MD segments, the plurality of gates and the plurality of MD segments being a first plurality of gates and a first plurality of MD segments, the IC device including: a third isolation structure and a fourth isolation structure extending parallel in a first direction and aligned with the first isolation structure and the second isolation structure on the front side of the semiconductor substrate; and a second circuit located between the third isolation structure and the fourth isolation structure and including a second plurality of stacked CFETs, the second plurality of stacked CFETs including a second plurality of gates and a second plurality of MD segments, a conductive structure located between the first circuit and the second circuit, and the MD segment being an MD segment among the second plurality of MD segments configured as a reference voltage connection of the second circuit. In some embodiments, the conductive structure is a first conductive structure, the MD segment further extending along a first direction from a first location to a fourth location, the first location being between a second location and a fourth location, and the IC device including: a third conductor extending in a second direction on the front side of the semiconductor substrate; a fourth conductor extending in a second direction on the back side of the semiconductor substrate; and a second conductive structure extending from the third conductor to the fourth conductor and including another portion of the MD segment located between the first location and the fourth location. In some embodiments, the circuit includes a plurality of stacked CFETs configured as a clock circuit.

[0140] In some embodiments, a method of manufacturing an IC device includes: constructing a first isolation structure and a second isolation structure, and a plurality of stacked CFETs, on the front side of a semiconductor substrate. Constructing the plurality of stacked CFETs includes: forming a plurality of gates and a plurality of MD segments extending in the first direction between the first isolation structure and the second isolation structure in a second direction perpendicular to the first direction; and forming an interconnect structure adjacent to and aligned with the plurality of gates in the first direction, wherein portions of the MD segments of the plurality of MD segments are aligned with the interconnect structure in a third direction perpendicular to each of the first and second directions. The method includes: forming a front-side via on a portion of the MD segment or one of the interconnect structures; forming a front-side conductor on the front-side via, the front-side conductor extending in the second direction; forming a back-side via on another of the MD segments or the interconnect structure; and forming a back-side conductor on the back-side via, the back-side conductor extending in the second direction. In some embodiments, forming the front-side via includes forming a front-side via on a portion of the MD segment, the portion of the MD segment comprising the front-side MD segment of an n-type transistor of a respective stacked CFET in the plurality of stacked CFETs. In some embodiments, forming a front via includes forming a first front via on a portion of the MD segment, and further includes forming a second front via on the MD segment; and forming a front conductor includes forming a first front conductor on the first front via, and further includes forming a second front conductor on the second front via, wherein the second front conductor extends in a second direction. In some embodiments, constructing a first isolation structure and a second isolation structure includes constructing a third isolation structure and a fourth isolation structure that extend parallel to each other in a first direction and are aligned with the first isolation structure and the second isolation structure in the front side of the semiconductor substrate, and forming an interconnect structure includes forming an interconnect structure between the third isolation structure and the fourth isolation structure. In some embodiments, constructing a plurality of stacked CFETs includes configuring the plurality of stacked CFETs as a clock circuit, the clock circuit including an MD segment configured to be connected to a reference voltage.

[0141] In some embodiments, a method for generating an IC layout includes: extending an interconnect region across the width of a cell; overlapping the interconnect region with a MD region; overlapping the interconnect region and the MD region with a front via region and a back via region; overlapping the front via region with a front metal region and overlapping the back via region and the back metal region, each of the front metal region and the back metal region extending in the cell width direction; and storing the IC layout including the cell in a memory device. In some embodiments, the cell is a first cell, and the MD region is a first MD region. The method includes: abutting the first cell with a second cell including a plurality of stacked CFETs, the plurality of stacked CFETs including a plurality of gate regions and MD regions, and abutting the first cell with the second cell includes aligning the plurality of gate regions with the interconnect region along the cell height direction, and abutting the second MD region of the plurality of MD regions with the first MD region. In some embodiments, the method includes arranging a plurality of gate regions and MD regions of a plurality of stacked CFETs in a cell, wherein arranging the plurality of gate regions includes aligning the plurality of gate regions with the interconnect region along the cell height direction, and arranging the plurality of MD regions includes including the MD regions in corresponding stacked CFETs of the plurality of stacked CFETs. In some embodiments, overlapping the front via region with the front metal region and overlapping the back via region with the back metal region includes configuring each of the front metal region and the back metal region as a portion of a reference voltage distribution grid.

[0142] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, comprising: The first isolation structure and the second isolation structure extend parallel to each other in a first direction on the front side of the semiconductor substrate; The circuit includes a plurality of stacked complementary field-effect transistors (CFETs), the plurality of stacked complementary field-effect transistors including a plurality of gates and a plurality of metallic defined (MD) segments extending in the first direction between the first isolation structure and the second isolation structure, wherein: Each of the plurality of gates extends from a first position along the first direction to a second position along the first direction, and One of the plurality of metallic defining segments is configured as a reference voltage connection for the circuit and extends from the first position to a third position, the third position being further along the first direction than the second position; A first conductive line extends on the front side of the semiconductor substrate in a second direction perpendicular to the first direction; A second conductive wire extends in the second direction on the back side of the semiconductor substrate; and A conductive structure extends from the first wire to the second wire along a third direction perpendicular to each of the first and second directions. The conductive structure includes a portion of the metallic defining segment located between the second position and the third position.

2. The integrated circuit device according to claim 1, wherein, The conductive structure further includes: An interconnect structure is adjacent to the portion of the metallic defining segment along the third direction; A front through-hole extends from the first conductor to one of the metallic defining segment or the interconnect structure; and A back-side through-hole extends from the second conductor to the metallic defined segment or another of the interconnect structures.

3. The integrated circuit device according to claim 2, wherein: Each of the plurality of gates is aligned with the interconnect structure along the first direction.

4. The integrated circuit device according to claim 1, wherein: The metallic defining segment among the plurality of metallic defining segments includes the front metallic defining segment of the n-type transistor of the respective stacked complementary field-effect transistor among the plurality of stacked complementary field-effect transistors.

5. The integrated circuit device according to claim 1, further comprising: A third conductive line extends in the second direction on the front side of the semiconductor substrate; as well as A front through-hole extends from the third conductor to the metallic defining segment.

6. The integrated circuit device according to claim 1, further comprising: The third and fourth isolation structures extend parallel to each other in the first direction on the front side of the semiconductor substrate and are aligned with the first and second isolation structures. The conductive structure is located between the third isolation structure and the fourth isolation structure.

7. The integrated circuit device according to claim 6, further comprising: A pseudo-stacked complementary field-effect transistor is located between the third isolation structure and the fourth isolation structure. The conductive structure is located between the pseudo-stacked complementary field-effect transistor and the stacked complementary field-effect transistor including the metallic defining segment.

8. The integrated circuit device according to claim 1, wherein: The conductive structure is located between the first isolation structure and the second isolation structure.

9. A method for manufacturing an integrated circuit device, the method comprising: A first isolation structure and a second isolation structure, as well as a plurality of stacked complementary field-effect transistors (CFETs), are constructed on the front side of a semiconductor substrate. The construction of the plurality of stacked complementary field-effect transistors includes: A plurality of gates and a plurality of metallic definition (MD) segments extending in the first direction are formed between the first isolation structure and the second isolation structure in a second direction perpendicular to the first direction; and An interconnect structure is formed, the interconnect structure being adjacent to the plurality of gates and aligned with the plurality of gates in the first direction. Wherein, a portion of one of the plurality of metallic defining segments is aligned with the interconnection structure in a third direction perpendicular to each of the first and second directions; A front-side through-hole is formed on the portion of the metallic defining segment or on one of the interconnect structures; A front guide wire is formed on the front through hole, and the front guide wire extends in the second direction; A back-side through-hole is formed on one of the metallic defining segments or the other of the interconnect structure; and A back-side conductor is formed on the back-side through hole, and the back-side conductor extends in the second direction.

10. A method for generating an integrated circuit layout diagram, the method comprising: This extends the interconnect region across the width of the cell; The interconnect region overlaps with the metallic defined (MD) region; The interconnection region and the metallic defining region overlap with the front through-hole region and the back through-hole region; The front through-hole region overlaps with the front metal region, and the back through-hole region overlaps with the back metal region, each of the front metal region and the back metal region extending in the unit width direction; as well as The integrated circuit layout diagram including the unit is stored in a storage device.

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