A method of manufacturing an image sensor and an image sensor
By employing an air grid structure in the image sensor and utilizing the expansion and oxidation of the substrate semiconductor layer to form an air gap, the problems of complex metal grid processes and light loss are solved, achieving efficient photonic crosstalk control and improved pixel shrinkage performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2025-12-15
- Publication Date
- 2026-06-09
Smart Images
Figure CN121335247B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for manufacturing an image sensor and an image sensor. Background Technology
[0002] Image sensors are devices that convert optical images into pixel signals for output. Based on the different photosensitive elements and photosensitive principles, they are divided into charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Among them, CMOS image sensors are widely used image sensors, including front-side illumination (FSI) image sensors and back-side illumination (BSI) image sensors.
[0003] Existing complementary metal-oxide-semiconductor (CMOS) image sensors require the formation of a metal grid to isolate incident light. However, in current technologies, the process of forming the metal grid is complex, resulting in high production costs and a tendency to cause metal contamination. The metal grid also leads to the loss of incident light, reducing the photosensitivity of the image sensor. Summary of the Invention
[0004] In view of the above problems, the purpose of this application is to provide a method for manufacturing an image sensor and an image sensor that controls photoelectric crosstalk without reducing light sensitivity by forming an air grid structure.
[0005] According to one aspect of the present invention, a method for manufacturing an image sensor is provided, comprising: forming a deep trench isolation structure extending from a first surface of a semiconductor substrate toward its interior; forming a dielectric layer on the first surface of the semiconductor substrate and forming a first trench extending from a surface of the dielectric layer away from the semiconductor substrate toward its interior, the first trench and the deep trench isolation structure being opposite to each other; forming a substrate semiconductor layer at least on the sidewalls of the first trench, wherein the substrate semiconductor layer exposes the bottom of the first trench; forming a second trench extending from the bottom of the first trench toward the interior of the dielectric layer using the substrate semiconductor layer as a mask; expanding and oxidizing the substrate semiconductor layer to form a filling dielectric layer that completely fills the first trench, the second trench forming an air gap whose top is covered by the filling dielectric layer; and forming an air grid structure, wherein the air grid structure includes a dielectric layer, an air gap inside the dielectric layer, and a filling dielectric layer covering the top of the air gap, the dielectric layer surrounding the air gap and the filling dielectric layer.
[0006] Optionally, the substrate semiconductor layer is a silicon layer.
[0007] Optionally, after the second trench is formed, the thickness of the substrate semiconductor layer on the sidewall of the first trench is D, the opening width of the first trench is W, and W / 4>D>W / 4.4.
[0008] Optionally, the method of forming a substrate semiconductor layer at least on the sidewalls of the first trench includes: forming a substrate semiconductor layer that conformally covers the surface of the dielectric layer away from the semiconductor substrate and the bottom and sidewalls of the first trench; removing the portion of the substrate semiconductor layer covering the bottom of the first trench, while a portion of the substrate semiconductor layer on the sidewalls of the first trench and the substrate semiconductor layer on the dielectric layer away from the surface of the semiconductor substrate are still retained.
[0009] Optionally, prior to forming the dielectric layer, an isolation layer is further formed on a first surface of the semiconductor substrate, and the dielectric layer is formed on the isolation layer.
[0010] Optionally, the second trench is formed using a wet etching process, with the substrate semiconductor layer located on the sidewall of the first trench serving as a protective layer for the sidewall of the first trench, and the isolation layer serving as a stop layer for downward etching.
[0011] Optionally, the method for forming a deep trench isolation structure includes: forming a first mask layer on a first surface of a semiconductor substrate; placing a mask on the first mask layer; transferring the pattern of the mask onto the first mask layer using a photolithography process to form a patterned first mask layer; etching the semiconductor substrate through the patterned first mask layer to form a deep trench in the semiconductor substrate; and filling the deep trench with an isolation dielectric to form a deep trench isolation structure; the method for forming the first trench includes: forming a hard mask layer and a second mask layer on the surface of a dielectric layer; using the mask for forming the deep trench, transferring the pattern of the mask onto the second mask layer and the hard mask layer using a photolithography process to form a patterned second mask layer and a hard mask layer; etching the dielectric layer through the patterned second mask layer and the hard mask layer to form the first trench in the dielectric layer.
[0012] Optionally, after the substrate semiconductor layer is expanded and oxidized, the filling dielectric layer on the surface of the dielectric layer is removed, and the hard mask layer is removed.
[0013] Optionally, the method of forming the air grid structure includes: forming a patterned mask layer on the surface of the dielectric layer, wherein a portion of the mask layer is retained opposite to the air gap, and the lateral dimension of the portion of the mask layer retained is larger than the lateral dimension of the air gap; and etching the dielectric layer via the patterned mask layer to form the air grid.
[0014] According to another aspect of the present invention, an image sensor is provided, comprising: a semiconductor substrate; a deep trench isolation structure extending from a first surface of the semiconductor substrate toward its interior; an isolation layer located on the first surface of the semiconductor substrate; and an air grid structure located on the isolation layer and opposite to the deep trench isolation structure; wherein the air grid structure includes a dielectric layer, an air gap inside the dielectric layer, and a filling dielectric layer covering the top of the air gap, the dielectric layer surrounding the air gap and the filling dielectric layer.
[0015] The unexpected technical effect of this application is:
[0016] The image sensor of this application embodiment is provided with an air grid structure. The air grid structure includes a dielectric layer, an air gap inside the dielectric layer, and a filling dielectric layer covering the top of the air gap. The dielectric layer surrounds the air gap and the filling dielectric layer. The total internal reflection effect in the air controls photon crosstalk without reducing light sensitivity, and provides next-generation grid technology support for pixel shrinkage of the image sensor.
[0017] In the image sensor manufacturing method of this application embodiment, the top of the air gap is sealed by the expansion oxidation of the substrate semiconductor layer. The top of the air gap can be completely sealed by controlling the thickness of the substrate semiconductor layer, thereby achieving controllability of the air gap size. This allows for the fabrication of air gaps with high aspect ratios, further improving the pixel shrinkage performance of the image sensor.
[0018] In the image sensor manufacturing method of this application embodiment, a substrate semiconductor layer is first formed, and then a second trench (air gap) is etched using the substrate semiconductor layer as a mask, which avoids introducing impurities into the second trench (air gap) during the film deposition process.
[0019] In the image sensor manufacturing method of this application embodiment, the mask for forming the first trench is the same as the mask for forming the deep trench, so there is no need to remake the mask. Furthermore, by using the mask for forming the deep trench, the final air grid structure and the deep trench isolation structure can be accurately aligned. Attached Figure Description
[0020] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0021] Figure 1 An existing image sensor is shown;
[0022] Figures 2a to 2c Cross-sectional views of various stages in the manufacturing process of existing image sensors are shown, in which:
[0023] Figure 2aA schematic diagram of a deep trench isolation structure extending from the first surface of a semiconductor substrate into its interior is shown.
[0024] Figure 2b A schematic diagram is shown showing a dielectric layer, a grid layer, and a hard mask layer sequentially formed on the first surface of a semiconductor substrate;
[0025] Figure 2c A schematic diagram showing patterned photoresist formed on the surface of a hard mask layer is shown;
[0026] Figure 3 A cross-sectional schematic diagram of an image sensor according to an embodiment of this application is shown;
[0027] Figure 4 A flowchart illustrating a method for manufacturing an image sensor according to an embodiment of this application is shown;
[0028] Figures 5a to 5h Cross-sectional views of various stages in the manufacturing process of the image sensor according to the application embodiment are shown, wherein:
[0029] Figure 5a A schematic diagram of a deep trench isolation structure extending from the first surface of a semiconductor substrate into its interior is shown.
[0030] Figure 5b A schematic diagram is shown showing an isolation layer and a dielectric layer sequentially formed on a first surface of a semiconductor substrate, and a first trench extending from the surface of the dielectric layer away from the semiconductor substrate toward its interior.
[0031] Figure 5c A schematic diagram of the formation of the substrate semiconductor layer is shown;
[0032] Figure 5d A schematic diagram is shown showing the selective removal of a portion of the substrate semiconductor layer covering the bottom of the first trench;
[0033] Figure 5e A schematic diagram showing the formation of the second trench is shown;
[0034] Figure 5f A schematic diagram is shown showing the formation of a filling dielectric layer by expansion and oxidation of a substrate semiconductor layer;
[0035] Figure 5g A schematic diagram is shown showing the removal of the fill dielectric layer on the surface of the dielectric layer and the removal of the hard mask layer;
[0036] Figure 5h A schematic diagram of forming a patterned mask layer on the surface of a dielectric layer is shown;
[0037] Figure 5i A schematic diagram is shown to form an air grille by etching a dielectric layer through a patterned mask layer. Detailed Implementation
[0038] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.
[0039] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.
[0040] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".
[0041] This application may be presented in various forms, some of which will be described below.
[0042] Figure 1 The image shown is an existing type of image sensor. For example... Figure 1 As shown, the image sensor includes a substrate 101, in which multiple photodiode regions are disposed and isolation trenches 110 are used to separate adjacent photodiode regions. The substrate 101 is made of a material such as silicon (Si). An insulating layer 120 is disposed on the surface of the substrate 101, and a grid structure 130a formed by stacking different materials is disposed on the surface of the insulating layer 120.
[0043] The grating structure 130a includes a first grating layer 131, a second grating layer 132, a third grating layer 133, and a fourth grating layer 134. The first grating layer 131 is, for example, a titanium (Ti) layer; the second grating layer 132 is, for example, a tungsten (W) layer; the third grating layer 133 is, for example, a titanium nitride (TiN) layer; and the fourth grating layer 134 is, for example, a TEOS (tetraethyl orthosilicate) layer. In existing image sensors, to eliminate optical crosstalk between color filters, the absorption characteristics of visible light by the metallic grating structure 130a are used to reduce photoelectron crosstalk. However, this reduces the photosensitivity of the image sensor and limits the reduction in pixel size.
[0044] Figures 2a to 2c Cross-sectional views of various stages in the manufacturing process of existing image sensors are shown. The following will combine... Figure 2a Paper Figure 2c The existing manufacturing methods for image sensors are described.
[0045] like Figure 2a As shown, an isolation trench 110 is formed extending from the first surface of the substrate 101 into its interior.
[0046] like Figure 2b As shown, an insulating layer 120, a grid layer 130, and a hard mask stack 140 are sequentially formed on the first surface of the substrate 101. The grid layer 130 includes a first grid layer 131, a second grid layer 132, a third grid layer 133, and a fourth grid layer 134 stacked sequentially from bottom to top. The first grid layer 131 is, for example, a titanium (Ti) layer, the second grid layer 132 is, for example, a tungsten (W) layer, the third grid layer 133 is, for example, a titanium nitride (TiN) layer, and the fourth grid layer 134 is, for example, a TEOS layer. The hard mask stack 140 includes a first hard mask layer 141, a second hard mask layer 142, and a third hard mask layer 143 stacked sequentially from bottom to top. The first hard mask layer 141 is, for example, an amorphous carbon (a-Carbon) layer, the second hard mask layer 142 is, for example, a silicon oxynitride (SiON) layer or an oxide layer, and the third hard mask layer 143 is, for example, a bottom anti-reflection coating (BARC).
[0047] like Figure 2c As shown, a patterned photoresist PR is formed on the surface of the hard mask stack 140, and the hard mask stack 140 and the grid layer 130 are etched through the patterned photoresist PR to form a grid structure 130a. After forming the grid structure 130a, the photoresist PR and the hard mask stack 140 are removed.
[0048] The process of forming the above-mentioned grid structure 130a is relatively complex, has high production costs, and is prone to metal contamination.
[0049] Figure 3 A cross-sectional schematic diagram of an image sensor according to an embodiment of this application is shown. Figure 3 As shown in the embodiment of this application, the image sensor includes a semiconductor substrate 201, within which a plurality of photodiode regions 201a are disposed, and a deep trench isolation (DTI) structure 210 for separating adjacent photodiode regions 201a. The semiconductor substrate 201 is made of, for example, silicon (Si). An isolation layer 220 is disposed on the surface of the semiconductor substrate 201, and an air grid structure 260 is disposed on the surface of the isolation layer 220. The air grid structure 260 includes a dielectric layer 230, an air gap AG inside the dielectric layer 230, and a filling dielectric layer 250a covering the top of the air gap AG. The dielectric layer 230 surrounds the air gap AG and the filling dielectric layer 250a. The image sensor of this embodiment exhibits an in-air total internal reflection effect, controlling photon crosstalk without reducing light sensitivity.
[0050] Figure 4 A flowchart illustrating a method for manufacturing an image sensor according to an embodiment of this application is shown, as follows: Figure 4 As shown, the method for manufacturing the image sensor in this embodiment includes:
[0051] S10: Forming a deep trench isolation structure extending from the first surface of the semiconductor substrate into its interior;
[0052] S20: A dielectric layer is formed on a first surface of a semiconductor substrate, and a first trench is formed extending from the surface of the dielectric layer away from the semiconductor substrate toward its interior;
[0053] S30: A substrate semiconductor layer is formed at least on the sidewall of the first trench, wherein the substrate semiconductor layer exposes the bottom of the first trench;
[0054] S40: Using the substrate semiconductor layer as a mask, a second trench is formed that extends from the bottom of the first trench into the interior of the dielectric layer;
[0055] S50: The substrate semiconductor layer is expanded and oxidized to form a filling dielectric layer that completely fills the first trench, and the second trench forms an air gap whose top is covered by the filling dielectric layer.
[0056] S60: Forming an air grid structure, wherein the air grid structure includes an air gap, a medium layer surrounding the air gap, and a filling medium layer covering the top of the air gap.
[0057] Figures 5a to 5h Cross-sectional views of various stages in the manufacturing process of the image sensor according to the application embodiment are shown below, in conjunction with... Figures 5a to 5h The manufacturing method of the image sensor according to the embodiments of this application will be described in detail.
[0058] Step S10: Form a deep trench isolation structure 210 extending from the first surface of the semiconductor substrate 201 into its interior, such as... Figure 5a As shown.
[0059] The method of forming a deep trench isolation structure 210 includes forming a mask layer on a first surface of a semiconductor substrate 201, placing a mask on the mask layer, transferring the pattern of the mask onto the first mask layer using a photolithography process to form a patterned mask layer, etching the semiconductor substrate 201 through the patterned mask layer to form a deep trench in the semiconductor substrate 201, and filling the deep trench with an isolation medium to form a deep trench isolation structure 210.
[0060] Step S20: An isolation layer 220 and a dielectric layer 230 are sequentially formed on the first surface of the semiconductor substrate 201, and a first trench 230a is formed extending from the surface of the dielectric layer 230 away from the semiconductor substrate 201 into its interior, as shown below. Figure 5b As shown.
[0061] In this step, an isolation layer 220 and a dielectric layer 230 are sequentially formed on a semiconductor substrate 201. The isolation layer 220 covers the first surface of the semiconductor substrate 201 and the surface of the deep trench isolation structure 210. The dielectric layer 230 is located on the isolation layer 220 and is isolated from the semiconductor substrate 201 and the deep trench isolation structure 210 via the isolation layer 220.
[0062] In this embodiment, the isolation layer 220 is a nitride layer (e.g., a SiN layer), and the dielectric layer 230 is an oxide layer (e.g., a SiO2 layer). The isolation layer 220 serves as an etching stop layer for the subsequent formation of the second trench, and also achieves isolation between the final air grid structure and the deep trench isolation structure. The dielectric layer 230 is subsequently used to form the sidewalls surrounding the air gap in the air grid structure.
[0063] Next, a hard mask layer 240 is formed on the dielectric layer 230, and a first mask layer PR1 is formed on the surface of the hard mask layer 240. Using the mask with deep trenches, the pattern of the mask is transferred to the first mask layer PR1 by photolithography, and the hard mask layer 240 is etched through the patterned first mask layer PR1 to form an opening in the hard mask layer 240.
[0064] Next, the dielectric layer 230 is etched through the openings of the first mask layer PR1 and the hard mask layer 240 to form a first trench 230a extending from the surface of the dielectric layer 230 away from the semiconductor substrate 201 and into it. After the first trench 230a is formed, the first mask layer PR1 is removed.
[0065] In this embodiment, the mask for forming the first groove is the same as the mask for forming the deep groove, so there is no need to remake the mask. Furthermore, the use of the mask for forming the deep groove ensures that the final air grid structure and the deep groove isolation structure can be accurately aligned.
[0066] In this embodiment, the hard mask layer 240 is a nitride layer (e.g., a SiN layer). In other embodiments, a hard mask layer can be provided as needed. The hard mask layer may include a single-material film layer or multiple film layers of different materials. This embodiment does not limit this.
[0067] S30: A substrate semiconductor layer 250 is formed at least on the sidewall of the first trench 230a, wherein the substrate semiconductor layer 250 exposes the bottom of the first trench, such as Figure 5c and Figure 5d As shown.
[0068] Specifically, such as Figure 5cAs shown, for example, a substrate semiconductor layer 250 is formed using a deposition process. The substrate semiconductor layer 250 conformally covers the surface of the hard mask layer 240 and the bottom and sidewalls of the first trench 230a. In this embodiment, the material of the substrate semiconductor layer 250 is, for example, silicon.
[0069] It is worth noting that during the deposition process, the growth rate of the thin film on a flat surface is usually faster, which makes the thickness of the substrate semiconductor layer 250 on the surface of the hard mask layer 240 greater than the thickness of the substrate semiconductor layer 250 at the bottom of the first trench 230a in this embodiment.
[0070] like Figure 5d As shown, the portion of the substrate semiconductor layer 250 covering the bottom of the first trench 230a is removed.
[0071] In this step, for example, a dry etching process is used to etch back the substrate semiconductor layer 250 to remove the portion of the substrate semiconductor layer 250 covering the bottom of the first trench 230a. It is worth noting that during this process, the substrate semiconductor layer 250 on the surface of the hard mask layer 240 has a thicker thickness than the substrate semiconductor layer 250 at the bottom of the first trench 230a. When the substrate semiconductor layer 250 at the bottom of the first trench 230a is completely etched, a portion of the substrate semiconductor layer 250 on the surface of the hard mask layer 240 is still retained, resulting in only the portion of the substrate semiconductor layer 250 covering the bottom of the first trench 230a being completely removed. Ultimately, the substrate semiconductor layer 250 at the bottom of the first trench 230a is completely removed, while a portion of the substrate semiconductor layer 250 on the sidewalls of the first trench 230a and the substrate semiconductor layer 250 on the surface of the dielectric layer 230 away from the semiconductor substrate 201 is still retained.
[0072] S40: Using the substrate semiconductor layer 250 as a mask, a second trench 230b is formed, extending from the bottom of the first trench 230a into the interior of the dielectric layer 230, as shown below. Figure 5e As shown.
[0073] In this step, for example, a wet etching process is used to etch the dielectric layer 230 to form a second trench 230b, which extends downward from the bottom of the first trench 230a. During the etching process, the substrate semiconductor layer 250 located on the sidewall of the first trench 230a serves as a protective layer for the sidewall of the first trench 230a, allowing the etchant to primarily etch downwards, thereby forming the second trench 230b. Furthermore, during the wet etching process, the isolation layer 220 serves as a stop layer for downward etching, ensuring that the bottom of the second trench 230b is located at the junction of the dielectric layer 230 and the isolation layer 220 or inside the isolation layer 220.
[0074] Furthermore, in Figure 5dIn the steps shown, the substrate semiconductor layer 250 on the surface of the dielectric layer 230 is also retained to prevent the substrate semiconductor layer 250 on the sidewall of the first trench 230a from falling off, thus ensuring the robustness of the substrate semiconductor layer 250 on the sidewall of the first trench 230a.
[0075] After wet etching, a portion of the substrate semiconductor layer 250 on the sidewall of the first trench 230a may also be removed. The thickness of the remaining substrate semiconductor layer 250 on the sidewall of the first trench 230a is D, and the opening width of the first trench 230a is W, where W / 4 > D > W / 4.4.
[0076] S50: The substrate semiconductor layer 250 is expanded and oxidized to form a filling dielectric layer 250a that completely fills the first trench 230a. The second trench 230b forms an air gap whose top is covered by the filling dielectric layer 250a. Figure 5f and Figure 5g As shown.
[0077] like Figure 5f As shown, for example, a wet oxidation process is used to oxidize the substrate semiconductor layer 250 to form an oxide layer. During the oxidation process of the substrate semiconductor layer 250, the volume expands. The substrate semiconductor layer 250 on the sidewall of the first trench 230a oxidizes and expands to form a filling dielectric layer 250a that completely fills the first trench 230a. The filling dielectric layer 250a covers the top of the second trench 230b, and the second trench 230b becomes an air gap AG whose top is sealed by the filling dielectric layer 250a. The substrate semiconductor layer 250 on the surface of the dielectric layer 230 oxidizes and expands to form a filling dielectric layer 250a that covers the surface of the dielectric layer 230.
[0078] In this embodiment, the substrate semiconductor layer 250 is made of silicon. Silicon reacts with oxygen or water vapor in a humid environment to form an oxide layer. During the oxidation process of the substrate semiconductor layer 250 (silicon), its volume expands approximately 2.2 times; in other words, 1 mm thick silicon oxide (SiO2) consumes approximately 0.45 mm of silicon (Si). Figure 5d In the steps shown, the thickness D of the remaining substrate semiconductor layer 250 on the sidewall of the first trench 230a and the opening width W of the first trench 230a satisfy W / 4>D>W / 4.4. This is to ensure that the substrate semiconductor layer 250 on the sidewall of the first trench 230a is completely oxidized, and that when the substrate semiconductor layer 250 on the sidewall of the first trench 230a is completely oxidized, it can completely fill the first trench 230a, thereby sealing the top of the second trench 230b, so that the second trench 230b becomes an air gap AG whose top is sealed by the dielectric layer 250a.
[0079] like Figure 5g As shown, the filling dielectric layer 250a on the surface of the dielectric layer 230 is removed, and the hard mask layer 240 is also removed.
[0080] In this step, for example, a CMP (Chemical Mechanical Polishing or Chemical Mechanical Planarization) process is used to remove the filler dielectric layer 250a above the dielectric layer 230, and the hard mask layer 240 on the dielectric layer 230 is also removed, exposing the surface of the dielectric layer 230. In other embodiments, for example, a CMP process is used to remove the filler dielectric layer 250a on the surface of the dielectric layer 230, and a wet etching process is used to remove the hard mask layer 240 on the dielectric layer 230.
[0081] S60: Forming an air grille structure 260, wherein the air grille structure 260 includes an air gap AG, a medium layer 230 surrounding the air gap AG, and a filling medium layer 250a covering the top of the air gap AG, such as Figure 5h and Figure 5i As shown.
[0082] like Figure 5h As shown, a patterned second mask layer PR2 is formed on the surface of the dielectric layer 230. The portion of the second mask layer PR2 that is retained is opposite to the second trench 230b (air gap AG), and the lateral dimension of the portion of the second mask layer PR2 that is retained is larger than the lateral dimension of the second trench 230b (air gap AG).
[0083] like Figure 5i As shown, an air grille is formed by etching the dielectric layer 230 via a patterned second mask layer PR2.
[0084] In this step, the dielectric layer 230 is etched via a patterned second mask layer PR2. During the etching process, the isolation layer 220 serves as a stop layer for etching. Furthermore, since the patterned second mask layer PR2 is opposite to the second trench 230b (air gap AG), and the lateral dimension of the second mask layer PR2 is larger than the lateral dimension of the second trench 230b (air gap AG), the remaining dielectric layer 230 surrounds the second trench 230b (air gap AG), forming an air grid.
[0085] The unexpected technical effect of this application is:
[0086] The image sensor of this application embodiment is provided with an air grid structure. The air grid structure includes a dielectric layer, an air gap inside the dielectric layer, and a filling dielectric layer covering the top of the air gap. The dielectric layer surrounds the air gap and the filling dielectric layer. The total internal reflection effect in the air controls photon crosstalk without reducing light sensitivity, and provides next-generation grid technology support for pixel shrinkage of the image sensor.
[0087] In the image sensor manufacturing method of this application embodiment, the top of the air gap is sealed by the expansion oxidation of the substrate semiconductor layer. The top of the air gap can be completely sealed by controlling the thickness of the substrate semiconductor layer, thereby achieving controllability of the air gap size. This allows for the fabrication of air gaps with high aspect ratios, further improving the pixel shrinkage performance of the image sensor.
[0088] In the image sensor manufacturing method of this application embodiment, a substrate semiconductor layer is first formed, and then a second trench (air gap) is etched using the substrate semiconductor layer as a mask, which avoids introducing impurities into the second trench (air gap) during the film deposition process.
[0089] In the image sensor manufacturing method of this application embodiment, the mask for forming the first trench is the same as the mask for forming the deep trench, so there is no need to remake the mask. Furthermore, by using the mask for forming the deep trench, the final air grid structure and the deep trench isolation structure can be accurately aligned.
[0090] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.
Claims
1. A method for manufacturing an image sensor, comprising: A deep trench isolation structure is formed that extends from the first surface of the semiconductor substrate into its interior; A dielectric layer is formed on a first surface of a semiconductor substrate, and a first trench is formed extending from the surface of the dielectric layer away from the semiconductor substrate into its interior, the first trench being opposite to the deep trench isolation structure; A substrate semiconductor layer is formed at least on the sidewall of the first trench, wherein the substrate semiconductor layer exposes the bottom of the first trench; Using the substrate semiconductor layer as a mask, a second trench is formed that extends from the bottom of the first trench into the interior of the dielectric layer; The substrate semiconductor layer is expanded and oxidized to form a filling dielectric layer that completely fills the first trench, and a second trench is formed where the top of the filling dielectric layer covers an air gap; and An air grid structure is formed, wherein the air grid structure includes a medium layer, an air gap inside the medium layer, and a filling medium layer covering the top of the air gap, the medium layer surrounding the air gap and the filling medium layer.
2. The method according to claim 1, wherein, The substrate semiconductor layer is a silicon layer.
3. The method according to claim 1 or 2, wherein, After the second trench is formed, the thickness of the substrate semiconductor layer on the sidewall of the first trench is D, the opening width of the first trench is W, and W / 4>D>W / 4.
4.
4. The method according to claim 1, wherein, Methods for forming a substrate semiconductor layer at least on the sidewalls of the first trench include: A substrate semiconductor layer is formed, which conformally covers the surface of the dielectric layer away from the semiconductor substrate and the bottom and sidewalls of the first trench; After removing the portion of the substrate semiconductor layer covering the bottom of the first trench, a portion of the substrate semiconductor layer on the sidewalls of the first trench and a portion of the substrate semiconductor layer away from the surface of the semiconductor substrate are still retained.
5. The method according to claim 1, wherein, Prior to forming the dielectric layer, the process further includes forming an isolation layer on a first surface of a semiconductor substrate, on which the dielectric layer is formed.
6. The method according to claim 5, wherein, The second trench is formed using a wet etching process. The substrate semiconductor layer located on the sidewall of the first trench serves as a protective layer for the sidewall of the first trench, and the isolation layer serves as a stop layer for downward etching.
7. The method according to claim 1, wherein, Methods for forming deep trench isolation structures include: A first mask layer is formed on the first surface of a semiconductor substrate; A mask is placed on the first mask layer, and the pattern of the mask is transferred to the first mask layer using photolithography to form a patterned first mask layer. Deep trenches are formed in a semiconductor substrate by etching a patterned first mask layer; and A deep trench is formed by filling the deep trench with an isolation medium. The methods for forming the first trench include: A hard mask layer and a second mask layer are formed on the surface of the dielectric layer; Using the same mask that forms deep trenches, a photolithography process is employed to transfer the pattern of the mask onto the second mask layer and the hard mask layer, forming a patterned second mask layer and a hard mask layer. The dielectric layer is etched via a patterned second mask layer and a hard mask layer to form a first trench in the dielectric layer.
8. The method according to claim 7, wherein, After the substrate semiconductor layer is expanded and oxidized, the filling dielectric layer on the surface of the dielectric layer is removed, and the hard mask layer is also removed.
9. The method according to claim 1, wherein, Methods for forming an air grille structure include: A patterned mask layer is formed on the surface of the dielectric layer, the portion of the mask layer that is retained is opposite to the air gap, and the lateral dimension of the portion of the mask layer that is retained is larger than the lateral dimension of the air gap; An air grille is formed by etching a dielectric layer through a patterned mask layer.
10. An image sensor formed by a method of manufacturing an image sensor according to any one of claims 1-9, comprising: Semiconductor substrate; A deep trench isolation structure extends from the first surface of a semiconductor substrate into its interior; An isolation layer is located on the first surface of the semiconductor substrate; An air grille structure is located on the isolation layer and is opposite to the deep trench isolation structure; The air grid structure includes a medium layer, an air gap inside the medium layer, and a filling medium layer covering the top of the air gap, wherein the medium layer surrounds the air gap and the filling medium layer.