Load power supply control circuit, printed circuit board and equipment

Abstract

The invention provides a load power supply control circuit, a printed circuit board and equipment. The load power supply control circuit comprises an interaction circuit, a processor, a time delay circuit and a startup and shutdown circuit. The interaction circuit is used for receiving a shutdown operation triggered by a user; the interaction circuit can respond to a shutdown operation, input a shutdown interrupt signal to the processor and input a shutdown instruction signal to the time delay circuit; the processor is used for running an operating system, and can respond to the shutdown interrupt signal to input a shutdown control signal to the startup and shutdown circuit when the operating system runs normally; the time delay circuit can respond to the shutdown instruction signal to input a shutdown control signal to the startup and shutdown circuit; the on-off circuit is used for controlling whether a load power supply supplies power to a plurality of preset active devices including a processor; the on-off circuit can control the load power supply to stop supplying power to the plurality of preset active devices in response to the shutdown control signal. The file system can be prevented from being damaged as much as possible on the premise of ensuring that the electronic equipment can be shut down.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a load power control circuit, a printed circuit board and a device. BACKGROUND

[0002] There are two ways to shut down the electronic device, the first way is to control the shutdown by hardware such as a power-on / off interaction device, and the user can directly cut off the power supply when triggering a key operation on the power-on / off interaction device; the second way is to control the shutdown by software, and the power-on / off interaction device cooperates with the processor, and the user can only trigger an input of a shutdown interrupt signal to the processor when triggering a shutdown operation on the power-on / off interaction device, and the power supply can be controlled to be disconnected by a shutdown control signal output by the processor in response to the shutdown interrupt signal.

[0003] The first way of controlling the shutdown by hardware can successfully shut down, but the software system cannot perceive the shutdown operation, and the file system may be damaged due to sudden power failure. The second way of controlling the shutdown by software can avoid file system damage, but may not be able to shut down due to software exceptions. SUMMARY

[0004] The present application provides a load power control circuit, a printed circuit board and a device to solve the problem that the first way of controlling the shutdown by hardware in the prior art may cause file system damage due to sudden power failure, and the second way of controlling the shutdown by software may not be able to shut down due to software exceptions.

[0005] In a first aspect, the present application provides a load power control circuit, comprising: an interaction circuit, a processor, a delay circuit and a power-on / off circuit; the interaction circuit is connected with the processor and the delay circuit; the processor and the delay circuit are connected with the power-on / off circuit;

[0006] The interaction circuit comprises an interaction device, the interaction device is used for receiving an interaction operation triggered by a user, and the interaction operation comprises a shutdown operation; the interaction circuit can input a shutdown interrupt signal to the processor and input a shutdown instruction signal to the delay circuit in response to the shutdown operation;

[0007] The processor is used for running an operating system; when the operating system is running normally, the processor can input a shutdown control signal to the power-on / off circuit within a first preset response time in response to the shutdown interrupt signal;

[0008] The delay circuit can input a shutdown control signal to the power-on / off circuit after a first preset response time in response to the shutdown instruction signal;

[0009] The switch machine circuit is configured to control whether the power supply supplies power to a plurality of preset active devices; the plurality of preset active devices includes the processor; the switch machine circuit is capable of, in response to the shutdown control signal, controlling the power supply to stop supplying power to the plurality of preset active devices.

[0010] In a second aspect, the present application provides a printed circuit board comprising the load power control circuit according to the first aspect.

[0011] In a third aspect, the present application provides an electronic device comprising the load power control circuit according to the first aspect.

[0012] The load power control circuit, the printed circuit board and the electronic device provided by the present application comprise an interactive circuit, a processor, a delay circuit and a switch machine circuit; the interactive circuit is connected with the processor and the delay circuit; the processor and the delay circuit are both connected with the switch machine circuit; the interactive circuit comprises an interactive device, the interactive device is configured to receive an interactive operation triggered by a user, the interactive operation comprises a shutdown operation; the interactive circuit is capable of, in response to the shutdown operation, inputting a shutdown interrupt signal to the processor and inputting a shutdown instruction signal to the delay circuit; the processor is configured to run an operating system; when the operating system is running normally, the processor is capable of, in response to the shutdown interrupt signal, inputting a shutdown control signal to the switch machine circuit within a first preset response duration; the delay circuit is capable of, in response to the shutdown instruction signal, inputting a shutdown control signal to the switch machine circuit after the first preset response duration; the switch machine circuit is configured to control whether the power supply supplies power to a plurality of preset active devices; the plurality of preset active devices includes the processor; the switch machine circuit is capable of, in response to the shutdown control signal, controlling the power supply to stop supplying power to the plurality of preset active devices. Since the interactive circuit is capable of, in response to the shutdown operation, inputting a shutdown interrupt signal to the processor and inputting a shutdown instruction signal to the delay circuit after the user triggers the shutdown operation, the processor is capable of, in response to the shutdown interrupt signal, inputting a shutdown control signal to the switch machine circuit within a first preset response duration when the operating system is running normally, and the switch machine circuit is capable of, in response to the shutdown control signal, controlling the power supply to stop supplying power to the plurality of preset active devices, the processor is unable to input a shutdown control signal to the switch machine circuit when the operating system is abnormal, but the delay circuit is capable of, in response to the shutdown instruction signal, inputting a shutdown control signal to the switch machine circuit after the first preset response duration, thereby achieving the shutdown in the software exception. In summary, the load power control circuit provided by the present application can avoid file system damage as much as possible while ensuring that the electronic device can be shut down, and at the same time, the user experience is guaranteed. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0014] Figure 1 Schematic diagram of load power supply control circuit provided for the embodiment of the present application Figure One ;

[0015] Figure 2 Schematic diagram of interaction circuit provided for the embodiment of the present application Figure One ;

[0016] Figure 3 Schematic diagram of interaction circuit provided for the embodiment of the present application Figure Two ;

[0017] Figure 4 Schematic diagram of interaction circuit provided for the embodiment of the present application Figure Three ;

[0018] Figure 5 Schematic diagram of delay circuit provided for the embodiment of the present application Figure One ;

[0019] Figure 6 Schematic diagram of delay circuit provided for the embodiment of the present application Figure Two ;

[0020] Figure 7 Schematic diagram of switch-on / off circuit provided for the embodiment of the present application Figure One ;

[0021] Figure 8 Schematic diagram of switch-on / off circuit provided for the embodiment of the present application Figure Two ;

[0022] Figure 9 Schematic diagram of switch-on / off circuit provided for the embodiment of the present application Figure Three ;

[0023] Figure 10 Schematic diagram of switch-on / off circuit provided for the embodiment of the present application Figure Four ;

[0024] Figure 11 Schematic diagram of NOT circuit provided for the embodiment of the present application

[0025] Figure 12 Schematic diagram of load power supply control circuit provided for the embodiment three of the present application Figure Two .

[0026] The specific embodiments of the present application have been shown in the above-mentioned drawings, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present application by any means, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0027] The terms "first", "second", "third", "fourth", "fifth", "sixth" and the like in the description and in the claims of the present application and the drawings hereto refer to objects but do not by themselves convey an order of precedence or a precedence in time. It is understood that the data thus designated can, on their own, be interchanged, such that the embodiments of the application described herein can be carried out in an order other than that illustrated or described herein. Furthermore, the terms "comprise" and "have" and any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or apparatus that comprises a list of steps or units is not necessarily limited to those steps or units that are clearly listed, but can include other steps or units not expressly listed or inherent to such process, method, product or apparatus.

[0028] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, like reference numerals refer to like elements, unless the context clearly dictates otherwise. The following description of exemplary embodiments is not intended to represent all embodiments in accordance with the present application. Rather, they merely represent typical embodiments in accordance with a portion of the application, as detailed in the appended claims.

[0029] First, the prior art related to the present application is described and analyzed in detail.

[0030] There are generally two ways to shut down an electronic device. The first way is to control the shutdown by a switch interaction device, such as a toggle switch, a button switch, a slide switch, a rotary switch, a touch switch, and the like, which is directly connected between the power supply and a plurality of preset active devices that need to be powered. When a user triggers a key operation on the switch interaction device, the connection between the power supply and the plurality of preset active devices that need to be powered can be directly disconnected, thereby achieving shutdown. The second way is to control the shutdown by software. The switch interaction device cooperates with a processor. The switch interaction device is not connected between the power supply and the plurality of preset active devices that need to be powered, but serves as a switch that inputs a shutdown interrupt signal to the processor. When a user triggers a shutdown operation on the switch interaction device, only a shutdown interrupt signal input to the processor can be triggered. The processor needs to respond to the shutdown interrupt signal to output a shutdown control signal. Only then can the shutdown control signal control the switch directly connected between the power supply and the plurality of preset active devices that need to be powered to be disconnected, thereby achieving shutdown.

[0031] In the above two shutdown modes, the first mode of hardware-controlled shutdown can succeed, but the software system cannot perceive the shutdown operation, and file system damage can occur due to sudden power failure. The second mode of software-controlled shutdown can avoid file system damage, but can fail to shut down due to software exceptions. If the shutdown fails, the user often needs to perform a forced shutdown operation to achieve hardware shutdown through a backup hardware-controlled shutdown circuit, and the user needs to operate twice, which is poor in user experience.

[0032] To solve the above technical problems, the present application proposes the following technical concept: if software-controlled shutdown and hardware-controlled shutdown can be combined, the software-controlled shutdown is preferred when the user triggers a shutdown operation, and the hardware-controlled shutdown can be used when the software fails to shut down, so that file system damage can be avoided as much as possible while ensuring that the electronic device can be shut down, and the user experience is guaranteed.

[0033] Therefore, the load power supply control circuit provided by the present application includes an interaction circuit, a processor, a delay circuit, and a shutdown circuit. The interaction circuit is connected to the processor and the delay circuit. The processor and the delay circuit are connected to the shutdown circuit. The interaction circuit includes an interaction device that receives a user-triggered interaction operation, which includes a shutdown operation. The interaction circuit can input a shutdown interrupt signal to the processor and a shutdown instruction signal to the delay circuit in response to the shutdown operation. The processor runs an operating system. When the operating system is running normally, the processor can input a shutdown control signal to the shutdown circuit within a first preset response time in response to the shutdown interrupt signal. The delay circuit can input a shutdown control signal to the shutdown circuit after the first preset response time in response to the shutdown instruction signal. The shutdown circuit controls whether the power supply supplies power to a plurality of preset active devices. The plurality of preset active devices include the processor. The shutdown circuit can control the power supply to stop supplying power to the plurality of preset active devices in response to the shutdown control signal. After the user triggers the shutdown operation, the interaction circuit can input the shutdown interrupt signal to the processor and the shutdown instruction signal to the delay circuit in response to the shutdown operation. When the operating system is running normally, the processor can input the shutdown control signal to the shutdown circuit within the first preset response time in response to the shutdown interrupt signal. The shutdown circuit can control the power supply to stop supplying power to the plurality of preset active devices in response to the shutdown control signal. When the operating system is abnormal, the processor cannot input the shutdown control signal to the shutdown circuit, but the delay circuit can input the shutdown control signal to the shutdown circuit after the first preset response time in response to the shutdown instruction signal, thereby achieving shutdown when the software is abnormal. In summary, the load power supply control circuit provided by the present application can ensure that the electronic device can be shut down, avoid file system damage as much as possible, and guarantee the user experience.

[0034] The technical solutions of the present application and how the technical solutions solve the above technical problems will be described in detail below with specific examples. The embodiments described in the following examples do not represent all the embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims. The following specific examples can be combined with each other, and some embodiments may not be described again for the same or similar concepts or processes.

[0035] Embodiment one

[0036] Figure 1 Schematic diagram of load power supply control circuit provided by embodiments of the present application Figure One As shown in Figure 1 , the load power supply control circuit provided by the embodiments includes an interaction circuit 11, a processor 12, a delay circuit 13, and a power-on / off circuit 14.

[0037] The interaction circuit 11 is connected with the processor 12 and the delay circuit 13; the processor 12 and the delay circuit 13 are both connected with the power-on / off circuit 14.

[0038] The interaction circuit 11 includes an interaction device, which is configured to receive a user-triggered interaction operation, the interaction operation including a power-off operation; the interaction circuit 11 is capable of inputting a power-off interrupt signal to the processor 12 and a power-off instruction signal to the delay circuit in response to the power-off operation.

[0039] The processor 12 is configured to run an operating system; when the operating system is running normally, the processor 12 is capable of inputting a power-off control signal to the power-on / off circuit 14 within a first preset response duration in response to the power-off interrupt signal.

[0040] The delay circuit 13 is capable of inputting a power-off control signal to the power-on / off circuit 14 after the first preset response duration in response to the power-off instruction signal.

[0041] The power-on / off circuit 14 is configured to control whether a power supply supplies power to a plurality of preset active devices; the plurality of preset active devices include the processor 12; the power-on / off circuit 14 is capable of controlling the power supply to stop supplying power to the plurality of preset active devices in response to the power-off control signal.

[0042] In the embodiments, the output end of the interaction circuit can be connected with the interrupt input end of the processor and the input end of the delay circuit. The processor can be a processor whose interrupt is triggered from low level to high level.

[0043] The interactive device can be a toggle switch, a button switch, a slide switch, a rotary switch, a touch switch, etc. When the electronic device is in the powered-on state, the power supply supplies power to the plurality of preset active devices, at this time, the interactive device can be in a closed state, and the output end of the interactive circuit can be at a low level. When the user triggers the power-off operation, the interactive device changes from the closed state to the open state, and the output end of the interactive circuit can change to a high level, so that a rising edge signal from a low level to a high level is generated and remains at a high level. Therefore, the power-off interrupt signal can be a rising edge signal from a low level to a high level, or a high level signal. The power-off instruction signal can also be a rising edge signal from a low level to a high level, or a high level signal.

[0044] Figure 2 Schematic diagram of the interactive circuit provided by the embodiment of the application Figure One . Alternatively, as shown in Figure 2 , the interactive circuit includes resistors R1, R2, R3, an NMOS tube Q0, a transistor T0, and a switch S0. The switch S0 is an interactive device, and the power-on operation is used to close the switch S0, and the power-off operation is used to open the switch S0.

[0045] One end of the switch S0 is grounded. The other end of the switch S0 is connected with one end of the resistor R1 and the base of the transistor T0.

[0046] The other end of the resistor R1 is connected with the power supply Vcc.

[0047] The emitter of the transistor T0 is grounded. The collector of the transistor T0 is connected with one end of the resistor R2 and the gate of the NMOS tube Q0.

[0048] The other end of the resistor R2 is connected with the power supply Vcc.

[0049] The source of the NMOS tube Q0 is grounded. The drain of the NMOS tube Q0 is connected with one end of the resistor R3.

[0050] The other end of the resistor R4 is connected with the power supply Vcc.

[0051] The power supply Vcc can be a 3.3V direct current power supply, and the ground is considered as a voltage of 0. The voltage of the power supply Vcc is a high level, and the voltage of the ground is a low level. The drain of the NMOS tube Q0 and one end of the resistor R3 can be used as the output end Vout11 of the interactive circuit.

[0052] When the switch S0 is closed, the base voltage of the transistor T0 is equal to the emitter voltage, the transistor T0 is in a cut-off state, and the collector voltage of the transistor T0 is the power supply voltage, so that the gate voltage of the NMOS tube Q0 is the power supply voltage, the NMOS tube Q0 is turned on, and the output end Vout11 of the interactive circuit is at a low level.

[0053] When the switch SO is off, the base voltage of the transistor TO is the voltage power supply, the emitter voltage is 0, the transistor TO is in the amplification state or saturation state, so that the collector voltage is 0, the gate voltage of the NMOS tube Q0 is 0, the NMOS tube Q0 is cut off, and then the output end Vout11 of the interaction circuit is high level.

[0054] In summary, when the user triggers the start operation, the switch SO changes from the closed state to the open state, the output end Vout11 of the interaction circuit changes from the low level to the high level, and the rising edge signal from the low level to the high level and the high level signal can be output.

[0055] Figure 3 The schematic diagram of the interaction circuit provided by the embodiment of the present application Figure Two . Optionally, as Figure 3 indicated, the interaction circuit can further include a resistance R4 and a capacitor C1 on the basis shown in Figure 2 .

[0056] The resistance R4 is connected between the other end of the switch SO and the base of the transistor TO. The resistance value of the resistance R1 is much larger than the resistance value of the resistance R4, for example, the resistance value of the resistance R1 is multiple times of the resistance value of the resistance R4, so that when the switch SO is closed, the transistor TO is cut off.

[0057] The capacitor C1 is connected between the gate of the NMOS tube Q0 and the ground, for stabilizing voltage and preventing interference.

[0058] The load power supply control circuit provided in the embodiment comprises an interaction circuit, a processor, a delay circuit and a switch-on-off circuit; the interaction circuit is connected with the processor and the delay circuit; the processor and the delay circuit are connected with the switch-on-off circuit; the interaction circuit comprises an interaction device, the interaction device is used for receiving an interaction operation triggered by a user, and the interaction operation comprises a shutdown operation; the interaction circuit can input a shutdown interrupt signal to the processor and input a shutdown instruction signal to the delay circuit in response to the shutdown operation; the processor is used for running an operating system; when the operating system is normally running, the processor can input a shutdown control signal to the switch-on-off circuit within a first preset response duration in response to the shutdown interrupt signal; the delay circuit can input the shutdown control signal to the switch-on-off circuit after the first preset response duration in response to the shutdown instruction signal; the switch-on-off circuit is used for controlling whether the power supply supplies power to a plurality of preset active devices; the plurality of preset active devices comprise the processor; and the switch-on-off circuit can control the power supply to stop supplying power to the plurality of preset active devices in response to the shutdown control signal. Since the interaction circuit can input the shutdown interrupt signal to the processor and input the shutdown instruction signal to the delay circuit in response to the shutdown operation after the user triggers the shutdown operation, the processor can input the shutdown control signal to the switch-on-off circuit within the first preset response duration in response to the shutdown interrupt signal when the operating system is normal, and the switch-on-off circuit controls the power supply to stop supplying power to the plurality of preset active devices in response to the shutdown control signal, when the operating system is abnormal, the processor cannot input the shutdown control signal to the switch-on-off circuit, but the delay circuit can input the shutdown control signal to the switch-on-off circuit after the first preset response duration in response to the shutdown instruction signal, thereby achieving the shutdown in the software exception. In summary, the load power supply control circuit can avoid file system damage as much as possible and guarantee user experience on the premise that the electronic device can be shut down.

[0059] Embodiment two

[0060] The load power supply control circuit provided in the embodiment two of the application, on the basis of the embodiment one, the interaction operation further comprises a start-up operation; the interaction circuit can input a start-up instruction signal to the delay circuit in response to the start-up operation; the delay circuit can input a start-up control signal to the switch-on-off circuit after a second preset response duration in response to the start-up instruction signal; the second preset response duration is shorter than the first preset response duration; and the switch-on-off circuit can control the power supply to start supplying power to the plurality of preset active devices in response to the start-up control signal.

[0061] In the embodiment, the load power supply control circuit can not only realize the shutdown of the electronic device, but also realize the start-up of the electronic device. When the electronic device is in the shutdown state, the processor has no power supply, therefore, when the user triggers the start-up operation, the interaction circuit can only input the start-up instruction signal to the delay circuit.

[0062] The power-on instruction signal and the power-off instruction signal are opposite signals. For example, when the power-off instruction signal is a high-level signal, the power-on instruction signal is a low-level signal.

[0063] When powering off, the processor outputs the power-off control signal first, and the delay circuit outputs the power-off control signal only when the processor cannot output the power-off control signal. When powering on, only the delay circuit can output the power-on control signal. Therefore, the second preset time length is shorter than the first preset response time length, so as to realize fast power-on and delayed power-off when the operating system is abnormal.

[0064] Figure 4 Schematic diagram of the interaction circuit provided by the embodiment of the application Figure Three Optionally, in the embodiment, the power-off interrupt signal and the power-off instruction signal are high-level signals, and the power-on instruction signal is a low-level signal. As shown in Figure 4 The interaction device 110 includes a switching device 1101. The power-on operation is used to close the switching device 1101, and the power-off operation is used to open the switching device 1101.

[0065] The interaction circuit 11 further includes a first current-limiting resistor 111, a second current-limiting resistor 112, a third current-limiting resistor 112, a first switching module 114, and a second switching module 115.

[0066] The first switching module 114 includes a first control end and a first switching structure, and the second switching module 115 includes a second control end and a second switching structure. The control end is used to control the conduction or disconnection of the corresponding switching structure.

[0067] One end of the switching device 1101 is grounded, and the other end is connected with the first control end and connected with the power supply Vcc through the first current-limiting resistor 111.

[0068] One end of the first switching structure is grounded, and the other end is connected with the second control end and connected with the power supply Vcc through the second current-limiting resistor 112.

[0069] One end of the second switching structure is grounded, and the other end is connected with the power supply Vcc through the third current-limiting resistor 113 and connected with the processor and the delay circuit as an output end Vout11 of the interaction circuit.

[0070] In the first switching module 114, when the first control end is a high-level signal, the first switching structure is turned on, and when the first control end is a low-level signal, the first switching structure is turned off. The first switching module can include a triode. The base of the triode can be used as the first control end. The emitter of the triode can be used as one end of the first switching structure. The collector of the triode can be used as the other end of the first switching structure.

[0071] In the second switch module 115, when the second control end is high, the second switch structure is turned on, and when the second control end is low, the second switch structure is turned off. The second switch module can include an NMOS tube. The gate of the NMOS tube can be used as the second control end. The source of the NMOS tube can be used as one end of the second switch structure. The drain of the NMOS tube can be used as the other end of the second switch structure.

[0072] The first current-limiting resistor 111, the second current-limiting resistor 112, and the third current-limiting resistor 113 are in the form of an interactive circuit. The current-limiting resistor can also be in the form of a current-limiting module composed of multiple resistors, and the like, which is not limited here.

[0073] Figure 5 Schematic diagram of the delay circuit provided in the embodiment Figure One Alternatively, in the embodiment, the shutdown interrupt signal and the shutdown instruction signal are high-level signals; the power-on instruction signal is a low-level signal, the shutdown control signal is a high-level signal, and the power-on control signal is a falling edge signal. As shown in Figure 5 The delay circuit 13 includes a third switch module 131, a fourth current-limiting resistor 132, a delay capacitor 133, a ground resistor 134, and a fourth switch module 135. The third switch module 131 includes a third control end and a third switch structure, and the fourth switch module 135 includes a fourth control end and a fourth switch structure.

[0074] The third control end 131 is an input end Vin13 of the delay circuit.

[0075] One end of the delay capacitor 133 is grounded, and the other end is connected to the power supply Vcc through the third switch structure, connected to the fourth control end, and grounded through the ground resistor 134.

[0076] One end of the fourth switch structure is grounded, and the other end is connected to the power supply Vcc of the control circuit through the fourth current-limiting resistor 132 and is an output end Vout13 of the delay circuit.

[0077] In the third switch module 131, when the third control end is high, the third switch structure is turned off, and when the third control end is low, the third switch structure is turned on. The third switch module can include a PMOS tube. The gate of the PMOS tube can be used as the third control end. The source of the PMOS tube can be used as one end of the third switch structure connected to the power supply Vcc of the control circuit. The drain of the PMOS tube can be used as the other end of the third switch structure connected to the delay capacitor 133.

[0078] In the fourth switch module 135, when the fourth control end is high, the fourth switch structure is turned on; when the fourth control end is low, the fourth switch structure is turned off. The fourth switch module can include an NMOS tube. The gate of the NMOS tube can be used as the fourth control end. The source of the NMOS tube can be used as one end of the fourth switch structure ground. The drain of the NMOS tube can be used as the other end connected with the fourth current-limiting resistor, and the output end Vout13 of the delay circuit.

[0079] When the interactive circuit inputs the power-on instruction signal to the delay circuit, the output end Vout13 of the delay circuit is low, at this time, the third control end is low, the third switch structure is turned on, and the control circuit power supply Vcc can quickly complete the charging of the delay capacitor 133. After the delay capacitor 133 is charged, the fourth control end becomes high, the fourth switch structure is turned on, the voltage of the output end Vout13 of the delay circuit is pulled down to 0, and the delay circuit outputs the power-on control signal.

[0080] When the interactive circuit inputs the power-off instruction signal to the delay circuit, the input end Vin13 of the delay circuit is high, at this time, the third control end is high, the third switch structure is turned off, and the delay capacitor 133 can only be discharged through the ground resistance 134 to realize the delay function of the delay circuit. The time delay of the discharge is related to the resistance value of the ground resistance 134 and the capacitance value of the delay capacitor 133. The greater the resistance value of the ground resistance, the longer the time delay. During the discharging process of the delay capacitor 133, the voltage of the fourth control end gradually decreases to low, and after the delay capacitor 133 is discharged, the fourth control end is low, the fourth switch structure is turned off, and then the voltage of the output end Vout13 of the delay circuit is pulled up to the voltage of the control circuit power supply by the current-limiting resistor 132. The output end Vout13 of the delay circuit is high, and the delay circuit outputs the power-off control signal.

[0081] Figure 6 The delay circuit provided by the embodiment of the present application Figure Two . Optionally, as Figure 6 indicated, the delay circuit can further include a resistor R5, a resistor R6 and a resistor R7 on the basis of Figure 2 .

[0082] The resistor R5 is connected between the third control end and the input end Vin13 of the delay circuit.

[0083] The resistor R6 is connected between the other end of the delay capacitor 133 and the third switch structure.

[0084] The resistor R7 is connected between the other end of the delay capacitor 133 and the fourth control end.

[0085] The resistance of the resistor R6 is much smaller than the sum of the resistance of the resistor R7 and the resistance of the ground resistor 134, so that the control circuit power supply Vcc can quickly charge the delay capacitor 133 at the start-up. The sum of the resistance of the resistor R7 and the resistance of the ground resistor 134 is much larger than the resistance of the resistor R6, so that the delay can be realized at the shut-down. Exemplarily, the resistance of the resistor R6 can be 100Ω, and the resistance of the resistor R7 and the resistance of the ground resistor 134 can be 470KΩ.

[0086] Embodiment three

[0087] Figure 7 A schematic of the switch-on / off circuit provided by the embodiment of the application Figure One As shown in Figure 7 , the switch-on / off circuit 14 includes a shut-down triggering module 141 and a switch-on / off executing module 142.

[0088] The shut-down triggering module 141 can input a shut-down signal to the switch-on / off executing module 142 in response to a shut-down control signal.

[0089] The switch-on / off executing module 142 can disconnect the power supply loop between the load power supply and the plurality of preset active devices in response to the shut-down signal.

[0090] Figure 8 A schematic of the switch-on / off circuit provided by the embodiment of the application Figure Two . Alternatively, the shut-down signal can be a low-level signal, as shown in Figure 8 , the shut-down triggering module 141 includes a fifth switch module 1411 and a sixth current-limiting resistor 1412; the switch-on / off executing module 142 includes a flip-flop 1421 and a sixth switch module 1422.

[0091] The fifth switch module 1411 includes a fifth control end and a fifth switch structure, and the sixth switch module 1422 includes a sixth control end and a sixth switch structure; the flip-flop 1421 includes a reset end and an inverting output end

[0092] The fifth control end is an input end Vin14 of the switch-on / off circuit.

[0093] One end of the fifth switch structure is grounded, and the other end is connected with the reset end and connected with the control circuit power supply Vcc through the sixth current-limiting resistor 1412.

[0094] The reset end is used for receiving the shut-down signal, and when the reset end changes from a high level to a low level, the inverting output end changes to a high level.

[0095] The sixth control end is connected with the inverting output end ;

[0096] The sixth switch structure is used to control the power supply circuit of multiple preset active devices; when the sixth control terminal is high, the sixth switch structure is open.

[0097] In this embodiment, when the sixth control terminal is high, the sixth switch structure is open, thereby disconnecting the power supply circuit between the load power supply and multiple preset active devices, thus achieving power-off. Conversely, when the sixth control terminal is low, the sixth switch structure is open, thereby enabling the load power supply to the multiple preset active devices.

[0098] The sixth switch module can be a power switch module. When the control terminal of the power switch module is at a high level, the switching structure of the power switch module is open, thereby disconnecting the power supply circuit of the load power supply to multiple preset active devices. When the control terminal of the power switch module is at a low level, the switching structure of the power switch module is open, thereby enabling the load power supply to supply power to multiple preset active devices.

[0099] The fifth switching module may include an NMOS transistor, whose gate can serve as the fifth control terminal. The source of the NMOS transistor can serve as one end of the fifth switching structure, and the drain of the NMOS transistor can serve as the other end of the fifth switching structure.

[0100] When the delay circuit or processor inputs a power-off control signal to the power-on / off circuit, the power-off control signal is a high-level signal. Therefore, the fifth control terminal is high-level, the fifth switch structure is turned on, causing the reset terminal of the flip-flop to change from high-level to low-level, which in turn causes the inverting output terminal of the flip-flop to... It becomes high level.

[0101] Inverting output of the flip-flop When the voltage is high, the sixth switch structure is open, thereby disconnecting the power supply circuit between the load power supply and multiple preset active devices, thus achieving shutdown.

[0102] Figure 9 A schematic diagram of the power-on / off circuit provided in the embodiments of this application. Figure Three Optionally, such as Figure 9 As shown, the power-on / off circuit includes a power-on trigger module 143 and a power-on / off execution module 142.

[0103] The power-on trigger module 143 can respond to the power-on control signal and input a power-on signal to the power-on / off execution module 142.

[0104] The power-on / off execution module 142 can respond to a power-on signal and connect the power supply circuit between the load power supply and multiple preset active devices.

[0105] Figure 10 A schematic diagram of the power-on / off circuit provided in the embodiments of this application. Figure Four Optionally, the power-on signal is a rising edge signal, such as...Figure 10 As shown in the figure, the power-on trigger module 143 comprises a NOT circuit 1431, and the power-on / off execution module 142 further comprises a pull-up resistor 1423; the flip-flop 1421 further comprises a signal input end D and a clock input end. When the sixth control end is at a low level, the sixth switch structure is turned on.

[0106] The NOT circuit 1431 is connected between the clock input end and the delay circuit, and is used for performing a NOT operation on the power-on control signal to obtain a power-on signal, and inputting the power-on signal to the clock input end.

[0107] The signal input end is connected with the control circuit power supply Vcc through the pull-up resistor 1423.

[0108] The flip-flop 1421 can, when the clock input end is inputted with a rising edge signal and the signal input end is at a high level, transmit the level signal of the signal input end D to the inverted output end after inversion, and change the inverted output end to a low level.

[0109] In this embodiment, when the delay circuit inputs the power-on control signal to the power-on / off circuit, the power-on control signal is a falling edge signal, the NOT circuit 1431 performs a NOT operation on the falling edge signal to obtain a rising edge signal, and outputs the rising edge signal as the power-on signal to the clock input end of the flip-flop. The clock input end of the flip-flop receives the rising edge signal, transmits the level signal of the signal input end D to the inverted output end after inversion, and changes the inverted output end to a low level. Since the signal input end is connected with the control circuit power supply Vcc through the pull-up resistor 1423 and is always at a high level, when the delay circuit inputs the power-on control signal to the power-on / off circuit, the inverted output end changes from a high level to a low level. Further, the sixth control end is at a low level, the sixth switch structure is turned on, the load power supply is in communication with the plurality of preset active devices, and the load power supply can supply power to the plurality of preset active devices.

[0110] In this embodiment, the flip-flop can be a D flip-flop. The flip-flop further comprises a signal output end Q, the level of the signal output end is opposite to the level of the inverted output end, and when the clock input end of the flip-flop receives the rising edge signal, the flip-flop transmits the level signal of the signal input end to the signal output end and transmits the inverted signal to the inverted output end after inversion.

[0111] Figure 11 A schematic diagram of the NOT circuit provided in the embodiments of the present application is shown. Optionally, as shown in the figure, the NOT circuit 1431 comprises a resistor R8, a resistor R9, an NMOS tube Q1 and a capacitor C2. Figure 11 One end of the resistor R9 serves as an input end Vin1431 of the NOT circuit, the other end is connected with the gate of the NMOS tube Q1, and is grounded through the capacitor C2.

[0112]

[0113] ​The source of the NMOS tube Q1 is grounded. The drain of the NMOS tube Q1 is connected with the control circuit power supply Vcc through the resistor R8 and serves as the output terminal Vout1431 of the inverter circuit.

[0114] The input terminal Vin1431 of the inverter circuit is the input terminal of the power-on triggering module, the output terminal Vout1431 of the inverter circuit is the output terminal of the power-on triggering module, and is connected with the power-on executing module.

[0115] The resistor R8 is used to pull up the voltage of the output terminal Vout1431 of the inverter circuit to the voltage of the control circuit power supply Vcc when the NMOS tube Q1 is turned on. The resistor R9 and the capacitor C2 are used for voltage stabilization and anti-interference.

[0116] Embodiment Three

[0117] Figure 12 Schematic diagram of the load power supply control circuit provided in Embodiment Three of the present application Figure Two As shown in Figure 12 , the load power supply control circuit provided in the present embodiment includes an interaction circuit 11, a processor 12, a delay circuit 13 and a power-on-off circuit 14.

[0118] The interaction circuit 11 includes a resistor R1, a resistor R2, a resistor R3, an NMOS tube Q0, a triode T0 and a switch S0. The switch S0 is an interaction device, and the power-on operation is used to close the switch S0, and the power-off operation is used to open the switch S0.

[0119] The delay circuit 13 includes a resistor R5, a PMOS tube Q2, an NMOS tube Q3, a resistor R6, a resistor R7, a resistor R11 and a capacitor C4.

[0120] The power-on-off circuit 14 includes a resistor R8, a resistor R9, an NMOS tube Q1, a capacitor C1, a resistor R12, a resistor R13, a capacitor C3, a D flip-flop, an NMOS tube Q4, a resistor R14, a resistor R15 and a capacitor C5.

[0121] The D flip-flop has a signal input terminal D, a clock input terminal, a signal output terminal Q, an inverted output terminal and a reset terminal.

[0122] One end of the switch S0 is grounded.

[0123] The other end of the switch S0 is connected with one end of the resistor R4.

[0124] The other end of the resistor R4 is connected with one end of the resistor R1 and the base of the triode T0.

[0125] The other end of the resistor R1 is connected with the control circuit power supply Vcc.

[0126] The emitter of the transistor T0 is connected to ground. The collector of the transistor T0 is connected to one end of the resistor R2, one end of the capacitor C1, and the gate of the NMOS transistor Q0.

[0127] The other end of the resistor R2 is connected to the control circuit power supply Vcc.

[0128] The other end of the capacitor C1 is connected to ground.

[0129] The source of the NMOS transistor Q0 is connected to ground. The drain of the NMOS transistor is connected to one end of the resistor R3, one end of the resistor R5, and the processor.

[0130] The other end of the resistor R3 is connected to the control circuit power supply Vcc.

[0131] The other end of the resistor R5 is connected to the gate of the PMOS transistor Q2.

[0132] The source of the PMOS transistor Q2 is connected to the control circuit power supply Vcc.

[0133] The drain of the PMOS transistor Q2 is connected to one end of the resistor R6.

[0134] The other end of the resistor R6 is connected to one end of the capacitor C4 and one end of the resistor R7.

[0135] The other end of the capacitor C4 is connected to ground.

[0136] The other end of the resistor R7 is connected to one end of the capacitor R10 and the gate of the NMOS transistor Q3.

[0137] The other end of the capacitor R10 is connected to ground.

[0138] The source of the NMOS transistor Q3 is connected to ground. The drain of the NMOS transistor is connected to one end of the resistor R11, one end of the resistor R8, and the gate of the NMOS transistor Q4.

[0139] The other end of the resistor R11 is connected to the control circuit power supply Vcc.

[0140] The other end of the resistor R8 is connected to one end of the capacitor C2 and the gate of the NMOS transistor Q1.

[0141] The other end of the capacitor C2 is connected to ground.

[0142] The source of the NMOS transistor Q1 is connected to ground. The drain of the NMOS transistor Q1 is connected to one end of the resistor R9, one end of the resistor R12, one end of the capacitor C3, and the clock input of the D flip-flop.

[0143] The other end of the resistor R9 is connected to the control circuit power supply Vcc.

[0144] The other end of the resistor R12 is connected to ground. The other end of the capacitor C3 is connected to ground.

[0145] The signal input end D of the D flip-flop is connected to one end of the resistor R13.

[0146] The other end of the resistor R13 is connected to the control circuit power supply Vcc.

[0147] The inverting output end of the D flip-flop The output end Vout of the load power supply control circuit is used to control whether the load power supply supplies power to the plurality of preset active devices. Exemplarily, when the inverting output end is at a high level, the load power supply stops supplying power to the plurality of preset active devices, realizing power-off; when the inverting output end is at a low level, the load power supply starts supplying power to the plurality of preset active devices, realizing power-on.

[0148] The drain of the NMOS tube Q4 is connected to one end of the capacitor C5, one end of the resistor R15, the reset end of the D flip-flop, and the drain of the NMOS tube Q5.

[0149] The other end of the resistor R15 is connected to the control circuit power supply Vcc.

[0150] The other end of the capacitor C5 is connected to ground. The source of the NMOS tube Q5 is connected to ground.

[0151] The drain of the NMOS tube Q5 is connected to one end of the resistor R14.

[0152] The other end of the resistor R14 is connected to the processor.

[0153] In an optional embodiment, the capacitor C15 is 1 μf, the capacitor C25 is 1 μf, the capacitor C35 is 1 nf, the capacitor C45 is 10 μf, and the capacitor C5 is 10 nf. The resistor R1 is 47 kΩ, the resistor R2 is 47 kΩ, the resistor R3 is 47 kΩ, the resistor R4 is 100 Ω, the resistor R5 is 100 Ω, the resistor R6 is 100 Ω, the resistor R7 is 470 kΩ, the resistor R8 is 10 kΩ, the resistor R9 is 100 kΩ, the resistor R10 is 470 kΩ, the resistor R11 is 10 kΩ, the resistor R12 is 470 kΩ, the resistor R13 is 100 kΩ, the resistor R14 is 100 Ω, and the resistor R15 is 100 kΩ.

[0154] When the user triggers the start operation, the switch S0 is closed, and the interactive circuit outputs a low level. At this time, the PMOS tube Q1 is turned on, and the power supply charges the capacitor C2 through the resistor R2 and the capacitor C2 quickly. After the capacitor C2 is charged, the delay circuit outputs a low level, and a high-to-low level is generated. Since the R2 is small, the charging time is very short, and the start delay is small. The high-to-low level is inverted through the NMOS tube Q5, and a low-to-high level is output at the gate of the NMOS tube Q5, to generate a rising edge signal and send it to the D flip-flop as a clock signal. The rising edge signal triggers the D flip-flop to output a low level, to realize the start operation.

[0155] When the user triggers the shutdown operation, the switch S0 is opened, and the interactive circuit outputs a high level. At this time, if the operating system running in the processor is normal, the software in the operating system can control the processor to output a high level. The high level is inverted through the NMOS tube Q3, and a low level is generated at the gate of the NMOS tube and sent to the flip-flop as an asynchronous reset signal, to cause the flip-flop to output a high level and realize the software shutdown.

[0156] If the operating system running in the processor is abnormal, the software in the operating system cannot control the processor to output a high level. Therefore, the high level of the interactive circuit is sent to the delay circuit at the same time, so that the PMOS tube Q1 is cut off, and the capacitor C2 can only be discharged to the ground through the resistor R7 and the resistor R10. The discharge time delay is determined by the resistance value of the resistor R7, the resistance value of the electronic R10, and the capacitance value of the capacitor C2. When the capacitor C2 is discharged to the closing threshold of the NMOS tube Q3, the NMOS tube Q3 is cut off, the delay circuit outputs a high level, and a low level is output at the gate of the NMOS tube Q4 after being inverted through the NMOS tube Q4, and is sent to the reset end of the flip-flop as an asynchronous reset signal, to cause the flip-flop to output a high level and realize the hardware shutdown. Since R7+R10 is large, the delay is long, thereby realizing the shutdown delay function. The specific delay value can be realized by selecting a capacitor C2 with different capacitance values. The shutdown delay can be set to 5 seconds.

[0157] The load power supply control circuit provided in the embodiment can avoid file system damage as much as possible and protect user experience on the premise that the electronic device can be shut down.

[0158] The embodiment of the application further provides a printed circuit board, which comprises the load power supply control circuit provided in any one of the above embodiments. The printed circuit board is used in an electronic device, can avoid file system damage as much as possible and protect user experience on the premise that the electronic device can be shut down.

[0159] The electronic device provided in the embodiment can realize power-on and power-off through the same interaction device, and further improves user experience.

[0160] The electronic device provided in the embodiment can realize power-on and power-off through the same interaction device, and further improves user experience.

[0161] It should be understood that the method embodiments described above are only illustrative, and the method of the present application can also be implemented in other ways. For example, the division of the modules in the above embodiments is only a logical functional division, and another division mode can be used in actual implementation. For example, a plurality of modules can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0162] In addition, each functional module in each embodiment of the present application can be integrated into one module, or each module can exist physically alone, or two or more modules can be integrated together, unless otherwise specified.

[0163] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited to the action order described, because according to the present application, some steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0164] It should be further noted that, although each step in the flowchart is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified in this document, the execution of these steps has no strict order limitation, and these steps can be executed in other order. Moreover, at least part of the steps in the flowchart can include a plurality of sub-steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or sub-steps or stages of other steps.

[0165] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0166] It is to be understood that the application is not limited to the precise construction herein disclosed and shown in the drawings, and that various changes in shape, size and arrangements of parts can be made without departing from the scope of the application. The scope of the application is limited only by the claims that follow.

Claims

1. A load power supply control circuit characterized by comprising: The application relates to a power-off and power-on circuit, which comprises an interaction circuit, a processor, a delay circuit and a power-off and power-on circuit; the interaction circuit is connected with the processor and the delay circuit; the processor and the delay circuit are connected with the power-off and power-on circuit; the interaction circuit comprises an interaction device which is used for receiving a user-triggered interaction operation, the interaction operation comprising a power-off operation; the interaction circuit can input a power-off interrupt signal to the processor and a power-off instruction signal to the delay circuit in response to the power-off operation; the processor is used for running an operating system; when the operating system normally runs, the processor can input a power-off control signal to the power-off and power-on circuit within a first preset response time in response to the power-off interrupt signal; the delay circuit can input a power-off control signal to the power-off and power-on circuit after the first preset response time in response to the power-off instruction signal; the power-off and power-on circuit is used for controlling whether a load power supply supplies power to a plurality of preset active devices, the plurality of preset active devices comprising the processor; the power-off and power-on circuit can control the load power supply to stop supplying power to the plurality of preset active devices in response to the power-off control signal. The interaction operation further comprises a power-on operation; the interaction circuit can further input a power-on instruction signal to the delay circuit in response to the power-on operation; the delay circuit can further input a power-on control signal to the power-off and power-on circuit after a second preset response time in response to the power-on instruction signal; the second preset response time is shorter than the first preset response time; the power-off and power-on circuit can further control the load power supply to start supplying power to the plurality of preset active devices in response to the power-on control signal. The power-off interrupt signal and the power-off instruction signal are both high-level signals; the power-on instruction signal is a low-level signal; the interaction device comprises a switch device; the power-on operation is used for closing the switch device, and the power-off operation is used for opening the switch device; the interaction circuit further comprises a first current-limiting resistor, a second current-limiting resistor, a third current-limiting resistor, a first switch module and a second switch module; the first switch module comprises a first control end and a first switch structure, and the second switch module comprises a second control end and a second switch structure; the control end is used for controlling the conduction or disconnection of the corresponding switch structure; one end of the switch device is grounded, and the other end is connected with the first control end and connected with a control circuit power supply through the first current-limiting resistor; one end of the first switch structure is grounded, and the other end is connected with the second control end and connected with the control circuit power supply through the second current-limiting resistor; one end of the second switch structure is grounded, and the other end is connected with the control circuit power supply through the third current-limiting resistor and connected with the processor and the delay circuit; the power-off control signal is a high-level signal, and the power-on control signal is a falling edge signal; the delay circuit comprises a third switch module, a fourth current-limiting resistor, a delay capacitor, a ground resistor and a fourth switch module; the third switch module comprises a third control end and a third switch structure, and the fourth switch module comprises a fourth control end and a fourth switch structure. ​ ​ ​ ​ ​ 2. The load power supply control circuit according to claim 1, characterized by ​ ​ ​ 3. The load power supply control circuit according to claim 2, wherein ​ ​ ​ ​ ​ ​ ​ 4. The load power supply control circuit according to claim 3, wherein ​ ​ The third control end is an input end of the delay circuit; One end of the delay capacitor is grounded, and the other end is connected with the power supply of the control circuit through the third switch structure, connected with the fourth control end, and grounded through the ground resistance; One end of the fourth switch structure is grounded, and the other end is connected with the power supply of the control circuit through the fourth current-limiting resistor and is an output end of the delay circuit.

5. The load power supply control circuit according to claim 4, wherein The shutdown circuit comprises a shutdown triggering module and a shutdown executing module; The shutdown triggering module is capable of inputting a shutdown signal to the shutdown executing module in response to the shutdown control signal; The shutdown executing module is capable of disconnecting the power supply loop between the load power supply and the plurality of preset active devices in response to the shutdown signal.

6. The load power supply control circuit according to claim 5, wherein The shutdown signal is a low-level signal; The shutdown triggering module comprises a fifth switch module and a sixth current-limiting resistor, and the shutdown executing module comprises a flip-flop and a sixth switch module; The fifth switch module comprises a fifth control end and a fifth switch structure, the sixth switch module comprises a sixth control end and a sixth switch structure, and the flip-flop comprises a reset end and an inverted output end; The fifth control end is an input end of the shutdown circuit; One end of the fifth switch structure is grounded, and the other end is connected with the reset end and connected with the power supply of the control circuit through the sixth current-limiting resistor; The reset end is used for receiving the shutdown signal, and the inverted output end becomes high level when the reset end changes from high level to low level; The sixth control end is connected with the inverted output end; The sixth switch structure is used for controlling the power supply loop of the plurality of preset active devices, and the sixth switch structure is disconnected when the sixth control end is high level.

7. The load power supply control circuit according to claim 6, wherein The shutdown circuit comprises a startup triggering module and a shutdown executing module; The startup triggering module is capable of inputting a startup signal to the shutdown executing module in response to the startup control signal; The shutdown executing module is capable of connecting the power supply loop between the load power supply and the plurality of preset active devices in response to the startup signal.

8. The load power supply control circuit according to claim 7, wherein The startup signal is a rising edge signal; The startup triggering module comprises a NOT circuit, the shutdown executing module further comprises a pull-up resistor, the flip-flop further comprises a signal input end and a clock input end, and the sixth switch structure is turned on when the sixth control end is low level; The NOT circuit is connected between the clock input end and the delay circuit, is used for performing a NOT operation on the startup control signal to obtain the startup signal, and inputs the startup signal to the clock input end; The signal input end is connected with the power supply of the control circuit through the pull-up resistor; The flip-flop is capable of changing the inverted output end to low level when the clock input end is inputted with a rising edge signal and the signal input end is high level.

9. A printed circuit board, characterized by The load power supply control circuit comprises the shutdown circuit.

10. An electronic device, comprising: The load power supply control circuit comprises the startup circuit.

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