Sram floating point in-memory computing architecture and computing method

Abstract

The application provides an SRAM floating point in-memory computing architecture and a computing method, which comprise an SRAM floating point in-memory computing core module, a weight processing module, an eigenvalue index alignment module, a digital multiplication module, a shift accumulation module and a fixed point to floating point module.The weight processing module comprises a weight index pre-alignment module, a large index weight storage and a weight index storage.The weight index pre-alignment module aligns the indexes of weights according to the size of the computing parallel degree, and the part of the floating point weights exceeding the threshold is stored in the large index weight storage, the maximum index of the remaining weights is stored in the weight index storage, and the remaining weights are aligned in index and then stored in the SRAM floating point in-memory computing core module.The floating point in-memory computing steps of the application are compatible with the fixed point steps, so the application simultaneously supports fixed point in-memory computing.Because the large index weights in a group of computing parallel degrees are less, the application can significantly improve the computing precision with a smaller area cost.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, specifically to an SRAM floating-point in-memory computing architecture and computing method. Background Technology

[0002] Low-Earth orbit (LEO) remote sensing constellations are equipped with numerous payloads, requiring onboard computing platforms to process massive amounts of remote sensing image data in real time to support all-weather, real-time on-orbit applications such as geographic monitoring and disaster early warning. Among these applications, neural network-based artificial intelligence algorithms have been widely used in on-orbit remote sensing image processing. Through target recognition, detection, classification, and information extraction, they significantly reduce the amount of data that needs to be transmitted, effectively alleviating bandwidth pressure on satellite-to-ground transmission. However, in the traditional von Neumann architecture, because neural network computation requires frequent data transfer between storage and computing units, most of the total energy consumption is used for reading and writing to storage units rather than computation.

[0003] In-memory computing architecture overcomes the aforementioned "memory wall" problem. Its core idea is to perform computational operations directly within the storage unit, thereby significantly reducing data movement and improving energy efficiency. Because in-memory computing is suitable for matrix multiplication-intensive artificial intelligence algorithms, it has wide applications in the field of artificial intelligence, especially in handling tasks such as target recognition, detection, and classification on-orbit satellites, greatly reducing hardware overhead and significantly improving computational energy efficiency. However, onboard in-memory computing architecture still faces the challenge of balancing computational accuracy and power consumption.

[0004] In spaceborne computing systems, the limited onboard hardware resources make it difficult to deploy high-precision neural network models, resulting in limited computational accuracy. Increasing accuracy typically leads to higher power consumption. Therefore, a balance between computational accuracy and power consumption must be considered in the hardware architecture design. Consequently, there is an urgent need for a floating-point in-memory computing architecture and method to reduce the overhead of floating-point computing resources.

[0005] Patent application CN120353429A discloses a floating-point arithmetic circuit and an in-memory arithmetic chip based on SRAM. The arithmetic circuit is used for: S1: calculating the exponent sum and mantissa product of the multi-bit floating-point input value and the multi-bit floating-point weight value bit by bit; S2: determining the maximum exponent among all exponent sums, and then calculating the difference between the maximum exponent and the exponent sums of each row; S3: first generating an adjustable initial decrement value, then comparing the decrement value with each difference to generate an addition control signal, and finally determining whether to input the mantissa product of each row into the adder tree for addition; S4: after comparing with the exponent sums of all rows, the decrement value is decremented, and step S3 is executed; when the decrement value reaches zero, the mantissa accumulation result is used as the total number of bits; S5: generating the multiplication-accumulation operation result based on the maximum exponent and the total number of bits. However, this patent cannot completely solve the existing technical problems, nor can it meet the needs of this invention. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide an SRAM floating-point in-memory computing architecture and computing method.

[0007] The SRAM floating-point in-memory computing architecture provided by the present invention includes: an SRAM floating-point in-memory computing core module, a weight processing module, an eigenvalue exponent alignment module, a digital multiplication module, a shift accumulation module, and a fixed-point to floating-point conversion module;

[0008] The SRAM floating-point storage core module is used to store weights in SRAM cells and perform parallel multiplication and accumulation. In both fixed-point and floating-point calculation modes, the SRAM floating-point storage core module performs parallel calculations based on the weight data and input feature values.

[0009] The weight processing module includes a weight index pre-alignment module, a large index weight memory, and a weight index memory. The weight index pre-alignment module is used to perform index alignment of weights according to the degree of computational parallelism in floating-point calculation mode, store floating-point weights exceeding the threshold into the large index weight memory, store the maximum index of the remaining weights into the weight index memory, and store the remaining weights after index alignment into the SRAM floating-point storage core module.

[0010] The eigenvalue exponent alignment module is used to transmit the eigenvalue corresponding to the large exponent weight to the digital multiplication module in floating-point calculation mode, forward the maximum exponent of the remaining eigenvalues ​​to the fixed-point to floating-point module, and transmit the remaining eigenvalues ​​after exponent alignment to the SRAM floating-point storage core module.

[0011] The digital multiplication module is used to perform a multiplication operation on the large exponential weights from the large exponential weight memory and the corresponding eigenvalues ​​from the eigenvalue exponential alignment module in floating-point calculation mode.

[0012] The shift-accumulate module is used to perform shift and accumulation operations on the output of the SRAM floating-point memory module;

[0013] The fixed-point to floating-point module is used to convert the output of the shift-accumulate module into a floating-point number and add it to the output of the digital multiplication module;

[0014] The weight index pre-alignment module is connected to the large index weight memory, the weight index memory and the SRAM floating-point storage core module.

[0015] The eigenvalue exponent alignment module is connected to the SRAM floating-point storage core module and the digital multiplication module;

[0016] The digital multiplication module is connected to the large exponential weight memory and the eigenvalue exponential alignment module, and is also connected to the fixed-point to floating-point module.

[0017] The shift-accumulator module is connected to the SRAM floating-point storage core module and the fixed-point to floating-point module;

[0018] The fixed-point to floating-point module is connected to the shift-accumulate module and the digital multiplication module.

[0019] Preferably, the SRAM floating-point memory module has a size of 128×128 and uses a standard 6T SRAM cell.

[0020] Preferably, the digital multiplication module is a general-purpose floating-point multiplication circuit that supports IEEE 754 standard 32-bit floating-point multiplication.

[0021] Preferably, the shift-accumulation module is a general-purpose shift-accumulation circuit that supports weighted exponential shift and eigenvalue exponential shift and accumulation operations of the multiplication-accumulation result.

[0022] Preferably, the fixed-point to floating-point module is a general-purpose floating-point addition circuit that supports IEEE 754 standard 32-bit floating-point addition.

[0023] The SRAM floating-point in-memory calculation method provided by the present invention includes the following steps:

[0024] Step S1: Adopt the weight exponent pre-alignment strategy, and perform exponent alignment of weights according to the size of the computational parallelism. Floating-point weights exceeding the threshold are stored in the large exponent weight memory, and the maximum exponent of the remaining weights is stored in the weight exponent memory. After exponent alignment of the remaining weights, they are stored in the SRAM array.

[0025] Step S2: Using an eigenvalue exponent alignment strategy, the eigenvalues ​​corresponding to the large exponent weights are directly connected to the digital multiplication module. The maximum exponent of the remaining eigenvalues ​​is forwarded to the fixed-point to floating-point module via the digital multiplication module. Then, the remaining eigenvalues ​​are exponent aligned and transmitted to the SRAM floating-point storage core module.

[0026] Step S3: Convert the calculation result of the shift accumulation module into a floating-point number through the fixed-point to floating-point conversion module, and add it to the result of the number multiplication module to finally obtain the floating-point result.

[0027] Preferably, in step S1, the threshold is determined based on the distribution of floating-point weights, including arranging the floating-point weights from largest to smallest and determining the floating-point weights that rank in a preset percentage as the threshold.

[0028] Preferably, in step S1, the exponent alignment of the weights includes: aligning the remaining weight exponents to the maximum exponent, wherein the alignment method includes shifting the mantissa to the right, and the number of right shifts is based on the difference between the maximum exponent and the exponent of the current weight.

[0029] Preferably, for a weight whose exponent is E, the mantissa is shifted right by S bits, where S is the difference between the maximum exponent and E. The sign bit is padded on the left, and the right shift is truncated or padded with zeros to conform to the data bit width of the SRAM array.

[0030] Preferably, the data width of the SRAM array is 32 bits, including 1 sign bit and 31 mantissa bits. The mantissa bits include 23 mantissa bits and an implicit 1. The truncation bit after right shift is 24 + S - 31.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] This invention provides an SRAM floating-point in-memory computing architecture and method that supports flexible switching between fixed-point and floating-point in-memory computing. In low-power scenarios, by controlling the shutdown of the weight processing module, eigenvalue exponent alignment module, digital multiplication module, and fixed-point to floating-point module, floating-point in-memory computing can be switched to fixed-point in-memory computing to reduce power consumption. Compared with traditional methods, by reusing SRAM in-memory computing cores for computing, the computing accuracy is significantly improved with a smaller area overhead. Attached Figure Description

[0033] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0034] Figure 1 A schematic diagram of an SRAM floating-point in-memory computing architecture provided by the present invention;

[0035] Figure 2 A schematic diagram of a weight index pre-alignment strategy provided by the present invention;

[0036] Figure 3 A schematic diagram of an eigenvalue exponential alignment strategy provided by the present invention;

[0037] Figure 4 This is a schematic diagram of a fixed-point to floating-point module provided by the present invention;

[0038] Figure 5 This is a flowchart illustrating an SRAM floating-point in-memory calculation method provided by the present invention.

[0039] Figure reference numerals: SRAM floating-point storage core module 101, weight processing module 102, eigenvalue exponent alignment module 103, digital multiplication module 104, shift accumulation module 105, fixed-point to floating-point module 106, weight exponent pre-alignment module 1021, large exponent weight memory 1022, weight exponent memory 1023. Detailed Implementation

[0040] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0041] Example

[0042] like Figure 1 As shown, this invention provides an SRAM floating-point in-memory computing architecture, including an SRAM floating-point in-memory computing core module 101, a weight processing module 102, an eigenvalue exponent alignment module 103, a digital multiplication module 104, a shift-accumulate module 105, and a fixed-point to floating-point conversion module 106, wherein:

[0043] The SRAM floating-point in-memory computing core module 101 is a general-purpose SRAM in-memory computing core that stores weights in SRAM cells and performs parallel multiplication and accumulation. In both fixed-point and floating-point computing modes, the SRAM floating-point in-memory computing core module performs parallel calculations based on the weight data and input feature values. The SRAM floating-point in-memory computing core module 101 can adopt either analog in-memory computing or digital in-memory computing, and its size can be set to 128×128. The SRAM cells used can be standard 6T cells.

[0044] The weight processing module 102 includes a weight exponent pre-alignment module 1021, a large exponent weight memory 1022, and a weight exponent memory 1023. In floating-point calculation mode, the weight exponent pre-alignment module 1021 performs exponent alignment on the weights according to the computational parallelism. For example, if the computational parallelism is set to 128, the floating-point weights exceeding a threshold are stored in the large exponent weight memory 1022, and the maximum exponent of the remaining weights is stored in the weight exponent memory 1023. The remaining weights are then exponent-aligned and stored in the SRAM floating-point storage core module 101. The threshold is determined manually based on the distribution of the floating-point weights. For example, if the floating-point weights are arranged from largest to smallest, the 5th largest floating-point weight is determined as the threshold. In fixed-point calculation mode, the weights can be directly mapped to the SRAM floating-point storage core module 101, eliminating the need for other modules to operate and thus reducing power consumption.

[0045] Figure 2 This is a schematic diagram of a weighted index pre-alignment strategy provided by the present invention. Figure 2 As shown, firstly, a threshold for the floating-point exponent is obtained based on the degree of parallelism in the calculation. For example, in a 32-bit floating-point number in the IEEE 754 standard, there is 1 sign bit, 8 exponent bits, and 23 mantissa bits. Setting the threshold to 8, the weights with an exponent greater than 8 are stored in the large exponent weight memory 1022, and the largest exponent among the remaining weights is stored in the weight exponent memory 1023 (less than or equal to 8). For example, if the largest exponent among the remaining weights is 7, then 7 is stored in the weight exponent memory 1023. The remaining weight exponents are aligned to the largest exponent of 7. For example, if the exponent bit of a number represents an exponent of -8, then the mantissa data 1.M needs to be right-shifted by 15 bits, and 15 sign bits are added to the left. If the data bits in the SRAM array are set to 32 bits, including 1 sign bit and 31 mantissa bits, then when the 24 mantissa bits of the number (plus the implicit 1) are right-shifted by 15 bits and placed into the SRAM array, there will be a truncation of 24 + 15 - 31 = 8 bits of data. Since this part of the data is small, it will not have a significant impact on the calculation result. If the right shift bit is less than 8, then 0 needs to be padded in the low bits to form 32 bits of data.

[0046] In the eigenvalue exponent alignment module 103, in floating-point calculation mode, the eigenvalue corresponding to the large exponent is directly connected to the digital multiplication module 104, and the largest exponent of the remaining eigenvalues ​​is forwarded to the fixed-point to floating-point module 106 via the digital multiplication module 104. The remaining eigenvalues ​​are then exponent-aligned and transmitted to the SRAM floating-point memory module 101. In fixed-point calculation mode, the eigenvalues ​​can be directly connected to the SRAM floating-point memory module 101.

[0047] Figure 3 This is a schematic diagram of an eigenvalue exponential alignment strategy provided by the present invention. For example... Figure 3 As shown, for example, in the 32-bit floating-point number of the IEEE 754 standard, the large exponent weight is obtained through the weight exponent pre-alignment strategy. The feature value corresponding to the large exponent weight is input into the digital multiplication module 104, and the largest exponent among the remaining feature values ​​is forwarded to the fixed-point to floating-point module 106 through the digital multiplication module 104. If the largest exponent among the remaining feature values ​​is 10, 10 is transmitted to the fixed-point to floating-point module 106, and the exponents of the remaining feature values ​​are aligned to the largest exponent 10. The alignment method is the same as the weight exponent pre-alignment strategy, and then sent to the SRAM floating-point storage core module 101.

[0048] The digital multiplication module 104 is a general-purpose floating-point multiplication circuit used for multiplying large exponential weights with corresponding eigenvalues ​​in floating-point calculation mode. It does not need to operate in fixed-point calculation mode. The digital multiplication module 104 can adopt a general-purpose floating-point multiplication circuit to realize the multiplication of two IEEE 754 standard 32-bit floating-point numbers.

[0049] The shift-accumulator module 105 is a general-purpose shift-accumulator circuit used to process the calculation results of the SRAM floating-point memory module 101, performing shift and accumulation operations on the data to be accumulated in the SRAM floating-point memory module 101. The shift-accumulator module 105 can employ a general-purpose shift-accumulator circuit to implement weighted exponential shift and eigenvalue exponential shift and accumulation operations on the multiplication-accumulation results.

[0050] The fixed-point to floating-point module 106 is a general floating-point addition circuit that converts the shift accumulation result into a floating-point number and adds the result to the calculation result of the digital multiplication module 104 to obtain the final floating-point result.

[0051] Figure 4 This is a schematic diagram of a fixed-point to floating-point conversion module provided by the present invention. Figure 4 As shown, after the shift accumulation result is input with the eigenvalue exponent and the weight exponent, a floating-point result is output. This floating-point result is then added to the digital multiplication result to obtain the final floating-point result. The digital floating-point addition can be performed using a general-purpose floating-point addition circuit to perform the addition calculation of two IEEE 754 standard 32-bit floating-point numbers.

[0052] The SRAM floating-point in-memory computing architecture provided by this invention, when performing floating-point calculations, transmits large exponent weights and corresponding feature values ​​to the digital multiplication module 104 for processing. Therefore, alignment can be performed with smaller exponents during alignment, reducing truncation errors and significantly improving calculation accuracy. Since the number of large exponent weights in a neural network is relatively small, the hardware overhead added to the digital multiplication module 104 is small, and calculation accuracy can be significantly improved with a small area overhead.

[0053] The SRAM floating-point in-memory computing architecture provided by this invention can also be used for fixed-point computing. When performing fixed-point computing, no alignment operation is required. The weights and feature values ​​are directly input into the SRAM floating-point in-memory computing core module 101. The shift-accumulation module 105 shifts and accumulates the output of the SRAM floating-point in-memory computing core module 101 to obtain the fixed-point computing result.

[0054] Figure 5 This is a flowchart illustrating an SRAM floating-point in-memory calculation method provided by the present invention. Figure 5 As shown, this invention provides an SRAM floating-point in-memory calculation method, including:

[0055] Step S1: The weight exponent pre-alignment strategy aligns the weights exponents according to the degree of computational parallelism. The floating-point weights exceeding the threshold are stored in the large exponent weight memory, and the maximum exponent of the remaining weights is stored in the weight exponent memory. The remaining weights are then exponent-aligned and stored in the SRAM array.

[0056] Step S2: The eigenvalue exponent alignment strategy directly connects the eigenvalues ​​corresponding to the large exponent weights to the digital multiplication module. The maximum exponent of the remaining eigenvalues ​​is forwarded to the fixed-point to floating-point module via the digital multiplication module. Then, the remaining eigenvalues ​​are exponent aligned and transmitted to the SRAM floating-point storage core module.

[0057] Step S3: The fixed-point to floating-point module converts the calculation result of the shift-accumulation module into a floating-point number, and adds it to the result of the number multiplication module to finally obtain the floating-point result.

[0058] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0059] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. An SRAM floating point in-memory computing system, comprising: Comprise: SRAM floating-point storage and computing core module, weight processing module, eigenvalue index alignment module, digital multiplication module, shift and accumulation module and fixed-point to floating-point module; The SRAM floating-point storage and computing core module is used for storing weights in SRAM units, performing parallel multiplication and accumulation, and performing parallel calculation according to weight data and input eigenvalues in fixed-point calculation mode and floating-point calculation mode; The weight processing module comprises a weight index pre-alignment module, a large index weight storage and a weight index storage; the weight index pre-alignment module is used for performing index alignment on weights according to calculation parallelism in floating-point calculation mode, storing floating-point weights exceeding a threshold into the large index weight storage, storing the maximum index of the remaining weights into the weight index storage, and storing the remaining weights after index alignment into the SRAM floating-point storage and computing core module; The eigenvalue index alignment module is used for transmitting eigenvalues corresponding to large index weights to the digital multiplication module, forwarding the maximum index of the remaining eigenvalues to the fixed-point to floating-point module, and transmitting the remaining eigenvalues after index alignment to the SRAM floating-point storage and computing core module in floating-point calculation mode; The digital multiplication module is used for performing multiplication operation on large index weights from the large index weight storage and corresponding eigenvalues from the eigenvalue index alignment module in floating-point calculation mode; The shift and accumulation module is used for performing shift and accumulation operation on the output result of the SRAM floating-point storage and computing core module; The fixed-point to floating-point module is used for converting the output result of the shift and accumulation module into a floating-point number and adding it with the output result of the digital multiplication module; The weight index pre-alignment module is connected with the large index weight storage, the weight index storage and the SRAM floating-point storage and computing core module; The eigenvalue index alignment module is connected with the SRAM floating-point storage and computing core module and the digital multiplication module; The digital multiplication module is connected with the large index weight storage and the eigenvalue index alignment module, and is connected with the fixed-point to floating-point module; The shift and accumulation module is connected with the SRAM floating-point storage and computing core module and the fixed-point to floating-point module; The fixed-point to floating-point module is connected with the shift and accumulation module and the digital multiplication module.

2. The SRAM floating compute-in-memory system of claim 1, wherein, The size of the SRAM floating-point storage and computing core module is 128*128, and a standard 6T SRAM unit is adopted.

3. The SRAM floating compute-in-memory system of claim 1, wherein, The digital multiplication module is a general floating-point multiplication circuit, which supports IEEE754 standard 32-bit floating-point multiplication.

4. The SRAM floating compute-in-memory system of claim 1, wherein, The shift and accumulation module is a general shift and accumulation circuit, which supports weight index shift and eigenvalue index shift and accumulation operation of multiplication and accumulation result.

5. The SRAM floating compute-in-memory system of claim 1, wherein, The fixed-point to floating-point module is a general floating-point addition circuit, which supports IEEE754 standard 32-bit floating-point addition.

6. An SRAM floating in-memory computing method based on the SRAM floating in-memory computing system of any one of claims 1 to 5, characterized in that, The method comprises the following steps: Step S1: Exponentially align the weights according to the size of the calculated parallel degree, and store the part of the floating-point weights exceeding the threshold in the large-exponent weight memory, store the maximum exponent of the remaining weights in the weight exponent memory, and store the remaining weights in the SRAM array after exponentially aligning them; Step S2: Connect the feature values corresponding to the large-exponent weights directly to the digital multiplication module, and forward the maximum exponent of the remaining feature values to the fixed-point to floating-point module through the digital multiplication module, then perform exponential alignment on the remaining feature values and transmit them to the SRAM floating-point computing core module; Step S3: Convert the calculation result of the shift and accumulation module to a floating-point number through the fixed-point to floating-point module, and add it to the result of the digital multiplication module to obtain a final floating-point result.

7. The SRAM floating compute-in-memory method of claim 6, wherein, In step S1, the threshold is determined according to the distribution of the floating-point weights, including arranging the floating-point weights from large to small, and determining the floating-point weights arranged in a preset percentage as the threshold.

8. The SRAM floating compute-in-memory method of claim 6, wherein, In step S1, the exponential alignment of the weights includes: exponentially aligning the remaining weights to the maximum exponent, and the alignment method includes right shifting the mantissa bits, and the number of right shifts is based on the difference between the maximum exponent and the exponent of the current weight.

9. The SRAM floating compute-in-memory method of claim 8, wherein, For a weight with an exponent represented by an exponent bit E, the mantissa bits are right shifted by S bits, where S is the difference between the maximum exponent and E, and the sign bit is left padded, and after right shifting, the bits are truncated or zero-padded to conform to the data bit width of the SRAM array.

10. The SRAM floating compute-in-memory method of claim 9, wherein, The data bit width of the SRAM array is 32 bits, including 1 bit of sign bit and 31 bits of mantissa bit, and the mantissa bit includes 23 bits of mantissa and 1 bit of implicit mantissa. After right shifting, the number of truncated bits is 24+S-31.

Images